Memory signal processing method and electronic equipment

Abstract

The invention provides a memory signal processing method and electronic equipment, and the method comprises the steps: responding to a target operation, and controlling a target line of the electronic equipment to enter an enabling state; the target circuit is connected with an embedded controller of the electronic equipment and a memory module of the electronic equipment; controlling the embedded controller to switch the memory module from a first working mode to a second working mode through the target line; under the condition that the memory module is in the second working mode, a memory parameter adjusting signal is sent to the memory module, so that the memory module is switched from the first running state to a second running state; wherein the performance of the memory module in the second running state is higher than the performance of the memory module in the first running state.

Description

Technical Field

[0001] The present disclosure relates to the field of electronic devices, and in particular to a memory signal processing method and electronic device. Background Art

[0002] Because memory that supports Extreme Memory Profile (XMP) is relatively expensive, most memory modules currently used in computers use Non-XMP memory modules that do not have an overclocking memory profile enabled. Non-XMP does not have the tuning function, resulting in lower memory performance. Summary of the Invention

[0003] The present disclosure provides a memory signal processing method and an electronic device to at least solve the above technical problems existing in the prior art.

[0004] According to a first aspect of the present disclosure, a memory signal processing method is provided, which is applied to an electronic device. The method includes:

[0005] In response to obtaining the target operation, controlling a target circuit of the electronic device to enter an enabled state; the target circuit is connected to an embedded controller of the electronic device and a memory module of the electronic device;

[0006] Controlling the embedded controller to switch the memory module from the first operating mode to the second operating mode through the target line;

[0007] When the memory module is in the second operating mode, sending a memory parameter adjustment signal to the memory module so that the memory module switches from the first operating state to the second operating state;

[0008] The performance of the memory module in the second operating state is higher than that in the first operating state.

[0009] In one possible implementation manner, controlling a target circuit of the electronic device to enter an enabled state includes:

[0010] Controlling the target circuit to be turned on so that the target circuit enters an enabled state; or

[0011] An enable signal is sent to an enable terminal of the embedded controller and / or the memory module connected to a target line, so that the target line enters an enabled state.

[0012] In one embodiment, controlling the embedded controller to switch the memory module from the first operating mode to the second operating mode via the target line includes:

[0013] Sending a mode switching instruction to the embedded controller;

[0014] Based on the mode switching instruction, switching the memory module from the first operating mode to the second operating mode;

[0015] The first working mode is characterized by prohibiting the adjustment of memory parameters, and the second working mode is characterized by enabling the adjustment of the memory parameters.

[0016] In one embodiment, sending a memory parameter adjustment signal to the memory module so that the memory module switches from the first operating state to the second operating state includes at least one of the following:

[0017] Based on the memory parameter adjustment signal, reducing the memory timing of the memory module so that the memory module is in a second operating state;

[0018] increasing the memory frequency of the memory module based on the memory parameter adjustment signal so that the memory module is in a second operating state;

[0019] increasing the voltage of the memory module based on the memory parameter adjustment signal so that the memory module is in a second operating state;

[0020] The second operating state is a state in which the memory module operates stably.

[0021] In one embodiment, reducing the memory timing of the memory module based on the memory parameter adjustment signal includes at least one of the following:

[0022] Reducing the CAS latency of the memory module;

[0023] Reducing the row address to column address delay of the memory module;

[0024] The row precharge time of the memory module is reduced.

[0025] In one possible implementation manner, after sending a memory parameter adjustment signal to the memory module so that the memory module switches from the first operating state to the second operating state, the method further includes:

[0026] In response to the memory module being in the second operating state, the target circuit of the electronic device is controlled to enter a disabled state, so that the memory module switches from the second operating mode to the first operating mode.

[0027] In one possible implementation manner, controlling a target circuit of the electronic device to enter a disabled state includes:

[0028] Control the target line to be disconnected; or,

[0029] A disabling signal is sent to an enabling terminal of the embedded controller and / or the memory module connected to the target line.

[0030] According to an objective aspect of the present disclosure, there is provided an electronic device comprising: a processor, an embedded controller, and a memory module;

[0031] The embedded controller is connected to the memory module via a target line;

[0032] When the target operation is obtained, the processor controls the target line to enter an enabled state, and controls the embedded controller to switch the memory module from the first operating mode to the second operating mode through the target line;

[0033] When the memory module is in the second operating mode, the processor sends a memory parameter adjustment signal to the memory module, so that the memory module switches from the first operating state to the second operating state;

[0034] The performance of the memory module in the second operating state is higher than that in the first operating state.

[0035] In one embodiment, the target circuit has a first switch, and when the processor obtains the target operation, the first switch is controlled to be closed, so that the target circuit enters an enabled state;

[0036] When the memory module is in the second operating state, the first switch is controlled to be disconnected, so that the target line enters a disabled state.

[0037] In one embodiment, the embedded controller has a first pin at a connection point with the target circuit, and the memory module has a second pin at a connection point with the target circuit. When the processor obtains a target operation, an enable signal is sent to the first pin and / or the second pin, so that the target circuit enters an enabled state.

[0038] When the memory module is in the second operating state, a disabling signal is sent to the first pin and / or the second pin, so that the target line enters a disabling state.

[0039] According to a third aspect of the present disclosure, another electronic device is provided, including:

[0040] at least one processor; and

[0041] a memory communicatively connected to the at least one processor; wherein,

[0042] The memory stores instructions that can be executed by the at least one processor. The instructions are executed by the at least one processor to enable the at least one processor to perform the method described in the present disclosure.

[0043] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause the computer to execute the method described in the present disclosure.

[0044] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings, in which several embodiments of the present disclosure are shown by way of example and not limitation, wherein:

[0046] In the drawings, the same or corresponding reference numerals denote the same or corresponding parts.

[0047] Figure 1 A schematic diagram of the implementation flow of the memory signal processing method according to an embodiment of the present disclosure is shown;

[0048] Figure 2 A schematic structural diagram of an electronic device according to an embodiment of the present disclosure is shown;

[0049] Figure 3 Another flow chart of the memory signal processing method according to an embodiment of the present disclosure is shown;

[0050] Figure 4 A schematic structural diagram of another electronic device according to an embodiment of the present disclosure is shown;

[0051] Figure 5 A schematic diagram of the structure of another electronic device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0052] To make the purposes, features, and advantages of the present disclosure more apparent and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative work shall fall within the scope of protection of the present disclosure.

[0053] Most of the memory currently used in computers is Non-XMP. Non-XMP memory refers to memory modules that don't have the extreme memory profile (XMP) technology enabled. XMP is a memory overclocking technology that automatically adjusts memory frequency and timing using preset profiles to improve system performance. However, XMP is relatively expensive, while Non-XMP is inexpensive, making Non-XMP more popular in the market. However, Non-XMP cannot adjust memory parameters, which can easily cause electronic devices to crash. This application can optimize Non-XMP memory parameters, thereby improving the performance of electronic devices.

[0054] A memory signal processing method and electronic device provided by the present application are described below with reference to the accompanying drawings.

[0055] like Figure 1 The present application provides a memory signal processing method, which is applied to an electronic device, and the method includes:

[0056] S101, in response to obtaining a target operation, controlling a target circuit of an electronic device to enter an enabled state; the target circuit is connected to an embedded controller of the electronic device and a memory module of the electronic device;

[0057] It is understandable that the electronic device provided in this application may be a smartphone, tablet computer, laptop computer, desktop computer, smart home appliance, artificial intelligence device, wearable device or virtual reality device, etc., and this application does not limit it here.

[0058] The target operation in this application may be a shortcut key, a target action, a key combination, etc. For example, the shortcut key may be F1 or F2, etc., and the target action may be a gesture instruction or a voice instruction in the interactive recognition area of the electronic device, etc. For example, the gesture instruction may be sliding the palm to the left or sliding the palm to the right, or directly speaking the voice, etc. The key combination may be Windows+T or Ctrl+P, etc. Among them, this application pre-sets shortcut keys, target actions and key combinations in the electronic device, so that after the electronic device obtains the above-mentioned target operation, it can control the target line to enter the enabled state.

[0059] Among them, such as Figure 2 As shown, the memory signal processing method provided in the present application can be implemented by a processor 1 (Central Processing Unit, CPU) in an electronic device. The target circuit in the present application is a circuit connecting an embedded controller 2 in the electronic device and a memory module 3 of the electronic device. The enabled state of the target circuit is a state in which a certain function can be realized.

[0060] For example, in the case of a laptop computer, during the laptop's startup process, the interactive recognition area monitors in real time whether a target operation is occurring. Upon detecting a target operation, such as a gesture command, the CPU controls the target circuit connecting the embedded controller 2 and the memory module 3 to enter an enabled state capable of performing the target function. The interactive recognition area can be the image range captured by the laptop's camera.

[0061] S102, controlling the embedded controller 2 to switch the memory module 3 from the first operating mode to the second operating mode via the target line;

[0062] It can be understood that in this application, the memory module 3 has two working modes, specifically the first working mode and the second working mode, wherein the performance of the memory module 3 running in the first working mode is different from the performance of the memory module 3 running in the second working mode.

[0063] The processor 1 is connected to the embedded controller 2. The processor 1 can send control instructions to the embedded controller 2. The embedded controller 2 implements the target function through the enable state of the target line according to the control instructions, and switches the memory module 3 from the first working mode to the second working mode.

[0064] For example, taking the electronic device as a laptop computer, when the laptop computer is not turned on, the memory module 3 is in the first working mode. During the startup process of the laptop computer, the interactive identification area recognizes the target operation, and the processor 1 controls the target line to enter an enabled state that can realize the target function. The processor 1 sends a control instruction to the embedded controller 2. Based on the control instruction, the embedded controller 2 switches the working mode of the memory module 3 from the first working mode to the second working mode through the target line.

[0065] S103, when the memory module 3 is in the second operating mode, sending a memory parameter adjustment signal to the memory module 3, so that the memory module 3 switches from the first operating state to the second operating state;

[0066] The performance of the memory module 3 in the second operating state is higher than that in the first operating state.

[0067] Specifically, after the operating mode of memory module 3 switches from the first operating mode to the second operating mode, while memory module 3 is in the second operating mode, processor 1 sends a memory parameter adjustment signal to memory module 3, and the memory parameters are adjusted according to the adjustment signal. After the memory parameters are adjusted, memory module 3 switches from the first operating state to the second operating state. It is understood that the first operating state is the operating state of memory module 3 in the first operating mode or the operating state of memory module 3 in the second operating mode when the memory parameters have not been adjusted, and the second operating state is the operating state of memory module 3 after the memory parameters have been adjusted. It is understood that the performance of memory module 3 in the second operating state is higher than that in the first operating state. In other words, after processor 1 adjusts the memory parameters of memory module 3, the performance of memory module 3 in the operating state is improved. Memory parameters are adjustable memory parameters, and adjustment of memory parameters plays a crucial role in the performance and operating speed of the electronic device's operating system. Therefore, adjusting memory parameters can optimize the operating performance of the electronic device.

[0068] For example, taking the electronic device as a laptop computer, after the memory module 3 in the laptop computer switches from the first operating mode to the second operating mode, the CPU sends an adjustment signal to the memory module 3, thereby tuning the memory parameters in the memory module 3. The tuned memory parameters enable the memory module 3 to operate in the second operating state.

[0069] The memory signal processing method provided in the present application is that during the startup process of an electronic device, if the processor 1 detects a target operation, such as a gesture command, a voice command, a shortcut key, or a combination key, the target circuit of the electronic device is controlled to enter an enabled state, and the enabled state can realize the switching of the working mode of the memory module 3. Thereby, the embedded controller 2 is controlled to switch the memory module 3 from the first working mode to the second working mode through the target circuit. After the memory module 3 switches to the second working mode, the processor 1 sends a memory parameter adjustment signal to the memory module 3, thereby adjusting the memory parameters of the memory module 3, so that the memory module 3 after the memory parameter adjustment switches from the first operating state to the second operating state with higher performance.

[0070] The memory signal processing method provided in this application improves the performance of memory module 3 by dynamically adjusting memory parameters when needed, overcoming the limitations of the low performance of non-XMP memory modules 3. By dynamically adjusting memory parameters, the flexibility and adaptability of memory module 3 are improved, better meeting the needs of different application scenarios. This application solves the problem of low performance of non-XMP memory modules 3 and improves the operational performance of memory modules 3.

[0071] In some embodiments, controlling a target circuit of an electronic device to enter an enabled state includes:

[0072] Control the target line to be turned on, so that the target line enters the enabled state; or,

[0073] An enable signal is sent to the enable terminal of the embedded controller 2 and / or the memory module 3 connected to the target line, so that the target line enters an enabled state.

[0074] It can be understood that the embedded controller 2 is connected to the memory module 3 through the target line, but when the target line is in an unconnected state, the target line cannot enter the enabled state, and the processor 1 needs to control the target line to be connected to enter the enabled state; or, even if the target line is in a conductive state, it cannot enter the enabled state when it does not receive the enable signal from the processor 1.

[0075] As an example, Figure 3 As shown, after receiving the instruction generated by the target operation, the processor 1 sends a control signal to control the target line to be turned on, so that the target line enters the enabled state; or, if the target line is turned on, the processor 1 can send an enable signal to the enable end of the embedded controller 2 connected to the target line, or send an enable signal to the enable end of the memory module 3 connected to the target line, or send the enable signal to the enable end of the embedded controller 2 connected to the target line and the enable end of the memory module 3 connected to the target line at the same time, so that the target line enters the enabled state.

[0076] For example, the conduction of the target circuit can be controlled by setting a switch. For example, a transistor is set in the target circuit, and the processor 1 controls the conduction and disconnection of the target circuit by controlling the on and off of the transistor. When the target circuit is conductive, it enters the enabled state. A first pin of the embedded controller 2 is connected to a second pin of the memory module 3 via the target circuit. The processor 1 can send an enable signal to the first pin to enable the target circuit. The processor 1 can also send an enable signal to the second pin to enable the target circuit. The processor 1 can also send an enable signal to the first pin and the second pin simultaneously to enable the target circuit.

[0077] This application controls the target circuit to be turned on or sends an enable signal to enable the target circuit to a state, thereby ensuring a smooth connection between the embedded controller 2 and the memory module 3, thereby achieving mode switching of the memory module 3. This application can control the target circuit of the electronic device to enter a state of enablement, ensuring that the memory module 3 can switch from the first operating mode to the second operating mode, thereby improving memory performance.

[0078] In some embodiments, controlling the embedded controller 2 to switch the memory module 3 from the first operating mode to the second operating mode via the target line includes:

[0079] Sending a mode switching instruction to embedded controller 2;

[0080] Based on the mode switching instruction, the memory module 3 is switched from the first operating mode to the second operating mode;

[0081] The first working mode is characterized by prohibiting the adjustment of the memory parameters, and the second working mode is characterized by enabling the adjustment of the memory parameters.

[0082] In this application, when the target circuit enters the enabled state, processor 1 sends a mode switch instruction to embedded controller 2. This mode switch instruction is used to notify embedded controller 2 to switch the operating mode of memory module 3. Embedded controller 2 thereby switches memory module 3 from the first operating mode to the second operating mode via the target circuit. In this application, the first operating mode is a mode that prohibits adjustment of memory parameters, while the second operating mode is a mode that enables adjustment of memory parameters. This approach solves the problem of memory module 3 being limited in its ability to adjust memory parameters under different operating modes.

[0083] The mode switching instruction can be sent to the embedded controller 2 via a software command or a hardware signal. Specifically, a mode switching algorithm can be preset in the processor 1 of the electronic device. When a mode switch is detected, the algorithm is triggered to generate a mode switching instruction and send the instruction to the embedded controller 2. Furthermore, a mode switching option can be provided through a user interface. When the user selects the option, the system generates and sends the mode switching instruction.

[0084] The memory module 3 provided in the present application includes a first working mode that prohibits the adjustment of memory parameters and a second working mode that enables the adjustment of memory parameters. When the memory module 3 is in the first working mode, the processor 1 cannot adjust the memory parameters. When the memory module 3 is in the second working mode, the processor 1 can adjust the memory parameters. It should be noted that only when the target line enters the enabled state can the memory module 3 switch from the first working mode to the second working mode.

[0085] Exemplarily, the CPU sends a mode switching instruction to the embedded controller 2. After receiving the mode switching instruction, the embedded controller 2 switches the memory module 3 from a first working mode that prohibits adjusting memory parameters to a second working mode that allows adjusting memory parameters through the target line.

[0086] The present application can realize the switching of the memory module 3 from the first working mode to the second working mode, thereby adjusting the memory parameters, improving the performance of the memory module 3, and improving the overall operating efficiency of the electronic device, overcoming the limitations of the existing memory module 3 in the adjustment performance.

[0087] In some embodiments, sending a memory parameter adjustment signal to the memory module 3 so that the memory module 3 switches from the first operating state to the second operating state includes at least one of the following:

[0088] Based on the memory parameter adjustment signal, reducing the memory timing of the memory module 3 so that the memory module 3 is in the second operating state;

[0089] Based on the memory parameter adjustment signal, increase the memory frequency of the memory module 3 so that the memory module 3 is in the second operating state;

[0090] Based on the memory parameter adjustment signal, increasing the voltage of the memory module 3 so that the memory module 3 is in the second operating state;

[0091] The second operating state is a state in which the memory module 3 operates stably.

[0092] The memory parameters provided in this application may include multiple parameters, such as memory timing, memory frequency, and memory voltage, and may also include other memory parameters, which are not limited in this application. Among them, memory frequency refers to the number of times the memory bar transmits data per second. Increasing the memory frequency can improve the performance of the memory module 3 in operation. Memory timing determines the latency of memory read and write operations and is usually composed of four values: CL, tRCD, tRP, and tRAS. The lower the timing value, the better the performance, but stability may be affected. In addition, adjusting the memory voltage can also improve the performance of the memory module 3 in operation.

[0093] For example, the CPU can optimize the performance of memory module 3 by sending memory parameter adjustment signals to memory module 3. For example, reducing memory timing can enable memory module 3 to complete data transfers in a shorter time, thereby improving performance; increasing memory frequency can increase the data transfer rate of memory module 3, thereby improving performance; and increasing memory voltage can enhance the stability and performance of memory module 3. Each memory parameter can be adjusted independently or in conjunction with other parameters, acting together to improve the performance of memory module 3, thus solving the problem of optimizing the performance of memory module 3.

[0094] For example, reducing memory timing can be achieved by reducing the CAS latency, row address to column address delay, and row precharge time of the memory module 3. Increasing memory frequency can be achieved by adjusting the clock frequency of the memory module 3. Increasing memory voltage can be achieved by adjusting the supply voltage of the memory module 3 to enhance its stability and performance.

[0095] This application effectively adjusts the timing, frequency, and voltage of memory module 3 by sending a memory parameter adjustment signal to memory module 3, thereby optimizing the performance of memory module 3. This application can achieve performance tuning of memory module 3 without enabling an overclocking memory profile, solving the problem of existing non-XMP memory modules 3 being unable to be tuned, allowing memory module 3 to maintain stable operation while improving performance.

[0096] In some embodiments, reducing the memory timing of the memory module 3 based on the memory parameter adjustment signal includes at least one of the following:

[0097] Reduce CAS latency of memory module 3;

[0098] Reduce the row address to column address delay of memory module 3;

[0099] Reduce the row precharge time of memory module 3.

[0100] It should be noted that memory timing is generally composed of four main parameters: CAS Latency (CL), tRCD (RAS to CAS Delay), tRP (RAS Precharge Time), and tRAS (Active to Precharge Delay). tRAS must be an appropriate value to ensure a proper ratio of these four parameters. These parameters collectively affect memory performance and response speed, and a reasonable ratio is crucial for optimizing memory performance.

[0101] For example, CAS latency is one of the key indicators for measuring memory performance. Lower CAS latency means that the memory can respond to read commands faster, thereby improving the overall performance of the system, especially in applications that require frequent access to memory, such as gaming and data processing. CAS latency directly affects the response speed of the memory. Reducing CAS latency can be achieved by adjusting the control circuit of the memory module 3, for example, by optimizing the instruction decoding and execution path of the memory module 3 so that the response time of the CAS signal is shortened. Reducing the row address to column address delay can be achieved by improving the address decoder of the memory module 3 so that the conversion of row addresses and column addresses is more efficient. Reducing the row precharge time can be achieved by optimizing the precharge circuit of the memory module 3 so that the waiting time of the memory unit in the precharge operation is reduced.

[0102] The present application significantly reduces the memory timing of the memory module 3 by reducing the memory timing of the memory module 3, thereby improving the overall performance of the memory module 3. These improvements can not only increase data access speed, but also reduce power consumption to a certain extent and improve system operating efficiency.

[0103] In some embodiments, after sending a memory parameter adjustment signal to the memory module 3 so that the memory module 3 switches from the first operating state to the second operating state, the method further includes:

[0104] In response to the memory module 3 being in the second operating state, the target circuit of the electronic device is controlled to enter a disabled state, so that the memory module 3 switches from the second operating mode to the first operating mode.

[0105] The present application can also send a memory parameter adjustment signal to the memory module 3 after the memory module 3 switches from the first operating state to the second operating state, so that after the memory module 3 switches from the first operating state to the second operating state, it also includes: in response to the memory module 3 being in the second operating state, controlling the target circuit of the electronic device to enter a non-enabled state, so that the memory module 3 switches from the second working mode to the first working mode. By controlling the target circuit to enter a non-enabled state after the performance of the memory module 3 is improved, the memory module 3 returns to the initial working mode, thereby ensuring that the memory module 3 can operate stably after the performance improvement.

[0106] For example, controlling the target circuit of the electronic device to enter a disabled state can be achieved in the following ways. For example, the target circuit can be disconnected, or a disable signal can be sent to the enable terminal of the embedded controller 2 and / or memory module 3 connected to the target circuit. This allows the memory module 3 to switch from the second operating mode back to the first operating mode, ensuring that it can return to the first operating mode after performance improvement.

[0107] This application not only improves the performance of the memory module 3, but also ensures its stability and reliability.

[0108] In some embodiments, controlling a target circuit of an electronic device to enter a disabled state includes:

[0109] The control target line is disconnected; or,

[0110] A disabling signal is sent to the enabling terminal of the embedded controller 2 and / or the memory module 3 connected to the target line.

[0111] This application enables the memory module 3 of the electronic device to be quickly switched back to the first operating mode by controlling the target circuit to enter the disabled state after the memory module 3 is in the second operating state. That is, the memory module 3 is switched from the second operating mode in which memory parameters can be adjusted to the first operating mode in which memory parameters cannot be adjusted, thereby optimizing memory performance and stabilizing operation. This ensures that while the performance of the memory module 3 is improved, the overall stability and reliability of the electronic device are guaranteed.

[0112] Exemplarily, the implementation of controlling the target line to enter a disabled state includes: controlling the target line to be disconnected through a hardware circuit so that the electrical signal cannot continue to be transmitted, such as setting a switch and controlling the conduction or disconnection of the target line by turning the switch on or off; or sending a disable signal to the enable end of the embedded controller 2 connected to the target line, or sending a disable signal to the enable end of the memory module 3 connected to the target line, or sending a disable signal to the enable ends of both the embedded controller 2 and the memory module 3 connected to the target line, so that the target line enters a disabled state. The above implementation methods are selected according to the specific application scenario and requirements.

[0113] The present application solves the stability problem of the memory module 3 after performance improvement and provides a more flexible and efficient memory control method, which not only improves the memory performance but also ensures the stable operation of the electronic device.

[0114] like Figure 4 As shown, the present application provides an electronic device, comprising: a processor 1, an embedded controller 2 and a memory module 3;

[0115] The embedded controller 2 is connected to the memory module 3 via a target line;

[0116] When the target operation is obtained, the processor 1 controls the target line to enter the enabled state, and controls the embedded controller 2 to switch the memory module 3 from the first working mode to the second working mode through the target line;

[0117] When the memory module 3 is in the second operating mode, the processor 1 sends a memory parameter adjustment signal to the memory module 3, so that the memory module 3 switches from the first operating state to the second operating state;

[0118] The performance of the memory module 3 in the second operating state is higher than that in the first operating state.

[0119] The electronic device provided by the present application includes a processor 1, an embedded controller 2 and a memory module 3. When the processor 1 obtains a target operation, it controls the target circuit to enter an enabled state, and controls the embedded controller 2 through the target circuit to switch the memory module 3 from a first operating mode to a second operating mode. When the memory module 3 is in the second operating mode, the processor 1 sends a memory parameter adjustment signal to the memory module 3, so that the memory module 3 switches from the first operating state to the second operating state, thereby improving the performance of the memory module 3. The present application realizes the switching of the operating mode of the memory module 3 by controlling the target circuit and the embedded controller 2 through the processor 1, and realizes the improvement of the operating state of the memory module 3 by sending the memory parameter adjustment signal, thereby solving the problem of low performance of the current memory module 3.

[0120] When obtaining the target operation, the processor 1 first controls the target line to enter the enabled state, so that the embedded controller 2 and the memory module 3 can communicate. Then, the processor 1 controls the embedded controller 2 to switch the memory module 3 from the first operating mode to the second operating mode through the target line. In the second operating mode, the processor 1 sends a memory parameter adjustment signal to the memory module 3, so that the memory module 3 switches from the first operating state to the second operating state. The performance of the memory module 3 in the second operating state is higher than the performance in the first operating state. This method can improve the performance of the memory module 3 by adjusting the memory parameters, such as reducing the memory timing, increasing the memory frequency or memory voltage, etc. These adjustment methods can be selected according to specific needs to ensure that the memory module 3 achieves higher performance under stable operation.

[0121] This application uses processor 1 to control the target circuit and embedded controller 2, achieving switching between the working mode and operating state of memory module 3, thus solving the current problem of low performance of memory module 3. This can enable electronic devices to have higher memory performance, effectively improving the overall performance of computers and meeting users' demand for high-performance memory.

[0122] In some embodiments, the target circuit has a first switch, and when the processor 1 obtains the target operation, the first switch is controlled to be closed, so that the target circuit enters an enabled state;

[0123] When the memory module 3 is in the second operating state, the first switch is controlled to be disconnected, so that the target line enters a disabled state.

[0124] It is understood that the target circuit can have a first switch, and the on / off of the target circuit can be controlled by controlling the closing and opening of the first switch. When the target circuit is on, it enters an enabled state, and when the target circuit is off, it enters a disabled state. Thus, when the target circuit is in the enabled state, the memory module 3 enters a second operating mode in which memory parameters can be adjusted, and when the target circuit is in the disabled state, the memory module 3 enters a first operating mode in which memory parameters cannot be adjusted. The processor 1 can control the closing and opening of the switch to switch the memory module 3 from the first operating mode to the second operating mode or from the second operating mode to the first operating mode.

[0125] For example, the first switch can be implemented in a variety of ways, such as a mechanical switch, an electronic switch, or a relay. Specifically, a mechanical switch can be implemented using a physical button or a toggle switch; an electronic switch can be implemented using a transistor or MOSFET in an integrated circuit; and a relay can be electromagnetically controlled to close and open the switch. Furthermore, the control signal for the first switch can be sent by processor 1 or transmitted using a dedicated control bus. A low-power electronic switch can also be used to reduce the impact on overall system power consumption.

[0126] By setting the first switch of the target circuit, the present application can effectively control the enabled state and the disabled state of the target circuit, thereby enabling the memory module 3 to switch between the first working mode and the second working mode, while ensuring the performance of the memory module 3, reducing power consumption and extending the service life of the device.

[0127] In some embodiments, such as Figure 4 As shown, the embedded controller 2 has a first pin at the connection with the target line, and the memory module 3 has a second pin at the connection with the target line. When the processor 1 obtains the target operation, an enable signal is sent to the first pin and / or the second pin, so that the target line enters the enabled state;

[0128] When the memory module 3 is in the second operating state, a disable signal is sent to the first pin and / or the second pin, so that the target line enters a disable state.

[0129] In the present application, the first pin at the connection between the embedded controller 2 and the target circuit and the second pin at the connection between the memory module 3 and the target circuit control the state of the target circuit by sending an enable signal and a disable signal. The function of the first pin and the second pin is to enable the target circuit to enter the enable state through the enable signal, so that the memory module 3 can operate in the second working mode, and switch to the second operating state with higher performance after obtaining the memory parameter adjustment signal; when the memory module 3 is in the second operating state, the target circuit is entered into the disable state by sending a disable signal, thereby restoring the memory module 3 to the first working mode. Specifically, the present application can control the enable state and the disable state of the target circuit so that the memory module 3 can switch to the second working mode in which the memory parameters can be adjusted when needed, thereby adjusting the memory parameters and improving the memory performance.

[0130] By way of example, the first pin and the second pin can be implemented in a variety of ways. For example, the first pin and the second pin can be standard digital input / output pins, controlling the enabled and disabled states of the target circuit via simple high and low level signals. Furthermore, the first pin and the second pin can be implemented via dedicated control circuitry integrated into the embedded controller 2 and the memory module 3, making the transmission and reception of control signals more stable and reliable. Furthermore, the connection between the first pin and the second pin can utilize a standard cable connection or a wire connection on a printed circuit board to ensure stable and reliable signal transmission.

[0131] Exemplarily, the first pin can be the GPIO pin of the embedded controller 2, and the second pin can be the PWR-EN pin of the memory module 3. The GPIO pin and PWR-EN pin of the present application can receive the enable signal or disable signal of the processor 1, so that the target line enters the enabled state or the disabled state.

[0132] This application addresses the issue of memory module 3's inability to adjust memory parameters by providing a first pin and a second pin at the connection between the embedded controller 2 and the memory module 3 and the target circuit, and controlling the state of the target circuit by sending an enable signal and a disable signal. This enables the memory module 3 to switch to a second, higher-performance operating state when needed, thereby resolving the issue of memory module 3's inability to adjust memory parameters. This application provides a more flexible and efficient memory performance adjustment method that can dynamically adjust memory performance based on actual needs, thereby improving the overall performance and response speed of the memory module 3.

[0133] An embodiment of the present application provides another electronic device, including:

[0134] at least one processor; and

[0135] a memory communicatively connected to the at least one processor; wherein,

[0136] The memory stores instructions that can be executed by the at least one processor. The instructions are executed by the at least one processor to enable the at least one processor to perform the method described in any one of the above embodiments.

[0137] An embodiment of the present application provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable a computer to execute the method described in any of the above embodiments.

[0138] According to an embodiment of the present application, the present application also provides an electronic device and a readable storage medium.

[0139] Figure 5A schematic block diagram of an example electronic device 800 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are provided as examples only and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0140] like Figure 5 As shown, the device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 into a random access memory (RAM) 803. Various programs and data required for the operation of the device 800 can also be stored in the RAM 803. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0141] Various components in device 800 are connected to I / O interface 805, including an input unit 806, such as a keyboard, mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a magnetic disk, optical disk, etc.; and a communication unit 809, such as a network card, modem, wireless communication transceiver, etc. The communication unit 809 allows device 800 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0142] The computing unit 801 can be a variety of general-purpose and / or specialized processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, central processing unit, micro-central processing unit, etc. The computing unit 801 performs the various methods and processes described above, such as the memory signal processing method. For example, in some embodiments, the memory signal processing method can be implemented as a computer software program that is tangibly contained in a machine-readable medium, such as the storage unit 808. In some embodiments, part or all of the computer program can be loaded and / or installed on the device 800 via the ROM 802 and / or the communication unit 809. When the computer program is loaded into the RAM 803 and executed by the computing unit 801, one or more steps of the memory signal processing method described above can be performed. Alternatively, in other embodiments, the computing unit 801 can be configured to perform the memory signal processing method by any other suitable means (e.g., by means of firmware).

[0143] Various embodiments of the systems and techniques described above can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on a chip (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0144] The program code for implementing the method of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or central processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the program code is executed by the processor or central processing unit, the functions / operations specified in the flow chart and / or block diagram are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0145] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in conjunction with an instruction execution system, device or equipment. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0146] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0147] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0148] A computer system may include a client and a server. The client and server are generally remote from each other and typically interact through a communication network. The client-server relationship arises through computer programs running on the respective computers and having a client-server relationship with each other. The server may be a cloud server, a server in a distributed system, or a server integrated with a blockchain.

[0149] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions of this disclosure can be achieved. This is not a limitation herein.

[0150] Furthermore, the terms "first" and "target" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature defined as "first" or "target" may explicitly or implicitly include at least one such feature. Throughout the present disclosure, "plurality" means two or more, unless otherwise specifically defined.

[0151] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A memory signal processing method, applied to an electronic device, comprising: In response to obtaining the target operation, controlling a target circuit of the electronic device to enter an enabled state; The target line connects the embedded controller of the electronic device and the memory module of the electronic device; Controlling the embedded controller to switch the memory module from the first operating mode to the second operating mode through the target line; When the memory module is in the second operating mode, sending a memory parameter adjustment signal to the memory module so that the memory module switches from the first operating state to the second operating state; The performance of the memory module in the second operating state is higher than that in the first operating state.

2. The method according to claim 1, wherein the step of controlling a target circuit of the electronic device to enter an enabled state comprises: Controlling the target circuit to be turned on so that the target circuit enters an enabled state; or, An enable signal is sent to an enable terminal of the embedded controller and / or the memory module connected to a target line, so that the target line enters an enabled state.

3. The method according to claim 1 , wherein controlling the embedded controller to switch the memory module from the first operating mode to the second operating mode via the target line comprises: Sending a mode switching instruction to the embedded controller; Based on the mode switching instruction, switching the memory module from the first operating mode to the second operating mode; The first working mode is characterized by prohibiting the adjustment of memory parameters, and the second working mode is characterized by enabling the adjustment of the memory parameters.

4. The method according to claim 1, wherein the sending of a memory parameter adjustment signal to the memory module so that the memory module switches from the first operating state to the second operating state comprises at least one of the following: Based on the memory parameter adjustment signal, reducing the memory timing of the memory module so that the memory module is in a second operating state; increasing the memory frequency of the memory module based on the memory parameter adjustment signal so that the memory module is in a second operating state; increasing the voltage of the memory module based on the memory parameter adjustment signal so that the memory module is in a second operating state; The second operating state is a state in which the memory module operates stably.

5. The method according to claim 4, wherein reducing the memory timing of the memory module based on the memory parameter adjustment signal comprises at least one of the following: Reducing the CAS latency of the memory module; Reducing the row address to column address delay of the memory module; The row precharge time of the memory module is reduced.

6. The method according to any one of claims 1 to 5, further comprising: after sending a memory parameter adjustment signal to the memory module so that the memory module switches from the first operating state to the second operating state; In response to the memory module being in the second operating state, the target circuit of the electronic device is controlled to enter a disabled state, so that the memory module switches from the second operating mode to the first operating mode.

7. The method according to claim 6, wherein the step of controlling the target circuit of the electronic device to enter a disabled state comprises: Controlling the target line to be disconnected; or, A disabling signal is sent to an enabling terminal of the embedded controller and / or the memory module connected to the target line.

8. An electronic device comprising: processors, embedded controllers, and memory modules; The embedded controller is connected to the memory module via a target line; When the target operation is obtained, the processor controls the target line to enter an enabled state, and controls the embedded controller to switch the memory module from the first operating mode to the second operating mode through the target line; When the memory module is in the second operating mode, the processor sends a memory parameter adjustment signal to the memory module, so that the memory module switches from the first operating state to the second operating state; The performance of the memory module in the second operating state is higher than that in the first operating state.

9. The electronic device according to claim 8, The target circuit has a first switch, and when the processor obtains the target operation, the first switch is controlled to be closed, so that the target circuit enters an enabled state; When the memory module is in the second operating state, the first switch is controlled to be disconnected, so that the target line enters a disabled state.

10. The electronic device according to claim 8, The embedded controller has a first pin at a connection point with the target circuit, and the memory module has a second pin at a connection point with the target circuit. When the processor obtains a target operation, an enable signal is sent to the first pin and / or the second pin, so that the target circuit enters an enabled state. When the memory module is in the second operating state, a disabling signal is sent to the first pin and / or the second pin, so that the target line enters a disabling state.

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