A cascaded anti-interference circuit suitable for an electrocardio monitoring device

Abstract

The embodiment of the application provides a cascade anti-interference circuit suitable for an electrocardio monitoring device, which comprises a sliding mean filter module, a notch filter module, a lifting wavelet decomposition module, a threshold calculation module, a threshold processing module and a lifting wavelet reconstruction module; while ensuring a small circuit scale, the ECG signal collected by the wearable electrocardio monitoring device is subjected to hierarchical noise reduction processing, and high signal-to-noise ratio ECG signal output is realized; for the ECG signal collected by the wearable electrocardio monitoring device, first, sliding mean filtering is performed to filter out baseline drift noise caused by human respiratory movement and other activities; the power frequency interference caused by the wired and wireless connection of the electromagnetic environment around the device is suppressed by using the notch filter module; finally, wavelet noise reduction is realized by using the lifting wavelet decomposition and reconstruction and threshold noise reduction method, the electromyographic interference caused by the autonomous or unconscious movement of the wearer is suppressed, and high signal-to-noise ratio ECG signal is output, which is used for physiological parameter extraction and electrocardio diagnosis.

Description

Technical Field

[0001] This invention relates to the field of digital integrated circuit technology, and in particular to a cascaded anti-interference circuit suitable for electrocardiogram monitoring equipment. Background Technology

[0002] Cardiovascular disease (CVD) has become a leading threat to global public health. Multiple social pressures and disrupted lifestyles have led to a continuous rise in CVD incidence, with a significant trend towards a younger patient population. Globally, approximately 18 million people die from cardiovascular disease each year, accounting for 31% of all deaths worldwide. my country has a large CVD patient population, with epidemiological surveys indicating over 330 million cases. Traditional electrocardiogram (ECG) examinations serve as the "gold standard" for clinical diagnosis; however, due to the large size of the devices and the intermittent nature of the monitoring, their use is limited to specialized medical settings such as hospitals, making it difficult to meet the needs of early warning and long-term health management for cardiovascular disease patients. Wearable ECG monitoring devices can provide solutions for the long-term health management of CVD patients by collecting physiological data in real time, and have significant clinical value. However, ECG signals, as typical weak physiological signals, are easily interfered with by various noises during acquisition, requiring pre-processing to reduce noise and meet the needs of clinical diagnosis. Summary of the Invention

[0003] This invention provides a cascaded anti-interference circuit suitable for electrocardiogram (ECG) monitoring devices to solve the noise interference problem in ECG signals acquired by existing wearable ECG monitoring devices.

[0004] This invention provides a cascaded anti-interference circuit suitable for electrocardiogram (ECG) monitoring equipment, comprising:

[0005] The sliding mean filtering module is used to receive the electrocardiogram (ECG) signal and extract the low-frequency component of the ECG signal to obtain the ECG signal after baseline drift is suppressed.

[0006] The notch filter module is used to receive the ECG signal processed by the sliding mean filter module, and determine the center frequency point and quality factor based on the frequency characteristic information of the power frequency interference, thereby eliminating the power frequency interference in the ECG signal.

[0007] The lifting wavelet decomposition module is used to receive the ECG signal processed by the notch filter module, and decompose the ECG signal into a first layer of detail coefficients, a second layer of detail coefficients, a third layer of detail coefficients, and a first layer of approximation coefficients through three layers of lifting wavelet decomposition.

[0008] The threshold calculation module is used to receive the second layer detail coefficient group and the third layer detail coefficient group, and perform median extraction and multiplication and division operations to obtain the threshold of the corresponding layer.

[0009] The threshold processing module is used to perform forced noise reduction processing on the first layer detail coefficient group, and to perform threshold noise reduction processing on the second layer detail coefficient group and the third layer detail coefficient group based on the threshold of the corresponding layer.

[0010] The lifting wavelet reconstruction module is used to receive the first layer detail coefficient group, the second layer detail coefficient group, the third layer detail coefficient group and the first layer approximation coefficient group processed by the threshold processing module, and perform layer-by-layer lifting wavelet reconstruction to output the noise-reduced ECG reconstruction signal.

[0011] Preferably, the moving average filtering module includes a shift register group, three two-input summers, a delay register, and a shifter; the window length of the shift register group is 32, which is used for data shifting and storage, and two sets of two-input summers are used to sum 32 data points, of which 31 data points can be reused.

[0012] Preferably, the notch filter module is a second-order infinite impulse response (IIR) filter.

[0013] Preferably, the lifting wavelet decomposition module includes a first-layer lifting wavelet decomposition unit, a second-layer lifting wavelet decomposition unit, and a third-layer lifting wavelet decomposition unit.

[0014] The approximate coefficient set obtained after the input signal passes through the first lifting wavelet decomposition unit is used as the input signal of the second lifting wavelet decomposition unit, and the approximate coefficient set of the second lifting wavelet decomposition unit is used as the input signal of the third lifting wavelet decomposition unit.

[0015] As a preferred embodiment, the first-layer lifting wavelet decomposition unit, the second-layer lifting wavelet decomposition unit, and the third-layer lifting wavelet decomposition unit all include a clock frequency division subunit, a sequence parity splitting subunit, and a prediction update subunit.

[0016] The clock division subunit generates and distributes the clocks for each part of the system by dividing the master clock at different levels.

[0017] The sequence parity splitting subunit splits the main sequence by recognizing clock pulses of different frequencies for prediction update operations;

[0018] The prediction update subunit approximates the approximate coefficient set and the detailed coefficient set through multiple prediction and update operations;

[0019] After single-level lifting wavelet decomposition, the original sequence is decomposed into a set of detail coefficients containing the detail parts and a set of approximate coefficients containing the remaining parts.

[0020] Preferably, the threshold calculation module includes a first absolute value extraction unit, a bitone network sorting median extraction unit, and a threshold multiplication operation unit;

[0021] The first absolute value extraction unit performs absolute value conversion on the input 16-bit signed number format signal, sorts the resulting absolute value sequence using a bitonic network, extracts the median based on the sorting position for threshold calculation, uses the extracted median for threshold multiplication calculation, and obtains the upper and lower thresholds for threshold processing from the results of the threshold multiplication calculation, which are then output to the threshold processing module.

[0022] The median extraction unit of the bitone network sorting includes a discriminator, a bitwise inverter, a two-input adder, a two-to-one selector, and a register. It determines the sign of the data by judging the high-order bits of the input signal. For positive numbers with a sign bit of 0, it outputs directly. For negative numbers with a sign bit of 1, it performs a bitwise inversion and adds 1. Finally, it selects and outputs the absolute value sequence of the input sequence.

[0023] The threshold multiplication unit includes two multipliers, two registers, four shifters, and two two-input summers; the two paths respectively calculate the upper and lower thresholds of the second-level detail coefficient group and the third-level detail coefficient group.

[0024] Preferably, the threshold processing unit includes a second absolute value extraction unit, a threshold discrimination unit, a nonlinear operation unit, and an output selection unit;

[0025] The second absolute value extraction unit is used to extract the absolute value of the input signal;

[0026] The threshold discrimination unit is used to generate a selection signal sel based on the relative magnitude of the absolute value and the upper and lower thresholds. It generates three different selection signals for three cases: the absolute value is less than the lower threshold, the absolute value is greater than the upper threshold, and the absolute value is between the upper and lower thresholds. When the absolute value is greater than the upper threshold, the input signal is directly output. When the absolute value is less than the lower threshold, the output is set to zero. When the absolute value is between the upper and lower thresholds, a non-linear operation is used for the output.

[0027] The nonlinear operation unit includes a division operation subunit, a squaring operation subunit, and a sign bit concatenation operation subunit.

[0028] Preferably, the lifting wavelet reconstruction module includes a cascaded first lifting wavelet reconstruction unit, a second lifting wavelet reconstruction unit, and a third lifting wavelet reconstruction unit.

[0029] The input signal of the first lifting wavelet reconstruction unit is the third-level detail coefficient group and the third-level approximation coefficient group after thresholding. The newly reconstructed second-level approximation coefficient group is connected to the second-level lifting wavelet reconstruction unit as the input signal. The newly reconstructed first-level approximation coefficient group with the thresholded second-level detail coefficient group is connected to the third-level lifting lower wavelet reconstruction unit as the input signal. The denoised ECG reconstruction signal is reconstructed with the first-level detail coefficient group after forced denoising.

[0030] Preferably, the first lifting wavelet reconstruction unit, the second lifting wavelet reconstruction unit, and the third lifting wavelet reconstruction unit all include a clock division subunit, an anti-prediction and anti-update subunit, and an odd-even sequence merging subunit.

[0031] The clock division subunit is used for the generation and distribution of the global clock, and the inverse prediction and inverse update subunit is used to perform multiple inverse predictions and inverse updates on the input approximation coefficient group and detail coefficient group to make them approximate the odd and even sequences of the reconstructed sequence. The ECG reconstructed signal is obtained by merging the odd and even sequences through the odd and even sequence merging subunit.

[0032] This invention provides a cascaded anti-interference circuit suitable for ECG monitoring devices, comprising a sliding mean filtering module, a notch filtering module, a lifting wavelet decomposition module, a threshold calculation module, a threshold processing module, and a lifting wavelet reconstruction module. While maintaining a relatively small circuit size, it performs hierarchical noise reduction processing on ECG signals acquired by wearable ECG monitoring devices to achieve a high signal-to-noise ratio (SNR) ECG signal output. For the ECG signals acquired by the wearable ECG monitoring device, the circuit first performs sliding mean filtering to remove baseline drift noise caused by human respiratory movements; secondly, it uses a notch filtering module to suppress power frequency interference caused by wired and wireless connections in the surrounding electromagnetic environment; finally, it uses lifting wavelet decomposition and reconstruction, along with threshold noise reduction, to achieve wavelet noise reduction, suppressing electromyographic interference caused by the wearer's voluntary or unconscious movements, thereby outputting a high SNR ECG signal for physiological parameter extraction and ECG diagnosis. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a schematic diagram of the overall structure provided in an embodiment of the present invention;

[0035] Figure 2This is a schematic diagram of the moving average filtering module provided in an embodiment of the present invention;

[0036] Figure 3 This is a schematic diagram of the notch filter module provided in an embodiment of the present invention;

[0037] Figure 4 This is a schematic diagram of the wavelet noise reduction module provided in an embodiment of the present invention;

[0038] Figure 5 This is a schematic diagram of the lifting wavelet decomposition module provided in an embodiment of the present invention;

[0039] Figure 6 This is a schematic diagram of a single-layer lifting wavelet decomposition module provided in an embodiment of the present invention;

[0040] Figure 7 This is a schematic diagram of the threshold calculation module provided in an embodiment of the present invention;

[0041] Figure 8 This is a schematic diagram of the absolute value extraction unit provided in an embodiment of the present invention;

[0042] Figure 9 This is a schematic diagram of a timing alignment unit provided in an embodiment of the present invention;

[0043] Figure 10 This is a schematic diagram of the threshold multiplication operation module provided in an embodiment of the present invention;

[0044] Figure 11 This is a schematic diagram of the threshold processing module provided in an embodiment of the present invention;

[0045] Figure 12 This is a schematic diagram of the lifting wavelet reconstruction module provided in an embodiment of the present invention;

[0046] Figure 13 This is a schematic diagram of a single-layer lifting wavelet reconstruction unit provided in an embodiment of the present invention. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0048] In the embodiments of this application, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0049] The terms "first" and "second" used in the embodiments of this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a system, product, or device that includes a series of components or units is not limited to the listed components or units, but may optionally include unlisted components or units, or may optionally include other components or units inherent to such products or devices. In the description of this application, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0050] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0051] Wearable ECG monitoring devices can provide solutions for the long-term health management of CVD patients by collecting physiological data in real time, and have important clinical value. However, ECG signals are typical weak physiological signals and are easily interfered with by various noises during the acquisition process. Noise reduction processing is required beforehand to meet the needs of clinical disease diagnosis.

[0052] Therefore, embodiments of the present invention provide a cascaded anti-interference circuit suitable for electrocardiogram monitoring devices, such as... Figure 1 As shown, it includes:

[0053] The sliding mean filtering module is used to receive the electrocardiogram (ECG) signal and extract the low-frequency component of the ECG signal to obtain the ECG signal after baseline drift is suppressed.

[0054] The sliding mean filtering module is connected to the ECG sensor. The input of the ECG sensor module is the human body electrical signal. By capturing the human body electrical signal, the ECG signal is acquired, and the signal is converted from digital to analog and then transmitted to the cascaded anti-interference circuit for noise suppression. The input of the sliding mean filtering module is the ECG signal acquired and digitized by the ECG sensor. Since the original ECG signal is easily interfered with by low-frequency baseline drift noise, the sliding mean filtering module is used to extract the low-frequency components to obtain the baseline drift signal.

[0055] The notch filter module is used to receive the ECG signal processed by the sliding mean filter module, and determine the center frequency point and quality factor based on the frequency characteristic information of the power frequency interference, thereby eliminating the power frequency interference in the ECG signal.

[0056] Specifically, the input of the notch filter module is the ECG signal after passing through the sliding mean filter module and undergoing difference processing. At this time, the baseline drift of the ECG signal is fully suppressed. The notch filter module is used to filter out the power frequency interference coupled into the circuit by the electromagnetic environment, and further improve the signal-to-noise ratio of the ECG signal.

[0057] The lifting wavelet decomposition module receives the ECG signal processed by the notch filter module and decomposes the ECG signal into a first-level detail coefficient group, a second-level detail coefficient group, a third-level detail coefficient group, and a first-level approximation coefficient group through three-level lifting wavelet decomposition. The input of the lifting wavelet decomposition module is the ECG signal after notch filtering. The ECG signal is decomposed into three groups of detail coefficients and one group of approximation coefficients through three-level lifting wavelet decomposition for subsequent extraction and suppression of electromyographic interference.

[0058] The threshold calculation module is used to receive the second layer detail coefficient group and the third layer detail coefficient group, and perform median extraction and multiplication and division operations to obtain the threshold of the corresponding layer; specifically, the threshold calculation module extracts the median after performing bitonic sorting on the second layer detail coefficient group and the third layer detail coefficient group, and performs threshold calculation based on the median to obtain the second layer threshold Th2 and the third layer threshold Th3 and output them;

[0059] The threshold calculation module includes a bitonic sorting unit and a threshold calculation unit. The bitonic sorting unit uses a sorting algorithm to sort the sequence by size and extract the median. The threshold calculation unit calculates the threshold based on the median and the threshold calculation formula.

[0060] The threshold calculation unit is designed to include two multipliers and one register. After the upper and lower thresholds are calculated using the multipliers, the register is used for registering the output.

[0061] For each set of detailed coefficients, the threshold calculation module will output two different thresholds. The upper and lower thresholds can facilitate the threshold processing module to perform non-linear double threshold processing.

[0062] The threshold processing module is used to perform forced noise reduction on the first layer detail coefficient group and threshold noise reduction on the second layer detail coefficient group and the third layer detail coefficient group based on the threshold of the corresponding layer. The threshold processing module includes two comparators, two selectors, one absolute value quantizer, one squarer, one divider and four registers for storing the output. According to the relationship between the input value and the upper and lower thresholds, it performs three operations: zeroing, improving function calculation and direct output, to meet the needs of threshold processing.

[0063] The lifting wavelet reconstruction module is used to receive the first layer detail coefficient group, the second layer detail coefficient group, the third layer detail coefficient group and the first layer approximation coefficient group processed by the threshold processing module, and perform layer-by-layer lifting wavelet reconstruction to output the noise-reduced ECG reconstruction signal.

[0064] Specifically, each layer of the lifting wavelet reconstruction module includes 3 inverse prediction operations, 2 inverse update operations, and 1 inverse normalization operation, comprising 10 multipliers, 9 delay registers, and 5 adders. The multipliers are used to input the inverse prediction and inverse update values, the delay registers are used for feedback operations, and the adders are used for iterating the internal inverse prediction and inverse update values.

[0065] Each layer of the lifting wavelet reconstruction module includes multiple inverse prediction and inverse update operations and inverse normalization operations. After each operation, the output is stored in a register. The pipeline structure avoids excessively long combinational logic and improves circuit performance.

[0066] Based on the above embodiments, as a preferred implementation method, such as Figure 2 As shown, the moving average filtering module includes a shift register group, three two-input summers, a delay register, and a shifter. The shift register group has a length of 32 and a data bit width of 16 bits, requiring 32×16 registers to store ECG data under different positions and delay conditions. Two sets of two-input summers are used to sum the 32 data points, of which 31 data points can be reused to optimize circuit area and power consumption. The summed data is averaged through shifting. The moving average filtering circuit has a window width of 32 and includes 32 delay registers and one right shifter. The circuit is used to extract baseline drift and suppress it by subtracting it from the original signal.

[0067] The sliding mean filtering module also includes a mean updater and a difference finder. The mean updater is used to update the window sum corresponding to different points and can reuse repeated data calculated from the mean of two adjacent data points to optimize circuit area and power consumption. The difference finder is used to subtract the noisy signal from the baseline drift signal to suppress baseline drift noise. The input of the shift register group is connected to the output of the ECG sensor, the input of the mean updater is connected to the output of the shift register group, and the input of the difference finder is connected to the output of the mean updater.

[0068] Based on the above embodiments, as a preferred implementation, the notch filter module is a second-order infinite impulse response (IIR) filter, such as... Figure 3 As shown, a direct Type I architecture is used for circuit implementation. The circuit includes four delay registers, five multipliers, and four adders. This circuit filters out power frequency interference coupled into the circuit from the external electromagnetic environment, improving the signal-to-noise ratio of the ECG signal. The notch filter module has a center frequency of 50Hz, a quality factor of 50, and a 3dB stopband width of 1Hz. The notch filter module can achieve targeted noise suppression at the center frequency point with minimal impact on the effective signal components near the center frequency point, achieving good power frequency interference suppression. The input of the notch filter module is connected to the output of the moving average filter module.

[0069] In this embodiment, the lifting wavelet decomposition module, the threshold calculation module, the threshold processing module, and the lifting wavelet reconstruction module constitute a wavelet denoising system, such as... Figure 4 As shown, the process includes three-layer lifting wavelet decomposition, forced denoising, thresholding, and three-layer wavelet reconstruction. The detail coefficients obtained from the first-layer lifting wavelet decomposition are subjected to forced denoising, the detail coefficients from the second and third-layer lifting wavelet decompositions are subjected to thresholding, and the third-layer approximation coefficients and the processed three-layer detail coefficients are subjected to three-layer lifting wavelet reconstruction to obtain the wavelet-denoised signal.

[0070] Based on the above embodiments, as a preferred implementation, the lifting wavelet decomposition module includes a first-layer lifting wavelet decomposition unit, a second-layer lifting wavelet decomposition unit, and a third-layer lifting wavelet decomposition unit;

[0071] The approximate coefficient set obtained after the input signal passes through the first lifting wavelet decomposition unit is used as the input signal of the second lifting wavelet decomposition unit, and the approximate coefficient set of the second lifting wavelet decomposition unit is used as the input signal of the third lifting wavelet decomposition unit.

[0072] The lifting wavelet decomposition module consists of three layers of decomposition circuits. Each layer includes a clock division unit, a sequence parity splitting unit, and a prediction update operation unit. The clock division unit is responsible for dividing the input clock signal by different multiples to provide a suitable working clock for the sequence parity splitting unit and the prediction update operation unit. The sequence parity splitting unit divides the input signal into even sequence groups and odd sequence groups according to the clock pulse. The prediction update operation unit performs multiple prediction and update operations on the even and odd sequence groups to continuously approximate the detail coefficients and approximation coefficients, finally completing the lifting wavelet decomposition. The input end of the lifting wavelet decomposition module is connected to the output end of the notch filter module. The three layers of lifting wavelet decomposition are cascaded, and the approximation coefficient group of each layer of lifting wavelet decomposition serves as the input signal for the next layer of lifting wavelet decomposition.

[0073] Specifically, the lifting wavelet decomposition module adopts a three-layer lifting wavelet decomposition structure and uses the sym4 wavelet basis function for wavelet decomposition;

[0074] Each layer of the lifting wavelet decomposition circuit includes 3 prediction operations, 2 update operations, and 1 normalization operation, comprising 10 multipliers, 9 delay registers, and 5 adders. The multipliers are used to input the prediction update values, the delay registers are used for feedback operations, and the adders are used for iterating the internal prediction update values.

[0075] Each layer of the lifting wavelet decomposition circuit includes multiple prediction update operations and normalization operations. After each operation, the output is stored in a register. The pipelined structure avoids excessively long combinational logic and improves circuit performance.

[0076] Based on the above embodiments, as a preferred implementation method, such as Figure 6 As shown, the first-layer lifting wavelet decomposition unit, the second-layer lifting wavelet decomposition unit, and the third-layer lifting wavelet decomposition unit all include a clock frequency division subunit, a sequence parity splitting subunit, and a prediction update subunit;

[0077] The clock division subunit generates and distributes clocks for various parts of the system by dividing the master clock at different levels; it divides the input clock signal by different multiples to provide a suitable working clock for the sequence parity splitting subunit and the prediction update operation subunit.

[0078] The sequence parity splitting subunit splits the main sequence by recognizing clock pulses of different frequencies for prediction update operations; the input signal is divided into even sequence groups and odd sequence groups according to the clock pulses.

[0079] The prediction and update subunit approximates the approximation coefficient group and the detail coefficient group through multiple prediction and update operations; it performs multiple prediction and update operations on the odd and even sequence group to continuously approximate the detail coefficients and approximation coefficients, and finally completes the lifting wavelet decomposition.

[0080] The input of the lifting wavelet decomposition module is connected to the output of the notch filter module. After single-layer lifting wavelet decomposition, the original sequence is decomposed into a set of detail coefficients containing detail parts and a set of approximate coefficients containing the remaining parts.

[0081] Based on the above embodiments, as a preferred implementation method, such as Figure 7 As shown, the threshold calculation module includes a first absolute value extraction unit, a bitone network sorting median extraction unit, and a threshold multiplication operation unit;

[0082] The first absolute value extraction unit is responsible for converting the input signed number signal into an absolute value for median extraction. The bitone network sorting median extraction unit sorts the absolute value of the signal using a bitone network and extracts the median based on the sorting result for threshold multiplication calculation. The threshold multiplication operation unit is responsible for performing further multiplication operations on the extracted median to obtain specific upper and lower thresholds. The timing alignment unit is used to perform timing alignment on the original ECG signal after time-stamping and extraction with the thresholds after multiplication to prevent timing misalignment in the threshold processing module. The input end of the threshold calculation module is connected to the output end of the lifting wavelet decomposition module, and the input signal is the second and third layer detail coefficients of the lifting wavelet decomposition module.

[0083] The structure of the first absolute value extraction unit is as follows: Figure 8 As shown, it includes a discriminator, a bitwise inverter, a two-input adder, a two-to-one selector, and a register. It determines the sign of the data by judging the high-order bits of the input signal. For positive numbers with a sign bit of 0, it outputs directly. For negative numbers with a sign bit of 1, it performs a bitwise inversion and then adds 1. Finally, it selects and outputs the absolute value sequence of the input sequence.

[0084] The structure of the timing alignment unit is as follows Figure 9As shown, the system includes two dual-port RAMs, a 6-bit counter, a value discriminator, a 2-to-1 multiplexer, an inverter, and an enable register. Since the median extraction module has a delay of 64 clock cycles, to ensure the threshold calculation result is aligned with the corresponding processed data segment timing, the two dual-port RAMs are used for repeated storage and retrieval via ping-pong operations to achieve a 64-cycle delay. At any given time, one of the two dual-port RAMs is in write mode while the other is in read mode, ensuring uninterrupted data transmission. The counter, value discriminator, and inverter jointly generate read / write control signals for the dual-port RAMs, and the 2-to-1 multiplexer is responsible for selecting the outputs of the two RAMs.

[0085] The median extraction unit of the bitone network sorting includes a discriminator, a bitwise inverter, a two-input adder, a two-to-one selector, and a register. It determines the sign of the data by judging the high-order bits of the input signal. For positive numbers with a sign bit of 0, it outputs directly. For negative numbers with a sign bit of 1, it performs a bitwise inversion and adds 1. Finally, it selects and outputs the absolute value sequence of the input sequence.

[0086] The threshold multiplication operation unit, such as Figure 10 As shown, it includes two multipliers, two registers, four shifters, and two two-input summers; the two paths calculate the upper and lower thresholds of the second-level detail coefficient group and the third-level detail coefficient group, respectively. The multiplication coefficients c1 and c2 can be implemented by shifting and adding to optimize the circuit area and power consumption. For each path, the upper and lower thresholds are 1.5 times each.

[0087] Based on the above embodiments, as a preferred implementation method, such as Figure 11 As shown, the threshold processing module includes a second absolute value extraction unit, a threshold discrimination unit, a nonlinear operation unit, and an output selection unit;

[0088] The second absolute value extraction unit is used to extract the absolute value of the input signal;

[0089] The threshold discrimination unit is used to generate a selection signal sel based on the relative magnitude of the absolute value and the upper and lower thresholds. It generates three different selection signals for three cases: the absolute value is less than the lower threshold, the absolute value is greater than the upper threshold, and the absolute value is between the upper and lower thresholds. When the absolute value is greater than the upper threshold, the input signal is directly output. When the absolute value is less than the lower threshold, the output is set to zero. When the absolute value is between the upper and lower thresholds, a non-linear operation is used for the output.

[0090] The nonlinear operation unit includes a division operation subunit, a squaring operation subunit, and a sign bit concatenation operation subunit.

[0091] Based on the above embodiments, as a preferred implementation method, such as Figure 12 As shown in the figure, the lifting wavelet reconstruction module includes a cascaded first lifting wavelet reconstruction unit, a second lifting wavelet reconstruction unit, and a third lifting wavelet reconstruction unit;

[0092] The input signal of the first lifting wavelet reconstruction unit is the third-level detail coefficient group and the third-level approximation coefficient group after thresholding. The newly reconstructed second-level approximation coefficient group is connected to the second-level lifting wavelet reconstruction unit as the input signal. The newly reconstructed first-level approximation coefficient group with the thresholded second-level detail coefficient group is connected to the third-level lifting lower wavelet reconstruction unit as the input signal. The denoised ECG reconstruction signal is reconstructed with the first-level detail coefficient group after forced denoising.

[0093] Based on the above embodiments, as a preferred implementation method, such as Figure 13 As shown, the first lifting wavelet reconstruction unit, the second lifting wavelet reconstruction unit, and the third lifting wavelet reconstruction unit all include a clock division subunit, an inverse prediction and inverse update subunit, and an odd-even sequence merging subunit;

[0094] The clock division subunit is used for the generation and distribution of the global clock, and the inverse prediction and inverse update subunit is used to perform multiple inverse predictions and inverse updates on the input approximation coefficient group and detail coefficient group to make them approximate the odd and even sequences of the reconstructed sequence. The ECG reconstructed signal is obtained by merging the odd and even sequences through the odd and even sequence merging subunit.

[0095] The various embodiments of the present invention can be combined arbitrarily to achieve different technical effects.

[0096] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive).

[0097] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. This program can be stored in a computer-readable storage medium, and when executed, it can include the processes described in the above method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as ROM or random access memory (RAM), magnetic disks, or optical disks.

[0098] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A cascaded anti-interference circuit suitable for electrocardiogram (ECG) monitoring equipment, characterized in that, include: The sliding mean filtering module is used to receive the electrocardiogram (ECG) signal and extract the low-frequency component of the ECG signal to obtain the ECG signal after baseline drift is suppressed. The notch filter module is used to receive the ECG signal processed by the sliding mean filter module, and determine the center frequency point and quality factor based on the frequency characteristic information of the power frequency interference, thereby eliminating the power frequency interference in the ECG signal. The lifting wavelet decomposition module is used to receive the ECG signal processed by the notch filter module, and decompose the ECG signal into a first layer of detail coefficients, a second layer of detail coefficients, a third layer of detail coefficients, and a first layer of approximation coefficients through three layers of lifting wavelet decomposition. The threshold calculation module is used to receive the second layer detail coefficient group and the third layer detail coefficient group, and perform median extraction and multiplication and division operations to obtain the threshold of the corresponding layer. The threshold processing module is used to perform forced noise reduction processing on the first layer detail coefficient group, and to perform threshold noise reduction processing on the second layer detail coefficient group and the third layer detail coefficient group based on the threshold of the corresponding layer. The lifting wavelet reconstruction module is used to receive the first layer detail coefficient group, the second layer detail coefficient group, the third layer detail coefficient group and the first layer approximation coefficient group processed by the threshold processing module, and perform layer-by-layer lifting wavelet reconstruction to output the noise-reduced ECG reconstruction signal.

2. The cascaded anti-interference circuit for ECG monitoring equipment according to claim 1, characterized in that, The sliding mean filtering module includes a shift register group, three two-input summers, a delay register, and a shifter; the window length of the shift register group is 32, which is used for data shifting and storage, and two sets of two-input summers are used to sum 32 data points, of which 31 data points can be reused.

3. The cascaded anti-interference circuit for ECG monitoring equipment according to claim 1, characterized in that, The notch filter module is a second-order infinite impulse response (IIR) filter.

4. The cascaded anti-interference circuit for ECG monitoring equipment according to claim 1, characterized in that, The lifting wavelet decomposition module includes a first-layer lifting wavelet decomposition unit, a second-layer lifting wavelet decomposition unit, and a third-layer lifting wavelet decomposition unit; The approximate coefficient set obtained after the input signal passes through the first lifting wavelet decomposition unit is used as the input signal of the second lifting wavelet decomposition unit, and the approximate coefficient set of the second lifting wavelet decomposition unit is used as the input signal of the third lifting wavelet decomposition unit.

5. The cascaded anti-interference circuit for ECG monitoring equipment according to claim 4, characterized in that, The first-layer lifting wavelet decomposition unit, the second-layer lifting wavelet decomposition unit, and the third-layer lifting wavelet decomposition unit all include a clock frequency division subunit, a sequence parity splitting subunit, and a prediction update subunit. The clock division subunit generates and distributes the clocks for each part of the system by dividing the master clock at different levels. The sequence parity splitting subunit splits the main sequence by recognizing clock pulses of different frequencies for prediction update operations; The prediction update subunit approximates the approximate coefficient set and the detailed coefficient set through multiple prediction and update operations; After single-level lifting wavelet decomposition, the original sequence is decomposed into a set of detail coefficients containing the detail parts and a set of approximate coefficients containing the remaining parts.

6. The cascaded anti-interference circuit for ECG monitoring equipment according to claim 1, characterized in that, The threshold calculation module includes a first absolute value extraction unit, a bitone network sorting median extraction unit, and a threshold multiplication operation unit; The first absolute value extraction unit performs absolute value conversion on the input 16-bit signed number format signal, sorts the resulting absolute value sequence using a bitonic network, extracts the median based on the sorting position for threshold calculation, uses the extracted median for threshold multiplication calculation, and obtains the upper and lower thresholds for threshold processing from the results of the threshold multiplication calculation, which are then output to the threshold processing module. The median extraction unit of the bitone network sorting includes a discriminator, a bitwise inverter, a two-input adder, a two-to-one selector, and a register. It determines the sign of the data by judging the high-order bits of the input signal. For positive numbers with a sign bit of 0, it outputs directly. For negative numbers with a sign bit of 1, it performs a bitwise inversion and adds 1. Finally, it selects and outputs the absolute value sequence of the input sequence. The threshold multiplication unit includes two multipliers, two registers, four shifters, and two two-input summers; the two paths respectively calculate the upper and lower thresholds of the second-level detail coefficient group and the third-level detail coefficient group.

7. The cascaded anti-interference circuit for ECG monitoring equipment according to claim 4, characterized in that, The threshold processing unit includes a second absolute value extraction unit, a threshold discrimination unit, a nonlinear operation unit, and an output selection unit; The second absolute value extraction unit is used to extract the absolute value of the input signal; The threshold discrimination unit is used to generate a selection signal sel based on the relative magnitude of the absolute value and the upper and lower thresholds. It generates three different selection signals for three cases: the absolute value is less than the lower threshold, the absolute value is greater than the upper threshold, and the absolute value is between the upper and lower thresholds. When the absolute value is greater than the upper threshold, the input signal is directly output. When the absolute value is less than the lower threshold, the output is set to zero. When the absolute value is between the upper and lower thresholds, a non-linear operation is used for the output. The nonlinear operation unit includes a division operation subunit, a squaring operation subunit, and a sign bit concatenation operation subunit.

8. The cascaded anti-interference circuit for ECG monitoring equipment according to claim 5, characterized in that, The lifting wavelet reconstruction module includes a cascaded first lifting wavelet reconstruction unit, a second lifting wavelet reconstruction unit, and a third lifting wavelet reconstruction unit. The input signal of the first lifting wavelet reconstruction unit is the third-level detail coefficient group and the third-level approximation coefficient group after thresholding. The newly reconstructed second-level approximation coefficient group is connected to the second-level lifting wavelet reconstruction unit as the input signal. The newly reconstructed first-level approximation coefficient group with the thresholded second-level detail coefficient group is connected to the third-level lifting lower wavelet reconstruction unit as the input signal. The denoised ECG reconstruction signal is reconstructed with the first-level detail coefficient group after forced denoising.

9. The cascaded anti-interference circuit for electrocardiogram monitoring equipment according to claim 8, characterized in that, The first lifting wavelet reconstruction unit, the second lifting wavelet reconstruction unit, and the third lifting wavelet reconstruction unit all include a clock frequency division subunit, an inverse prediction and inverse update subunit, and an odd-even sequence merging subunit. The clock division subunit is used for the generation and distribution of the global clock, and the inverse prediction and inverse update subunit is used to perform multiple inverse predictions and inverse updates on the input approximation coefficient group and detail coefficient group to make them approximate the odd and even sequences of the reconstructed sequence. The ECG reconstructed signal is obtained by merging the odd and even sequences through the odd and even sequence merging subunit.

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