Memory including bit line posts

Abstract

The invention relates to a memory including bit line posts. A memory may include: a plurality of word lines formed of N layers in which M word lines of the plurality of word lines are arranged, where N and M are both integers of 2 or more; a plurality of bit line columns; and a plurality of memory cells disposed at intersections between the plurality of word lines and the plurality of bit line posts, respectively. Among the plurality of word lines, two or more of the plurality of word lines may be grouped together and driven together.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2024-0021609, filed on February 15, 2024, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a memory, and more particularly, to a memory including a three-dimensional memory cell. Background Art

[0004] Recently, in order to cope with capacity increase and miniaturization of memories, technology for realizing a three-dimensional (3D) memory in which a plurality of memory cells are stacked has been studied. Summary of the Invention

[0005] In an embodiment of the present disclosure, a memory may include: a plurality of word lines, the plurality of word lines being formed by N layers, M word lines of the plurality of word lines being arranged in each layer, wherein N and M are both integers of 2 or greater; a plurality of bit line pillars; and a plurality of memory cells, respectively arranged at intersections between the plurality of word lines and the plurality of bit line pillars, wherein two or more word lines of the plurality of word lines may be grouped together and driven together.

[0006] In an embodiment of the present disclosure, a memory may include: a plurality of word lines; a plurality of bit lines; and a plurality of memory cells connected to one of the plurality of word lines and one of the plurality of bit lines, wherein two or more of the plurality of word lines may be grouped together and driven together. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 and Figure 2 is a diagram illustrating a structure of a word line in a cell array of a memory according to an embodiment of the present disclosure.

[0008] Figure 3 It is shown for Figure 1 and Figure 2 FIG. 1 is a diagram of the bit lines in FIG. 1 and FIG. 2 , which illustrate the electrical connections between the bit line pillars.

[0009] Figure 4 yes Figures 1 to 3 A side view of the cell array is shown.

[0010] Figure 5 It shows Figures 1 to 4 A circuit diagram showing the electrical connections between the word lines, bit line pillars, and memory cells of the Nth layer in a cell array.

[0011] Figure 6 FIG. 4 is a diagram illustrating a structure of a word line in a cell array of a memory according to another embodiment of the present disclosure.

[0012] Figure 7 It is shown for Figure 6 FIG. 1 is a diagram of the bit lines in FIG. 1 and FIG. 2 , which illustrate the electrical connections between the bit line pillars.

[0013] Figure 8 yes Figure 6 and Figure 7 A side view of the cell array is shown.

[0014] Figure 9 It shows Figures 6 to 8 A circuit diagram showing the electrical connections between the word lines, bit line pillars, and memory cells of the Nth layer in a cell array is shown. DETAILED DESCRIPTION

[0015] Various embodiments of the present disclosure are directed to providing a higher-integration memory with a reduced area.

[0016] The embodiments of the present disclosure can reduce the area of a memory and further integrate the memory.

[0017] Hereinafter, embodiments according to the technical spirit of the present disclosure will be described with reference to the accompanying drawings.

[0018] Figure 1 and Figure 2 1 is a diagram illustrating a structure of word lines in a cell array 100 of a memory according to an embodiment of the present disclosure. The cell array 100 may be formed of N layers, where N is an integer of 2 or greater, and may include M word lines WL arranged in each layer, where M is an integer of 2 or greater and is 12 here. Figure 1 can be a plan view showing the Nth layer, and Figure 2 It can be a plan view showing the third floor. Figure 1 and Figure 2 , the first direction “I” may be perpendicular to the second direction “II”.

[0019] Reference Figure 1 , the cell array 100 may include word lines WL0_N to WL11_N and bit line pillars BLP0 to BLP35. The bit line pillars BLP0 to BLP35 may refer to pillar-shaped bit lines. The bit line pillars BLP0 to BLP35 may be arranged to pass between two word lines in each word line layer and intersect the two word lines. For example, the bit line pillars BLP0 to BLP5 may pass between the word lines WL0_3 and WL1_3 in the third layer ( Figure 2 ) and between the word lines WL0_N and WL1_N in the Nth layer ( Figure 1 ).

[0020] Memory cells (not shown) may be respectively arranged at the intersections between word lines WL and bit line pillars BLP. Since the bit line pillars BLP intersect two word lines WL for each word line layer, the cell array 100 may include [the number of bit line pillars] × [the number of word line layers] × 2 memory cells. For example, a memory cell may be arranged at the intersection between the bit line pillar BLP0 of the first layer and the word line WL0_1, and a memory cell may be arranged at the intersection between the bit line pillar BLP0 of the first layer and the word line WL1_1. Similarly, memory cells may be respectively arranged at the intersections between the bit line pillars BLP0 of the second layer to the Nth layer and the word lines WL0_2 to WL0_N and WL1_2 to WL1_N.

[0021] Two or more word lines per layer can be grouped together and driven together. Figure 1 and Figure 2 In FIG, two word lines connected by arrows can be shorted to each other and driven together. That is, word lines WL0 and WL2 can be shorted to each other and driven together, word lines WL1 and WL3 can be shorted to each other and driven together, word lines WL4 and WL6 can be shorted to each other and driven together, word lines WL5 and WL7 can be shorted to each other and driven together, word lines WL8 and WL10 can be shorted to each other and driven together, and word lines WL9 and WL11 can be shorted to each other and driven together. This is not only for Figure 1 The word lines WL0_N to WL11_N of the Nth layer are shown Figure 2 The word lines WL0_3 to WL11_3 of the third layer shown may be the same, and may also be the same for word lines of all layers.

[0022] Figure 1 The word lines WL0_N to WL11_N of the Nth layer are shown, and Figure 2 The word lines WL0_3 to WL11_3 of the third layer are shown. The word lines of the remaining layers may also have the same Figure 1 and Figure 2 The same structure as in .

[0023] Figure 3 It is shown for Figure 1 and Figure 2 FIG. 1 is a diagram of the bit lines BL0 to BL11 that are electrically connected between the bit line pillars BLP0 to BLP35 . Figure 3 Also shown are bit line sense amplifier arrays 310 and 320 surrounding the cell array 100 .

[0024] The bit lines BL0 to BL11 may be disposed under the word lines WL0_1 to WL11_1 of the first layer. The bit lines BL0 to BL11 may be lines for connecting the bit line pillars BLP0 to BLP35 and the bit line sense amplifier arrays 310 and 320.

[0025] Reference Figure 3 , bitline pillars BLP0, BLP12, and BLP24 can be connected to bitline BL0. Therefore, bitline pillars BLP0, BLP12, and BLP24 can be electrically the same bitline. Bitline pillars BLP6, BLP18, and BLP30 can be connected to bitline BL1. Therefore, bitline pillars BLP6, BLP18, and BLP30 can be electrically the same bitline. Similarly, because bitline pillars BLP1, BLP13, and BLP25 are connected to bitline BL2, bitline pillars BLP1, BLP13, and BLP25 can be the same bitline, and because bitline pillars BLP7, BLP19, and BLP31 are connected to bitline BL3, bitline pillars BLP7, BLP19, and BLP31 can be the same bitline.

[0026] That is to say, in Figure 3 In FIG. 1 , bit line pillars BLPX, BLPX+12, and BLPX+24 (where X is an integer between 0 and 11) may be electrically connected to the same bit line.

[0027] Half of the bit lines BL0 to BL11, for example, the even-numbered bit lines BL0, BL2, BL4, BL6, BL8, and BL10, can be connected to the bit line sense amplifier array 310, while the other half (for example, the odd-numbered bit lines BL1, BL3, BL5, BL7, BL9, and BL11) can be connected to the bit line sense amplifier array 320. The bit line sense amplifier arrays 310 and 320 can sense and amplify data transmitted to the connected bit lines. Each of the bit line sense amplifier arrays 310 and 320 may include a plurality of bit line sense amplifiers.

[0028] Figure 4 yes Figures 1 to 3 The side view of the cell array 100 is shown. Figure 4 The third direction "III" can be Figures 1 to 3 The first direction "I" and the second direction "II" are directions orthogonal to the plane defined by the plane.

[0029] Reference Figure 4 , it can be seen that each of the bit line pillars BLP0, BLP6, BLP12, BLP18, BLP24, and BLP30 intersects two word lines in each layer from the first layer to the Nth layer. For example, it can be seen that the bit line pillar BLP0 intersects the word lines WL0_1 to WL0_N and WL1_1 to WL1_N in the first layer to the Nth layer. In other words, each of the bit line pillars BLP0, BLP6, BLP12, BLP18, BLP24, and BLP30 can intersect 2×N word lines.

[0030] Under the word lines WL0_1 to WL11_1 of the first layer, a bit line BL0 may be provided to electrically connect some of the bit line pillars BLP0, BLP6, BLP12, BLP18, BLP24, and BLP30 (BLP0, BLP12, and BLP24, see Figure 3 ).

[0031] Figure 5 It shows Figures 1 to 4 FIG. 1 is a circuit diagram showing electrical connections between word lines WL0_N to WL11_N, bit line pillars BLP0 to BLP35 , and memory cells MC0_N to MC71_N of the Nth layer in the cell array 100 .

[0032] Memory cells MC0_N to MC71_N may be disposed at intersections between bitline pillars BLP0 to BLP35 and wordlines WL0_N to WL11_N, respectively. Because each bitline pillar BLP0 to BLP35 intersects two wordlines, the number of memory cells MC0_N to MC71_N in the Nth layer may be twice the number of bitline pillars BLP0 to BLP35. Each memory cell MC0_N to MC71_N may include a capacitor for storing data and a transistor for transmitting the data stored in the capacitor to the bitline pillar under control of a wordline.

[0033] The following describes the operation when word lines WL0_N and WL2_N, which are shorted to each other, are activated simultaneously. When word line WL0 is activated, the transistors of memory cells MC0_N to MC5_N can be turned on, so that the data stored in the capacitors of memory cells MC0_N to MC5_N can be transferred to bit line pillars BLP0 to BLP5. When word line WL2 is activated, the transistors of memory cells MC12_N to MC17_N are turned on, so that the data stored in the capacitors of memory cells MC12_N to MC17_N can be transferred to bit line pillars BLP6 to BLP11. The data of bit line pillars BLP0 to BLP5 can be transferred to bit line sense amplifier array 310 through bit lines BL0, BL2, BL4, BL6, BL8, and BL10 and sensed and amplified, and the data of bit line pillars BLP6 to BLP11 can be transferred to bit line sense amplifier array 320 through bit lines BL1, BL3, BL5, BL7, BL9, and BL11 and sensed and amplified. That is, even if the two word lines WL0_N and WL2_N are activated at the same time, data of the memory cells MC0_N to MC5_N and MC12_N to MC17_N may be transferred to bit lines BL0 to BL11 different from each other and sensed and amplified.

[0034] Similarly, when word lines WL1_N and WL3_N are simultaneously activated, data of memory cells MC6_N to MC11_N corresponding to word line WL1_N can be transmitted to the bit line sense amplifier array 310 through bit line pillars BLP0 to BLP5 and bit lines BL0, BL2, BL4, BL6, BL8, and BL10, and be sensed and amplified. Data of memory cells MC18_N to MC23_N corresponding to word line WL3_N can be transmitted to the bit line sense amplifier array 320 through bit line pillars BLP6 to BLP11 and bit lines BL1, BL3, BL5, BL7, BL9, and BL11, and be sensed and amplified.

[0035] exist Figures 1 to 5 In the cell array 100 shown, because the word lines WL are short-circuited in pairs, the word lines WL can be formed into a pair and driven simultaneously. With this structure, the number of word lines WL that need to be driven can be reduced by half, which means that the area of the word line driver circuit (not shown) can be reduced by half. Since the word line driver circuit occupies a large area in the memory, when the area of the word line driver circuit is reduced by half, the area of the memory can be reduced, and a higher-integrated memory can be manufactured.

[0036] Figure 6 6 is a diagram illustrating a structure of word lines in a cell array 600 of a memory according to another embodiment of the present invention. The cell array 600 may be formed of N layers and include M word lines WL arranged in each layer. Figure 6 It can be a plan view showing the Nth layer. Figure 6 , the first direction “I” may be perpendicular to the second direction “II”.

[0037] Reference Figure 6 ,and Figure 1 Similarly, the cell array 600 may include word lines WL0_N to WL11_N and bit line pillars BLP0 to BLP35. The bit line pillars BLP0 to BLP35 may refer to pillar-shaped bit lines. The bit line pillars BLP0 to BLP35 may be arranged to pass between two word lines in each word line layer and intersect the two word lines. For example, the bit line pillars BLP0 to BLP5 may pass between the word lines WL0_N and WL1_N in the Nth layer ( Figure 1 ).

[0038] The word lines of each layer can be grouped into three and driven simultaneously. Figure 6, word lines connected by arrows may be shorted to each other and driven together. Word lines WL0_N, WL2_N, and WL4_N may be shorted to each other and driven together, word lines WL1_N, WL3_N, and WL5_N may be shorted to each other and driven together, word lines WL6_N, WL8_N, and WL10_N may be shorted to each other and driven together, and word lines WL7_N, WL9_N, and WL11_N may be shorted to each other and driven together.

[0039] Figure 6 The word lines WL0_N to WL11_N of the Nth layer are shown, and the word lines of the remaining layers may also have the same Figure 6 The same structure as in .

[0040] Figure 7 It is shown for Figure 6 FIG. 1 is a diagram of the bit lines BL0 to BL17 showing electrical connections between the bit line pillars BLP0 to BLP35 . Figure 7 Also shown are bit line sense amplifier arrays 710 and 720 surrounding the cell array 600 .

[0041] The bit lines BL0 to BL17 may be disposed under the word lines WL0_1 to WL11_1 of the first layer. The bit lines BL0 to BL17 may be lines for connecting the bit line pillars BLP0 to BLP35 and the bit line sense amplifier arrays 710 and 720.

[0042] Reference Figure 7 , bitline pillars BLP0 and BLP18 can be connected to bitline BL0. Therefore, bitline pillars BLP0 and BLP18 can be electrically the same bitline. Bitline pillars BLP6 and BLP24 can be connected to bitline BL1. Therefore, bitline pillars BLP6 and BLP24 can be electrically the same bitline. Similarly, because bitline pillars BLP12 and BLP30 are connected to bitline BL2, bitline pillars BLP12 and BLP30 can be the same bitline.

[0043] That is to say, in Figure 7 In the embodiment, bit line pillars BLPK and BLPK+18 (where K is an integer between 0 and 17) may be the same bit line that is electrically connected.

[0044] Half of the bit lines BL0 to BL17, for example, the even-numbered bit lines BL0, BL2, BL4, BL6, BL8, BL10, BL12, BL14, and BL16, can be connected to the bit line sense amplifier array 710, while the other half (for example, the odd-numbered bit lines BL1, BL3, BL5, BL7, BL9, BL11, BL13, BL15, and BL17) can be connected to the bit line sense amplifier array 720. The bit line sense amplifier arrays 710 and 720 can sense and amplify data transmitted to the connected bit lines. Each of the bit line sense amplifier arrays 710 and 720 may include a plurality of bit line sense amplifiers.

[0045] Figure 8 yes Figure 6 and Figure 7 A side view of the cell array 600 is shown in FIG. Figure 8 The third direction "III" can be Figure 6 and Figure 8 The first direction "I" and the second direction "II" are directions orthogonal to the plane defined by the plane.

[0046] Reference Figure 8 , it can be seen that each of the bit line pillars BLP0, BLP6, BLP12, BLP18, BLP24, and BLP30 intersects two word lines in each layer from the first layer to the Nth layer. For example, it can be seen that the bit line pillar BLP0 intersects the word lines WL0_1 to WL0_N and WL1_1 to WL1_N in the first layer to the Nth layer. In other words, each of the bit line pillars BLP0, BLP6, BLP12, BLP18, BLP24, and BLP30 can intersect 2×N word lines.

[0047] Under the word lines WL0_1 to WL11_1 of the first layer, a bit line BL0 may be provided to electrically connect some of the bit line pillars BLP0, BLP6, BLP12, BLP18, BLP24, and BLP30 (BLP0 and BLP18, see Figure 7 ).

[0048] Figure 9 It shows Figures 6 to 8 0_N to WL11_N, bit line pillars BLP0 to BLP35, and memory cells MC0_N to MC71_N in the Nth layer of the cell array 600 shown in FIG.

[0049] Memory cells MC0_N to MC71_N may be disposed at intersections between bitline pillars BLP0 to BLP35 and wordlines WL0_N to WL11_N, respectively. Because each bitline pillar BLP0 to BLP35 intersects two wordlines, the number of memory cells MC0_N to MC71_N in the Nth layer may be twice the number of bitline pillars BLP0 to BLP35. Each memory cell MC0_N to MC71_N may include a capacitor for storing data and a transistor for transmitting the data stored in the capacitor to the bitline pillar under control of a wordline.

[0050] The following describes the operation when the word lines WL0_N, WL2_N, and WL4_N, which are short-circuited to each other, are activated simultaneously. When word line WL0_N is activated, the transistors of memory cells MC0_N to MC5_N can be turned on, so that the data stored in the capacitors of memory cells MC0_N to MC5_N can be transferred to bit line pillars BLP0 to BLP5. When word line WL2_N is activated, the transistors of memory cells MC12_N to MC17_N are turned on, so that the data stored in the capacitors of memory cells MC12_N to MC17_N can be transferred to bit line pillars BLP6 to BLP11. When word line WL4_N is activated, the transistors of memory cells MC24_N to MC29_N are turned on, so that the data stored in the capacitors of memory cells MC24_N to MC29_N can be transferred to bit line pillars BLP12 to BLP17. The data of bit line pillars BLP0 to BLP5 can be transmitted to bit lines BL0, BL3, BL6, BL9, BL12, and BL15, the data of bit line pillars BLP6 to BLP11 can be transmitted to bit lines BL1, BL4, BL7, BL10, BL13, and BL16, and the data of bit line pillars BLP12 to BLP17 can be transmitted to bit lines BL2, BL5, BL8, BL11, BL14, and BL17. The data of bit lines BL0 to BL17 can be sensed and amplified by bit line sense amplifier arrays 710 and 720.

[0051] Even when word lines WL1_N, WL3_N, and WL5_N are activated simultaneously, even when word lines WL6_N, WL8_N, and WL10_N are activated simultaneously, and even when word lines WL7_N, WL9_N, and WL11_N are activated simultaneously, the data of 18 memory cells can be transmitted to the bit line sense amplifier arrays 710 and 720 through the 18 bit line pillars and 18 bit lines, and be sensed and amplified as described above.

[0052] exist Figures 6 to 9In the cell array 600 shown, because three word lines WL are shorted, the word lines WL can be driven simultaneously in groups of three. With this structure, the number of word lines WL to be driven can be reduced by 1 / 3, which means that the area of the word line driver circuit can be greatly reduced.

[0053] Although the embodiments according to the technical ideas of the present disclosure have been described above with reference to the accompanying drawings, this is only for describing the embodiments according to the concept of the present disclosure, and the present disclosure is not limited to the above embodiments. Without departing from the technical ideas of the present disclosure defined in the appended claims, those skilled in the art to which the present disclosure belongs may make various types of replacements, modifications, and changes to the embodiments, and it should be interpreted that these replacements, modifications, and changes all fall within the scope of the present disclosure. In addition, these embodiments can be combined to form additional embodiments.

Claims

1. A memory comprising: a plurality of word lines, the plurality of word lines being formed of N layers, M word lines of the plurality of word lines being arranged in each layer, wherein N and M are both integers of 2 or greater; a plurality of bitline pillars; as well as a plurality of memory cells, each of which is disposed at an intersection between the plurality of word lines and the plurality of bit line pillars; Two or more word lines among the plurality of word lines are grouped together and driven together.

2. The memory according to claim 1, wherein Among the plurality of word lines, grouped word lines are included in the same layer.

3. The memory according to claim 2, wherein The plurality of bit line pillars are electrically connected to each other and form a group in units of L, where L is an integer of 2 or greater.

4. The memory according to claim 3, wherein Among the bit line pillars, bit line pillars intersecting the group of word lines are not electrically connected to each other.

5. The memory according to claim 1, wherein Each of the plurality of memory cells includes a transistor and a capacitor. The memory according to claim 1 , wherein: A first half of the plurality of bit line pillars is connected to a first bit line sense amplifier, which is arranged on a first side in a direction perpendicular to the plurality of bit line pillars; and a second half of the plurality of bit line pillars is connected to a second bit line sense amplifier, which is arranged on a second side in the direction perpendicular to the plurality of bit line pillars.

7. The memory according to claim 1, wherein Groups of the plurality of word lines are shorted to each other.

8. The memory according to claim 1, wherein Each of the plurality of bit line pillars is disposed to pass between two word lines in each of the N layers.

9. A memory comprising: multiple word lines; a plurality of bit lines; as well as a plurality of memory cells connected to one of the plurality of word lines and one of the plurality of bit lines, Two or more word lines among the plurality of word lines are grouped together and driven together.

10. The memory according to claim 9, wherein The word lines of the group include a first word line and a second word line, and Among the plurality of bit lines, a first bit line connected to a memory cell connected to the first word line and a second bit line connected to a memory cell connected to the second word line do not overlap with each other.

11. The memory according to claim 9, wherein Each of the plurality of memory cells includes a transistor and a capacitor.

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