Split gate type flash memory and programming method

Abstract

The invention discloses a split-gate flash memory and a programming method.According to the programming method, the number of electrons bound by traps in an oxide material layer of a storage unit can be reduced by conducting programming operation on the storage unit, conducting first programming verification operation on the storage unit and conducting defect removing operation on the storage unit; therefore, the escape number of electrons bound by traps in the oxide material layer after programming operation is reduced, the drop amplitude of the threshold voltage of the programmed memory cell is further reduced, and the problem that programming is not in place due to drop of the threshold voltage of the programmed memory cell can be improved; and performing a second programming verification operation on the memory cell to at least check the effect of the defect removal operation.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a split-gate flash memory and a programming method. Background Art

[0002] Flash memory (Flash) has the advantages of high density, low price, and electrically programmable and erasable properties, making it widely used in non-volatile memory devices. Floating gate Flash memory has a stacked gate structure consisting of a floating gate (FG) and a control gate, which is coupled to control the storage and release of electrons in the floating gate. Currently, NAND Flash and NOR Flash are widely used. NAND Flash's structure offers extremely high cell storage density and fast write and erase speeds, but it can only store data and cannot address and run programs directly. NOR Flash's structure offers faster read speeds, and running code on NOR Flash does not require any software support, so fewer drivers are required, but the storage density is lower.

[0003] Split gate flash memory is a new flash memory structure that includes two split gates. Each split gate consists of a control gate and a floating gate. The two split gates are separated by a word line (WL). It has the advantages of higher reliability, faster programming and erasing speeds, and can also run programs directly in Flash.

[0004] However, after the split-gate flash memory undergoes one or more erase and program cycles, the threshold voltage of the storage cell in the split-gate flash memory will decrease, resulting in the problem of incomplete programming. Summary of the Invention

[0005] The present application provides a split-gate flash memory and a programming method to alleviate the technical problem of incomplete programming caused by a drop in the threshold voltage of a memory cell after programming.

[0006] In a first aspect, the present application provides a programming method for a split-gate flash memory, wherein the split-gate flash memory includes a storage cell, each storage cell includes a substrate, a floating gate material layer, and an oxide material layer located between the substrate and the floating gate material layer, the programming method including: performing a programming operation on the storage cell; performing a first programming verification operation on the storage cell; performing a defect removal operation on the storage cell; and performing a second programming verification operation on the storage cell.

[0007] In a second aspect, the present application provides a split-gate flash memory that executes the above-mentioned programming method.

[0008] In some embodiments, the memory cell further includes a word line, a control gate, and a source-drain doping portion, and a defect removal operation is performed on the memory cell, including: controlling the bound carriers in the oxide material layer to flow out through at least one of the word line, the control gate, and the source-drain doping portion.

[0009] In some embodiments, controlling bound carriers in the oxide material layer to flow out through at least one of a word line, a control gate, and a source / drain doped portion includes applying a first forward voltage difference to the word line and the control gate.

[0010] In some embodiments, applying a first forward voltage difference to the word line and the control gate includes: applying a first word line voltage to the word line, the first word line voltage being greater than or equal to 0V; and applying a first control voltage to the control gate, the first control voltage being less than 0V.

[0011] In some embodiments, applying a first forward voltage difference to the word line and the control gate further includes: configuring the control gate to include a first control gate and a second control gate; setting the first word line voltage to be less than or equal to 3V; and applying a first control voltage to at least one of the first control gate and the second control gate, the first control voltage being greater than or equal to -8V and less than or equal to -3V.

[0012] In some embodiments, controlling bound carriers in the oxide material layer to flow out through at least one of a word line, a control gate, and a source / drain doped portion includes applying a second forward voltage difference to the substrate and the word line, the source / drain doped portion, and the control gate.

[0013] In some embodiments, applying a second forward voltage difference to the substrate and the word line, the source-drain doped portion, and the control gate includes: applying a first voltage to the word line, the source-drain doped portion, and the control gate, the first voltage being equal to 0V; and applying a first substrate voltage to the substrate, the first substrate voltage being greater than 0V.

[0014] In some embodiments, applying a first substrate voltage to the substrate, the first substrate voltage being greater than 0V, includes setting the first substrate voltage to be greater than or equal to 3V and less than or equal to 8V.

[0015] In some embodiments, controlling bound carriers in the oxide material layer to flow out through at least one of a word line, a control gate, and a source / drain doped portion includes applying a third forward voltage difference to the source / drain doped portion, the word line, and the control gate.

[0016] In some embodiments, applying a third forward voltage difference to the source and drain doped portions and the word line and control gate includes: applying a second voltage to the word line and the control gate, the second voltage being equal to 0V; applying a first line voltage to the source and drain doped portions, the first line voltage being greater than 0V.

[0017] In some embodiments, applying a first line voltage to the source-drain doping portion, the first line voltage being greater than 0V, includes: configuring the source-drain doping portion to include a first source-drain doping portion and a second source-drain doping portion; applying a first line voltage to at least one of the first source-drain doping portion and the second source-drain doping portion, the first line voltage being greater than or equal to 3V and less than or equal to 8V.

[0018] In some embodiments, a defect removal operation is performed on the memory cell after performing N programming operations, where N is an integer greater than or equal to 2.

[0019] In some embodiments, after performing a second programming verification operation on the memory cell, the process further includes: determining whether the threshold voltage of the memory cell is greater than or equal to the programming verification voltage of the second programming verification operation; if so, terminating the current programming operation; or, if not, proceeding to "performing a programming operation on the memory cell."

[0020] The split-gate flash memory and programming method provided in the present application can reduce the number of electrons trapped in the oxide material layer of the storage cell by performing a programming operation on the storage cell, performing a first programming verification operation on the storage cell, and performing a defect removal operation on the storage cell, thereby reducing the number of electrons trapped in the oxide material layer that escape after the programming operation, thereby reducing the decrease in the threshold voltage of the storage cell after programming, and can improve the problem of incomplete programming caused by the decrease in the threshold voltage of the storage cell after programming.

[0021] Furthermore, by performing a second programming verification operation on the memory cell, the number of trapped electrons in the oxide material layer of the memory cell can be measured. For example, if the threshold voltage is greater than or equal to the verification voltage of the second programming verification operation, it means that the number of trapped electrons in the oxide material layer is small, and the decrease in the threshold voltage after the programming operation will not cause the problem of incomplete programming; if the threshold voltage is less than the verification voltage of the second programming verification operation, it means that the number of trapped electrons in the oxide material layer is large, and the decrease in the threshold voltage after the programming operation will cause the problem of incomplete programming. Therefore, it can be seen that the second programming verification operation can at least verify the effect of the defect removal operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0023] Figure 1 Schematic diagram of the model structure of split-gate flash memory in related technology.

[0024] Figure 2 for Figure 1 A simplified schematic diagram of split-gate flash memory is shown.

[0025] Figure 3 Schematic diagram of the principle of threshold voltage drop after programming of split-gate flash memory in related art.

[0026] Figure 4 for Figure 3 Schematic diagram of the change of the threshold voltage of the storage cell of the split-gate flash memory.

[0027] Figure 5 for Figure 3 The diagram shows the programming principle of the split-gate flash memory.

[0028] Figure 6 For Figure 3 A schematic diagram illustrating the principle of programming a bit in a storage cell of a split-gate flash memory is shown.

[0029] Figure 7 For Figure 3 A schematic diagram showing the principle of programming another bit in a memory cell of a split-gate flash memory is shown.

[0030] Figure 8 For Figure 3 A schematic diagram illustrating the principle of reading a bit in a storage unit of a split-gate flash memory is shown.

[0031] Figure 9 For Figure 3 A schematic diagram showing the principle of reading another bit in a storage unit of a split-gate flash memory is shown.

[0032] Figure 10 For Figure 3 A schematic diagram showing the principle of erasing a storage unit of a split-gate flash memory is shown.

[0033] Figure 11 A flowchart of the programming method provided in an embodiment of the present application.

[0034] Figure 12 for Figure 11 Schematic diagram of the first principle of the programming method shown.

[0035] Figure 13 for Figure 11 Schematic diagram of the second principle of the programming method shown.

[0036] Figure 14 for Figure 11 Schematic diagram of the third principle of the programming method shown. DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0038] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of the indicated technical features. The features specified as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0039] In the related art, a split gate flash memory includes multiple storage cells, see Figures 1 to 3 、 Figure 12 、 Figure 13 as well as Figure 14 Each memory cell includes a substrate PSUB, a source-drain doped portion, a floating gate material layer, a dielectric layer 104, a control gate material layer, a word line WL, and an oxide material layer 103. The source-drain doped portion includes a first source-drain doped portion SD0 and a second source-drain doped portion SD1. The floating gate material layer is formed with a first floating gate FG0 and a second floating gate FG1. The control gate material layer is formed with a first control gate CG0 and a second control gate CG1.

[0040] The first floating gate FG0 and the first control gate CG0 form a first split gate, and the second floating gate FG1 and the second control gate CG1 form a second split gate. The first split gate and the second split gate are separated by a word line WL.

[0041] The first source / drain doped portion SD0 is located on the left side between the substrate PSUB and the oxide material layer 103, and the second source / drain doped portion SD1 is located on the right side between the substrate PSUB and the oxide material layer 103. The oxide material layer 103 is also located between any two of the substrate PSUB, the floating gate material layer, the dielectric layer 104, the control gate material layer, and the word line WL.

[0042] like Figure 2 As shown, the first source-drain doped portion SD0 is used to connect to the first bit line BL0 , and the second source-drain doped portion SD1 is used to connect to the second bit line BL1 .

[0043] The above-mentioned memory cell can enter the programming state and the erasing state by applying different voltages on the first control gate CG0 and the second control gate CG1. The programming state is achieved by using the hot carrier injection (HCI) effect, and the erasing state is achieved by using the tunneling (Fowler-Nordheim, FN) effect of the split gate and the side wall of the word line WL.

[0044] However, after one or more erase and program cycles, the number of traps in the oxide material layer 103 increases, which binds electrons (e) and affects the distribution of the threshold voltage. Figure 3 As shown, during programming, a voltage of 8-10V, for example, 8.5V, is applied to the first control gate CG0, a voltage of 0V is applied to the first source-drain doped part SD0, a voltage of 5.5V is applied to the second source-drain doped part SD1, and a voltage of 1.5V is applied to the word line WL. At this time, the electrons on the substrate PSUB tunnel into the floating gate, but some of the electrons are bound by traps in the oxide material layer 103, and the electrons bound in the traps are also counted into the floating gate. After the programming is completed, the electrons in the traps escape.

[0045] Among them, V WL Represents the word line voltage. V CG0 Represents the voltage of the first control gate CG0. V CG1 V represents the voltage of the second control gate CG1. SD0 V represents the voltage of the first source-drain doped part SD0. SD1 represents the voltage of the second source-drain doped part SD1.

[0046] This will reduce the threshold voltage of the memory cell, for example, Figure 4 As shown, the horizontal axis represents the threshold voltage (Vth), and the vertical axis represents the number of memory cells (Count). If the threshold voltage before the electrons in the trap escape is Vth0, the threshold voltage after the electrons in the trap escape is Vth1. Since Vth0 is greater than Vth1, this will lead to incomplete programming.

[0047] The programming principle of NORD Flash is as follows Figure 5 As shown, the programming voltage is Figure 6As shown, taking programming the first control gate CG0 of the memory cell to the left of the arrow as an example, applying 0V to the bit line BLU1 and 5.5V (Vppd) to the bit line BLD1 creates a strong electric field across the channel. Furthermore, applying 8-10V to the first control gate CG0, 4-6V to the second control gate CG1, and 1.5V to the word line WL, along with 0V to the first source / drain doped portion SD0 and 5.5V to the second source / drain doped portion SD1, creates an inversion layer in the channel. Electrons in the inversion layer drift in the strong electric field, gradually increasing their energy and becoming high-energy hot carriers. Electrons travel from the first source / drain doped portion SD0 through the channel beneath the second control gate CG1 and word line WL, ultimately arriving at the channel beneath the first control gate CG0. Because the voltage on the first control gate CG0 is higher, electrons in the channel tunnel into the first floating gate FG0, raising the threshold voltage.

[0048] Among them, Figure 6 As shown, the bit lines BLU0 , BLD0 , and BLU1 all have a program inhibit current (2 μA_inh) of 2 μA, and a program inhibit voltage (Vppd_inh) is applied to the bit line BLU2 .

[0049] Similarly, if Figure 7 As shown, programming can also be performed on the second control gate CG1 of the memory cell on the left side of the arrow. A voltage of 5.5V (Vppd) is applied to the bit line BLU1, and 0V is applied to the bit line BLD1. This creates a strong electric field across the channel. Furthermore, a voltage of 8-10V is applied to the second control gate CG1, a voltage of 4-6V is applied to the first control gate CG0, and a voltage of 1.5V is applied to the word line WL. Furthermore, a voltage of 5.5V is applied to the first source / drain doped portion SD0, and a voltage of 0V is applied to the second source / drain doped portion SD1. This causes an inversion layer to form in the channel. Electrons in the inversion layer drift in the strong electric field, gradually increasing their energy and becoming high-energy hot carriers. Electrons travel from the second source / drain doped portion SD1 through the channel under the first control gate CG0 and word line WL, ultimately arriving at the channel beneath the second control gate CG1. Because the voltage on the second control gate CG1 is higher, electrons in the channel tunnel into the second floating gate FG1, raising the threshold voltage.

[0050] Among them, Figure 7 As shown, the bit lines BLU0 and BLD0 are both applied with a program inhibit voltage (Vppd_inh), and the bit lines BLU1, BLU2, and BLD2 each have a program inhibit current (2μA_inh) of 2μA.

[0051] After programming, you can Figure 8The memory cell on the left side of the middle arrow performs a read operation. Taking the memory bit corresponding to the first control gate CG0 as an example, a voltage of 0V is applied to the first control gate CG0 and a voltage of 1V is applied to the word line WL (WL <0> ) applies a 4V voltage, a 5V voltage to the second control gate CG1, a 0.8V read voltage (0.8V_SA) to the bit line BLU1, and a 0V voltage to the bit line BLD1. Each bit line can be connected to a sense amplifier (SA), which reads the data in the corresponding memory cell through the corresponding bit line. After programming is completed, the programmed memory cell (cell) needs to be read to confirm whether the programming is successful. If the programming of the memory cell is correct, the current sensed by the sense amplifier is 30-40uA. If the current is too low, the programming operation needs to be repeated.

[0052] A read inhibit voltage (0.8V_inh) of 0.8V is applied to both the bit lines BLU0 and BLD0, and a voltage of 0V is applied to both the bit lines BLU2 and BLD2.

[0053] If necessary, you can Figure 9 The memory cell on the left side of the middle arrow performs a read operation. Taking the memory bit corresponding to the second control gate CG1 as an example, a voltage of 0V is applied to the second control gate CG1 and a voltage of 1V is applied to the word line WL (WL <0> ) applies a 4V voltage to the control gate, a 5V voltage to the first control gate CG0, a 0V voltage to the bit line BLU1, and a 0.8V read voltage (0.8V_SA) to the bit line BLD1. Each bit line can be connected to a sense amplifier (SA), which reads the data in the corresponding memory cell through the corresponding bit line. After programming is completed, the programmed memory cell (cell) needs to be read to confirm whether the programming is successful. If the programming of the memory cell is correct, the current sensed by the sense amplifier is 30-40uA. If the current is too low, the programming operation needs to be repeated.

[0054] A voltage of 0V is applied to both the bit lines BLU0 and BLD0 , and a read inhibit voltage (0.8V_inh) of 0.8V is applied to both the bit lines BLU2 and BLD2 .

[0055] The erasing principle of NORD Flash is as follows Figure 10 As shown, the first capacitor is the capacitor between the control gate and the floating gate, the second capacitor is the capacitor between the substrate PSUB and the floating gate, the third capacitor is the capacitor between the floating gate and the word line WL, and the fourth capacitor is the capacitor between the word line WL and the substrate PSUB.

[0056] If NORD is to be erased, a voltage of 8 to 10 V can be applied to the word line WL, and a voltage of -6 to -10 V can be applied to the first control gate CG0 and the second control gate CG1. The voltage difference between the word line WL and the first control gate CG0 and the second control gate CG1 will cause the electrons on the first floating gate FG0 and the second floating gate FG1 to tunnel to the word line WL and flow away, and the threshold voltage will drop.

[0057] Similarly, after erasing is completed, it is necessary to confirm whether the erased storage unit (cell) is successfully erased by a read operation, such as Figure 8 and Figure 9 As shown, a corresponding voltage is applied to the selected bit line BL and compared with the reference current. The current of the correctly erased cell is 0uA. If the current is too large, the erase operation needs to be performed again.

[0058] Among them, V PSUB The voltage applied to the substrate PSUB may be -5V. The voltage applied to the first floating gate FG0 and the second floating gate FG1 may be -5V.

[0059] In view of the aforementioned problem that the threshold voltage of the memory cell decreases after programming, resulting in incomplete programming, this embodiment provides a programming method for a split-gate flash memory, such as Figure 11 As shown, the programming method includes the following steps:

[0060] Perform programming operation on the memory cell.

[0061] A first program verify (PV) operation is performed on the memory cell.

[0062] Perform a detrap operation on the memory cell.

[0063] A second program verification operation is performed on the memory cells.

[0064] It can be understood that the programming method provided in this embodiment can reduce the number of electrons trapped in the oxide material layer 103 of the memory cell by performing a programming operation on the memory cell, performing a first programming verification operation on the memory cell, and performing a defect removal operation on the memory cell, thereby reducing the number of electrons trapped in the oxide material layer 103 that escape after the programming operation, thereby reducing the decrease in the threshold voltage of the memory cell after programming, and can improve the problem of incomplete programming caused by the decrease in the threshold voltage of the memory cell after programming.

[0065] Furthermore, by performing a second programming verification operation on the memory cell, the number of trapped electrons in the oxide material layer 103 of the memory cell can be measured. For example, if the threshold voltage is greater than or equal to the verification voltage of the second programming verification operation, it means that the number of trapped electrons in the oxide material layer 103 is small, and the decrease in the threshold voltage after the programming operation will not lead to the problem of incomplete programming; if the threshold voltage is less than the verification voltage of the second programming verification operation, it means that the number of trapped electrons in the oxide material layer 103 is large, and the decrease in the threshold voltage after the programming operation will lead to the problem of incomplete programming. Therefore, it can be seen that the second programming verification operation can at least verify the effect of the defect removal operation.

[0066] It should be noted that the programming method provided in this application can be applied to split-gate flash memories of various structures and is not limited to the structure provided in this application.

[0067] In one embodiment, performing a defect removal operation on the memory cell may include controlling the bound carriers in the oxide material layer 103 to flow out through at least one of the word line WL, the control gate, and the source / drain doping portion.

[0068] It should be noted that this can also reduce the number of electrons trapped in the oxide material layer 103 of the storage unit, thereby reducing the number of electrons trapped in the oxide material layer 103 that escape after the programming operation, thereby reducing the decrease in the threshold voltage of the storage unit after programming, and can improve the problem of incomplete programming caused by the decrease in the threshold voltage of the storage unit after programming.

[0069] In one embodiment, controlling the bound carriers in the oxide material layer 103 to flow out through at least one of the word line WL, the control gate, and the source / drain doped portion includes: applying a first forward voltage difference to the word line WL and the control gate.

[0070] It should be noted that a first forward voltage difference is applied to the word line WL and the control gate to form an electric field of corresponding strength on the sidewall between the word line WL and the control gate, causing electron tunneling, such as Figure 12 As shown, at least part of the electrons trapped in the oxide material layer 103 tunnel out from the word line WL, thereby reducing the number of electrons trapped in the oxide material layer 103 that escape after the programming operation, thereby reducing the decrease in the threshold voltage of the memory cell after programming, and can improve the problem of incomplete programming caused by the decrease in the threshold voltage of the memory cell after programming.

[0071] The first forward voltage difference may be a voltage difference between a first word line voltage applied to the word line WL and a first control voltage applied to the control gate, wherein the first word line voltage is greater than or equal to 0V and the first control voltage is less than 0V.

[0072] In one embodiment, the control gate includes a first control gate CG0 and a second control gate CG1. A first control voltage may be applied to at least one of the first control gate CG0 and the second control gate CG1. The first word line voltage is less than or equal to 3V. The first control voltage is greater than or equal to -8V and less than or equal to -3V.

[0073] For example, the voltage V applied to the word line WL WL The voltage V applied to the first control gate CG0 can be 1.5 V. CG0 The voltage V applied to the second control gate CG1 is -5 V. CG1 , the voltage V of the first source-drain doped part SD0 SD0 , and the voltage V of the second source-drain doped portion SD1 SD1 Both are 0V.

[0074] This is similar to a weak erase operation, which reduces the migration amount of the threshold voltage (Vth) after programming is completed. It is smaller than the normal erase voltage difference, and the electrons in the traps in the oxide material layer 103 can be tunneled out from the word line WL. The first control gate CG0 and the second control gate CG1 are the same, and both have just completed the programming operation and the first programming verification operation. The programming operation is performed on each sector (Sector), and Detrap follows the first programming verification operation, so the negative voltage applied to the first control gate CG0 can also be performed in units of sectors. Unlike the normal erase operation, the erase operation of the prior art erases all cells at the same time in order to pursue speed, and here a weak erase operation is performed on each sector.

[0075] Among them, for cells that have not been programmed, whether their threshold voltage changes or not is not considered, so there is no need to perform Detrap, which improves the efficiency of Detrap.

[0076] In one embodiment, controlling bound carriers in the oxide material layer 103 to flow out through at least one of the word line WL, the control gate, and the source / drain doping portion includes applying a second forward voltage difference to the substrate PSUB and the word line WL, the source / drain doping portion, and the control gate.

[0077] It should be noted that a second forward voltage difference is applied to the substrate PSUB and the word line WL, the source and drain doping parts and the control gate, such as Figure 13As shown, at least part of the electrons trapped in the oxide material layer 103 will be sucked out and enter the substrate PSUB, and then flow out through the bit line, thereby reducing the number of electrons trapped in the oxide material layer 103 that escape after the programming operation, thereby reducing the decrease in the threshold voltage of the memory cell after programming, and can improve the problem of incomplete programming caused by the decrease in the threshold voltage of the memory cell after programming.

[0078] The second forward voltage difference may be the difference between a first substrate voltage applied to the substrate PSUB and a first voltage applied to the word line WL, the source / drain doped portion, and the control gate.

[0079] In one embodiment, the first substrate voltage is greater than or equal to 3V and less than or equal to 8V.

[0080] For example, the voltage V applied to the word line WL WL The voltage V applied to the first control gate CG0 can be 0 V. CG0 is 0 V. The voltage V applied to the second control gate CG1 is CG1 , the voltage V of the first source-drain doped part SD0 SD0 , and the voltage V of the second source-drain doped portion SD1 SD1 The voltage V applied to the substrate PSUB is 0V. PSUB is 5V.

[0081] In one embodiment, controlling bound carriers in the oxide material layer 103 to flow out through at least one of the word line WL, the control gate, and the source / drain doping portion includes applying a third forward voltage difference to the source / drain doping portion, the word line WL, and the control gate.

[0082] It should be noted that a third forward voltage difference is applied to the source / drain doping portion, the word line WL, and the control gate, such as Figure 14 As shown, at least a portion of the electrons trapped in the oxide material layer 103 flow out directly through the bit line, thereby reducing the number of electrons trapped in the oxide material layer 103 that escape after the programming operation, thereby reducing the decrease in the threshold voltage of the memory cell after programming, and can improve the problem of incomplete programming caused by the decrease in the threshold voltage of the memory cell after programming.

[0083] The third forward voltage difference may be a difference between a first bit line voltage applied to the source / drain doped portion and a second voltage applied to the word line WL and the control gate, wherein the second voltage is equal to 0V and the first bit line voltage is greater than 0V.

[0084] The source-drain doped portion includes a first source-drain doped portion SD0 and a second source-drain doped portion SD1. A first line voltage may be applied to at least one of the first source-drain doped portion SD0 and the second source-drain doped portion SD1. The first line voltage is greater than or equal to 3V and less than or equal to 8V.

[0085] In one embodiment, Figure 11 As shown, after performing the second programming verification operation on the memory cell, it also includes: determining whether the threshold voltage of the memory cell is greater than or equal to the programming verification voltage of the second programming verification operation; if so, ending this programming operation; or, if not, going to "performing a programming operation on the memory cell".

[0086] It should be noted that in all the above embodiments, a detrap is performed after program and programverify in each sector. The threshold voltage of the corresponding memory cell after the detrap is then checked. If the threshold voltage drops below the program-verify voltage, programming is repeated. If it does not drop below the program-verify voltage, the process ends.

[0087] After program and program verify, detrap is performed. The threshold voltage will inevitably drop after detrap, and then a second programming verification operation is performed to verify whether the threshold voltage is greater than the programming verification voltage. If the threshold voltage is greater than the programming verification voltage, it means that there are not many electrons in the previous trap, and the threshold voltage does not drop much after detrap, and all operations are completed. If the threshold voltage is less than the programming verification voltage, it means that there are many electrons in the trap, and the threshold voltage drops below the programming verification voltage after detrap. It will fail after the second programming verification operation, and then return to the programming operation step. If the second programming verification operation after detrap finds that the threshold voltage is greater than the programming verification voltage, the detrap can be terminated.

[0088] In one embodiment, performing a defect removal operation on the memory cell further includes: performing a defect removal operation on the memory cell after performing N programming operations, where N is an integer greater than or equal to 2.

[0089] It should be noted that after multiple programming cycles (e.g., 1k cycles), the number of trapped electrons increases. Although the threshold voltage is temporarily greater than the program verify voltage after programming and program verification, a large number of electrons will escape after a period of time, causing the threshold voltage of a large number of cells to drop below the program verify voltage, resulting in insufficient programming and even stored data errors. However, it is not necessary to perform a detrap on every cell after each programming cycle. This is because after a detrap, the number of trapped electrons decreases, suppressing the drop in the threshold voltage of a large number of cells. After many subsequent programming cycles, the threshold voltage will not drop below the program verify voltage. Although it is inevitable that the threshold voltage of some cells will drop below the program verify voltage, it can be determined after program verify that it is insufficient and reprogrammed until its threshold voltage exceeds the program verify voltage. Therefore, performing a detrap after each programming cycle will reduce the programming speed. It is recommended to perform a detrap only after every 1k program / erase cycles, when a significant drop in threshold voltage is detected. This can minimize the impact on programming speed.

[0090] Under normal circumstances, if the program verification fails, the program-program verification cycle is generally performed again. If the program is insufficient, the threshold voltage of the cell is not programmed above the program verification voltage, and the program is performed again until the threshold voltage is greater than the program verification voltage.

[0091] Among them, the threshold voltage does not reach the programming verification voltage, not because the program is not in place, but because the electrons in the trap escape. For example, after a sufficient number of program and program verify, the threshold voltage of the cell has reached the programming verification voltage, but because the programmed electrons do not enter the floating gate, but enter the traps in the oxide material layer 103, the electrons in the traps and the electrons in the floating gate will also cause the threshold voltage to increase. After a period of time, the electrons in the traps escape, the threshold voltage drops, and it leads to insufficient programming. The result of these two types of insufficient programming is that the threshold voltage is less than the programming verification voltage, but the reasons are different.

[0092] Regardless of the magnitude of the threshold voltage drop, as long as the threshold voltage does not fall below the programming verification voltage, detrap or programming is considered successful. However, if a large number of electrons are trapped and escape, causing the threshold voltage to fall below the programming verification voltage, reprogramming is required. For example, a cell's threshold voltage may be (PV + 10)V after programming. After a period of time, electrons escape, causing the threshold voltage to drop by 9V. However, its threshold voltage is still greater than PV, so programming is considered successful. On the other hand, a cell's threshold voltage may be (PV + 1)V. After a period of time, electrons escape, causing the threshold voltage to drop by 2V. Since its threshold voltage is less than PV, programming is considered insufficient. In this section, PV represents the programming verification voltage.

[0093] In one embodiment, this embodiment provides a split-gate flash memory that executes the above-mentioned programming method.

[0094] It can be understood that since the split-gate flash memory provided in this embodiment executes the above-mentioned programming method, it can also reduce the number of electrons trapped in the oxide material layer 103 of the storage cell by performing a programming operation on the storage cell, performing a first programming verification operation on the storage cell, and performing a defect removal operation on the storage cell, thereby reducing the number of electrons trapped in the oxide material layer 103 that escape after the programming operation, thereby reducing the decrease in the threshold voltage of the storage cell after programming, and can improve the problem of incomplete programming caused by the decrease in the threshold voltage of the storage cell after programming.

[0095] Furthermore, by performing a second programming verification operation on the memory cell, the number of trapped electrons in the oxide material layer 103 of the memory cell can be measured. For example, if the threshold voltage is greater than or equal to the verification voltage of the second programming verification operation, it means that the number of trapped electrons in the oxide material layer 103 is small, and the decrease in the threshold voltage after the programming operation will not lead to the problem of incomplete programming; if the threshold voltage is less than the verification voltage of the second programming verification operation, it means that the number of trapped electrons in the oxide material layer 103 is large, and the decrease in the threshold voltage after the programming operation will lead to the problem of incomplete programming. Therefore, it can be seen that the second programming verification operation can at least verify the effect of the defect removal operation.

[0096] In summary, the programming method provided in this application can reduce the impact of electrons in the trap on the drop in threshold voltage after programming. The method has a simple structure and is easy to implement, thereby improving the reliability and accuracy of NORD Flash reading.

[0097] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0098] The above is a detailed introduction to the split-gate flash memory and programming method provided in the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for programming a split-gate flash memory, characterized in that: The split-gate flash memory includes storage cells, each of which includes a substrate, a floating gate material layer, and an oxide material layer located between the substrate and the floating gate material layer. The programming method includes: performing a programming operation on the memory cell; performing a first program verification operation on the memory cell; performing a defect removal operation on the storage unit; A second program verification operation is performed on the memory cell.

2. The programming method according to claim 1, wherein: The memory cell further includes a word line, a control gate, and a source-drain doping portion, and performing a defect removal operation on the memory cell includes: The bound carriers in the oxide material layer are controlled to flow out through at least one of the word line, the control gate, and the source-drain doped portion.

3. The programming method according to claim 1 or 2, characterized in that: The controlling the bound carriers in the oxide material layer to flow out through at least one of the word line, the control gate, and the source-drain doped portion includes: A first forward voltage difference is applied to the word line and the control gate.

4. The programming method according to claim 3, wherein: Applying a first forward voltage difference to the word line and the control gate includes: Applying a first word line voltage to the word line, where the first word line voltage is greater than or equal to 0V; A first control voltage is applied to the control gate, where the first control voltage is less than 0V.

5. The programming method according to claim 4, characterized in that: The applying a first forward voltage difference to the word line and the control gate further comprises: Configuring the control gate to include a first control gate and a second control gate; Setting the first word line voltage to be less than or equal to 3V; The first control voltage is applied to at least one of the first control gate and the second control gate, where the first control voltage is greater than or equal to −8V and less than or equal to −3V.

6. The programming method according to claim 1 or 2, characterized in that: The controlling the bound carriers in the oxide material layer to flow out through at least one of the word line, the control gate, and the source-drain doped portion includes: A second forward voltage difference is applied to the substrate, the word line, the source / drain doped portion, and the control gate.

7. The programming method according to claim 6, wherein: Applying a second forward voltage difference to the substrate, the word line, the source / drain doped portion, and the control gate includes: Applying a first voltage to the word line, the source / drain doped portion, and the control gate, wherein the first voltage is equal to 0V; A first substrate voltage is applied to the substrate, where the first substrate voltage is greater than 0V.

8. The programming method according to claim 7, characterized in that: The step of applying a first substrate voltage to the substrate, wherein the first substrate voltage is greater than 0V, comprises: The first substrate voltage is set to be greater than or equal to 3V and less than or equal to 8V.

9. The programming method according to claim 1 or 2, characterized in that: The controlling the bound carriers in the oxide material layer to flow out through at least one of the word line, the control gate, and the source-drain doped portion includes: A third forward voltage difference is applied to the source-drain doped portion, the word line, and the control gate.

10. The programming method according to claim 9, characterized in that: Applying a third forward voltage difference to the source / drain doped portion, the word line, and the control gate includes: Applying a second voltage to the word line and the control gate, wherein the second voltage is equal to 0V; A first bit line voltage is applied to the source-drain doped portion, where the first bit line voltage is greater than 0V.

11. The programming method according to claim 10, characterized in that: The step of applying a first bit line voltage to the source-drain doped portion, wherein the first bit line voltage is greater than 0V, comprises: Configuring the source-drain doped portion to include a first source-drain doped portion and a second source-drain doped portion; The first bit line voltage is applied to at least one of the first source-drain doped portion and the second source-drain doped portion, where the first bit line voltage is greater than or equal to 3V and less than or equal to 8V.

12. The programming method according to claim 1 or 2, characterized in that: The performing a defect removal operation on the memory cell further includes: After executing the programming operation N times, a defect removal operation is performed on the memory cell, where N is an integer greater than or equal to 2.

13. The programming method according to claim 1 or 2, characterized in that: After performing the second program verification operation on the memory cell, the method further includes: determining whether a threshold voltage of the memory cell is greater than or equal to a program verification voltage of the second program verification operation; If yes, then end this programming operation; or, if no, go to "perform programming operation on the memory cell".

14. A split-gate flash memory, characterized in that: The split-gate flash memory executes the programming method as described in any one of claims 1 to 13.

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