Power supply system, server and voltage adjustment method

Abstract

The present application provides a power supply system, server, and voltage adjustment method, which can be applied to the field of power supply technology. The power supply system includes: a power supply, configured to generate a pulse-width modulation signal based on control parameters, and to generate an output voltage based on the pulse-width modulation signal; a sampling circuit, electrically connected to the power supply, configured to sample the phase voltage generated by the power supply during the process of generating the output voltage to obtain a sampling signal; and a control circuit, electrically connected to the power supply and the sampling circuit, configured to receive a power status signal from the power supply and a sampling signal from the sampling circuit, and to adjust the control parameters of the power supply according to the sampling signal in response to the power status signal indicating a power supply abnormality.

Description

Technical Field

[0001] The present application relates to the field of power supply technology, and in particular to a power supply system, a server, and a voltage adjustment method. Background Art

[0002] With the development of artificial intelligence and big data, the application of artificial intelligence (AI) servers is becoming increasingly widespread. The stability and reliability of the power supply in AI servers are crucial to the overall operation of the AI ​​server system. Furthermore, if the voltage loop of the AI ​​server's power supply is unstable, it may hinder the normal operation of the AI ​​server. Summary of the Invention

[0003] The present application provides a power supply system, a server, and a voltage adjustment method.

[0004] According to a first aspect of the present application, a power supply system is provided, comprising: a power supply, configured to generate a pulse width modulation signal based on a control parameter and to generate an output voltage based on the pulse width modulation signal; a sampling circuit, electrically connected to the power supply, configured to sample a phase voltage generated by the power supply in the process of generating the output voltage to obtain a sampling signal; and a control circuit, electrically connected to the power supply and the sampling circuit, configured to receive a power status signal from the power supply and a sampling signal from the sampling circuit, and to adjust a control parameter of the power supply according to the sampling signal in response to the power status signal indicating that the power supply is abnormal.

[0005] According to a second aspect of the present application, a server is provided, comprising the above-mentioned power supply system.

[0006] According to a third aspect of the present application, a voltage adjustment method is provided, including: a power supply generates a pulse width modulation signal based on a control parameter, and generates an output voltage based on the pulse width modulation signal; a sampling circuit samples a phase voltage generated by the power supply in the process of generating the output voltage to obtain a sampling signal; a control circuit receives a power status signal from the power supply and a sampling signal from the sampling circuit, and in response to the power status signal indicating that the power supply is abnormal, adjusts the control parameters of the power supply according to the sampling signal.

[0007] According to an embodiment of the present application, a control circuit can receive a power supply status signal and, based on the power supply status signal, monitor whether the power supply is abnormal. Furthermore, the control circuit can receive a sampling signal obtained by sampling the power supply phase voltage using a sampling circuit. In this way, if the power supply signal is abnormal, the control parameters of the power supply can be adjusted promptly based on the sampling signal, thereby improving the stability of the power supply voltage loop. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above contents and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:

[0009] Figure 1 A schematic diagram of a power supply system according to an embodiment of the present application is shown.

[0010] Figure 2 A schematic diagram of a power supply system according to another embodiment of the present application is shown.

[0011] Figure 3 A schematic diagram of a voltage adjustment method according to an embodiment of the present application is shown.

[0012] Figure 4A FIG. 4 shows a waveform diagram of a digital voltage signal in a first adjustment mode according to an embodiment of the present application.

[0013] Figure 4B FIG. 4 shows a waveform diagram of a digital voltage signal in a second adjustment mode according to an embodiment of the present application.

[0014] Figure 5A A schematic diagram of a power supply system according to another embodiment of the present application is shown.

[0015] Figure 5B A schematic diagram of a power supply system according to another embodiment of the present application is shown.

[0016] Figure 5C A schematic diagram of a power supply according to an embodiment of the present application is shown.

[0017] Figure 6 A schematic diagram of a server according to an embodiment of the present application is shown.

[0018] Figure 7 A schematic diagram of a voltage adjustment method according to another embodiment of the present application is shown. DETAILED DESCRIPTION

[0019] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present application. In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present application. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present application.

[0020] The terms used herein are only for describing specific embodiments and are not intended to limit the present application. The terms "comprise," "include," etc. used herein indicate the presence of features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0021] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0022] When expressions such as "at least one of A, B, and C, etc." are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0023] After long-term operation of AI servers, the aging of the power supply and changes in the parameters of components such as capacitors and inductors within the server can cause instability in the power supply's voltage output loop, thereby affecting the power quality of the power supply output. Because it is difficult to monitor and control the stability of the power supply's voltage output loop, an unstable loop may falsely trigger the power supply's overcurrent protection (OCP).

[0024] In one solution, a complex programmable logic device (CPLD) can be used to send an enable signal to the power supply to drive it. When operating normally, the power supply can send a feedback signal to the CPLD. However, this approach does not monitor and control the stability of the power supply's output voltage. In the event of loop instability, this can lead to abnormal conditions such as excessive output voltage ripple, which can damage back-end devices powered by the power supply, affecting the normal operation of the AI ​​server and even risk burning out the server motherboard. Examples of back-end devices include a central processing unit (CPU) and a platform controller hub (PCH).

[0025] This application proposes a power supply system that can be applied to an artificial intelligence server, which can adaptively adjust the point-of-load power supply (POL) in the power supply system to stabilize the output voltage of the POL power supply.

[0026] Figure 1 A schematic diagram of a power supply system according to an embodiment of the present application is shown.

[0027] like Figure 1 As shown, the power supply system of this embodiment may include a power supply, a sampling circuit and a control circuit.

[0028] In some embodiments, a power supply can generate a pulse-width modulated signal based on control parameters, and generate a phase voltage based on the pulse-width modulated signal. For example, the control parameters may include proportional, integral, and differential parameters. The power supply's memory may contain predefined firmware. Based on this predefined firmware, the power supply can generate a pulse-width modulated signal according to the control parameters. The power supply can then generate a phase voltage based on the pulse-width modulated signal. In some embodiments, the power supply can filter the phase voltage and perform other processing to generate an output voltage, which can then be provided to the aforementioned backend device to power the backend device. In some embodiments, the power supply can include a power control unit (also known as a control stage) and a power unit (also known as a power stage). Therefore, this power supply is also referred to as a controller-power stage (Controller+Powerstage) power supply. This type of power supply will be described in further detail below.

[0029] The sampling circuit can be electrically connected to the power supply, specifically to a switch node of the power supply, and can sample the phase voltage of the power supply to obtain a sampling signal. For example, the sampling circuit can sample the phase voltage of the power supply at multiple consecutive moments to obtain sampling signals of the phase voltage at multiple moments. The sampling circuit can then provide the sampling signals of the phase voltage at multiple moments to the control circuit.

[0030] The control circuit can be electrically connected to the power supply and the sampling circuit and can receive a power status signal from the power supply and a sampling signal from the sampling circuit. In response to the power status signal indicating a power supply abnormality, the control circuit can adjust the control parameters of the power supply based on the sampling signal. For example, the control circuit can calculate new control parameters based on the sampling signal using a proportional-integral-differential algorithm and send these new control parameters to the power supply, so that the power supply can generate phase voltages based on the new control parameters. This allows adjustment of the phase voltages, and thus the output voltage.

[0031] Thus, in an embodiment of the present application, the control circuit can receive a power supply status signal and can monitor whether the power supply is abnormal based on the power supply status signal. The control circuit can receive a sampling signal obtained by sampling the phase voltage of the power supply by the sampling circuit. Thus, in the case of an abnormal power supply signal, the control parameters of the power supply can be adjusted in a timely manner according to the sampling signal, thereby improving the stability of the voltage loop of the power supply. Since the stability of the power supply loop is improved, the unstable voltage loop caused by factors such as aging of components and changes in component parameters in the power supply system is at least partially avoided, thereby reducing the risk of erroneous triggering of overcurrent protection due to loop abnormalities, avoiding the mainboard from being burned and the back-end equipment powered by the power supply from being damaged.

[0032] Figure 2 A schematic diagram of a power supply system according to another embodiment of the present application is shown.

[0033] like Figure 2 As shown, the control circuit may include an analog-to-digital conversion unit. For example, the analog-to-digital conversion unit may be a high-speed analog-to-digital converter. The analog-to-digital conversion unit may be electrically connected to a sampling circuit and receive a sampling signal from the sampling circuit. The analog-to-digital conversion unit may then perform analog-to-digital conversion on the sampling signal to obtain a digital voltage signal. The analog-to-digital conversion unit may then provide the digital voltage signal to a digital signal processor (DSP).

[0034] The digital signal processor can be electrically connected to the analog-to-digital conversion unit via a differential line to receive a digital voltage signal from the analog-to-digital conversion unit via the differential line. In addition, the digital signal processor can be electrically connected to a power supply to receive a voltage status signal. The digital signal processor can then monitor whether the phase voltage of the power supply is stable based on the power supply state indicated by the voltage status signal. In one embodiment of the present application, the digital signal processor can also provide an enable signal to the power supply to drive the power supply to supply power. The digital signal processor can then receive a voltage status signal from the power supply. In this way, the digital signal processor can determine whether the phase voltage of the power supply is in a stable state based on the voltage status signal, so that when the power status signal indicates that the phase voltage of the power supply is not stable, the phase voltage of the power supply can be adjusted.

[0035] On this basis, the digital signal processor can determine the jitter parameter of the power supply based on the received digital voltage signal when detecting that the phase voltage is unstable. For example, the digital signal processor can determine the jitter parameter based on the signal edge of the digital voltage signal. The jitter parameter can be used to indicate whether the phase voltage of the power supply is in an overvoltage state. For example, the jitter parameter can be compared with a predetermined value. If the jitter parameter is greater than the predetermined value, it can be determined that the phase voltage is overvoltage; otherwise, it can be determined that the phase voltage is not overvoltage.

[0036] If the dithering parameters indicate that the phase voltage of the power supply is overvoltage, the digital signal processor can process the digital voltage signal based on a proportional-integral-differential algorithm to obtain new control parameters. The digital signal processor can then control the phase voltage of the power supply based on the new control parameters. If the dithering parameters indicate that the phase voltage of the power supply is not overvoltage, the digital signal processor can stop calculating the control parameters so that the power supply provides the phase voltage according to the original control parameters. This process is repeated until the digital signal processor detects that the phase voltage has stabilized, at which point the digital signal processor can stop controlling the phase voltage of the power supply. In this way, by calculating the dithering parameters based on the digital voltage signal and then determining whether to generate new control parameters for providing to the power supply based on the dithering parameters, the accuracy of the voltage loop adjustment can be improved, thereby improving the stability of the voltage loop.

[0037] For example, the digital signal processor can calculate jitter parameters in any of multiple modes. The multiple modes can include a first adjustment mode and a second adjustment mode. For example, the power supply control unit can also generate a mode indication signal for indicating an adjustment mode supported by the power supply. The digital signal processor can receive the mode indication signal from the power supply control unit and, based on the mode indication signal, select an adjustment mode that matches the mode indication signal from the first adjustment mode and the second adjustment mode, and adjust the control parameters of the power supply according to the selected adjustment mode. In one embodiment of the present application, the power supply can be replaced. In this way, when the replaced power supply detects that it is electrically connected to the digital signal processor, the replaced power supply can send the mode indication signal to the digital signal processor via a signal bus to indicate the adjustment mode it supports. The digital signal processor then selects an appropriate adjustment mode from the first adjustment mode and the second adjustment mode based on the adjustment mode indicated by the mode indication signal to adjust the control parameters of the power supply. In this way, the present application can support stability adjustment of power supplies in different modes and improve the loop stability of power supplies that support different adjustment modes.

[0038] For example, the first adjustment mode may be a pulse width modulation mode. The second adjustment mode may be a constant on-time mode. In one embodiment of the present application, when the digital signal processor is in the pulse width modulation mode, in response to detecting that the phase voltage of the power supply is not stable, the digital signal processor may utilize the processing strategy of the pulse width modulation mode to calculate the jitter parameters of the power supply based on the signal edge of the digital voltage signal. In another embodiment of the present application, when the digital signal processor is in the constant on-time mode, in response to detecting that the phase voltage of the power supply is not stable, the digital signal processor may utilize the processing strategy of the constant on-time mode to calculate the jitter parameters of the power supply based on the signal edge of the digital voltage signal. In this way, the overvoltage status of the power supply of different modes is determined based on the jitter parameters of different modes, so that the phase voltage of the power supply of different modes can be adjusted by control parameters.

[0039] The power supply may include a power control unit and a power unit. For example, the power control unit may be electrically connected to a control circuit. Specifically, the power control unit may be electrically connected to a digital signal processor in the control circuit and receive control parameters from the digital signal processor. The power control unit may then generate a pulse-width modulated signal based on the control parameters. For example, the power control unit may process the control parameters based on predetermined firmware to generate the corresponding pulse-width modulated signal.

[0040] The power unit can be electrically connected to the power control unit and receive a pulse width modulation signal. Then, the power unit can generate a phase voltage based on the pulse width modulation signal. For example, the power unit can be implemented based on a switching device. In one embodiment of the present application, the power control unit can determine the pulse width of the pulse width modulation signal based on the control parameters, and then provide the pulse width modulation signal of the pulse width to the power unit to control the on-time of the switching device in the power unit to achieve control of the phase voltage. In another embodiment of the present application, the power control unit can also control the off-time of the switching device in the power unit to achieve control of the phase voltage. In this way, the power control unit can generate a pulse width modulation signal based on the control parameters from the control circuit, and then the power unit generates a corresponding phase voltage based on the pulse width modulation signal, which can achieve adjustment of the phase voltage output by the power unit, thereby improving the stability of the power supply loop.

[0041] In an embodiment of the present application, the digital signal processor can calculate the time intervals from each rising edge to the falling edge of the digital voltage signal in the first adjustment mode to obtain a conduction time series. Based on the conduction time series, a jitter parameter is calculated. If the jitter parameter is greater than a predetermined value, the digital signal processor can generate new control parameters using a proportional-integral-differential algorithm and provide the new control parameters to the power supply.

[0042] Specifically, the digital signal processor can determine the signal edge interval duration based on any rising edge in the digital voltage signal and the next falling edge after the rising edge in the first adjustment mode. For example, in the first adjustment mode, the time t of the next falling edge after the rising edge is calculated with the rising edge as the time reference 0, thereby obtaining a signal edge interval duration. After the calculation, the signal edge interval duration is recalculated with the next rising edge as the time reference 0. In this way, taking 1000 calculations within a single sampling cycle of the sampling signal as an example, 1000 signal edge interval durations t1, t2, ..., t1000 can be calculated one by one, thereby obtaining a conduction time sequence including multiple signal edge interval durations. Then, the maximum duration and the minimum duration can be determined from the 1000 signal edge interval durations t1, t2, ..., t1000. The maximum duration of the first adjustment mode can be expressed as Tmax=max(t1, t2, ..., t1000), and the minimum duration of the first adjustment mode can be expressed as Tmin=min(t1, t2, ..., t1000). Here, max(t1, t2, ..., t1000) indicates the maximum value determined from t1, t2, ..., t1000; min(t1, t2, ..., t1000) indicates the minimum value determined from t1, t2, ..., t1000.

[0043] The digital signal processor can then determine the difference between the maximum duration and the minimum duration, and determine the sum of the maximum duration and the minimum duration. The digital signal processor can then determine a jitter parameter based on the difference and the sum. For example, the jitter parameter can be calculated based on the maximum duration and the minimum duration using the following formula:

[0044] Jitter_T=2*(Tmax-Tmin) / (Tmax+Tmin) (1)

[0045] In formula (1), Jitter_T of the first adjustment mode represents a jitter parameter; Tmax of the first adjustment mode represents a maximum duration; and Tmin of the first adjustment mode represents a minimum duration.

[0046] In another embodiment of the present application, the digital signal processor can further calculate the time intervals between each rising edge of the digital voltage signal in the second adjustment mode to obtain a switching cycle sequence. The digital signal processor can then calculate a jitter parameter based on the switching cycle sequence. If the jitter parameter is greater than a predetermined value, the digital signal processor can generate a new control parameter using a proportional-integral-differential algorithm and provide the new control parameter to the power supply.

[0047] For example, in the second adjustment mode, the time t of the next rising edge after the rising edge is calculated, using the rising edge as time reference 0, to obtain a single edge interval duration. After this calculation, the edge interval duration is recalculated, using the next rising edge as time reference 0. In this way, taking 1000 calculations within a single sampling period of the sampled signal as an example, 1000 edge interval durations h1, h2, ..., h1000 can be calculated one by one, thereby obtaining a switching cycle sequence including multiple edge interval durations. The maximum and minimum durations can then be determined from these 1000 edge interval durations h1, h2, ..., h1000. The maximum duration of the second adjustment mode can be expressed as Hmax = max(h1, h2, ..., h1000), and the minimum duration of the second adjustment mode can be expressed as Hmin = min(h1, h2, ..., h1000). Among them, max(h1, h2, ..., h1000) means determining the maximum value from h1, h2, ..., h1000; min(h1, h2, ..., h1000) means determining the minimum value from h1, h2, ..., h1000.

[0048] The digital signal processor can then determine a first square value of the maximum duration and a second square value of the minimum duration. The digital signal processor can then determine a squared difference between the first square value and the second square value, and determine the product of the maximum duration and the minimum duration. The digital signal processor can then divide the squared difference by the product of the durations to obtain a jitter parameter. For example, the jitter parameter can be calculated based on the maximum duration and the minimum duration using the following formula:

[0049] Jitter_H=(Hmax*Hmax-Hmin*Hmin) / (2*Hmax*Hmin) (2)

[0050] In formula (2), Jitter_H of the second adjustment mode represents the jitter parameter; Hmax of the second adjustment mode represents the maximum duration; and Hmin of the second adjustment mode represents the minimum duration.

[0051] Furthermore, in an embodiment of the present application, the digital signal processor may compare the jitter parameter with a predetermined value to obtain a comparison result. Then, upon determining that the comparison result indicates that the jitter parameter is greater than the predetermined value, the digital signal processor may determine that the phase voltage of the power supply is overvoltage. Thereafter, the digital signal processor may calculate the control parameter based on the digital voltage signal, and adjust the original control parameter of the power supply based on the control parameter to obtain the adjusted control parameter, so that the power supply provides the phase voltage based on the adjusted control parameter. In addition, the digital signal processor may also determine that the phase voltage of the power supply is not overvoltage and stop adjusting the original control parameter of the power supply in response to determining that the comparison result indicates that the jitter parameter is less than or equal to the predetermined value. Specifically, the phase voltage control process under different modes is described below.

[0052] Figure 3 A schematic diagram of a voltage adjustment method according to an embodiment of the present application is shown.

[0053] like Figure 3 As shown, the voltage adjustment method of this embodiment may include the following operations:

[0054] In operation S310 , the sampling circuit samples the phase voltage of the power supply to obtain a sampling signal.

[0055] In operation S320 , the analog-to-digital conversion unit converts the sampled signal into a digital voltage signal.

[0056] In operation S330, the digital signal processor determines whether it is in the first adjustment mode or the second adjustment mode. If it is in the first adjustment mode, operation S341 is performed. If it is in the second adjustment mode, operation S351 is performed.

[0057] In operation S341 , the digital signal processor determines a dithering parameter based on time intervals from each rising edge to a falling edge of a digital voltage signal in a first adjustment mode.

[0058] In operation S342, the digital signal processor determines whether the jitter parameter is greater than a predetermined value of the first adjustment mode. If yes, operation S343 is performed. If no, operation S344 is performed.

[0059] In operation S343 , the digital signal processor adjusts a control parameter of the power supply based on the digital voltage signal in a first adjustment mode.

[0060] In operation S344 , the digital signal processor stops adjusting the control parameter in the first adjustment mode.

[0061] In operation S351 , the digital signal processor determines a dithering parameter based on time intervals from rising edges to rising edges of a digital voltage signal in a second adjustment mode.

[0062] In operation S352, the digital signal processor determines whether the jitter parameter is greater than a predetermined value of the second adjustment mode. If yes, operation S353 is performed. If no, operation S354 is performed.

[0063] In operation S353 , the digital signal processor adjusts a control parameter of the power supply based on the digital voltage signal in the second adjustment mode.

[0064] In operation S354 , the digital signal processor stops adjusting the control parameter in the second adjustment mode.

[0065] Figure 4A FIG1 shows a waveform diagram of a digital voltage signal in the first adjustment mode according to an embodiment of the present application. The unit of voltage may be volt (V), and the unit of time may be nanosecond (ns). Figure 4A As shown, in the first adjustment mode, the maximum duration of the first adjustment mode can be Tmax=max(t1, t2, ..., t1000)=79.4ns, and the minimum duration of the first adjustment mode can be Tmin=min(t1, t2, ..., t1000)=131ns.

[0066] Thus, the Jitter_T of the first adjustment mode can be calculated by the above formula (1) as 2*(Tmax-Tmin) / (Tmax+Tmin)=49.05%. When the predetermined value Spec_pwm of the first adjustment mode is 40%, it can be determined that the jitter parameter Jitter_T is greater than the predetermined value Spec_pwm corresponding to the jitter parameter. In this case, the digital signal processor can use the proportional integral differential algorithm to calculate the control parameters based on the digital voltage signal, namely the proportional parameter Kp_pwm of the first adjustment mode, the integral parameter Ki_pwm of the first adjustment mode, and the differential parameter Kd_pwm of the first adjustment mode. Then, the control parameters can be sent to the power supply via a signal bus (for example, an inter-integrated circuit bus (I2C)). The power supply can adjust its original control parameters based on the received control parameters. On the contrary, when the jitter parameter Jitter_T of the first adjustment mode is less than or equal to the predetermined value Spec_pwm corresponding to the jitter parameter, the adjustment of the control parameters of the power supply is stopped, so that the power supply provides the phase voltage according to the original control parameters.

[0067] Figure 4B FIG1 shows a waveform diagram of a digital voltage signal in the second adjustment mode according to an embodiment of the present application. The unit of voltage may be volt (V), and the unit of time may be nanosecond (ns). Figure 4BAs shown, in the second adjustment mode, the maximum duration of the second adjustment mode can be Hmax=max(h1, h2, ..., h1000)=916ns, and the minimum duration of the second adjustment mode can be Hmin=min(h1, h2, ..., h1000)=776ns.

[0068] Thus, the Jitter_H of the second adjustment mode can be calculated by the above formula (2) as (Hmax*Hmax-Hmin*Hmin) / (2*Hmax*Hmin)=16.66%. When the predetermined value Spec_cot of the second adjustment mode is 15%, it can be determined that the jitter parameter Jitter_H of the second adjustment mode is greater than the predetermined value Spec_cot corresponding to the jitter parameter. In this case, the digital signal processor can use the proportional integral differential algorithm to calculate the control parameters based on the digital voltage signal, namely the proportional parameter Kp_cot of the second adjustment mode, the integral parameter Ki_cot of the second adjustment mode, and the differential parameter Kd_cot of the second adjustment mode. Then, the control parameters can be sent to the power supply through the internal integrated circuit bus. The power supply can adjust its original control parameters based on the received control parameters. On the contrary, when the jitter parameter Jitter_H of the second adjustment mode is less than or equal to the predetermined value Spec_cot corresponding to the jitter parameter, the control parameters of the power supply are stopped from being adjusted so that the power supply provides the phase voltage according to the original control parameters.

[0069] Based on this, the duration of each signal edge interval in the aforementioned conduction time sequence or switching cycle sequence of the present application corresponds to the duration of the power supply voltage overvoltage. Thus, through the above calculation method, it is possible to determine whether the proportion of the overvoltage duration to the entire sampling period is too high, and thus determine that the power supply control parameters need to be adjusted, thereby allowing timely processing of the power supply control parameters. This improves the stability of the power supply loop.

[0070] The above describes the specific method for adjusting the phase voltage of the power supply by the digital signal processor. The following describes the other units and specific circuit structures of the power supply system of the present application. Specifically, in an embodiment of the present application, the sampling circuit can be electrically connected to the analog-to-digital conversion unit via a first differential line. The analog-to-digital conversion unit can be electrically connected to the digital signal processor via a second differential line. In this way, the sampling circuit can provide the sampled signal obtained by sampling to the analog-to-digital conversion unit, and the analog-to-digital conversion unit can then provide the converted digital voltage signal to the digital signal processor.

[0071] Specifically, the sampling circuit may include a first sampling resistor and a second sampling resistor. The first end of the first sampling resistor is electrically connected to the switch node of the power unit to collect the phase voltage at the switch node. The second end of the first sampling resistor is electrically connected to the first end of the second sampling resistor, and is electrically connected to the first input end of the analog-to-digital conversion unit through the first line in the first differential line. The second end of the second sampling resistor is electrically connected to the ground end, and is electrically connected to the second input end of the analog-to-digital conversion unit through the second line in the first differential line. In this way, the phase voltage of the power supply can be sampled. The following is combined with Figure 5A Provide explanation. Figure 5A A schematic diagram of a power supply system according to another embodiment of the present application is shown.

[0072] like Figure 5A As shown, the power supply system of this embodiment may include a power supply, a first sampling resistor R21, a second sampling resistor R22, an analog-to-digital conversion unit, and a digital signal processor.

[0073] On this basis, the digital signal processor can provide an enable signal P5V_EN to the power supply and control whether the power supply is working according to the high and low levels of the enable signal P5V_EN. When the power supply is working, the power supply can pass the power supply status signal P5V_PG_CPLD to the digital signal processor so that the digital signal processor adjusts the phase voltage of the power supply according to the state indicated by the power supply status signal P5V_PG_CPLD. For example, the phase voltage can be sampled by dividing the voltage by the first sampling resistor R21 and the second sampling resistor R22 to obtain the sampling signal P5V_SW_MONITOR. The analog-to-digital conversion unit can perform analog-to-digital conversion on the sampling signal P5V_SW_MONITOR and provide the obtained digital voltage signals P5V_SW_D0+ and P5V_SW_D0- in the form of differential signals to the digital signal processor.

[0074] Specifically, the digital signal processor outputs an enable signal P5V_EN=1, that is, outputs an enable signal P5V_EN of an effective level to drive the power supply to start working, so that the power supply outputs a phase voltage P5V_SW via the switch node SW, and can simultaneously output a power status signal P5V_PG_CPLD. On this basis, the phase voltage P5V_SW output by the power supply can be divided by the first sampling resistor R21 and the second sampling resistor R22 to obtain a sampling signal P5V_SW_MONITOR, and the sampling signal P5V_SW_MONITOR is passed to the analog-to-digital conversion unit. For example, the analog-to-digital conversion unit can be a single-channel high-speed converter ADC12SJ1600, which has low power consumption, high sampling rate and 12-bit resolution, and is suitable for a variety of multi-channel communication and test systems.

[0075] The analog-to-digital conversion unit then performs analog-to-digital conversion on the received sampled signal P5V_SW_MONITOR to obtain digital voltage signals P5V_SW_D0+ and P5V_SW_D0- in the form of differential signals, and transmits these digital voltage signals P5V_SW_D0+ and P5V_SW_D0- in the form of differential signals to a digital signal processor. The digital signal processor, for example, can be a C64xx series DSP as its core processor, with an operating frequency of up to 1000 MHz, and can receive the digital voltage signals P5V_SW_D0+ and P5V_SW_D0- transmitted by the analog-to-digital conversion unit in real time.

[0076] The digital signal processor receives the digital voltage signals P5V_SW_D0+ and P5V_SW_D0- from the analog-to-digital conversion unit and determines control parameters based on the digital voltage signals P5V_SW_D0+ and P5V_SW_D0 received during the switching cycle. The digital signal processor then transmits the control parameters to the power supply via the inter-IC bus. The serial data line of the inter-IC bus is represented by SDA (Serial Data Line), and the serial clock line is represented by SCL (Serial Clock Line). This allows the power supply's phase voltages to be adjusted.

[0077] In addition, Figure 5A Also shown are the input voltage P12V of the power supply, the output inductor L21 for filtering, the output capacitor C21 for filtering, the filtered phase voltage P5V, the port PG of the power supply for outputting the power status signal P5V_PG_CPLD, the voltage port VCC, the resistor R23 and the capacitor C22. This application does not limit this and will not be described one by one here.

[0078] In addition, the power supply system of this embodiment may further include a management controller. For example, the management controller may be a baseboard management controller (BMC). The digital signal processor may be electrically connected to the power supply and the management controller via a signal bus (such as the inter-integrated circuit bus described above). On this basis, the digital signal processor may send control parameters to the management controller and the power supply via the signal bus to adjust the phase voltage of the power supply, and the management controller may record the number of times the digital signal processor adjusts the power supply based on the control parameters. Figure 5B For example, Figure 5B A schematic diagram of a power supply system according to another embodiment of the present application is shown.

[0079] like Figure 5BAs shown, the control system of this embodiment may include a power supply, a first sampling resistor R21, a second sampling resistor R22, an analog-to-digital conversion unit, and a digital signal processor. The specific functions and connections of the power supply, the first sampling resistor R21, the second sampling resistor R22, the analog-to-digital conversion unit, and the digital signal processor can be referred to in the previous description and are not repeated here.

[0080] Further, in Figure 5B In the embodiment, the baseboard management controller may correspond to the management controller described above. On this basis, the baseboard management controller may receive control parameters from the digital signal processor via SDA and SCL, and upon receiving the control parameters, record the number of times the digital signal processor adjusts the power supply. In addition, the baseboard management controller may also be electrically connected to other power supplies that are different from the above-mentioned power supplies. In this way, predetermined firmware may be burned into multiple power supplies including the above-mentioned power supplies and other power supplies by controlling the baseboard management controller. For example, the predetermined firmware may include data such as voltage regulator configuration data (Voltage Regulator Configuration Data, VR CODE). Furthermore, the embodiments of the present application are not limited to this. In other embodiments of the present application, the baseboard management controller may also be used to burn initial control parameters into the multiple power supplies so that the multiple power supplies can operate based on the initial control parameters.

[0081] In addition, in one embodiment of the present application, the digital signal processor can also be electrically connected to the debug interface via a signal bus, and can send control parameters to the debug interface via the signal bus. Figure 5B ,exist Figure 5B The debug interface can also be electrically connected to the SDA and SCL lines. This allows adjustments to the power supply's firmware to ensure that all specifications meet design requirements. If a power supply error occurs, the error message can be read through the power supply via an adapter (dongle), facilitating troubleshooting.

[0082] The above has described the various units of the power supply system of the embodiment of the present application. On this basis, for the power supply in the power supply system of the embodiment of the present application, the following is combined with Figure 5C Further explanation is given. Figure 5C A schematic diagram of a power supply according to an embodiment of the present application is shown.

[0083] like Figure 5CAs shown, the power supply of this embodiment may include a power control unit and a power unit. In some embodiments, the power unit may include a switching device, and is not limited thereto. In some embodiments, it may also include devices such as capacitors and inductors, which are not limited in this application. The power unit may include a switching node SW. The switching node SW may be the connection point between a high-frequency switching tube (such as a metal-oxide-semiconductor field-effect transistor (MOSFET)) in the power unit and an energy storage element (such as an inductor or a transformer), and its voltage switches rapidly between the input voltage and the ground to form a high-frequency square wave. The voltage at the switching node is the phase voltage.

[0084] The power unit can provide voltage by turning on and off the switching device under the control of the pulse width modulation signal provided by the power control unit. In this way, the voltage of the switch node can change at a high frequency as the operating state (e.g., on or off) of the switching device switches at a high frequency. The phase voltage can be the average value of the switch node voltage when the power unit is pulse-width modulated. In other words, the phase voltage can be controlled by the duty cycle of the pulse width modulation. In this way, in one embodiment of the present application, the power control unit can generate a pulse width modulation signal with a corresponding duty cycle based on the control parameter and provide the pulse width modulation signal to the power unit, thereby adjusting the phase voltage at the switch node of the power unit.

[0085] Figure 6 A schematic diagram of a server according to an embodiment of the present application is shown.

[0086] like Figure 6 As shown, the server 600 of this embodiment may include a power supply system 610 , which may be any of the above-mentioned power supply systems.

[0087] It should be noted that this application only uses a 12V to 5V power supply in an AI server as an example. It should be understood that the embodiments of this application are not limited to this. This application can also be extended to power supplies with other input voltages and phase voltage proportional-integral-differential regulation. At the same time, in addition to AI server application scenarios, it can also be extended to switches, new energy vehicles and other fields.

[0088] Figure 7 A schematic diagram of a voltage adjustment method according to another embodiment of the present application is shown.

[0089] like Figure 7 As shown, the voltage adjustment method of this embodiment may include operations S710 to S740.

[0090] In operation S710 , a power supply generates a pulse width modulation signal based on a control parameter and produces power based on the pulse width modulation signal.

[0091] In operation S720 , the sampling circuit samples the phase voltage generated by the power supply in the process of generating the output voltage to obtain a sampling signal.

[0092] In operation S730 , the control circuit receives a power state signal from the power supply and a sampling signal from the sampling circuit.

[0093] In operation S740 , the control circuit adjusts a control parameter of the power supply according to the sampling signal in response to the power status signal indicating that the power supply is abnormal.

[0094] It should be understood that the voltage adjustment method of the present application is not limited to this, and the voltage adjustment method of the present application may also include the above methods.

[0095] For example, adjusting the control parameters of a power supply based on a sampled signal may include: a control circuit performing analog-to-digital conversion on the sampled signal to obtain a digital voltage signal. In a first adjustment mode, the control circuit calculates the time intervals from each rising edge to each falling edge of the digital voltage signal to obtain a conduction time sequence; based on the conduction time sequence, a jitter parameter is calculated; and in response to the jitter parameter being greater than a predetermined value, a new control parameter is generated using a proportional-integral-differential algorithm and provided to the power supply. In a second adjustment mode, the control circuit calculates the time intervals from each rising edge to each rising edge of the digital voltage signal to obtain a switching cycle sequence; based on the switching cycle sequence, a jitter parameter is calculated; and in response to the jitter parameter being greater than a predetermined value, a new control parameter is generated using a proportional-integral-differential algorithm and provided to the power supply.

[0096] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the above-mentioned module, program segment, or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of the boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0097] Those skilled in the art will appreciate that the features described in the various embodiments of this application may be combined and / or coupled in various ways, even if such combinations or couplings are not explicitly described in this application. In particular, the features described in the various embodiments of this application may be combined and / or coupled in various ways without departing from the spirit and teachings of this application. All such combinations and / or couplings fall within the scope of this application.

[0098] The embodiments of the present application have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present application. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be advantageously used in combination. Without departing from the scope of the present application, those skilled in the art may make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present application.

Claims

1. A power supply system, characterized in that: The power supply system comprises: a power supply for generating a pulse width modulation signal based on a control parameter and generating an output voltage based on the pulse width modulation signal; The sampling circuit is electrically connected to the power supply and is used to sample the phase voltage generated by the power supply in the process of generating the output voltage to obtain a sampling signal; a control circuit electrically connected to the power supply and the sampling circuit, configured to receive a power status signal from the power supply and a sampling signal from the sampling circuit, and in response to the power status signal indicating a power supply abnormality, adjust a control parameter of the power supply according to the sampling signal; The power supply includes a power control unit electrically connected to the control circuit and configured to generate a mode indication signal, the mode indication signal being configured to indicate an adjustment mode supported by the power supply; The control circuit is further configured to: receiving a mode indication signal from a power control unit; selecting, according to the mode indication signal, an adjustment mode that matches the mode indication signal from the first adjustment mode and the second adjustment mode; Adjust the control parameters of the power supply according to the selected adjustment mode; The control circuit is further configured to: Perform analog-to-digital conversion on the sampled signal to obtain a digital voltage signal; In response to the power status signal indicating a power abnormality, In the first adjustment mode, the time intervals from each rising edge to the falling edge of the digital voltage signal are calculated to obtain a conduction time series. Based on the conduction time series, the jitter parameter is calculated. When the jitter parameter is greater than a predetermined value, a new control parameter is calculated using a proportional-integral-differential algorithm and provided to the power supply. In the second adjustment mode, the time intervals between each rising edge of the digital voltage signal are calculated to obtain a switching cycle sequence. Based on the switching cycle sequence, the jitter parameter is calculated. When the jitter parameter is greater than a predetermined value, a new control parameter is generated through a proportional-integral-differential algorithm and provided to the power supply.

2. The power supply system according to claim 1, wherein: The control circuit comprises: An analog-to-digital conversion unit, used to perform analog-to-digital conversion on the sampling signal to obtain a digital voltage signal; Digital signal processors for: A power status signal from a power supply and a digital voltage signal from an analog-to-digital conversion unit are received, wherein the power status signal is used to indicate power supply abnormality, and the digital voltage signal is used to calculate jitter parameters.

3. The power supply system according to claim 2, wherein: The digital signal processor is further configured to: In the first adjustment mode, the time intervals from each rising edge to the falling edge of the digital voltage signal are calculated to obtain a conduction time sequence; Calculate jitter parameters based on the conduction time series; When the jitter parameter is greater than a predetermined value, a new control parameter is calculated by a proportional-integral-differential algorithm; Provide new control parameters to the power supply.

4. The power supply system according to claim 2, wherein: The digital signal processor is further configured to: In the second adjustment mode, the time intervals between each rising edge of the digital voltage signal are calculated to obtain a switching cycle sequence; Calculate jitter parameters based on the switching cycle sequence; When the jitter parameter is greater than a predetermined value, a new control parameter is generated by a proportional-integral-differential algorithm; Provide new control parameters to the power supply.

5. The power supply system according to any one of claims 1 to 4, characterized in that: The power control unit is further configured to generate a pulse width modulation signal based on control parameters from the control circuit, and provide a power status signal; The power supply further includes: a power unit electrically connected to the power control unit and configured to generate an output voltage based on a pulse width modulation signal.

6. The power supply system according to claim 5, characterized in that: The sampling circuit includes a first sampling resistor and a second sampling resistor; A first end of the first sampling resistor is electrically connected to a switch node of the power unit for providing a phase voltage; a second end of the first sampling resistor is electrically connected to a first end of the second sampling resistor and a first input end of the analog-to-digital conversion unit of the control circuit; The second end of the second sampling resistor is electrically connected to the ground end and the second input end of the analog-to-digital conversion unit.

7. A server, characterized in that: The invention comprises a power supply system as claimed in any one of claims 1 to 6.

8. A voltage adjustment method, characterized in that: The voltage adjustment method is performed by the power supply system according to any one of claims 1 to 6, wherein the voltage adjustment method comprises: The power supply generates a pulse width modulation signal based on the control parameter and produces an output voltage based on the pulse width modulation signal; The sampling circuit samples the phase voltage generated by the power supply in the process of generating the output voltage to obtain a sampling signal; The control circuit receives a power status signal from the power supply and a sampling signal from the sampling circuit, and in response to the power status signal indicating that the power supply is abnormal, adjusts the control parameters of the power supply according to the sampling signal.

9. The voltage adjustment method according to claim 8, wherein: Adjust the control parameters of the power supply according to the sampling signal, including: Perform analog-to-digital conversion on the sampled signal to obtain a digital voltage signal; In a first adjustment mode, the time intervals from each rising edge to the falling edge of the digital voltage signal are calculated to obtain a conduction time series; a jitter parameter is calculated based on the conduction time series; and if the jitter parameter is greater than a predetermined value, a new control parameter is generated using a proportional-integral-differential algorithm, and the new control parameter is provided to the power supply; In the second adjustment mode, the time intervals between each rising edge of the digital voltage signal are calculated to obtain a switching cycle sequence; based on the switching cycle sequence, a jitter parameter is calculated; when the jitter parameter is greater than a predetermined value, a new control parameter is generated through a proportional-integral-differential algorithm, and the new control parameter is provided to the power supply.

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