Low-noise low-mismatch charge pump circuit applied to frequency synthesizer circuit

Abstract

The invention discloses a low-noise low-mismatch charge pump circuit applied to a frequency synthesizer circuit, and belongs to the field of integrated circuits. The charge pump core part suppresses current mismatch and reduces noise of an output signal through various optimized circuit structures; the rail-to-rail operational amplifier ensures the stability of an output direct current point of the charge pump circuit and is used for weakening the charge sharing effect of the charge pump; the transmission gate switch circuit part can reduce static and dynamic mismatch of upper and lower paths of current and weaken clock feed-through and charge injection effects of the charge pump circuit; and the Power-Down circuit part can cut off the input current when the circuit does not work, so that the power consumption of the system is reduced. By applying the charge pump technology, low output noise and low current mismatch of the charge pump circuit can be realized, the switching speed of the charge pump is improved, and the charge pump circuit has better interference resistance to power supply noise, so that the stray and noise performance of a frequency synthesizer is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a low-noise and low-mismatch charge pump circuit used in a frequency synthesizer circuit. Background Art

[0002] The function of the charge pump in the charge pump phase-locked loop frequency synthesizer system is to convert the phase signal of the frequency detector into an analog signal, realizing the conversion of the phase signal to a current signal. The low-pass filter converts the current signal into a voltage signal to tune the voltage-controlled oscillator to output a clock signal of appropriate frequency.

[0003] A related art invention relates to a wide-temperature-range, low-mismatch charge pump circuit comprising a charge pump core circuit, a bandgap reference source, and a current compensation circuit. This structure stabilizes the charge pump's output current under varying temperatures and processes, ensuring the system's spurious performance, thereby improving both charge pump performance and robustness. However, the use of a single-tube switch results in a dynamic mismatch between the upper and lower current paths of the charge pump, preventing the charge pump's output DC point from maintaining stability. Furthermore, the lack of a current shutdown mechanism increases the system's overall power consumption. Furthermore, because this structure has limited power supply noise suppression, crosstalk and noise on the power supply can increase the output noise of the charge pump circuit. Furthermore, when the upper and lower charge pump switches are turned off, circuit performance is limited by leakage current in the subthreshold MOS transistors (particularly in deep submicron CMOS processes), impacting the performance of the phase-locked loop (PLL) during lock.

[0004] As the core module of a charge pump phase-locked loop (PLL), the charge pump's design matching characteristics and noise performance directly determine the reference spurious and phase noise performance of the entire PLL system, and also affect the PLL system's stability. In the clock design field, designers need to focus on product stability and robustness. Therefore, they need to improve the stability and dynamic matching of the charge pump circuit to achieve low output noise and minimize current mismatch.

[0005] During the charge pump design process, designers must consider many non-ideal effects, such as static mismatches such as leakage current and device mismatch, as well as dynamic mismatches such as channel charge injection, clock feedthrough, and charge sharing. The superposition of various non-ideal effects during charge pump operation will cause periodic ripples on the output control voltage, which in turn converts into reference spurs in the output signal. In existing technologies, the effects of charge injection and clock feedthrough can be improved by adding complementary switches, and the influence of charge sharing can be reduced by using a source switch structure. However, although the above method reduces the mismatch of the charge pump to a certain extent, it is still difficult to meet the noise performance requirements of high signal-to-noise ratio scenarios. Summary of the Invention

[0006] The present invention provides a low-noise and low-mismatch charge pump circuit for use in a frequency synthesizer circuit. The circuit can achieve low output noise and low current mismatch in the charge pump circuit, increase the speed of the charge pump switch, and have better immunity to power supply noise, thereby improving the spurious and noise performance of the frequency synthesizer.

[0007] A first embodiment of the present invention provides a low-noise, low-mismatch charge pump circuit for use in a frequency synthesizer circuit, comprising:

[0008] The charge pump core circuit uses a variety of optimized circuit structures to suppress current mismatch;

[0009] A rail-to-rail operational amplifier circuit, used to maintain the stability of the DC output point of the charge pump core circuit when the input signal changes;

[0010] The transmission gate switch circuit consists of a complementary switch and a dummy switch to suppress the clock feedthrough and charge injection effects of the switch;

[0011] The power-down circuit uses a transmission gate switch circuit to cut off the input current when the circuit is not working, thereby reducing power consumption.

[0012] Optionally, in one embodiment of the present invention, the charge pump core circuit includes: TG 10 The IN terminal of the TG is connected to the IBIAS input terminal of the charge pump; 10 The OUT terminal is connected to the positive terminal of R0, NM 11 Gate terminal, NM 13 Gate terminal, NM 15 Gate terminal, NM 17 The gate terminal; R 10 The negative terminal is connected to NM 11 Drain terminal, NM 10 Gate terminal, NM 12 Gate terminal, NM 14 Gate terminal, NM 16 Gate terminal; NM 10 The source and NM 12 Source, NM 14 Source, NM 16 The source terminal of TG9, the SP input terminal of TG 10 The SP input terminal is connected to the ground GND; NM 11 The source and NM 10 The drain end is connected to NM 13 The source and NM 12 The drain end is connected to NM 15 The source and NM 14 The drain end is connected to NM17 The source and NM 16 The drain end is connected to NM 13 The drain terminal is connected to TG 11 OUT terminal, TG 13 OUT terminal, TG 15 OUT terminal, TG 17 OUT terminal; NM 15 The drain terminal is connected to TG 19 OUT terminal; NM 17 The drain end and PM 14a～d Gate terminal, PM 14d Drain, PM 11 Gate terminal, PM 13 The gate terminal is connected; PM 14a The drain end and PM 14b The source end is connected to PM 14b The drain end and PM 14c The source end is connected to PM 14c The drain end and PM 14d The source end is connected to PM 11 Source and PM 10 The drain end is connected to PM 11 The drain terminal is connected to TG 110 IN terminal; TG 110 The OUT terminal and TG 19 IN terminal, R 1c The negative terminal of OP1 is connected to the non-inverting input terminal of OP1; PM 10 The gate terminal and PM 12 The gate terminal, C 1c The positive terminal of OP1 is connected to the output OUT terminal of OP1; C 1c The negative terminal of R 1c The positive end of PM 12 The drain end and PM 13 The source end is connected to PM 14a Source and PM 10 Source, PM 12 The source end, TG 19 SN end, TG 110 The SN terminal is connected to the power supply voltage VDD; PM 13 The drain terminal and TG 12 IN terminal, TG 14 IN terminal, TG 16 IN terminal, TG 18 The IN end of TG is connected; 11 The IN terminal and TG 12 The OUT terminal, the inverting input terminal of OP1, the non-inverting input terminal of OP2, and the output terminal CP_OUT of the charge pump are connected; TG 13The IN terminal and TG 14 The OUT terminal of OP2, the OUT terminal of OP2 and the inverting input terminal are connected; TG 16 The OUT terminal and TG 18 OUT terminal is connected to TG 15 The IN terminal and TG 17 The UP input of the charge pump is connected to the transmission gate switch TG 12 SP end, TG 14 SN end, TG 15 SN end, TG 17 The UPN input of the charge pump is connected to the SP terminal of the 12 SN end, TG 14 SP end, TG 15 SP end, TG 17 The SN terminal of the charge pump is connected to the TG 11 SN end, TG 13 SP end, TG 16 SN end, TG 18 The SP end of the charge pump is connected to the DNN input end of the TG 11 SP end, TG 13 SN end, TG 16 SP end, TG 18 SN end is connected to TG 10 The SN end of the TG is connected to the PDB port; 10 The SP end is connected to the PDBB port.

[0013] Optionally, in one embodiment of the present invention, NM 10 、NM 12 、NM 14 、NM 16 The width-to-length ratio is 1:5:1:1; NM 11 、NM 13 、NM 15 、NM 17 The aspect ratio of PM is 1:5:1:1; 10 、PM 11 、PM 12 、PM 13 、PM 14a～14d The aspect ratio is 1:1:5:5:1:1:1:1; TG 11～18 The switch size remains the same, TG 19 TG 110 The switch size remains the same and is TG 11～18 1 / 5 of.

[0014] Optionally, in one embodiment of the present invention, the rail-to-rail operational amplifier OP1 includes: NM 20 The gate terminal and NM 21 The gate terminal is connected to the VN terminal of the bias circuit; NM 20 The source and NM 21 Source, NM 24 Source, NM 25 Source, NM 28 The source end is connected to the ground GND; NM 20 The drain end and PM 20 Drain, PM 20 Gate terminal, PM 21 Gate terminal, PM 24 Gate terminal, PM 25 The gate terminal is connected to the VP terminal of the bias circuit; NM 21 The drain terminal and NM 22 Source, NM 23 The source end is connected to the OP1 INP input end and the NM 22 Gate terminal, PM 22 The gate terminal of OP1 is connected to the INN input terminal of NM 23 Gate terminal, PM 23 The gate terminal is connected; NM 22 The drain end and PM 25 Drain, PM 27 The source end is connected to NM 23 The drain end and PM 24 Drain, PM 26 The source end is connected to PM 20 Source and PM 21 Source, PM 24 Source, PM 25 Source, PM 28 The source end is connected to the power supply voltage VDD; PM 21 The drain end and PM 22 Source, PM 23 The source end is connected to PM 22 The drain terminal and NM 25 Drain terminal, NM 27 The source end is connected to PM 23 The drain terminal and NM 24 Drain terminal, NM 26 The source end is connected to NM 24 The gate terminal and NM 25 Gate terminal, NM 26 Drain, PM 26 The drain end is connected to NM 24 The drain terminal and NM 26 The source end is connected to NM25 The drain terminal and NM 27 The source end is connected to NM 26 The gate terminal and NM 27 The gate terminal is connected to the VBN terminal of the bias circuit; PM 26 The gate terminal and PM 27 The gate terminal is connected to the VBP terminal of the bias circuit; PM 25 The drain end and PM 27 The source end is connected to NM 27 The drain end and PM 27 The drain terminal, C 2c The positive end, NM 28 The gate terminal is connected; C 2c The negative terminal of R 2c The positive end is connected to NM 28 The drain end and PM 28 The drain terminal, R 2c The negative terminal of the MOSFET is connected to the OUT terminal of OP1.

[0015] Optionally, in one embodiment of the present invention, NM 20 、NM 21 The width-to-length ratio remains the same; NM 22 、NM 23 The width-to-length ratio remains the same; NM 24 、NM 25 The width-to-length ratio remains the same; NM 26 、NM 27 The aspect ratio of PM 20 、PM 21 、PM 24 、PM 25 、PM 28 The aspect ratio is 1:1:12:12:24; PM 22 、PM 23 The aspect ratio of PM 26 、PM 27 Keep the aspect ratio consistent.

[0016] Optionally, in one embodiment of the present invention, the rail-to-rail operational amplifier OP2 includes: NM 30 The gate terminal and NM 31 Gate terminal, NM 34 Gate terminal, NM 35 Gate terminal, NM 38 The gate terminal is connected to the VN terminal of the bias circuit; NM 30 The source and NM 31 Source, NM 34 Source, NM 35 Source, NM 38The source end is connected to the ground GND; NM 30 The drain end and PM 30 Drain, PM 30 Gate terminal, PM 31 The gate terminal is connected to the VP terminal of the bias circuit; NM 31 The drain terminal and NM 32 Source, NM 33 The source end is connected to the OP1 INP input end and the NM 32 Gate terminal, PM 32 The gate terminal of OP1 is connected to the INN input terminal of NM 33 Gate terminal, PM 33 The gate terminal is connected; NM 32 The drain end and PM 35 Drain, PM 37 The source end is connected to NM 33 The drain end and PM 34 Drain, PM 36 The source end is connected to PM 30 Source and PM 31 Source, PM 34 Source, PM 35 Source, PM 38 The source end is connected to the power supply voltage VDD; PM 31 The drain end and PM 32 Source, PM 33 The source end is connected to PM 32 The drain terminal and NM 35 Drain terminal, NM 37 The source end is connected to PM 33 The drain terminal and NM 34 Drain terminal, NM 36 The source end is connected to PM 34 The gate terminal and PM 35 Gate terminal, PM 36 Drain terminal, NM 36 The drain end is connected to NM 34 The drain terminal and NM 36 The source end is connected to NM 35 The drain terminal and NM 37 The source end is connected to NM 36 The gate terminal and NM 37 The gate terminal is connected to the VBN terminal of the bias circuit; PM 36 The gate terminal and PM 37 The gate terminal is connected to the VBP terminal of the bias circuit; PM 35 The drain end and PM 37 The source end is connected to NM 37 The drain end and PM 37Drain, PM 38 The gate terminal, C 3c The positive end of C 3c The negative terminal of R 3c The positive end of PM 38 The drain terminal and NM 38 The drain terminal, R 3c The negative end of the OP1 is connected to the OUT end of OP2.

[0017] Optionally, in one embodiment of the present invention, PM 30 、PM 31 The aspect ratio of PM 32 、PM 33 The aspect ratio of PM 34 、PM 35 The aspect ratio of PM 36 、PM 37 The width-to-length ratio remains the same; NM 30 、NM 31 、NM 34 、NM 35 、NM 38 The width-to-length ratio is 1:1:2:2:4; NM 32 、NM 33 The width-to-length ratio remains the same; NM 36 、NM 37 Keep the aspect ratio consistent.

[0018] Optionally, in one embodiment of the present invention, the transmission gate switch TG includes: NM 40 The drain terminal and NM 41 Source, NM 41 Drain, PM 41 Source, PM 41 Drain, PM 40 The drain end is connected to the IN end of NM 40 The source and NM 42 Source, NM 42 Drain, PM 42 Source, PM 42 Drain, PM 40 The source end is connected to the OUT end; NM 40 The gate terminal and PM 41 Gate terminal, PM 42 The gate terminal is connected to the SN terminal of the transmission gate switch; PM 40 The gate terminal and NM 41 Gate terminal, NM 42 The gate terminal is connected to the SP terminal of the transmission gate switch.

[0019] Optionally, in one embodiment of the present invention, the bias circuit includes: TG 50 The IN terminal of the TG is connected to the IBIAS input terminal of the charge pump; 50 The OUT terminal and NM 50 Drain terminal, NM 50 Gate terminal, NM 51 Gate terminal, NM 52 The gate terminal is connected to the VN terminal of the bias circuit; NM 50 Source, NM 51 Source, NM 52 Source, NM 54 Source, NM 56 The source end is connected to the ground GND; NM 51 The drain end and PM 50a～d Gate terminal, PM 50d Drain, PM 52 Gate terminal, PM 54 Gate terminal, PM 56 The gate terminal is connected; PM 50a The drain end and PM 50b The source end is connected to PM 50b The drain end and PM 50c The source end is connected to PM 50c The drain end and PM 50d The source end is connected to NM 52 The drain terminal and NM 53 The source end is connected to NM 53 The gate terminal and NM 53 Drain, PM 52 Drain, PM 51 Gate terminal, PM 53 Gate terminal, PM 55 The gate terminal is connected to the VBN terminal of the bias circuit; PM 51 The drain end and PM 52 The source end is connected to PM 53 The drain end and PM 54 The source end is connected to PM 55 The drain end and PM 56 The source end is connected to PM 50a Source and PM 51 Source, PM 53 Source, PM 55 The source end is connected to the power supply voltage VDD; PM 54 The drain terminal and NM 55 Drain terminal, NM 54 The gate terminal is connected; NM 55 The source and NM 54 The drain end is connected to PM 56The drain terminal and NM 56 Drain terminal, NM 56 Gate terminal, NM 55 The gate terminal of TG0 is connected to the VBP terminal of the bias circuit; the SN terminal of TG0 is connected to the PDB port; the SP terminal of TG0 is connected to the PDBB port.

[0020] A second embodiment of the present invention provides an integrated circuit, comprising the low-noise, low-mismatch charge pump circuit used in a frequency synthesizer circuit as described in the above embodiment.

[0021] The low-noise and low-mismatch charge pump circuit used in a frequency synthesizer circuit according to an embodiment of the present invention has the following beneficial effects:

[0022] 1. The charge pump core circuit of the present invention significantly improves current replication accuracy and suppresses non-ideal effects of the charge pump by clamping two gain-stable op amps with a current-steering structure featuring complementary switches. By employing a transmission gate switching circuit with a complementary structure and a dummy switch, high-frequency glitches are offset, the smoothness of charging and discharging is optimized, and the dynamic matching characteristics of the upper and lower current paths are ensured, thereby optimizing spurious performance.

[0023] 2. The charge pump core circuit of the present invention employs a low-voltage cascode current mirror structure to suppress the channel length effect of transistors, ensuring the current replication accuracy of the charge pump circuit. This improves the static matching characteristics of the charge pump circuit, optimizes spurious performance, and enhances the charge pump circuit's ability to suppress power supply noise.

[0024] 3. The charge pump core circuit of the present invention optimizes the charge sharing effect of the charge pump circuit by adopting two rail-to-rail operational amplifiers with stable gain and low output noise, improves the speed of charge pump switching, and effectively reduces the output current noise of the charge pump, thereby optimizing the phase noise performance of the frequency synthesizer system.

[0025] 4. The charge pump core circuit of the present invention, by adding a power-down circuit part, can cut off the input channel of the bias current when the charge pump circuit is not working, thereby realizing a low-power design of the chip.

[0026] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0028] Figure 1A schematic diagram of a charge pump core circuit according to an embodiment of the present invention;

[0029] Figure 2 Schematic diagram of a rail-to-rail operational amplifier circuit according to an embodiment of the present invention;

[0030] Figure 3 Schematic diagram of another rail-to-rail operational amplifier circuit according to an embodiment of the present invention;

[0031] Figure 4 Schematic diagram of a transmission gate switch circuit according to an embodiment of the present invention;

[0032] Figure 5 Schematic diagram of a power-down circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] The following describes embodiments of the present invention in detail, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and are not to be construed as limiting the present invention.

[0034] The low-noise and low-mismatch charge pump circuit used in a frequency synthesizer circuit of the present invention comprises a charge pump core circuit, two rail-to-rail operational amplifier circuits, eleven transmission gate switch circuits and a power-down circuit.

[0035] The core of the charge pump suppresses current mismatch and reduces output signal noise through a variety of optimized circuit structures. The rail-to-rail operational amplifier maintains stable high gain and very low output noise when the input signal changes. The transmission gate switch circuit consists of complementary switches and dummy switches to suppress the clock feedthrough and charge injection effects of the switch. The power-down circuit uses a transmission gate switch circuit, which reduces power consumption when the circuit is not operating.

[0036] like Figure 1 As shown, in one embodiment of the present invention, the charge pump core circuit includes: TG 10 The IN terminal of the TG is connected to the IBIAS input terminal of the charge pump; 10 The OUT terminal is connected to the positive terminal of R0, NM 11 Gate terminal, NM 13 Gate terminal, NM 15 Gate terminal, NM 17 The gate terminal; R 10 The negative terminal is connected to NM 11 Drain terminal, NM 10 Gate terminal, NM 12 Gate terminal, NM 14 Gate terminal, NM16 Gate terminal; NM 10 The source and NM 12 Source, NM 14 Source, NM 16 The source terminal of TG9, the SP input terminal of TG 10 The SP input terminal is connected to the ground GND; NM 11 The source and NM 10 The drain end is connected to NM 13 The source and NM 12 The drain end is connected to NM 15 The source and NM 14 The drain end is connected to NM 17 The source and NM 16 The drain end is connected to NM 13 The drain terminal is connected to TG 11 OUT terminal, TG 13 OUT terminal, TG 15 OUT terminal, TG 17 OUT terminal; NM 15 The drain terminal is connected to TG 19 OUT terminal; NM 17 The drain end and PM 14a～d Gate terminal, PM 14d Drain, PM 11 Gate terminal, PM 13 The gate terminal is connected; PM 14a The drain end and PM 14b The source end is connected to PM 14b The drain end and PM 14c The source end is connected to PM 14c The drain end and PM 14d The source end is connected to PM 11 Source and PM 10 The drain end is connected to PM 11 The drain terminal is connected to TG 110 IN terminal; TG 110 The OUT terminal and TG 19 IN terminal, R 1c The negative terminal of OP1 is connected to the non-inverting input terminal of OP1; PM 10 The gate terminal and PM 12 The gate terminal, C 1c The positive terminal of OP1 is connected to the output OUT terminal of OP1; C 1c The negative terminal of R 1c The positive end of PM 12 The drain end and PM 13 The source end is connected to PM 14a Source and PM 10 Source, PM12 The source end, TG 19 SN end, TG 110 The SN terminal is connected to the power supply voltage VDD; PM 13 The drain terminal and TG 12 IN terminal, TG 14 IN terminal, TG 16 IN terminal, TG 18 The IN end of TG is connected; 11 The IN terminal and TG 12 The OUT terminal, the inverting input terminal of OP1, the non-inverting input terminal of OP2, and the output terminal CP_OUT of the charge pump are connected; TG 13 The IN terminal and TG 14 The OUT terminal of OP2, the OUT terminal of OP2 and the inverting input terminal are connected; TG 16 The OUT terminal and TG 18 OUT terminal is connected to TG 15 The IN terminal and TG 17 The UP input of the charge pump is connected to the transmission gate switch TG 12 SP end, TG 14 SN end, TG 15 SN end, TG 17 The UPN input of the charge pump is connected to the SP terminal of the 12 SN end, TG 14 SP end, TG 15 SP end, TG 17 The SN terminal of the charge pump is connected to the TG 11 SN end, TG 13 SP end, TG 16 SN end, TG 18 The SP end of the charge pump is connected to the DNN input end of the TG 11 SP end, TG 13 SN end, TG 16 SP end, TG 18 SN end is connected to TG 10 The SN end of the TG is connected to the PDB port; 10 The SP end is connected to the PDBB port.

[0037] In one embodiment of the present invention, NM 10 、NM 12 、NM 14 、NM 16 The width-to-length ratio is 1:5:1:1; NM 11 、NM 13 、NM 15 、NM 17The aspect ratio of PM is 1:5:1:1; 10 、PM 11 、PM 12 、PM 13 、PM 14a～14d The aspect ratio is 1:1:5:5:1:1:1:1; TG 11～18 The switch size remains the same, TG 19 TG 110 The switch size remains the same and is TG 11～18 1 / 5 of.

[0038] The working principle and specific optimization of the charge pump core circuit are as follows: 10～17 , PM 11～14 A current mirror is formed to provide bias voltage for the charge pump, forming a low-voltage cascode current mirror, which suppresses the channel length effect of the transistor and improves the current replication accuracy, thereby improving the static matching characteristics of the charge pump circuit. The use of the cascode current mirror can also improve the power supply rejection ratio of the circuit; OP1 and OP2 are two rail-to-rail operational amplifiers with stable gain. The non-inverting input and inverting input of OP1 are respectively connected to the fixed level of the replication branch and the output port CP_OUT, realizing clamping between the main branch of the charge pump and the replication branch, reducing the mismatch of the circuit; the non-inverting input and inverting input of OP2 are respectively connected to the output port CP_OUT and the mirror branch to reduce the charge sharing effect; the transmission gate switch TG 11 TG 13 and transmission gate switch TG 12 TG 14 Two sets of differential switches are formed respectively, which are controlled by two sets of differential signals DN, DNN and UP, UPN respectively. The non-ideal effect of the circuit is effectively suppressed in the process of control signal conversion. When UP is low and DN is low, the transmission gate switch TG 12 TG 13 Open, transmission gate switch TG 11 TG 14 Shutdown, current flows to the CP_OUT port, the charge pump is charged, when UP is high and DN is high, the transmission gate switch TG 11 TG 14 Open, transmission gate switch TG 12 TG 13When the mirror is turned off, current flows from the CP_OUT port into the charge pump, and the charge pump discharges. The function of the op amp OP2 is to make its output constantly track the potential output of the charge pump's output terminal CP_OUT. Therefore, whether the control switches at both ends of the mirror are closed or open, the current source drains of the PMOS and NMOS tubes are always connected to the output terminal CP_OUT or the output terminal of the op amp OP2 through a set of switches, so that the current source can always remain in the on state. When the current source is needed to charge or discharge the output terminal, the current source current does not need to increase from 0 to the specified value, but directly operates at the specified current value, thereby greatly improving the speed of opening and closing the charge pump switch. The transmission gate switch TG 19 TG 110 Always keep the open state, keep the charge pump output branch open and the replica branch working in the same state, reducing the circuit mismatch; transmission gate switch TG 15 TG 17 Controlled by differential signals UP and UPN, the transmission gate switch TG 16 TG 18 Controlled by differential signals DN and DNN, it is used to balance the upper and lower loads and optimize the dynamic matching characteristics of the charge pump circuit output.

[0039] like Figure 2 As shown, in one embodiment of the present invention, the rail-to-rail operational amplifier OP1 includes: NM 20 The gate terminal and NM 21 The gate terminal is connected to the VN terminal of the bias circuit; NM 20 The source and NM 21 Source, NM 24 Source, NM 25 Source, NM 28 The source end is connected to the ground GND; NM 20 The drain end and PM 20 Drain, PM 20 Gate terminal, PM 21 Gate terminal, PM 24 Gate terminal, PM 25 The gate terminal is connected to the VP terminal of the bias circuit; NM 21 The drain terminal and NM 22 Source, NM 23 The source end is connected to the OP1 INP input end and the NM 22 Gate terminal, PM 22 The gate terminal of OP1 is connected to the INN input terminal of NM 23 Gate terminal, PM 23 The gate terminal is connected; NM 22 The drain end and PM 25 Drain, PM 27 The source end is connected to NM23 The drain end and PM 24 Drain, PM 26 The source end is connected to PM 20 Source and PM 21 Source, PM 24 Source, PM 25 Source, PM 28 The source end is connected to the power supply voltage VDD; PM 21 The drain end and PM 22 Source, PM 23 The source end is connected to PM 22 The drain terminal and NM 25 Drain terminal, NM 27 The source end is connected to PM 23 The drain terminal and NM 24 Drain terminal, NM 26 The source end is connected to NM 24 The gate terminal and NM 25 Gate terminal, NM 26 Drain, PM 26 The drain end is connected to NM 24 The drain terminal and NM 26 The source end is connected to NM 25 The drain terminal and NM 27 The source end is connected to NM 26 The gate terminal and NM 27 The gate terminal is connected to the VBN terminal of the bias circuit; PM 26 The gate terminal and PM 27 The gate terminal is connected to the VBP terminal of the bias circuit; PM 25 The drain end and PM 27 The source end is connected to NM 27 The drain end and PM 27 The drain terminal, C 2c The positive end, NM 28 The gate terminal is connected; C 2c The negative terminal of R 2c The positive end is connected to NM 28 The drain end and PM 28 The drain terminal, R 2c The negative terminal of the MOSFET is connected to the OUT terminal of OP1.

[0040] In one embodiment of the present invention, NM 20 、NM 21 The width-to-length ratio remains the same; NM 22 、NM 23 The width-to-length ratio remains the same; NM 24 、NM 25 The width-to-length ratio remains the same; NM 26 、NM27 The aspect ratio of PM 20 、PM 21 、PM 24 、PM 25 、PM 28 The aspect ratio is 1:1:12:12:24; PM 22 、PM 23 The aspect ratio of PM 26 、PM 27 Keep the aspect ratio consistent.

[0041] like Figure 3 As shown, in one embodiment of the present invention, the rail-to-rail operational amplifier OP2 includes: NM 30 The gate terminal and NM 31 Gate terminal, NM 34 Gate terminal, NM 35 Gate terminal, NM 38 The gate terminal is connected to the VN terminal of the bias circuit; NM 30 The source and NM 31 Source, NM 34 Source, NM 35 Source, NM 38 The source end is connected to the ground GND; NM 30 The drain end and PM 30 Drain, PM 30 Gate terminal, PM 31 The gate terminal is connected to the VP terminal of the bias circuit; NM 31 The drain terminal and NM 32 Source, NM 33 The source end is connected to the OP1 INP input end and the NM 32 Gate terminal, PM 32 The gate terminal of OP1 is connected to the INN input terminal of NM 33 Gate terminal, PM 33 The gate terminal is connected; NM 32 The drain end and PM 35 Drain, PM 37 The source end is connected to NM 33 The drain end and PM 34 Drain, PM 36 The source end is connected to PM 30 Source and PM 31 Source, PM 34 Source, PM 35 Source, PM 38 The source end is connected to the power supply voltage VDD; PM 31 The drain end and PM 32 Source, PM33 The source end is connected to PM 32 The drain terminal and NM 35 Drain terminal, NM 37 The source end is connected to PM 33 The drain terminal and NM 34 Drain terminal, NM 36 The source end is connected to PM 34 The gate terminal and PM 35 Gate terminal, PM 36 Drain terminal, NM 36 The drain end is connected to NM 34 The drain terminal and NM 36 The source end is connected to NM 35 The drain terminal and NM 37 The source end is connected to NM 36 The gate terminal and NM 37 The gate terminal is connected to the VBN terminal of the bias circuit; PM 36 The gate terminal and PM 37 The gate terminal is connected to the VBP terminal of the bias circuit; PM 35 The drain end and PM 37 The source end is connected to NM 37 The drain end and PM 37 Drain, PM 38 The gate terminal, C 3c The positive end of C 3c The negative terminal of R 3c The positive end of PM 38 The drain terminal and NM 38 The drain terminal, R 3c The negative end of the OP1 is connected to the OUT end of OP2.

[0042] In one embodiment of the present invention, PM 30 、PM 31 The aspect ratio of PM 32 、PM 33 The aspect ratio of PM 34 、PM 35 The aspect ratio of PM 36 、PM 37 The width-to-length ratio remains the same; NM 30 、NM 31 、NM 34 、NM 35 、NM 38 The width-to-length ratio is 1:1:2:2:4; NM 32 、NM 33 The width-to-length ratio remains the same; NM 36 、NM 37 Keep the aspect ratio consistent.

[0043] like Figure 4 As shown, in one embodiment of the present invention, the transmission gate switch TG includes: NM 40 The drain terminal and NM 41 Source, NM 41 Drain, PM 41 Source, PM 41 Drain, PM 40 The drain end is connected to the IN end of NM 40 The source and NM 42 Source, NM 42 Drain, PM 42 Source, PM 42 Drain, PM 40 The source end is connected to the OUT end; NM 40 The gate terminal and PM 41 Gate terminal, PM 42 The gate terminal is connected to the SN terminal of the transmission gate switch; PM 40 The gate terminal and NM 41 Gate terminal, NM 42 The gate terminal is connected to the SP terminal of the transmission gate switch.

[0044] In one embodiment of the present invention, NM 40 、NM 41 、NM 42 The aspect ratio of PM is 2:1:1; 40 、PM 41 、PM 42 The width-to-length ratio is 2:1:1.

[0045] like Figure 5 As shown, in one embodiment of the present invention, the bias circuit includes: TG 50 The IN terminal of the TG is connected to the IBIAS input terminal of the charge pump; 50 The OUT terminal and NM 50 Drain terminal, NM 50 Gate terminal, NM 51 Gate terminal, NM 52 The gate terminal is connected to the VN terminal of the bias circuit; NM 50 Source, NM 51 Source, NM 52 Source, NM 54 Source, NM 56 The source end is connected to the ground GND; NM 51 The drain end and PM 50a～d Gate terminal, PM 50d Drain, PM 52 Gate terminal, PM54 Gate terminal, PM 56 The gate terminal is connected; PM 50a The drain end and PM 50b The source end is connected to PM 50b The drain end and PM 50c The source end is connected to PM 50c The drain end and PM 50d The source end is connected to NM 52 The drain terminal and NM 53 The source end is connected to NM 53 The gate terminal and NM 53 Drain, PM 52 Drain, PM 51 Gate terminal, PM 53 Gate terminal, PM 55 The gate terminal is connected to the VBN terminal of the bias circuit; PM 51 The drain end and PM 52 The source end is connected to PM 53 The drain end and PM 54 The source end is connected to PM 55 The drain end and PM 56 The source end is connected to PM 50a Source and PM 51 Source, PM 53 Source, PM 55 The source end is connected to the power supply voltage VDD; PM 54 The drain terminal and NM 55 Drain terminal, NM 54 The gate terminal is connected; NM 55 The source and NM 54 The drain end is connected to PM 56 The drain terminal and NM 56 Drain terminal, NM 56 Gate terminal, NM 55 The gate terminal of TG0 is connected to the VBP terminal of the bias circuit; the SN terminal of TG0 is connected to the PDB port; the SP terminal of TG0 is connected to the PDBB port.

[0046] In one embodiment of the present invention, NM 50 、NM 51 、NM 52 The width-to-length ratio of PM is consistent; 50a～50d 、PM 51 、PM 52 、PM 53 、PM 54 、PM 55 、PM 56 The width-to-length ratio is consistent; NM 54 、NM 55 、NM56 The width-to-length ratio is consistent.

[0047] The low-noise, low-mismatch charge pump circuit used in a frequency synthesizer circuit according to an embodiment of the present invention primarily optimizes the core components, significantly improving the circuit's static and dynamic matching characteristics. An optimized design is also employed for the rail-to-rail operational amplifier therein, ensuring its output noise is as low as possible while maintaining stable gain. Compared to conventional charge pumps, the present invention utilizes a current-steering charge pump structure. The "double-clamp" structure of two rail-to-rail operational amplifiers effectively stabilizes the DC point of the charge pump output port, significantly reducing the impact of the charge sharing effect on the output signal. Furthermore, the use of complementary switches and dummy switches effectively avoids mismatch currents caused by single-tube switches, reducing non-idealities caused by clock feedthrough and charge injection effects. This results in the entire charge pump circuit having excellent matching characteristics and relatively good noise characteristics. Furthermore, because the current flowing into the power supply and the ground current of the charge pump can be continuously stable, the charge pump structure exhibits low power supply crosstalk. Furthermore, the present invention utilizes a low-voltage cascode current mirror to improve current replication accuracy and the ability to suppress power supply noise.

[0048] The charge pump core suppresses current mismatch and reduces output signal noise through multiple optimized circuit structures. A rail-to-rail operational amplifier ensures the stability of the charge pump circuit's output DC point, reducing the charge pump's charge-sharing effect. The transmission gate switch circuit reduces the static and dynamic mismatch between the upper and lower current paths, weakening the charge pump circuit's clock feedthrough and charge injection effects. The power-down circuit shuts off the input current when the circuit is not operating, reducing system power consumption. The charge pump technology described in this invention achieves low output noise and low current mismatch in the charge pump circuit, increases charge pump switching speed, and provides improved immunity to power supply noise, thereby enhancing the spurious and noise performance of the frequency synthesizer.

[0049] The present invention further provides an integrated circuit comprising the low-noise and low-mismatch charge pump circuit described in the above embodiment for use in a frequency synthesizer circuit.

[0050] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction.

[0051] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "N" means at least two, such as two, three, etc., unless otherwise specifically defined.

Claims

1. A low-noise, low-mismatch charge pump circuit for use in a frequency synthesizer circuit, characterized in that: include: The charge pump core circuit uses a variety of optimized circuit structures to suppress current mismatch; A rail-to-rail operational amplifier circuit, used to maintain the stability of the DC output point of the charge pump core circuit when the input signal changes; The transmission gate switch circuit consists of a complementary switch and a dummy switch to suppress the clock feedthrough and charge injection effects of the switch; The power-down circuit uses a transmission gate switch circuit to cut off the input current when the circuit is not working, thereby reducing power consumption.

2. The circuit according to claim 1, wherein: The charge pump core circuit includes: TG 10 The IN terminal of the TG is connected to the IBIAS input terminal of the charge pump; 10 The OUT terminal is connected to the positive terminal of R0, NM 11 Gate terminal, NM 13 Gate terminal, NM 15 Gate terminal, NM 17 The gate terminal; R 10 The negative terminal is connected to NM 11 Drain terminal, NM 10 Gate terminal, NM 12 Gate terminal, NM 14 Gate terminal, NM 16 Gate terminal; NM 10 The source and NM 12 Source, NM 14 Source, NM 16 The source terminal of TG9, the SP input terminal of TG 10 The SP input terminal is connected to the ground GND; NM 11 The source and NM 10 The drain end is connected to NM 13 The source and NM 12 The drain end is connected to NM 15 The source and NM 14 The drain end is connected to NM 17 The source and NM 16 The drain end is connected to NM 13 The drain terminal is connected to TG 11 OUT terminal, TG 13 OUT terminal, TG 15 OUT terminal, TG 17 OUT terminal; NM 15 The drain terminal is connected to TG 19 OUT terminal; NM 17 The drain end and PM 14a～d Gate terminal, PM 14d Drain, PM 11 Gate terminal, PM 13 The gate terminal is connected; PM 14a The drain end and PM 14b The source end is connected to PM 14b The drain end and PM 14c The source end is connected to PM 14c The drain end and PM 14d The source end is connected to PM 11 Source and PM 10 The drain end is connected to PM 11 The drain terminal is connected to TG 110 IN terminal; TG 110 The OUT terminal and TG 19 IN terminal, R 1c The negative terminal of OP1 is connected to the non-inverting input terminal of OP1; PM 10 The gate terminal and PM 12 The gate terminal, C 1c The positive terminal of OP1 is connected to the output OUT terminal of OP1; C 1c The negative terminal of R 1c The positive end of PM 12 The drain end and PM 13 The source end is connected to PM 14a Source and PM 10 Source, PM 12 The source end, TG 19 SN end, TG 110 The SN terminal is connected to the power supply voltage VDD; PM 13 The drain terminal and TG 12 IN terminal, TG 14 IN terminal, TG 16 IN terminal, TG 18 The IN end of TG is connected; 11 The IN terminal and TG 12 The OUT terminal, the inverting input terminal of OP1, the non-inverting input terminal of OP2, and the output terminal CP_OUT of the charge pump are connected; TG 13 The IN terminal and TG 14 The OUT terminal of OP2, the OUT terminal of OP2 and the inverting input terminal are connected; TG 16 The OUT terminal and TG 18 OUT terminal is connected to TG 15 The IN terminal and TG 17 The UP input of the charge pump is connected to the transmission gate switch TG 12 SP end, TG 14 SN end, TG 15 SN end, TG 17 The UPN input of the charge pump is connected to the SP terminal of the 12 SN end, TG 14 SP end, TG 15 SP end, TG 17 The SN terminal of the charge pump is connected to the TG 11 SN end, TG 13 SP end, TG 16 SN end, TG 18 The SP end of the charge pump is connected to the DNN input end of the TG 11 SP end, TG 13 SN end, TG 16 SP end, TG 18 SN end is connected to TG 10 The SN end of the TG is connected to the PDB port; 10 The SP end is connected to the PDBB port.

3. The circuit according to claim 2, characterized in that NM 10 、NM 12 、NM 14 、NM 16 The width-to-length ratio is 1:5:1:1; NM 11 、NM 13 、NM 15 、NM 17 The aspect ratio of PM is 1:5:1:1; 10 、PM 11 、PM 12 、PM 13 、PM 14a～14d The aspect ratio is 1:1:5:5:1:1:1:1; TG 11～18 The switch size remains the same, TG 19 TG 110 The switch size remains the same and is TG 11～18 1 / 5 of.

4. The circuit according to claim 1, wherein: The rail-to-rail operational amplifier OP1 includes: NM 20 The gate terminal and NM 21 The gate terminal is connected to the VN terminal of the bias circuit; NM 20 The source and NM 21 Source, NM 24 Source, NM 25 Source, NM 28 The source end is connected to the ground GND; NM 20 The drain end and PM 20 Drain, PM 20 Gate terminal, PM 21 Gate terminal, PM 24 Gate terminal, PM 25 The gate terminal is connected to the VP terminal of the bias circuit; NM 21 The drain terminal and NM 22 Source, NM 23 The source end is connected to the OP1 INP input end and the NM 22 Gate terminal, PM 22 The gate terminal of OP1 is connected to the INN input terminal of NM 23 Gate terminal, PM 23 The gate terminal is connected; NM 22 The drain end and PM 25 Drain, PM 27 The source end is connected to NM 23 The drain end and PM 24 Drain, PM 26 The source end is connected to PM 20 Source and PM 21 Source, PM 24 Source, PM 25 Source, PM 28 The source end is connected to the power supply voltage VDD; PM 21 The drain end and PM 22 Source, PM 23 The source end is connected to PM 22 The drain terminal and NM 25 Drain terminal, NM 27 The source end is connected to PM 23 The drain terminal and NM 24 Drain terminal, NM 26 The source end is connected to NM 24 The gate terminal and NM 25 Gate terminal, NM 26 Drain, PM 26 The drain end is connected to NM 24 The drain terminal and NM 26 The source end is connected to NM 25 The drain terminal and NM 27 The source end is connected to NM 26 The gate terminal and NM 27 The gate terminal is connected to the VBN terminal of the bias circuit; PM 26 The gate terminal and PM 27 The gate terminal is connected to the VBP terminal of the bias circuit; PM 25 The drain end and PM 27 The source end is connected to NM 27 The drain end and PM 27 The drain terminal, C 2c The positive end, NM 28 The gate terminal is connected; C 2c The negative terminal of R 2c The positive end is connected to NM 28 The drain end and PM 28 The drain terminal, R 2c The negative terminal of the MOSFET is connected to the OUT terminal of OP1.

5. The circuit according to claim 4, characterized in that NM 20 、NM 21 The width-to-length ratio remains the same; NM 22 、NM 23 The width-to-length ratio remains the same; NM 24 、NM 25 The width-to-length ratio remains the same; NM 26 、NM 27 The aspect ratio of PM 20 、PM 21 、PM 24 、PM 25 、PM 28 The aspect ratio is 1:1:12:12:24; PM 22 、PM 23 The aspect ratio of PM 26 、PM 27 Keep the aspect ratio consistent.

6. The circuit according to claim 1, wherein: The rail-to-rail operational amplifier OP2 includes: NM 30 The gate terminal and NM 31 Gate terminal, NM 34 Gate terminal, NM 35 Gate terminal, NM 38 The gate terminal is connected to the VN terminal of the bias circuit; NM 30 The source and NM 31 Source, NM 34 Source, NM 35 Source, NM 38 The source end is connected to the ground GND; NM 30 The drain end and PM 30 Drain, PM 30 Gate terminal, PM 31 The gate terminal is connected to the VP terminal of the bias circuit; NM 31 The drain terminal and NM 32 Source, NM 33 The source end is connected to the OP1 INP input end and the NM 32 Gate terminal, PM 32 The gate terminal of OP1 is connected to the INN input terminal of NM 33 Gate terminal, PM 33 The gate terminal is connected; NM 32 The drain end and PM 35 Drain, PM 37 The source end is connected to NM 33 The drain end and PM 34 Drain, PM 36 The source end is connected to PM 30 Source and PM 31 Source, PM 34 Source, PM 35 Source, PM 38 The source end is connected to the power supply voltage VDD; PM 31 The drain end and PM 32 Source, PM 33 The source end is connected to PM 32 The drain terminal and NM 35 Drain terminal, NM 37 The source end is connected to PM 33 The drain terminal and NM 34 Drain terminal, NM 36 The source end is connected to PM 34 The gate terminal and PM 35 Gate terminal, PM 36 Drain terminal, NM 36 The drain end is connected to NM 34 The drain terminal and NM 36 The source end is connected to NM 35 The drain terminal and NM 37 The source end is connected to NM 36 The gate terminal and NM 37 The gate terminal is connected to the VBN terminal of the bias circuit; PM 36 The gate terminal and PM 37 The gate terminal is connected to the VBP terminal of the bias circuit; PM 35 The drain end and PM 37 The source end is connected to NM 37 The drain end and PM 37 Drain, PM 38 The gate terminal, C 3c The positive end of C 3c The negative terminal of R 3c The positive end of PM 38 The drain terminal and NM 38 The drain terminal, R 3c The negative end of the OP1 is connected to the OUT end of OP2.

7. The circuit according to claim 6, characterized in that PM 30 、PM 31 The aspect ratio of PM 32 、PM 33 The aspect ratio of PM 34 、PM 35 The aspect ratio of PM 36 、PM 37 The width-to-length ratio remains the same; NM 30 、NM 31 、NM 34 、NM 35 、NM 38 The width-to-length ratio is 1:1:2:2:4; NM 32 、NM 33 The width-to-length ratio remains the same; NM 36 、NM 37 Keep the aspect ratio consistent.

8. The circuit according to claim 1, wherein: The transmission gate switch TG includes: NM 40 The drain terminal and NM 41 Source, NM 41 Drain, PM 41 Source, PM 41 Drain, PM 40 The drain end is connected to the IN end of NM 40 The source and NM 42 Source, NM 42 Drain, PM 42 Source, PM 42 Drain, PM 40 The source end is connected to the OUT end; NM 40 The gate terminal and PM 41 Gate terminal, PM 42 The gate terminal is connected to the SN terminal of the transmission gate switch; PM 40 The gate terminal and NM 41 Gate terminal, NM 42 The gate terminal is connected to the SP terminal of the transmission gate switch.

9. The circuit according to claim 1, wherein: The bias circuit includes: TG 50 The IN terminal of the TG is connected to the IBIAS input terminal of the charge pump; 50 The OUT terminal and NM 50 Drain terminal, NM 50 Gate terminal, NM 51 Gate terminal, NM 52 The gate terminal is connected to the VN terminal of the bias circuit; NM 50 Source, NM 51 Source, NM 52 Source, NM 54 Source, NM 56 The source end is connected to the ground GND; NM 51 The drain end and PM 50a～d Gate terminal, PM 50d Drain, PM 52 Gate terminal, PM 54 Gate terminal, PM 56 The gate terminal is connected; PM 50a The drain end and PM 50b The source end is connected to PM 50b The drain end and PM 50c The source end is connected to PM 50c The drain end and PM 50d The source end is connected to NM 52 The drain terminal and NM 53 The source end is connected to NM 53 The gate terminal and NM 53 Drain, PM 52 Drain, PM 51 Gate terminal, PM 53 Gate terminal, PM 55 The gate terminal is connected to the VBN terminal of the bias circuit; PM 51 The drain end and PM 52 The source end is connected to PM 53 The drain end and PM 54 The source end is connected to PM 55 The drain end and PM 56 The source end is connected to PM 50a Source and PM 51 Source, PM 53 Source, PM 55 The source end is connected to the power supply voltage VDD; PM 54 The drain terminal and NM 55 Drain terminal, NM 54 The gate terminal is connected; NM 55 The source and NM 54 The drain end is connected to PM 56 The drain terminal and NM 56 Drain terminal, NM 56 Gate terminal, NM 55 The gate terminal of TG0 is connected to the VBP terminal of the bias circuit; the SN terminal of TG0 is connected to the PDB port; the SP terminal of TG0 is connected to the PDBB port.

10. An integrated circuit, characterized in that: The invention comprises the low-noise and low-mismatch charge pump circuit used in a frequency synthesizer circuit as described in any one of claims 1 to 9.

Images