Control method, device, equipment and product for dual three-level inverter

Abstract

The invention discloses a control method, device, equipment and product of a dual three-level inverter, and the method comprises the steps: obtaining a zero-sequence current and a neutral-point potential in the dual three-level inverter when the dual three-level inverter operates; traversing all selectable clamping combinations, and calculating the zero-sequence voltage of the dual three-level inverter and the neutral-point current of the dual three-level inverter which are correspondingly generated; and selecting the corresponding clamping combination when the positive and negative directions of the zero-sequence voltage and the zero-sequence current are opposite and the positive and negative directions of the midpoint current and the midpoint potential are opposite as the clamping combination selected by the first three-level inverter and the second three-level inverter. According to the dual three-level inverter, the appropriate clamping combination of the first three-level inverter and the second three-level inverter can be selected, zero-sequence current suppression and neutral-point potential balance in the dual three-level inverter are achieved, the output performance of the dual three-level inverter is improved, meanwhile, the switching action frequency of the dual three-level inverter can be reduced, and therefore switching loss is reduced.

Description

Technical Field

[0001] The present invention belongs to the field of dual three-level inverters, and in particular relates to a control method, device, equipment and product for a dual three-level inverter. Background Art

[0002] The dual three-level inverter for permanent magnet synchronous motors is driven by two three-level inverters, so it has high flexibility, strong fault tolerance and high DC voltage utilization. It is widely used in new energy electric vehicles, aerospace and other fields.

[0003] Dual three-level inverters offer the advantages of reduced costs and a simple system structure, as the two inverters only need to share a single power supply. However, a disadvantage is that the direct connection of the two inverters, which share a single power supply, creates a zero-sequence path and generates zero-sequence current. Therefore, there is a need to suppress the zero-sequence current. At the same time, the midpoint potential balance of the dual three-level inverters also needs to be addressed. Summary of the Invention

[0004] In view of this, the present invention aims to overcome the defects in the prior art and proposes a control method, device, equipment and product for a dual three-level inverter.

[0005] To achieve the above object, the technical solution of the present invention is achieved as follows: In a first aspect, the present invention discloses a control method for a dual three-level inverter, wherein the dual three-level inverter is composed of a first three-level inverter and a second three-level inverter, including: Obtaining the zero-sequence current and midpoint potential in the dual three-level inverter when the dual three-level inverter is running; Traversing all optional clamping combinations when the first three-level inverter and the second three-level inverter output the required AC voltage, and calculating the corresponding zero-sequence voltage of the dual three-level inverter and the midpoint current of the dual three-level inverter; A clamping combination corresponding to when the zero-sequence voltage and the zero-sequence current are in opposite directions and the midpoint current and the midpoint potential are in opposite directions is selected as the clamping combination selected by the first three-level inverter and the second three-level inverter.

[0006] In one embodiment of the present invention, all optional clamping combinations when the first three-level inverter and the second three-level inverter output AC voltages are traversed to calculate the corresponding generated zero-sequence voltage and midpoint current of the dual three-level inverter, including: the zero-sequence voltage of the dual three-level inverter is the difference between the zero-sequence voltage generated by the first three-level inverter and the zero-sequence voltage generated by the second three-level inverter; and the midpoint current of the dual three-level inverter is the difference between the midpoint current generated by the first three-level inverter and the midpoint current generated by the second three-level inverter.

[0007] In one embodiment of the present invention, all optional clamp combinations include: all clamp combinations in which one phase is fixed at an optional clamp when the first three-level inverter outputs the required AC voltage and one phase is fixed at an optional clamp when the second three-level inverter outputs the required AC voltage.

[0008] In one embodiment of the present invention, the zero-sequence voltage generated by the first three-level inverter is the average zero-sequence voltage generated by the first three-level inverter within one carrier cycle; and the zero-sequence voltage generated by the second three-level inverter is the average zero-sequence voltage generated by the second three-level inverter within one carrier cycle.

[0009] In one embodiment of the present invention, the average zero-sequence voltage of the first three-level inverter is the average value of the product of the voltage values of the switching states of the zero vector, the one vector, and the two vectors of the first three-level inverter with respect to the midpoint of the DC side and the corresponding action time within one carrier cycle; the average zero-sequence voltage of the second three-level inverter is the average value of the product of the voltage values of the switching states of the zero vector, the one vector, and the two vectors of the second three-level inverter with respect to the midpoint of the DC side and the corresponding action time within one carrier cycle.

[0010] In one embodiment of the present invention, the midpoint current generated by the first three-level inverter is the average midpoint current of the first three-level inverter in one carrier cycle, and the midpoint current generated by the second three-level inverter is the average midpoint current of the second three-level inverter in one carrier cycle.

[0011] In a second aspect, the present invention discloses a control device for a dual three-level inverter, the device comprising: An acquisition module is used to acquire the zero-sequence current and midpoint potential in the dual three-level inverter when the dual three-level inverter is in operation; the dual three-level inverter is composed of a first three-level inverter and a second three-level inverter; a calculation module, configured to traverse all optional clamping combinations when the first three-level inverter and the second three-level inverter output the required AC voltage, and calculate the corresponding zero-sequence voltage of the dual three-level inverter and the midpoint current of the dual three-level inverter; The selection module is used to select a clamping combination corresponding to when the zero-sequence voltage and the zero-sequence current are in opposite directions and the midpoint current and the midpoint potential are in opposite directions, as the clamping combination selected by the first three-level inverter and the second three-level inverter.

[0012] In a third aspect, the present invention discloses an electronic device comprising: one or more processors; a storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the above method.

[0013] In a fourth aspect, the present invention discloses a computer-readable storage medium having a computer program stored thereon, which implements the above method when executed by a processor.

[0014] In a fifth aspect, the present invention discloses a computer program product, comprising a computer program, which is executed by a processor to execute the above method.

[0015] Compared with the prior art, the present invention has the following advantages: The present invention discloses a control method, device, equipment, and product for a dual three-level inverter, comprising: obtaining a zero-sequence current and a midpoint potential in the dual three-level inverter when the dual three-level inverter is in operation; traversing all optional clamping combinations when a first three-level inverter and a second three-level inverter output a required AC voltage, and calculating the corresponding generated zero-sequence voltage of the dual three-level inverter and the midpoint current of the dual three-level inverter; selecting a clamping combination corresponding to when the zero-sequence voltage and the zero-sequence current are opposite in positive and negative directions, and the midpoint current and the midpoint potential are opposite in positive and negative directions, as the clamping combination selected by the first three-level inverter and the second three-level inverter. The present invention discloses a control method, device, equipment, and product for a dual three-level inverter, which can select an appropriate clamping combination of the first three-level inverter and the second three-level inverter, achieve zero-sequence current suppression and midpoint potential balance in the dual three-level inverter, improve the output performance of the dual three-level inverter, and at the same time save the number of switching operations of the dual three-level inverter, thereby reducing switching losses. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which constitute a part of the present invention, are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0017] In the attached figure: Figure 1 Schematic diagram of a control method for a dual three-level inverter according to an embodiment of the present invention; Figure 2 Schematic diagram of a dual three-level inverter according to an embodiment of the present invention; Figure 3 A schematic diagram of a three-level space vector diagram of a three-level inverter according to an embodiment of the present invention; Figure 4 Schematic diagram of a control device for a dual three-level inverter according to an embodiment of the present invention; Figure 5 The present invention provides a control electronic device for a dual three-level inverter according to an embodiment of the present invention. DETAILED DESCRIPTION

[0018] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0019] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention.

[0020] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0021] In the description of the present invention, it should be further clarified that the terms "first," "second," etc. are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first," "second," etc. may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0022] Dual three-level inverters offer advantages such as reduced costs and a simple system structure, as both inverters share a single power supply. However, a disadvantage is that the direct connection of the two inverters, sharing a single power supply, creates a zero-sequence path, generating zero-sequence current. This leads to the need to suppress the zero-sequence current and, at the same time, address the issue of midpoint potential balance within the dual three-level inverter. The present invention discloses a control method, apparatus, device, and product for a dual three-level inverter. By selecting a suitable clamping combination of a first three-level inverter and a second three-level inverter, this method suppresses zero-sequence current and balances the midpoint potential within the dual three-level inverter, improving the output performance of the dual three-level inverter while reducing the number of switching operations within the dual three-level inverter, thereby reducing switching losses.

[0023] The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0024] In one embodiment of the present invention, Figure 1 and Figure 2As shown, a control method for a dual three-level inverter, the method comprising: Step S101: The dual three-level inverter is composed of a first three-level inverter and a second three-level inverter, and a zero-sequence current and a midpoint potential in the dual three-level inverter are obtained when the dual three-level inverter is in operation. Step S102: traverse all optional clamping combinations when the first three-level inverter and the second three-level inverter output the required AC voltage, and calculate the corresponding dual three-level inverter zero-sequence voltage and dual three-level inverter midpoint current; In this embodiment, all optional clamping combinations when the first three-level inverter and the second three-level inverter output AC voltages are traversed, and corresponding zero-sequence voltages and midpoint currents of the dual three-level inverters are calculated. This includes: the zero-sequence voltage of the dual three-level inverter is a difference between a zero-sequence voltage generated by the first three-level inverter and a zero-sequence voltage generated by the second three-level inverter; and the midpoint current of the dual three-level inverter is a difference between a midpoint current generated by the first three-level inverter and a midpoint current generated by the second three-level inverter.

[0025] In this embodiment, based on 180-degree decoupling, the following relationship exists: ; in, V ref is the synthetic voltage vector of the dual three-level inverter system, V ref1 is the resultant voltage vector of the first three-level inverter, V ref2 is the resultant voltage vector of the second three-level inverter; Furthermore, the zero-sequence voltage of the dual three-level inverter has the following relationship: ; in, is the zero-sequence voltage of the dual three-level inverter; is the zero-sequence voltage generated by the first three-level inverter; is the zero-sequence voltage generated by the second three-level inverter; Furthermore, there is the following relationship: ; in, is the midpoint current of the dual three-level inverter; is the midpoint current generated by the first three-level inverter; is the midpoint current generated by the second three-level inverter; Step S103: Selecting a clamping combination corresponding to the case where the zero-sequence voltage and the zero-sequence current are opposite in positive and negative directions, and the midpoint current and the midpoint potential are opposite in positive and negative directions, as the clamping combination selected by the first three-level inverter and the second three-level inverter.

[0026] Furthermore, for example, the following relationship is known to exist: ; in, Indicates the zero-sequence current of the dual three-level inverter, Indicates the zero-sequence voltage of the dual three-level inverter; Therefore, when the selected clamp combination makes the zero-sequence voltage and the zero-sequence current in opposite directions, the zero-sequence current can be clamped. inhibition; For example, the following relationship is known to exist: ; in, Indicates the midpoint potential of the dual three-level inverter, Indicates the midpoint current of the dual three-level inverter; Therefore, when the selected clamp combination makes the midpoint current and the midpoint potential in opposite directions, the midpoint potential can be The balancing effect; In the previous embodiment, in another embodiment of the present invention, the zero-sequence voltage generated by the first three-level inverter is an average zero-sequence voltage generated by the first three-level inverter within one carrier cycle; and the zero-sequence voltage generated by the second three-level inverter is an average zero-sequence voltage generated by the second three-level inverter within one carrier cycle.

[0027] In the previous embodiment, in another embodiment of the present invention, the average zero-sequence voltage of the first three-level inverter is an average value of the product of the voltage values of the switching states of the zero vector, the one vector, and the two vectors of the first three-level inverter with respect to the midpoint of the DC side and the corresponding action time within one carrier cycle; and the average zero-sequence voltage of the second three-level inverter is an average value of the product of the voltage values of the switching states of the zero vector, the one vector, and the two vectors of the second three-level inverter with respect to the midpoint of the DC side and the corresponding action time within one carrier cycle.

[0028] In this embodiment, illustratively, there is the following relationship: ; in, Indicates the zero-sequence voltage of the dual three-level inverter; Represents a carrier cycle; T 0 、T 1 as well as T2 Indicates the action time of zero vector, one vector and two vectors within a carrier cycle; V 0x 、 V 1x 、V 2x are the switching states of the zero vector, one vector, and two vectors of the current inverter x (x=1, 2; x=1 is the first three-level inverter, x=2 is the second three-level inverter) with respect to the voltage at the DC side midpoint; For example, V 11 When it is a vector ONN state, V 11 = - ; For example, when inverter 1 generates vectors in the first and second small sectors of the first large sector, the following relationship exists: ; in, Represents a carrier cycle; =max( A , B , C ), =mid( A , B , C ), =min( A , B , C ), 、 as well as Respectively represent the maximum value, the middle value and the minimum value; A , B , C It is the A, B, and C three-phase reference voltage of any inverter.

[0029] In the previous embodiment, in another embodiment of the present invention, the midpoint current generated by the first three-level inverter is an average midpoint current of the first three-level inverter within one carrier cycle, and the midpoint current generated by the second three-level inverter is an average midpoint current of the second three-level inverter within one carrier cycle.

[0030] For example, there is the following relationship ; in, Indicates the midpoint current of the dual three-level inverter; is the DC side voltage of the dual three-level inverter; yes Can represent Three-phase, The first three-level inverter Phase reference voltage, The second three-level inverter The phase reference voltage can be obtained from the motor system through the double closed-loop control part; It corresponds Phase current; In the previous embodiment, in another embodiment of the present invention, all optional clamping combinations include: all clamping combinations in which one phase is fixed at an optional clamp when the first three-level inverter outputs the required AC voltage and one phase is fixed at an optional clamp when the second three-level inverter outputs the required AC voltage.

[0031] For example, Figure 3 As shown in FIG, when the voltage vector synthesized by the first three-level inverter and the second three-level inverter is in the 1st and 2nd small sectors of the first large sector and the 1st and 2nd small sectors of the fourth large sector, all existing clamping states are combined, and then the positive and negative states of the corresponding zero-sequence voltage and midpoint current are calculated, as shown in Table 1: Table 1: Zero-sequence voltage and midpoint current status in the first large sector 1 and the second small sector

[0032] In Table 1, “+” represents that the current zero-sequence voltage or midpoint current state is positive, “-” represents that the current zero-sequence voltage or midpoint current state is negative, “\” represents that the positive and negative states of the zero-sequence voltage in this small sector are not unique, and “0” represents that the midpoint current in the current combination is zero.

[0033] Furthermore, a clamping combination corresponding to when the zero-sequence voltage and the zero-sequence current are in opposite directions and the midpoint current and the midpoint potential are in opposite directions is selected as the clamping combination selected by the first three-level inverter and the second three-level inverter.

[0034] Furthermore, based on the above clamping combinations, the clamping combinations can be further screened according to the following criteria: the zero-sequence voltage or midpoint current has the same positive and negative states in small sectors 1 and 2 (adjacent small sectors) and does not contain "\" or "0". At the same time, the calculated zero-sequence voltage is excluded, and the clamping combinations in Table 2 are obtained as the retained clamping combinations for the first three-level inverter and the second three-level inverter: Table 2 Zero-sequence voltage and midpoint current corresponding to the inverter clamping state

[0035] In this embodiment, according to the positive and negative states of the zero-sequence current and the mid-point potential in the current system, the zero-sequence current is used as the horizontal axis and the mid-point potential is used as the vertical axis. According to the obtained positive and negative states, it is divided into four quadrants. According to the zero-sequence current and the mid-point potential in the current system, the two inverters respectively select the corresponding clamping state with suppression and balancing effects to suppress and balance the zero-sequence current and the mid-point potential.

[0036] Similarly, when the voltage vector synthesized by the first three-level inverter and the second three-level inverter is in another large sector, the above process can also be used to select an appropriate clamping combination for the first three-level inverter and the second three-level inverter, thereby achieving zero-sequence current suppression and midpoint potential balance of the dual three-level inverter in the dual three-level inverter. At the same time, because both the first three-level inverter and the second three-level inverter have limited clamping, the number of switching operations of the dual three-level inverter is reduced, thereby reducing switching losses.

[0037] Compared with the traditional method for suppressing zero-sequence current, the present invention does not add additional third harmonics to the current.

[0038] like Figure 4 As shown, the present invention also discloses a control device for a dual three-level inverter, comprising: An acquisition module 401 is configured to acquire a zero-sequence current and a midpoint potential in the dual three-level inverter when the dual three-level inverter is in operation; the dual three-level inverter is composed of a first three-level inverter and a second three-level inverter; a calculation module 402 configured to traverse all optional clamping combinations when the first three-level inverter and the second three-level inverter output the required AC voltage, and calculate the corresponding zero-sequence voltage of the dual three-level inverter and the midpoint current of the dual three-level inverter; The selection module 403 is configured to select a clamping combination corresponding to when the zero-sequence voltage and the zero-sequence current are opposite in positive and negative directions, and the midpoint current and the midpoint potential are opposite in positive and negative directions, as the clamping combination selected by the first three-level inverter and the second three-level inverter.

[0039] The present invention also discloses an electronic device, such as Figure 5 As shown, an embodiment is disclosed, which is a block diagram of an electronic device suitable for controlling the dual three-level inverter.

[0040] The electronic device 50 of this embodiment includes a processor 501, which can perform various appropriate actions and processes according to the program stored in the ROM 502 or the program loaded from the storage part 508 into the RAM 503. The processor 501 may include, for example, a general-purpose microprocessor, an instruction set processor and / or a related chipset and / or a dedicated microprocessor, etc. The processor 501 may also include onboard memory for caching purposes. The processor 501 may include a single processing unit or multiple processing units for performing different actions of the method flow according to the embodiment of the present invention.

[0041] RAM 503 stores various programs and data required for the operation of electronic device 50. Processor 501, ROM 502, and RAM 503 are interconnected via bus 504. Processor 501 executes the programs in ROM 502 and / or RAM 503 to perform various operations according to the method flow of the embodiment of the present invention. It should be noted that the programs may also be stored in one or more memories other than ROM 502 and RAM 503, and processor 501 may also execute the programs stored in one or more memories to perform various operations according to the method flow of the embodiment of the present invention.

[0042] According to an embodiment of the present invention, the electronic device 50 may further include an I / O interface 505, which is also connected to the bus 504. The electronic device 50 may further include one or more of the following components connected to the I / O interface 505: an input portion 506 including a keyboard, a mouse, etc.; an output portion 507 including a cathode ray tube, a liquid crystal display, and a speaker; a storage portion 508 including a hard disk; and a communication portion 509 including a network interface card such as a LAN card or a modem. The communication portion 509 performs communication processing via a network such as the Internet. A drive 5010 is also connected to the I / O interface 505 as needed. A removable medium 5011, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed in the drive 5010 as needed, so that a computer program read therefrom can be installed into the storage portion 508 as needed.

[0043] The present invention also provides a computer-readable storage medium.

[0044] The computer-readable storage medium may be included in the electronic device / device system described in the above embodiments, or may exist independently and not be incorporated into the electronic device / device. The computer-readable storage medium carries one or more programs that, when executed, implement the method according to the embodiments of the present invention.

[0045] According to an embodiment of the present invention, a computer-readable storage medium may be a non-volatile computer-readable storage medium. Examples include, but are not limited to, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM) or flash memory, a portable compact disk read-only memory (CDROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the present invention, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0046] Embodiments of the present invention also include a computer program product.

[0047] The computer program product includes a computer program, which contains program code for executing the method provided by the embodiment of the present invention. When the computer program product runs on an electronic device, the program code is used to enable the electronic device to implement the method provided by the embodiment of the present invention.

[0048] In one embodiment, the computer program may be stored on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may be transmitted and distributed in the form of a signal over a network medium. The program code contained in the computer program may be transmitted using any appropriate network medium, including but not limited to wireless, wired, or any suitable combination thereof.

[0049] According to an embodiment of the present invention, the program code for executing the computer program provided by the embodiment of the present invention can be written by any combination of one or more programming languages. Specifically, these computing programs can be implemented using high-level procedural and / or object-oriented programming languages. Programming languages include, but are not limited to, Java, C++, Python, C language or similar programming languages. The program code can be executed entirely on the user computing device, partially on the user device, partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device can be connected to the user computing device through any type of network, including a local area network or a wide area network, or can be connected to an external computing device.

[0050] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of the systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each box in the flowchart or block diagram may represent a module, program segment, or portion of code, which contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the boxes may occur in an order different from that marked in the accompanying drawings. For example, two boxes shown in succession may actually be executed substantially in parallel, or they may sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, as well as the combination of boxes in the block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or may be implemented using a combination of dedicated hardware and computer instructions. It will be understood by those skilled in the art that the features described in the various embodiments and / or claims of the present invention may be combined and / or coupled in various ways, even if such combinations or couplings are not explicitly described in the present invention. In particular, without departing from the spirit and teachings of the present invention, the features described in the various embodiments and / or claims of the present invention may be combined and / or coupled in various ways, and all such combinations and / or couplings fall within the scope of the present invention.

[0051] The embodiments of the present invention have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present invention. Although each embodiment has been described above separately, this does not mean that the measures in each embodiment cannot be advantageously used in combination. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A control method for a dual three-level inverter, characterized in that: The dual three-level inverter is composed of a first three-level inverter and a second three-level inverter, and the method includes: obtaining a zero-sequence current and a midpoint potential in the dual three-level inverter when the dual three-level inverter is in operation; Traversing all optional clamping combinations when the first three-level inverter and the second three-level inverter output a required AC voltage, and calculating correspondingly generated dual three-level inverter zero-sequence voltage and dual three-level inverter midpoint current; selecting a clamping combination corresponding to the case where the zero-sequence voltage and the zero-sequence current are in opposite directions, and the midpoint current and the midpoint potential are in opposite directions, as the clamping combination selected for the first three-level inverter and the second three-level inverter; All optional clamp combinations include: all clamp combinations in which one phase is fixed at an optional clamp when the first three-level inverter outputs the required AC voltage and one phase is fixed at an optional clamp when the second three-level inverter outputs the required AC voltage.

2. A control method for a dual three-level inverter according to claim 1, characterized in that: The traversing all optional clamping combinations when the first three-level inverter and the second three-level inverter output an AC voltage, and calculating the corresponding generated dual three-level inverter zero-sequence voltage and dual three-level inverter midpoint current, includes: the dual three-level inverter zero-sequence voltage is a difference between a zero-sequence voltage generated by the first three-level inverter and a zero-sequence voltage generated by the second three-level inverter; and the dual three-level inverter midpoint current is a difference between a midpoint current generated by the first three-level inverter and a midpoint current generated by the second three-level inverter.

3. The control method for a dual three-level inverter according to claim 2, characterized in that: The zero-sequence voltage generated by the first three-level inverter is the average zero-sequence voltage generated by the first three-level inverter in one carrier cycle; the zero-sequence voltage generated by the second three-level inverter is the average zero-sequence voltage generated by the second three-level inverter in one carrier cycle.

4. The control method for a dual three-level inverter according to claim 3, characterized in that: The average zero-sequence voltage of the first three-level inverter is the average value of the product of the voltage values of the switching states of the zero vector, the one vector, and the two vectors of the first three-level inverter with respect to the midpoint of the DC side and the corresponding action time within a carrier cycle; the average zero-sequence voltage of the second three-level inverter is the average value of the product of the voltage values of the switching states of the zero vector, the one vector, and the two vectors of the second three-level inverter with respect to the midpoint of the DC side and the corresponding action time within a carrier cycle.

5. The control method for a dual three-level inverter according to claim 1, characterized in that: The midpoint current generated by the first three-level inverter is an average midpoint current of the first three-level inverter in one carrier cycle, and the midpoint current generated by the second three-level inverter is an average midpoint current of the second three-level inverter in one carrier cycle.

6. A control device for a dual three-level inverter, characterized in that: The device comprises: an acquisition module, configured to acquire a zero-sequence current and a midpoint potential in the dual three-level inverter when the dual three-level inverter is in operation; the dual three-level inverter comprises a first three-level inverter and a second three-level inverter; a calculation module, configured to traverse all optional clamping combinations when the first three-level inverter and the second three-level inverter output a required AC voltage, and calculate the corresponding zero-sequence voltage of the dual three-level inverter and the midpoint current of the dual three-level inverter; a selection module, configured to select a clamp combination corresponding to when the zero-sequence voltage and the zero-sequence current are in opposite directions, and when the midpoint current and the midpoint potential are in opposite directions, as the clamp combination selected by the first three-level inverter and the second three-level inverter; wherein all optional clamp combinations include: all clamp combinations in which one phase is fixed at one optional clamp when the first three-level inverter outputs a required AC voltage, and all clamp combinations in which one phase is fixed at one optional clamp when the second three-level inverter outputs the required AC voltage.

7. An electronic device, characterized in that: include: one or more processors; A storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors are enabled to implement the method according to any one of claims 1 to 5.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that When the computer program is executed by a processor, it implements the method described in any one of claims 1 to 5.

9. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the method according to any one of claims 1 to 5 is implemented.

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