BLDC motor rotating speed calculation method based on FPGA

Abstract

The invention discloses a BLDC motor rotating speed calculation method based on an FPGA, and belongs to the field of motor control technology and FPGA digital system design, and the method comprises the steps: collecting three Hall signals in a BLDC motor, and carrying out the preprocessing of the three Hall signals, and obtaining the preprocessed three Hall signals; judging whether static faults and line sequence faults exist in the three paths of preprocessed Hall signals or not; judging the rotation state of the BLDC motor, wherein the rotation state comprises forward rotation, reverse rotation and stalling; fusing the three paths of preprocessed Hall signals to obtain one path of low-frequency signal; performing sliding frequency counting on the high-frequency signal and the low-frequency signal to respectively obtain a high-frequency accumulated value and a low-frequency count value; wherein the high-frequency signal is a system clock frequency signal; and calculating the rotating speed of the BLDC motor according to the high-frequency accumulated value and the low-frequency count value. The method can be compatible with high-speed and low-speed use scenes at the same time, multiple motors can be controlled at the same time to achieve rotation speed calculation, and rotation speed calculation is high in real-time performance, calculation precision and reliability.

Description

Technical Field

[0001] The present invention belongs to the field of motor control technology and FPGA digital system design, and particularly relates to a BLDC motor speed calculation method based on FPGA. Background Art

[0002] BLDC motors, short for brushless DC motors, are widely used in industrial automation, consumer electronics, electric vehicles, and other fields due to their high efficiency, low noise, and long life. Speed control is crucial for achieving precise speed regulation, torque stability, and energy efficiency optimization. Maintaining dynamic balance requires real-time feedback to adjust the PWM duty cycle or optimize the commutation strategy. Six-step commutation control is a common control method for BLDC motors, which controls motor motion by switching the current between the motor phases.

[0003] In terms of control chips, the motor system's control core is primarily implemented using microcontrollers (MCUs), application-specific integrated circuits (ASICs), DSPs, and FPGAs. The main market advantage of BLDC motor controllers based on MCUs is their low price. However, MCUs operate at a relatively slow speed, making them difficult to meet the system's computational precision requirements. ASICs, while highly integrated, inexpensive, and robust against interference, can only implement relatively simple control algorithms and are inadequate for specialized applications. DSPs utilize a Harvard architecture, offering superior data processing speed and capacity compared to traditional MCUs. They are ideal motor controllers for high-speed data acquisition and rapid computation. However, DSPs are expensive, require numerous peripheral components, and require time-sharing serial processing of system data, slowing system response. FPGAs offer rich internal resources, flexible interface design, and reprogrammability. They implement control logic in hardware and process data in parallel, improving system efficiency, reducing implementation costs, and offering high portability and reliability. Therefore, using FPGAs for motor control offers significant advantages.

[0004] Traditional BLDC motor speed calculation methods primarily rely on the period method (T method) and the frequency method (M method). The T method calculates speed by measuring the number of clock pulses within a fixed period. This method is suitable for low-speed scenarios (<10K RPM), but suffers from insufficient resolution at high speeds. The M method calculates speed by counting the number of cycles within a fixed time period. This method is suitable for high speeds, but suffers from significant errors at low speeds. The T method suffers from insufficient resolution at high speeds due to the small number of pulses, while the M method performs poorly at low speeds. A hybrid M / T method can compensate for this, but this increases algorithm complexity, resource usage, and cost. Summary of the Invention

[0005] In response to the above-mentioned deficiencies in the prior art, the present invention provides an FPGA-based BLDC motor speed calculation method that solves the problems of low applicability, slow response speed, high resource usage, poor portability, poor modifiability, poor verifiability, and uncertain reliability of the prior art.

[0006] In order to achieve the above-mentioned object of the invention, the technical solution adopted by the present invention is: a BLDC motor speed calculation method based on FPGA, comprising: Collecting three-way Hall signals from the BLDC motor and preprocessing them to obtain preprocessed three-way Hall signals; Determine whether the three Hall signals after preprocessing have static faults and line sequence faults; Determine the rotation state of the BLDC motor, including forward, reverse and stop; By fusing the three pre-processed Hall signals, a low-frequency signal is obtained; Perform sliding frequency counting on the high-frequency signal and the low-frequency signal to obtain a high-frequency accumulated value and a low-frequency count value respectively; wherein the high-frequency signal is a system clock frequency signal; The BLDC motor speed is calculated based on the high-frequency accumulated value and the low-frequency count value.

[0007] Furthermore, the preprocessing includes: The three collected Hall signals are clocked twice in the clock domain; The three Hall signals after the beat are shifted and filtered, and the three filtered Hall signals and one Hall valid signal are output.

[0008] Furthermore, the specific method for determining whether the three Hall signals after preprocessing have static faults and line sequence faults is as follows: The states of the three Hall signals are determined on the rising edge of each Hall valid signal; the three Hall signals have 8 states: 000, 001, 010, 011, 100, 101, 110, and 111, with 000 and 111 being invalid states. When the invalid state of the three Hall signals occurs continuously for a number of times reaching a preset value, the Hall signals are judged to be static faults; The commutation sequence of the three filtered Hall signals is obtained. When the commutation sequence is inconsistent with the fixed commutation sequence of the BLDC motor, it is determined to be a line sequence fault. When the result of the determination is a line sequence fault for a preset number of consecutive times, the Hall signal is determined to be a line sequence fault.

[0009] Furthermore, the specific method for determining the rotation state of the BLDC motor is: Set the state machine jump sequence number. The jump sequence numbers in the forward state are: 001-011-010-110-100-101-001; the jump sequence numbers in the reverse state are: 001-101-100-110-010-011-001; The state machine jump number is determined according to the signal values of the three filtered Hall signals within the stop judgment time, and the rotation state of the BLDC motor is obtained according to the state machine jump number. If no change in the three Hall signals is detected after the stop judgment time, the motor is determined to be in a stopped state.

[0010] Furthermore, the calculation expression for the stop time is: =(rotational speed*clock frequency (Hz)) / (number of pole pairs*6) in, For the judgment stop time.

[0011] Furthermore, the specific method of fusing the three pre-processed Hall signals to obtain a low-frequency signal is as follows: The three pre-processed Hall signals are merged into a three-bit register, and the signals in the three-bit register are clocked to obtain a set of register signals. The register signal is compared with the three pre-processed Hall signals. When any one of the three pre-processed Hall signals changes, a trigger is used to flip the changed signal under the control of the clock to generate a low-frequency signal.

[0012] Furthermore, the specific method of performing sliding frequency counting on the high-frequency signal and the low-frequency signal to obtain the high-frequency accumulated value and the low-frequency count value respectively is as follows: Monitor the rotation state of the BLDC motor; when the rotation state of the BLDC motor changes, generate a state change signal; when the state change signal is valid, stop the high-low frequency conversion, clear the high-frequency accumulated value and the low-frequency count value; collect the rising edge of a low-frequency signal, and start the high-low frequency conversion when the rising edge appears; set the sliding order to M; initialize the low-frequency count value to 0, when the rising edge of the low-frequency signal is valid, the low-frequency count value increases from 0 to M in sequence, and when the low-frequency count value is M, keep the low-frequency count value at M; initialize the high-frequency accumulated value to 1, when the rising edge of the low-frequency signal is valid, start counting the high-frequency accumulated value, and one counting cycle is the frequency cycle of the low-frequency signal; accumulate the high-frequency count values of M counting cycles to obtain the high-frequency accumulated value.

[0013] Furthermore, the specific method for calculating the BLDC motor speed based on the high-frequency accumulated value and the low-frequency count value is: Get the low-frequency fixed-point number. The calculation expression is: low-frequency fixed-point number = low-frequency count value * clock frequency (Hz) * 60s / 3; Get the high-frequency fixed-point number, the calculation expression is: high-frequency fixed-point number = high-frequency accumulated value * pole pair number; Convert low-frequency fixed-point numbers and high-frequency fixed-point numbers to low-frequency floating-point numbers and high-frequency floating-point numbers through the fixed-point to floating-point IP core; The floating-point division IP core calculates the ratio of the low-frequency floating-point number to the high-frequency floating-point number to obtain the BLDC motor speed. The expression is: BLDC motor speed (rpm) = low-frequency floating-point number / high-frequency floating-point number.

[0014] The beneficial effects of the present invention are: 1. The motor speed calculation in this invention depends on the BLDC motor's Hall signal generation period. The shorter the Hall signal generation period, the faster the speed calculation, making it compatible with both high-speed and low-speed usage scenarios. After the BLDC motor stabilizes, the FPGA can update the speed in real time with a delay of less than 1µs, demonstrating strong real-time performance.

[0015] 2. The present invention can output the speed result through one round of calculation. Compared with the M / T method, it does not need to be divided into high-speed algorithm and low-speed algorithm, nor does it need to calculate the three Hall signals separately. It saves resources while improving the calculation rate.

[0016] 3. The present invention uses Verilog HDL to complete the design. Verilog HDL is a hardware description language that can be recognized by all FPGA development tools. Therefore, the present invention can be used, transplanted and copied in all FPGAs, and has strong portability. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 The following is a flow chart of a method for calculating the speed of a BLDC motor based on FPGA provided in an embodiment. DETAILED DESCRIPTION

[0018] The specific embodiments of the present invention are described below to facilitate understanding of the present invention by those skilled in the art. However, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the appended claims, these changes are obvious, and all inventions and creations utilizing the concepts of the present invention are protected.

[0019] like Figure 1 As shown, in one embodiment of the present invention, a method for calculating the speed of a BLDC motor based on FPGA includes the following steps: S1. Collect the three Hall signals W, V, and U from the BLDC motor and preprocess them to obtain the preprocessed three Hall signals. Preprocessing includes: using Verilog HDL, a hardware description language that can be recognized by all FPGA development tools, to double-beat the three collected Hall signals in the clock domain to achieve clock synchronization and metastability suppression; The three Hall signals after beating are shifted and filtered. The number of shifts and the signal acquisition cycle can be configured according to specific needs. When the data collected in each cycle are consistent, the data collected for the last time is stored, and the three Hall signals after filtering and one Hall valid signal are output.

[0020] S2. Determine whether the three Hall signals after preprocessing have static faults and line sequence faults; The specific method is: The states of the three Hall signals are determined on the rising edge of each Hall valid signal; the three Hall signals have 8 states: 000, 001, 010, 011, 100, 101, 110, and 111, with 000 and 111 being invalid states. When the three filtered Hall signals collected for 100 consecutive times are all in an invalid state, the Hall signal is judged to be a static fault. The number of judgments can be configured through parameters according to actual needs; The commutation sequence of the three filtered Hall signals is obtained. If the commutation sequence is inconsistent with the fixed commutation sequence of the BLDC motor, it is determined to be a line sequence fault. If the result of 100 consecutive determinations is a line sequence fault, the Hall signal is determined to be a line sequence fault. The number of determinations can be configured through parameters according to actual needs.

[0021] Since the Hall signal may be unstable when the motor is just started, a delay of 10ms is set after power-on before determining static faults or line sequence faults. The delay time can be configured through parameters.

[0022] If the Hall signal fails, directly using these signals to calculate the motor speed may lead to incorrect results and may even damage the motor system. Therefore, before calculating the speed, it is necessary to check for Hall signal failures and detect signal abnormalities in time to avoid using incorrect signals for speed calculation.

[0023] S3, judging the rotation state of the BLDC motor, including forward rotation, reverse rotation and stop; The specific method is: Set the state machine jump sequence number. The jump sequence numbers in the forward state are: 001-011-010-110-100-101-001; the jump sequence numbers in the reverse state are: 001-101-100-110-010-011-001; The state machine jump sequence number is determined based on the signal values of the three Hall signals after filtering within the stop time, and the rotation state of the BLDC motor is obtained based on the state machine jump sequence number. If no change in the three Hall signals is detected after the stop time, the motor is determined to be in a stopped state. The calculation expression is: =(rotational speed*clock frequency (Hz)) / (number of pole pairs*6).

[0024] S4, obtaining a low-frequency signal by fusing the three pre-processed Hall signals; Specifically: The three pre-processed Hall signals are merged into a three-bit register, and the signals in the three-bit register are clocked to obtain a set of register signals. The register signal is compared with the three pre-processed Hall signals. When any one of the three pre-processed Hall signals changes, a trigger is used to flip the changed signal under the control of the clock to generate a low-frequency signal.

[0025] S5. Perform sliding frequency counting on the high-frequency signal and the low-frequency signal to obtain a high-frequency accumulated value and a low-frequency count value, respectively; wherein the high-frequency signal is a system clock frequency signal, and the low-frequency signal is a frequency signal generated according to the three Hall signals; The specific method is: Monitor the rotation state of the BLDC motor; when the rotation state of the BLDC motor changes, generate a state change signal; when the state change signal is valid, stop the high-low frequency conversion, clear the high-frequency accumulated value and the low-frequency count value; collect the rising edge of a low-frequency signal, and start the high-low frequency conversion when the rising edge appears; set the sliding order to M; initialize the low-frequency count value to 0, when the rising edge of the low-frequency signal is valid, the low-frequency count value increases from 0 to M in sequence, and when the low-frequency count value is M, maintain the low-frequency count value at M; initialize the high-frequency accumulated value to 1, when the rising edge of the low-frequency signal is valid, start counting the high-frequency accumulated value, and the counting period is the frequency period of the low-frequency signal, that is, count the number of system clocks in the low-frequency period, and the number of system clocks counted in each period is a high-frequency count value; accumulate the high-frequency count values of M counting periods to obtain the high-frequency accumulated value.

[0026] S6, calculating the BLDC motor speed based on the high-frequency accumulated value and the low-frequency count value; The specific method is: Get the low-frequency fixed-point number and latch it. The calculation expression is: low-frequency fixed-point number = low-frequency count value * clock frequency (Hz) * 60s / 3; Obtain the high-frequency fixed-point number and latch it. The calculation expression is: high-frequency fixed-point number = high-frequency accumulated value * pole pair number; Convert low-frequency fixed-point numbers and high-frequency fixed-point numbers to low-frequency floating-point numbers and high-frequency floating-point numbers through the fixed-point to floating-point IP core; The floating-point division IP core calculates the ratio of the low-frequency floating-point number to the high-frequency floating-point number to obtain the BLDC motor speed. The expression is: BLDC motor speed (rpm) = low-frequency floating-point number / high-frequency floating-point number.

[0027] All of the above steps are completed using Verilog HDL. Verilog HDL is a hardware description language that can be recognized by all FPGA development tools. Therefore, the present invention can be used, ported, and replicated in all FPGAs. This demonstrates the portability and applicability of the present invention.

[0028] In summary, the present invention is compatible with both high-speed and low-speed usage scenarios, and has strong real-time speed calculation, high calculation accuracy, and high reliability. It solves the problems of traditional BLDC motor speed calculation methods that are not compatible with both high-speed and low-speed usage scenarios, have slow response speed, high resource usage, poor portability, poor modifiability, poor verifiability, and uncertain reliability.

Claims

1. A BLDC motor speed calculation method based on FPGA, characterized in that: include: Collecting three-way Hall signals from the BLDC motor and preprocessing them to obtain preprocessed three-way Hall signals; Determine whether the three Hall signals after preprocessing have static faults and line sequence faults; Determine the rotation state of the BLDC motor, including forward, reverse and stop; The three pre-processed Hall signals are integrated to obtain a low-frequency signal. Perform sliding frequency counting on the high-frequency signal and the low-frequency signal to obtain a high-frequency accumulated value and a low-frequency count value respectively; wherein the high-frequency signal is a system clock frequency signal; The BLDC motor speed is calculated based on the high-frequency accumulated value and the low-frequency count value.

2. The BLDC motor speed calculation method based on FPGA according to claim 1, characterized in that: The pretreatment includes: The three collected Hall signals are clocked twice in the clock domain; The three Hall signals after the beat are shifted and filtered, and the three filtered Hall signals and one Hall valid signal are output.

3. The BLDC motor speed calculation method based on FPGA according to claim 2, characterized in that: The specific method for judging whether the three Hall signals after preprocessing have static faults and line sequence faults is as follows: The states of the three Hall signals are determined on the rising edge of each Hall valid signal; the three Hall signals have 8 states: 000, 001, 010, 011, 100, 101, 110, and 111, with 000 and 111 being invalid states. When the invalid state of the three Hall signals occurs continuously for a number of times reaching a preset value, the Hall signals are judged to be static faults; The commutation sequence of the three filtered Hall signals is obtained. When the commutation sequence is inconsistent with the fixed commutation sequence of the BLDC motor, it is determined to be a line sequence fault. When the result of the determination is a line sequence fault for a preset number of consecutive times, the Hall signal is determined to be a line sequence fault.

4. The BLDC motor speed calculation method based on FPGA according to claim 1, characterized in that: The specific method for judging the rotation state of the BLDC motor is: Set the state machine jump sequence number. The jump sequence numbers in the forward state are: 001-011-010-110-100-101-001; the jump sequence numbers in the reverse state are: 001-101-100-110-010-011-001; During the stop time, the state machine jump sequence number is determined based on the signal values of the three filtered Hall signals, and the rotation state of the BLDC motor is obtained based on the state machine jump sequence number. When no change is detected in the three Hall signals within the stop judgment time, it is determined that the motor is in a stopped state.

5. The BLDC motor speed calculation method based on FPGA according to claim 4, characterized in that: The calculation expression of the stop time is: =(rotational speed*clock frequency (Hz)) / (number of pole pairs*6) in, For the judgment stop time.

6. The method for calculating the BLDC motor speed based on FPGA according to claim 1, wherein: The specific method of fusing the three pre-processed Hall signals to obtain a low-frequency signal is as follows: The three pre-processed Hall signals are merged into a three-bit register, and the signals in the three-bit register are clocked to obtain a set of register signals. The register signal is compared with the three pre-processed Hall signals. When any one of the three pre-processed Hall signals changes, a trigger is used to flip the changed signal under the control of the clock to generate a low-frequency signal.

7. The method for calculating the BLDC motor speed based on FPGA according to claim 3, characterized in that: The specific method of performing sliding frequency counting on high-frequency signals and low-frequency signals to obtain high-frequency accumulated values and low-frequency count values respectively is as follows: Monitor the rotation state of the BLDC motor; when the rotation state of the BLDC motor changes, generate a state change signal; when the state change signal is valid, stop the high-low frequency conversion, clear the high-frequency accumulated value and the low-frequency count value; collect the rising edge of a low-frequency signal, and start the high-low frequency conversion when the rising edge appears; set the sliding order to M; initialize the low-frequency count value to 0, when the rising edge of the low-frequency signal is valid, the low-frequency count value increases from 0 to M in sequence, and when the low-frequency count value is M, keep the low-frequency count value at M; initialize the high-frequency accumulated value to 1, when the rising edge of the low-frequency signal is valid, start counting the high-frequency accumulated value, and one counting cycle is the frequency cycle of the low-frequency signal; accumulate the high-frequency count values of M counting cycles to obtain the high-frequency accumulated value.

8. The method for calculating the BLDC motor speed based on FPGA according to claim 4, characterized in that: The specific method for calculating the BLDC motor speed based on the high-frequency accumulated value and the low-frequency count value is: Get the low-frequency fixed-point number. The calculation expression is: low-frequency fixed-point number = low-frequency count value * clock frequency (Hz) * 60s / 3; Get the high-frequency fixed-point number, the calculation expression is: high-frequency fixed-point number = high-frequency accumulated value * pole pair number; Convert low-frequency fixed-point numbers and high-frequency fixed-point numbers to low-frequency floating-point numbers and high-frequency floating-point numbers through the fixed-point to floating-point IP core; The floating-point division IP core calculates the ratio of the low-frequency floating-point number to the high-frequency floating-point number to obtain the BLDC motor speed. The expression is: BLDC motor speed (rpm) = low-frequency floating-point number / high-frequency floating-point number.

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