Double-loop control oscillator circuit with jitter frequency

Abstract

The invention discloses a double-loop control oscillator circuit with jitter frequency. The double-loop control oscillator circuit comprises a comparator COMP1, an RS trigger, an 8-bit add-subtract counter, a variable capacitor Variable cap, a PMOS tube M1, a PMOS tube M3, an NMOS tube M2, an NMOS tube M4, a grounding capacitor CAP1, a Schmitt trigger SMIT, a NAND gate NAND, a NOR gate NOR, a phase inverter INV1, a phase inverter INV2, a phase inverter INV3 and a phase inverter INV4. According to the invention, the external variable resistor is adopted to configure the magnitude of the output current of the current source to charge and discharge the variable capacitor, and the 8-bit add-subtract counter is utilized to output a six-bit binary signal to the variable capacitor to control the increase and decrease of the variable capacitor, so that the increase and decrease of the pulse frequency are realized, and the periodic frequency jitter is realized. The method can effectively improve the electromagnetic interference of the switching power supply.

Description

Technical Field

[0001] The present invention belongs to the technical field of power management chips, and in particular relates to a dual-loop controlled oscillator circuit with a jitter frequency. Background Art

[0002] The development of frequency-dithering oscillators in switching power supplies is primarily related to addressing electromagnetic interference (EMI). With the increasing prevalence of electronic devices and the increasing operating frequencies of switching power supplies, EMI has become increasingly severe, impacting the stability and reliability of these devices. Consequently, researchers have sought effective EMI mitigation techniques, leading to the development of frequency dithering. Frequency dithering disperses EMI energy and reduces EMI peaks by periodically varying the operating frequency of a switching power supply within a certain range, rather than fixing it to a specific frequency. Initially used in high-frequency digital circuits, this technique has gradually evolved into switching power supplies, becoming an effective method for mitigating EMI in switching power supplies. Oscillators with frequency dithering achieve frequency dithering by periodically varying the capacitance of the oscillator's internal variable capacitor. This design is simple in structure and effective, effectively reducing EMI within the chip. Circuit simulations using a BCD process show that the oscillator's center frequency dithers within a certain range, meeting EMI requirements. In summary, this paper presents a high-precision oscillator circuit with frequency dithering and dual-loop control for switching power supplies. Summary of the Invention

[0003] In view of the above-mentioned deficiencies in the prior art, the present invention provides a dual-loop controlled oscillator circuit with a jitter frequency, which solves the problem that the frequency jitter range of the traditional frequency jitter circuit is a fixed value and has strong electromagnetic interference.

[0004] To achieve the above-mentioned object, the present invention adopts the following technical solution: a dual-loop controlled oscillator circuit with a jitter frequency, comprising a comparator COMP_1, an RS trigger, an 8-bit up / down counter, a variable capacitor Variable cap, PMOS transistors M1, PMOS transistors M3, NMOS transistors M2, NMOS transistors M4, a grounding capacitor CAP1, a Schmitt trigger SMIT, a NAND gate NAND, a NOR gate NOR, inverters INV_1, INV_2, INV_3, and INV_4;

[0005] The source of the PMOS transistor M1 inputs the capacitor charging current. The gate of the PMOS transistor M1 is connected to the gate of the PMOS transistor M2, the output of the inverter INV_3, and the input of the inverter INV_4. The drain of the PMOS transistor M1 is connected to the drain of the PMOS transistor M2, one end of the variable capacitor Variable cap, and the positive electrode of the comparator COMP_1. The source of the PMOS transistor M2 is grounded, and the other end of the variable capacitor Variable cap is grounded. The variable capacitor Variable cap is also connected to the signal output port of the 8-bit up-down counter. The negative electrode of the comparator COMP_1 is connected to the reference voltage. The output of the comparator COMP_1 is connected to the S port of the RS flip-flop via a NOR gate NOR.

[0006] The source of the PMOS transistor M3 inputs a bias current. The gate of the PMOS transistor M3 is connected to the gate of the PMOS transistor M4 and the output of the inverter INV_4 respectively. The drain of the PMOS transistor M3 is connected to the drain of the PMOS transistor M4, the grounding capacitor CAP1, and the positive terminal of the Schmitt trigger SMIT respectively. The output of the Schmitt trigger SMIT is connected to the input of the inverter INV_2 through the inverter INV_1 and the NAND gate NAND in sequence. The output of the NAND gate NAND is also connected to the R port of the RS trigger. The auxiliary output port of the RS trigger is connected to the input of the inverter INV_3. The output of the inverter INV_2 is connected to the clk port of the 8-bit up-down counter.

[0007] Furthermore, the 8-bit up / down counter includes D flip-flops DFF_1 to D flip-flops DFF_8, XOR gates XOR_1 to XOR gates XOR_6, inverters INV_5 to INV_10, and the signal output ports of the 8-bit up / down counter include Q <1> ~Q <6> and QN <1> ~QN <6> ;

[0008] The clk port of the D flip-flop DFF_1 serves as the clk port of the 8-bit up-down counter. The Q NOT port of the D flip-flop DFF_1 is connected to the D port of the D flip-flop DFF_1 and the clk port of the D flip-flop DFF_2, respectively. The Q NOT port of the D flip-flop DFF_2 is connected to the D port of the D flip-flop DFF_2 and the clk port of the D flip-flop DFF_3, respectively. The Q port of the D flip-flop DFF_2 is connected to the first input port of the exclusive OR gate XOR_1. The Q NOT port of the D flip-flop DFF_3 is connected to the D port of the D flip-flop DFF_3 and the clk port of the D flip-flop DFF_4, respectively. The Q port of the D flip-flop DFF_3 is connected to the first input port of the exclusive OR gate XOR_2. The Q NOT port of the D flip-flop DFF_4 is connected to the D port of the D flip-flop DFF_4 and the clk port of the D flip-flop DFF_5, respectively. The Q port of the D flip-flop DFF_4 connected to the first input port of the exclusive OR gate XOR_3, the Q NOT port of the D flip-flop DFF_5 is respectively connected to the D port of the D flip-flop DFF_5 and the clk port of the D flip-flop DFF_6, the Q port of the D flip-flop DFF_5 is respectively connected to the D port of the D flip-flop DFF_6 and the clk port of the D flip-flop DFF_7, the Q port of the D flip-flop DFF_6 is respectively connected to the first input port of the exclusive OR gate XOR_5, the Q NOT port of the D flip-flop DFF_7 is respectively connected to the D port of the D flip-flop DFF_7 and the clk port of the D flip-flop DFF_8, the Q port of the D flip-flop DFF_7 is connected to the first input port of the exclusive OR gate XOR_6, and the Q NOT port of the D flip-flop DFF_8 is respectively connected to the second input ports of the exclusive OR gates XOR_1 to XOR_6;

[0009] The output of XOR gate XOR_1 is connected to the input of inverter INV_5 and serves as Q <1> , the output of inverter INV_5 serves as QN <1> , the output of XOR gate XOR_2 is connected to the input of inverter INV_6 and serves as Q <2> , the output of inverter INV_6 serves as QN <2> , the output of XOR gate XOR_3 is connected to the input of inverter INV_7 and serves as Q <3> , the output of inverter INV_7 serves as QN <3> , the output of XOR gate XOR_4 is connected to the input of inverter INV_8 and serves as Q <4> The output of inverter INV_8 serves as QN <4> , the output of XOR gate XOR_5 is connected to the input of inverter INV_9 and serves as Q <5> The output of inverter INV_9 serves as QN <5> , the output of XOR gate XOR_6 is connected to the input of inverter INV_10 and serves as Q <6> , the output of inverter INV_10 serves as QN <6> .

[0010] Furthermore, the variable capacitor Variable cap includes a capacitor C0, a grounding capacitor C1 to a grounding capacitor C6, and an NMOS transistor M5 to an NMOS transistor M16;

[0011] The positive end of capacitor C0 is connected to the drain of NMOS tube M5, the drain of NMOS tube M6, the drain of NMOS tube M7, the drain of NMOS tube M8, the drain of NMOS tube M9 and the drain of NMOS tube M10 respectively, and serves as one end of variable capacitor Variable cap. The negative end of capacitor C0 serves as the other end of variable capacitor Variable cap. The gate of NMOS tube M5, the gate of NMOS tube M6, the gate of NMOS tube M7, the gate of NMOS tube M8, the gate of NMOS tube M9 and the gate of NMOS tube M10 are connected to QN <1> ~QN <6> One-to-one connection;

[0012] The source of the NMOS transistor M5 is connected to the drain of the NMOS transistor M11 and the grounding capacitor C1 respectively. The source of the NMOS transistor M11 is grounded. The source of the NMOS transistor M6 is connected to the drain of the NMOS transistor M12 and the grounding capacitor C2 respectively. The source of the NMOS transistor M12 is grounded. The source of the NMOS transistor M7 is connected to the drain of the NMOS transistor M13 and the grounding capacitor C3 respectively. The source of the NMOS transistor M13 is grounded. The source of the NMOS transistor M8 is connected to the drain of the NMOS transistor M14 and the grounding capacitor C4 respectively. The source of the S transistor M14 is grounded, the source of the NMOS transistor M9 is connected to the drain of the NMOS transistor M15 and the grounding capacitor C5 respectively, the source of the NMOS transistor M15 is grounded, the source of the NMOS transistor M10 is connected to the drain of the NMOS transistor M16 and the grounding capacitor C6 respectively, and the source of the NMOS transistor M16 is grounded; the gates of the NMOS transistors M11, M12, M13, M14, M15 and M16 are connected to the Q <1> ~Q <6> One-to-one connection.

[0013] The beneficial effects of the present invention are:

[0014] (1) The present invention provides a dual-loop controlled oscillator circuit with a jitter frequency. An external variable resistor is used to configure the output current of the current source to charge and discharge the variable capacitor. An 8-bit up / down counter is used to output a six-bit binary signal to the variable capacitor to control the increase and decrease of the variable capacitor, thereby increasing and decreasing the pulse frequency and achieving periodic frequency jitter. This method can effectively improve the electromagnetic interference of the switching power supply.

[0015] (2) The present invention realizes dual-loop control of output pulses through an RS trigger, which effectively improves the stability of the output frequency.

[0016] (3) The oscillator output pulse frequency range proposed by the present invention is: 100kHz-1000kHz, and the frequency jitter range is: ±6%, which is more suitable for the wide range and high precision requirements of the clock signal in the power management chip circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a schematic diagram of a dual-loop controlled oscillator circuit with jitter frequency according to the present invention.

[0018] Figure 2 This is the schematic diagram of an 8-bit up / down counter.

[0019] Figure 3 This is the schematic diagram of the variable capacitor Variable cap. DETAILED DESCRIPTION

[0020] The specific embodiments of the present invention are described below to facilitate understanding of the present invention by those skilled in the art. However, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the appended claims, these changes are obvious, and all inventions and creations utilizing the concepts of the present invention are protected.

[0021] like Figure 1 As shown, in one embodiment of the present invention, a dual-loop controlled oscillator circuit with a jitter frequency includes a comparator COMP_1, an RS trigger, an 8-bit up / down counter, a variable capacitor Variable cap, a PMOS transistor M1, a PMOS transistor M3, an NMOS transistor M2, an NMOS transistor M4, a grounding capacitor CAP1, a Schmitt trigger SMIT, a NAND gate NAND, a NOR gate NOR, inverters INV_1, INV_2, INV_3, and INV_4;

[0022] The source of the PMOS transistor M1 inputs the capacitor charging current. The gate of the PMOS transistor M1 is connected to the gate of the PMOS transistor M2, the output of the inverter INV_3, and the input of the inverter INV_4. The drain of the PMOS transistor M1 is connected to the drain of the PMOS transistor M2, one end of the variable capacitor Variable cap, and the positive electrode of the comparator COMP_1. The source of the PMOS transistor M2 is grounded, and the other end of the variable capacitor Variable cap is grounded. The variable capacitor Variable cap is also connected to the signal output port of the 8-bit up-down counter. The negative electrode of the comparator COMP_1 is connected to the reference voltage. The output of the comparator COMP_1 is connected to the S port of the RS flip-flop via a NOR gate NOR.

[0023] The source of the PMOS transistor M3 inputs a bias current. The gate of the PMOS transistor M3 is connected to the gate of the PMOS transistor M4 and the output of the inverter INV_4 respectively. The drain of the PMOS transistor M3 is connected to the drain of the PMOS transistor M4, the grounding capacitor CAP1, and the positive terminal of the Schmitt trigger SMIT respectively. The output of the Schmitt trigger SMIT is connected to the input of the inverter INV_2 through the inverter INV_1 and the NAND gate NAND in sequence. The output of the NAND gate NAND is also connected to the R port of the RS trigger. The auxiliary output port of the RS trigger is connected to the input of the inverter INV_3. The output of the inverter INV_2 is connected to the clk port of the 8-bit up-down counter.

[0024] like Figure 2 As shown, the 8-bit up-down counter includes D flip-flops DFF_1 to D flip-flops DFF_8, XOR gates XOR_1 to XOR gates XOR_6, inverters INV_5 to INV_10, and the signal output ports of the 8-bit up-down counter include Q <1> ~Q <6> and QN <1> ~QN <6> ;

[0025] The clk port of the D flip-flop DFF_1 serves as the clk port of the 8-bit up-down counter. The Q NOT port of the D flip-flop DFF_1 is connected to the D port of the D flip-flop DFF_1 and the clk port of the D flip-flop DFF_2, respectively. The Q NOT port of the D flip-flop DFF_2 is connected to the D port of the D flip-flop DFF_2 and the clk port of the D flip-flop DFF_3, respectively. The Q port of the D flip-flop DFF_2 is connected to the first input port of the exclusive OR gate XOR_1. The Q NOT port of the D flip-flop DFF_3 is connected to the D port of the D flip-flop DFF_3 and the clk port of the D flip-flop DFF_4, respectively. The Q port of the D flip-flop DFF_3 is connected to the first input port of the exclusive OR gate XOR_2. The Q NOT port of the D flip-flop DFF_4 is connected to the D port of the D flip-flop DFF_4 and the clk port of the D flip-flop DFF_5, respectively. The Q port of the D flip-flop DFF_4 connected to the first input port of the exclusive OR gate XOR_3, the Q NOT port of the D flip-flop DFF_5 is respectively connected to the D port of the D flip-flop DFF_5 and the clk port of the D flip-flop DFF_6, the Q port of the D flip-flop DFF_5 is respectively connected to the D port of the D flip-flop DFF_6 and the clk port of the D flip-flop DFF_7, the Q port of the D flip-flop DFF_6 is respectively connected to the first input port of the exclusive OR gate XOR_5, the Q NOT port of the D flip-flop DFF_7 is respectively connected to the D port of the D flip-flop DFF_7 and the clk port of the D flip-flop DFF_8, the Q port of the D flip-flop DFF_7 is connected to the first input port of the exclusive OR gate XOR_6, and the Q NOT port of the D flip-flop DFF_8 is respectively connected to the second input ports of the exclusive OR gates XOR_1 to XOR_6;

[0026] The output of XOR gate XOR_1 is connected to the input of inverter INV_5 and serves as Q <1> , the output of inverter INV_5 serves as QN <1> , the output of XOR gate XOR_2 is connected to the input of inverter INV_6 and serves as Q <2> , the output of inverter INV_6 serves as QN <2> , the output of XOR gate XOR_3 is connected to the input of inverter INV_7 and serves as Q <3> , the output of inverter INV_7 serves as QN <3> , the output of XOR gate XOR_4 is connected to the input of inverter INV_8 and serves as Q <4> The output of inverter INV_8 serves as QN <4> , the output of XOR gate XOR_5 is connected to the input of inverter INV_9 and serves as Q <5> The output of inverter INV_9 serves as QN <5> , the output of XOR gate XOR_6 is connected to the input of inverter INV_10 and serves as Q <6> , the output of inverter INV_10 serves as QN <6> .

[0027] like Figure 3 As shown, the variable capacitor Variable cap includes capacitor C0, grounding capacitors C1 to C6, and NMOS transistors M5 to M16;

[0028] The positive end of capacitor C0 is connected to the drain of NMOS tube M5, the drain of NMOS tube M6, the drain of NMOS tube M7, the drain of NMOS tube M8, the drain of NMOS tube M9 and the drain of NMOS tube M10 respectively, and serves as one end of variable capacitor Variable cap. The negative end of capacitor C0 serves as the other end of variable capacitor Variable cap. The gate of NMOS tube M5, the gate of NMOS tube M6, the gate of NMOS tube M7, the gate of NMOS tube M8, the gate of NMOS tube M9 and the gate of NMOS tube M10 are connected to QN <1> ~QN <6> One-to-one connection;

[0029] The source of the NMOS transistor M5 is connected to the drain of the NMOS transistor M11 and the grounding capacitor C1 respectively. The source of the NMOS transistor M11 is grounded. The source of the NMOS transistor M6 is connected to the drain of the NMOS transistor M12 and the grounding capacitor C2 respectively. The source of the NMOS transistor M12 is grounded. The source of the NMOS transistor M7 is connected to the drain of the NMOS transistor M13 and the grounding capacitor C3 respectively. The source of the NMOS transistor M13 is grounded. The source of the NMOS transistor M8 is connected to the drain of the NMOS transistor M14 and the grounding capacitor C4 respectively. The source of the S transistor M14 is grounded, the source of the NMOS transistor M9 is connected to the drain of the NMOS transistor M15 and the grounding capacitor C5 respectively, the source of the NMOS transistor M15 is grounded, the source of the NMOS transistor M10 is connected to the drain of the NMOS transistor M16 and the grounding capacitor C6 respectively, and the source of the NMOS transistor M16 is grounded; the gates of the NMOS transistors M11, M12, M13, M14, M15 and M16 are connected to the Q <1> ~Q <6> One-to-one connection.

[0030] The working process of the dual-loop controlled oscillator circuit with jitter frequency provided by the present invention is specifically as follows:

[0031] like Figure 1 As shown, the capacitor charging current ISET, the bias current Ibias and the comparator reference voltage VREF are set;

[0032] Assume the capacitance of the variable cap is C var When ISET starts to charge the capacitor, the capacitor voltage V capIt is less than the reference voltage VREF, so the comparator outputs a low level, and the enable signal ENN is a low level. Therefore, the signal passes through the NOR gate and enters the S terminal of the RS trigger. At this time, S=1, R=0. Should The output signal controls M3 to turn off and M4 to turn on after passing through the first-stage inverter, and the capacitor CAP1 discharges, so SMIT outputs a high level and enters the R terminal of the RS trigger after passing through the logic. At this time, S=1, R=1, When ISET charges the variable capacitor Variable cap to a value greater than VREF, the comparator COMP_1 outputs a high level. At this time, the RS trigger: S=0, R=1. Should The output signal passes through two inverters to control M1 to turn off and M2 to turn on. The variable capacitor Variable cap begins to discharge, and the comparator COMP_1 outputs a low level. At this time, S=1, R=1. When the bias current Ibias charges the capacitor CAP1 to the comparison threshold of the Schmitt trigger SMIT, SMIT outputs a low level. At this time, the RS trigger: S=1, R=0, After completing one cycle, the CLKO port outputs one pulse cycle;

[0033] like Figure 2 As shown in the figure, the CLKO signal enters the CP terminal of the 8-bit up-down counter DFF_1. After being divided by eight, the Q terminal signal of each D flip-flop is connected to the Q terminal signal of the D flip-flop DFF_8. The terminal signal is XORed and outputs a 6-bit digital signal, Q <6> ~Q <1> The changing pattern is: 000000→111111→000000. The six-bit binary signal enters the variable capacitor Variable cap to control the increase and decrease of the capacitance, thereby increasing and decreasing the pulse frequency and achieving periodic frequency jitter.

[0034] The calculation formula of frequency f is:

[0035]

[0036] Where, I SET is the capacitor charging current ISET, C var is the capacitance of the variable cap, V ref is the reference voltage VREF;

[0037] I SET *t=C var *V ref

[0038]

[0039] In the description of the present invention, it should be understood that the terms "center", "thickness", "upper", "lower", "horizontal", "top", "bottom", "inner", "outer", "radial", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying the relative importance or the number of technical features implicitly specified. Therefore, the features defined by "first", "second", and "third" may explicitly or implicitly include one or more of such features.

Claims

1. A dual-loop controlled oscillator circuit with a jitter frequency, characterized in that: It includes comparator COMP_1, RS trigger, 8-bit up / down counter, variable capacitor Variable cap, PMOS transistor M1, PMOS transistor M3, NMOS transistor M2, NMOS transistor M4, grounding capacitor CAP1, Schmitt trigger SMIT, NAND gate NAND, NOR gate NOR, inverter INV_1, inverter INV_2, inverter INV_3 and inverter INV_4; The source of the PMOS transistor M1 inputs the capacitor charging current. The gate of the PMOS transistor M1 is connected to the gate of the PMOS transistor M2, the output of the inverter INV_3, and the input of the inverter INV_4. The drain of the PMOS transistor M1 is connected to the drain of the PMOS transistor M2, one end of the variable capacitor Variable cap, and the positive electrode of the comparator COMP_1. The source of the PMOS transistor M2 is grounded, and the other end of the variable capacitor Variable cap is grounded. The variable capacitor Variable cap is also connected to the signal output port of the 8-bit up-down counter. The negative electrode of the comparator COMP_1 is connected to the reference voltage. The output of the comparator COMP_1 is connected to the S port of the RS flip-flop via a NOR gate NOR. The source of the PMOS transistor M3 inputs a bias current. The gate of the PMOS transistor M3 is connected to the gate of the PMOS transistor M4 and the output of the inverter INV_4 respectively. The drain of the PMOS transistor M3 is connected to the drain of the PMOS transistor M4, the grounding capacitor CAP1, and the positive terminal of the Schmitt trigger SMIT respectively. The output of the Schmitt trigger SMIT is connected to the input of the inverter INV_2 through the inverter INV_1 and the NAND gate NAND in sequence. The output of the NAND gate NAND is also connected to the R port of the RS trigger. The auxiliary output port of the RS trigger is connected to the input of the inverter INV_3. The output of the inverter INV_2 is connected to the clk port of the 8-bit up-down counter.

2. The dual-loop controlled oscillator circuit with jitter frequency according to claim 1, characterized in that: The 8-bit up / down counter includes D flip-flops DFF_1 to DFF_8, XOR gates XOR_1 to XOR gates XOR_6, inverters INV_5 to INV_10, and the signal output ports of the 8-bit up / down counter include Q <1> ~Q <6> and QN <1> ~QN <6> ; The clk port of the D flip-flop DFF_1 serves as the clk port of the 8-bit up-down counter. The Q NOT port of the D flip-flop DFF_1 is connected to the D port of the D flip-flop DFF_1 and the clk port of the D flip-flop DFF_2, respectively. The Q NOT port of the D flip-flop DFF_2 is connected to the D port of the D flip-flop DFF_2 and the clk port of the D flip-flop DFF_3, respectively. The Q port of the D flip-flop DFF_2 is connected to the first input port of the exclusive OR gate XOR_1. The Q NOT port of the D flip-flop DFF_3 is connected to the D port of the D flip-flop DFF_3 and the clk port of the D flip-flop DFF_4, respectively. The Q port of the D flip-flop DFF_3 is connected to the first input port of the exclusive OR gate XOR_2. The Q NOT port of the D flip-flop DFF_4 is connected to the D port of the D flip-flop DFF_4 and the clk port of the D flip-flop DFF_5, respectively. The Q port of the D flip-flop DFF_4 connected to the first input port of the exclusive OR gate XOR_3, the Q NOT port of the D flip-flop DFF_5 is respectively connected to the D port of the D flip-flop DFF_5 and the clk port of the D flip-flop DFF_6, the Q port of the D flip-flop DFF_5 is respectively connected to the D port of the D flip-flop DFF_6 and the clk port of the D flip-flop DFF_7, the Q port of the D flip-flop DFF_6 is respectively connected to the first input port of the exclusive OR gate XOR_5, the Q NOT port of the D flip-flop DFF_7 is respectively connected to the D port of the D flip-flop DFF_7 and the clk port of the D flip-flop DFF_8, the Q port of the D flip-flop DFF_7 is connected to the first input port of the exclusive OR gate XOR_6, and the Q NOT port of the D flip-flop DFF_8 is respectively connected to the second input ports of the exclusive OR gates XOR_1 to XOR_6; The output of XOR gate XOR_1 is connected to the input of inverter INV_5 and serves as Q <1> , the output of inverter INV_5 serves as QN <1> , the output of XOR gate XOR_2 is connected to the input of inverter INV_6 and serves as Q <2> , the output of inverter INV_6 serves as QN <2> , the output of XOR gate XOR_3 is connected to the input of inverter INV_7 and serves as Q <3> , the output of inverter INV_7 serves as QN <3> , the output of XOR gate XOR_4 is connected to the input of inverter INV_8 and serves as Q <4> The output of inverter INV_8 serves as QN <4> , the output of XOR gate XOR_5 is connected to the input of inverter INV_9 and serves as Q <5> The output of inverter INV_9 serves as QN <5> , the output of XOR gate XOR_6 is connected to the input of inverter INV_10 and serves as Q <6> , the output of inverter INV_10 serves as QN <6> .

3. The dual-loop controlled oscillator circuit with jitter frequency according to claim 1, characterized in that: The variable capacitor Variable cap includes capacitor C0, grounding capacitors C1 to C6, and NMOS transistors M5 to M16; The positive end of capacitor C0 is connected to the drain of NMOS tube M5, the drain of NMOS tube M6, the drain of NMOS tube M7, the drain of NMOS tube M8, the drain of NMOS tube M9 and the drain of NMOS tube M10 respectively, and serves as one end of variable capacitor Variable cap. The negative end of capacitor C0 serves as the other end of variable capacitor Variable cap. The gate of NMOS tube M5, the gate of NMOS tube M6, the gate of NMOS tube M7, the gate of NMOS tube M8, the gate of NMOS tube M9 and the gate of NMOS tube M10 are connected to QN <1> ~QN <6> One-to-one connection; The source of the NMOS transistor M5 is connected to the drain of the NMOS transistor M11 and the grounding capacitor C1 respectively. The source of the NMOS transistor M11 is grounded. The source of the NMOS transistor M6 is connected to the drain of the NMOS transistor M12 and the grounding capacitor C2 respectively. The source of the NMOS transistor M12 is grounded. The source of the NMOS transistor M7 is connected to the drain of the NMOS transistor M13 and the grounding capacitor C3 respectively. The source of the NMOS transistor M13 is grounded. The source of the NMOS transistor M8 is connected to the drain of the NMOS transistor M14 and the grounding capacitor C4 respectively. The source of the S transistor M14 is grounded, the source of the NMOS transistor M9 is connected to the drain of the NMOS transistor M15 and the grounding capacitor C5 respectively, the source of the NMOS transistor M15 is grounded, the source of the NMOS transistor M10 is connected to the drain of the NMOS transistor M16 and the grounding capacitor C6 respectively, and the source of the NMOS transistor M16 is grounded; the gates of the NMOS transistors M11, M12, M13, M14, M15 and M16 are connected to the Q <1> ~Q <6> One-to-one connection.

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