Interface method for power hardware-in-loop system

Abstract

The invention belongs to the technical field of power hardware-in-loop system testing, and particularly relates to an interface method for a power hardware-in-loop system, which collects digital side voltage and physical side current signals in real time, and accurately adjusts signal amplitude through a voltage proportionality coefficient. And high-precision digital-to-analog conversion is adopted to realize accurate signal transmission and amplification processing. In addition, according to the algorithm, an RC first-order equivalent circuit and a second-order low-pass filter in the FPGA high-speed processing unit are used for conducting filtering processing on a physical side current signal, and the physical side current signal passes through a current proportionality coefficient and is fed back to a digital side controlled current source. By optimizing the signal transmission path and the filtering compensation method, noise interference in the transmission process is effectively reduced, the operation stability of the system under complex working conditions and the accuracy and reliability of simulation testing are remarkably improved, and the method is suitable for performance evaluation and simulation testing of new energy power generation equipment.

Description

Technical Field

[0001] The invention belongs to the technical field of power hardware-in-the-loop system testing, and in particular relates to an interface method for a power hardware-in-the-loop system. Background Art

[0002] Renewable energy is gradually replacing traditional fossil fuels. The large-scale integration of new energy sources, represented by photovoltaic and wind power, is gradually transforming the power system from a structure dominated by synchronous machines to one dominated by power electronics. Due to the low inertia of new energy sources, the frequency and voltage fluctuations of the power system when subjected to disturbances are significantly increased, posing new challenges to grid stability. To study the operating characteristics of new energy systems under complex operating conditions and assess their impact on the power grid, power hardware-in-the-loop (HIL) systems have been widely used. These systems connect simulation environments with physical devices in real time, enabling real-time transmission of analog signals such as voltage and current through interface algorithm modules, thereby simulating the operating conditions of a near-real power grid.

[0003] However, in existing power hardware-in-the-loop systems, the interface algorithm module still has the following problems: On the one hand, analog signal transmission is susceptible to noise interference. In power hardware-in-the-loop systems, analog signals such as voltage and current have quantization errors during the digital-to-analog conversion and analog-to-digital conversion processes, and are also affected by factors such as electromagnetic interference during the transmission process. These noise signals accumulate in the system, reducing the accuracy of the test data and affecting the credibility of the test results. On the other hand, there are hidden dangers in the stability of the power hardware-in-the-loop system. Because the interface algorithm module needs to transmit power signals between the simulation and physical devices in real time, factors such as signal delay and phase offset may cause instability in the test system. In severe cases, it may even trigger protection actions, causing the test system to paralyze.

[0004] To address the above problems, the present invention proposes a method for interfacing power hardware-in-the-loop systems, which significantly improves the accuracy of signal transmission and system stability, thereby improving the simulation accuracy of new energy equipment under complex power grid conditions, and providing strong technical support for the stable operation and optimized design of new energy power generation systems. Summary of the Invention

[0005] The purpose of the present invention is to provide an interface method for a power hardware-in-the-loop system, which can solve the problems of signal noise interference and insufficient stability existing in the interface algorithm module of the existing power hardware-in-the-loop system.

[0006] The technical solutions adopted by the present invention are as follows:

[0007] An interface method for a power hardware-in-the-loop system, comprising the following steps:

[0008] Step 1: Obtain the output voltage on the digital side and the output current on the physical side of the current power hardware in the loop system to obtain a voltage signal and an analog current signal.

[0009] Step 2: The digital side voltage obtained in step 1 is transmitted to the physical side linear power amplifier through the voltage proportional coefficient. In step 2, the digital side voltage is transmitted to the physical side linear power amplifier through the voltage proportional coefficient, which specifically includes the following steps:

[0010] Step 201: The real-time simulator converts the voltage signal collected in step 1 into a voltage proportional coefficient k. v Perform reduction processing to complete the adaptive adjustment of the signal amplitude and obtain a digital voltage signal with stable amplitude and accuracy;

[0011] Step 202: The real-time simulator converts the digital voltage signal into a high-fidelity analog voltage signal through a high-precision digital-to-analog conversion module, and reliably transmits the processed signal to the voltage signal input terminal of the linear power amplifier;

[0012] Step 203: After receiving the high-precision analog voltage signal, the linear power amplifier performs high-speed and high-precision amplification processing on the analog signal.

[0013] Step 3: Feedback the physical side output current to the digital side controlled current source through the interface algorithm module; In step 3, feeding back the physical side output current to the digital side controlled current source through the interface algorithm module specifically includes the following steps:

[0014] Step 301: using a linear power amplifier to accurately transmit the analog current signal collected in step 1 to a real-time simulator;

[0015] Step 302: Use a real-time simulator to convert the received analog signal into a high-precision digital signal, and reliably transmit the digital signal to the FPGA high-speed computing unit to complete data processing and filtering; in step 302, in order to address the noise generated by the linear power amplifier current sensor during the sampling or transmission of analog quantities, an RC first-order low-pass filter is added during the FPGA sampling process to filter out high-frequency interference signals; wherein, R i is the filter resistor of the simulation circuit in FPGA, C i is the filter capacitor of the simulation circuit in FPGA, and the bandwidth f of the first-order low-pass filter i for

[0016]

[0017] Step 303: The digital signal output by the FPGA high-speed operation unit is filtered through a second-order low-pass filter and a current proportional coefficient k. iAfter processing, the current is fed back to the controlled current source; in step 303, the FPGA output is filtered through a second-order low-pass filter and a current proportional coefficient k i , specifically including the following steps:

[0018] Step 3031: Filter the filtered current signal through a second-order low-pass filter GPL(s)

[0019]

[0020] GPL(s) is the transfer function of the second-order low-pass filter; ω n is the natural angular frequency of the filter; ζ is the damping ratio; s is the complex frequency variable;

[0021] Step 3032: The current signal after being filtered by the second-order low-pass filter is filtered by the current proportional gain coefficient k. i After proportional amplification, it is fed back to the digital side controlled current source.

[0022] Step 4: According to Step 2 and Step 3, the interface algorithm module is optimized to complete the noise reduction process; Step 4 specifically includes the following steps:

[0023] Step 401: The voltage signal outputted by the simulator port is collected in real time and transmitted to the linear power amplifier via the interface algorithm module, thereby achieving accurate and stable physical interaction between the simulator and the physical side.

[0024] Step 402: The current signal on the physical side is collected in real time, and accurately transmitted to the controlled current source on the digital side through the optimized interface algorithm module. The digital side then performs precise calculations and updates to generate a voltage signal at the simulator output port.

[0025] The technical effects achieved by the present invention are:

[0026] The present invention first collects the output voltage on the digital side and the output current on the physical side at the same time; then, by setting the voltage proportional coefficient, the voltage signal collected on the digital side is converted into a high-fidelity analog signal through a high-precision digital-to-analog conversion module, and then amplified by a linear power amplifier to achieve stable adaptation of the signal amplitude; at the same time, the current signal output from the physical side is transmitted to the real-time simulator through the linear power amplifier, sampled and filtered by the high-speed FPGA module, and fed back to the controlled current source through a second-order low-pass filter and a current proportional coefficient. By optimizing the signal transmission path and adopting filtering compensation technology, the algorithm effectively reduces the noise accumulation caused by quantization error, electromagnetic interference and transmission delay, and significantly improves the accuracy of test data and the overall reliability of the system. In addition, the present invention improves the operating stability of the power hardware-in-the-loop system under complex working conditions, ensures that the test data is more authentic and consistent, and provides solid technical support for the simulation test and performance evaluation of new energy power generation equipment.

[0027] The present invention effectively suppresses noise interference in voltage and current signal transmission, ensures the accuracy and authenticity of test data, improves simulation verification effects, and significantly improves power hardware-in-the-loop system simulation effects and data reliability.

[0028] The present invention significantly improves system stability, effectively reduces signal delay and oscillation risks, ensures power matching between the simulation platform and physical equipment, reduces the occurrence rate of failures, ensures safe and reliable operation of the system, and significantly improves the coordinated response performance of the equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a system block diagram of an interface method for a power hardware-in-the-loop system according to the present invention.

[0030] Figure 2 This is the topology diagram of the power hardware-in-the-loop system described in the present invention.

[0031] Figure 3 This is the grid-connected inverter power hardware-in-the-loop system described in the present invention.

[0032] Figure 4 Schematic diagram of grid-connected current experimental results before and after the present invention is adopted in the grid-connected inverter power hardware in the loop system;

[0033] Figure 5 This is a schematic diagram of the experimental results of the current tracking of the power hardware-in-the-loop system under active current step conditions.

[0034] Figure 6 The present invention is a flowchart of an interface method for a power hardware-in-the-loop system. DETAILED DESCRIPTION

[0035] In order to make the purpose and advantages of the present invention more clearly understood, the present invention is described in detail below with reference to the following examples. It should be understood that the following text is only used to describe one or more specific embodiments of the present invention and does not strictly limit the scope of protection of the present invention.

[0036] like Figures 1-6 As shown, an interface method for a power hardware-in-the-loop system is characterized by comprising the following steps:

[0037] Step 1: Obtain the output voltage on the digital side and the output current on the physical side of the current power hardware in the loop system to obtain the voltage signal and analog current signal;

[0038] Step 2: The digital side voltage obtained in step 1 is transferred to the physical side linear power amplifier through the voltage proportional coefficient;

[0039] In step 2, the digital side voltage is transferred to the physical side linear power amplifier through the voltage proportional coefficient, which specifically includes the following steps:

[0040] Step 201: The real-time simulator converts the voltage signal collected in step 1 into a voltage proportional coefficient k. v Perform reduction processing to complete the adaptive adjustment of the signal amplitude and obtain a digital voltage signal with stable amplitude and accuracy;

[0041] Step 202: The real-time simulator converts the digital voltage signal into a high-fidelity analog voltage signal through a high-precision digital-to-analog conversion module, and reliably transmits the processed signal to the voltage signal input terminal of the linear power amplifier to ensure high precision and stability of the signal transmission process;

[0042] Step 203: After receiving the high-precision analog voltage signal, the linear power amplifier performs high-speed and high-precision amplification processing on the analog signal to ensure high reliability, stability and accuracy of the operation of the entire power hardware-in-the-loop system.

[0043] Step 3: Feedback the physical side output current to the digital side controlled current source through the interface algorithm module;

[0044] In step 3, the physical side output current is fed back to the digital side controlled current source through the interface algorithm module, which specifically includes the following steps:

[0045] Step 301: Using a linear power amplifier, accurately transmit the analog current signal collected in step 1 to a real-time simulator to ensure the accuracy and stability of signal transmission;

[0046] Step 302: Use a real-time simulator to convert the received analog signal into a high-precision digital signal, and reliably transmit the digital signal to the FPGA high-speed computing unit to complete efficient data processing and filtering; in step 302, in order to address the noise generated by the linear power amplifier current sensor during the sampling or transmission of analog quantities, an RC first-order low-pass filter is added during the FPGA sampling process to filter out high-frequency interference signals; wherein, R i is the filter resistor of the simulation circuit in FPGA, C i is the filter capacitor of the simulation circuit in FPGA, and the bandwidth f of the first-order low-pass filter i for

[0047]

[0048] Step 303: The digital signal output by the FPGA high-speed operation unit is filtered through a second-order low-pass filter and a current proportional coefficient k. i After processing, the signal is fed back to the controlled current source to ensure that the signal has high stability and accuracy, effectively improving the control accuracy and response performance of the overall system; in step 303, the FPGA output is filtered through a second-order low-pass filter and the current proportional coefficient k i , specifically including the following steps:

[0049] Step 3031: Filter the filtered current signal through a second-order low-pass filter GPL(s)

[0050]

[0051] GPL(s) is the transfer function of the second-order low-pass filter; ω n is the natural angular frequency (cut-off angular frequency) of the filter; ζ is the damping ratio; s is the complex frequency variable (Laplacian operator);

[0052] Step 3032: The current signal after being filtered by the second-order low-pass filter is filtered by the current proportional gain coefficient k. i After proportional amplification, it is fed back to the controlled current source on the digital side to ensure high stability, high precision and real-time response performance of the feedback signal.

[0053] Step 4: According to Step 2 and Step 3, the interface algorithm module is optimized to complete the noise reduction process; Step 4 specifically includes the following steps:

[0054] Step 401: The voltage signal outputted by the simulator port is collected in real time and transmitted to the linear power amplifier efficiently and accurately through the interface algorithm module, thereby achieving precise and stable physical interaction between the simulator and the physical side.

[0055] Step 402: The current signal on the physical side is collected in real time and accurately transmitted to the controlled current source on the digital side through the optimized interface algorithm module. The digital side then performs precise calculations and updates to generate a voltage signal at the simulator output port.

[0056] Combining steps 2 and 3 above, through the optimization of the interface algorithm module, the signal noise has been effectively reduced, which greatly improves the operational stability of the power hardware-in-the-loop system and ensures the safety, reliability and precise operation of the system.

[0057] The present invention is specifically used, such as Figure 3 As shown, Figure 3 Taking the grid-connected inverter as an example, the interface algorithm module of the power hardware is introduced. The real-time simulator (digital side) simulates the actual grid operation and transmits the voltage signal to the linear power amplifier, while the feedback current signal is transmitted to the real-time simulator. On the actual physical side, the grid-connected inverter is connected to the LC filter (where L f and C f Represent the filter inductor and filter capacitor respectively) are physically connected to the linear power amplifier.

[0058] Specifically, Figure 4 It represents the grid-connected current of the power hardware before and after the present invention is adopted in the ring system, wherein i2 represents the actual grid-connected current, i 2s is the sampled grid-connected current, i 2f is the grid-connected current processed by the RC filter, i 2c This is the grid-connected current processed by a second-order filter. It can be seen that by adopting the power interface algorithm module of the present invention, noise interference in current signal transmission is effectively suppressed. Compared with traditional processing methods, the filtered current waveform is smoother and noise is significantly reduced. This method can ensure accurate and authentic test data, improve simulation verification results, and significantly enhance the simulation effect and data reliability of power hardware-in-the-loop systems.

[0059] Specifically, Figure 5 Indicates the current tracking status of the power hardware in the loop system under active current step conditions. Figure 5 It can be observed that the grid-connected voltage v of phase a of the power hardware-in-the-loop system a and a-phase grid-connected current i a The algorithm of the present invention effectively reduces transient noise, ensuring that the system can quickly and smoothly respond to step changes in input, thereby improving the accuracy and reliability of the system. This control can effectively reduce signal delay and oscillation risks, lower the occurrence of failures, and ensure safe system operation.

[0060] The present invention first collects the output voltage on the digital side and the output current on the physical side at the same time; then, by setting the voltage proportional coefficient, the voltage signal collected on the digital side is converted into a high-fidelity analog signal through a high-precision digital-to-analog conversion module, and then amplified by a linear power amplifier to achieve stable adaptation of the signal amplitude; at the same time, the current signal output from the physical side is transmitted to the real-time simulator through the linear power amplifier, sampled and filtered by the high-speed FPGA module, and fed back to the controlled current source through a second-order low-pass filter and a current proportional coefficient. By optimizing the signal transmission path and adopting filtering compensation technology, the algorithm effectively reduces the noise accumulation caused by quantization error, electromagnetic interference and transmission delay, and significantly improves the accuracy of test data and the overall reliability of the system. In addition, the present invention improves the operating stability of the power hardware-in-the-loop system under complex working conditions, ensures that the test data is more authentic and consistent, and provides solid technical support for the simulation test and performance evaluation of new energy power generation equipment.

[0061] The present invention effectively suppresses noise interference in voltage and current signal transmission, ensures the accuracy and authenticity of test data, improves simulation verification effects, and significantly improves power hardware-in-the-loop system simulation effects and data reliability.

[0062] The present invention significantly improves system stability, effectively reduces signal delay and oscillation risks, ensures power matching between the simulation platform and physical equipment, reduces the occurrence rate of failures, ensures safe and reliable operation of the system, and significantly improves the coordinated response performance of the equipment.

[0063] The foregoing is merely a preferred embodiment of the present invention. It should be noted that those skilled in the art may make various improvements and modifications without departing from the principles of the present invention, and such improvements and modifications are also within the scope of protection of the present invention. Structures, devices, and operating methods not specifically described or explained herein shall, unless otherwise specified or limited, be implemented in accordance with conventional means in the art.

Claims

1. An interface method for a power hardware-in-the-loop system, characterized by: The following steps are involved: Step 1: Obtain the output voltage on the digital side and the output current on the physical side of the current power hardware in the loop system to obtain the voltage signal and analog current signal; Step 2: The digital side voltage obtained in step 1 is transferred to the physical side linear power amplifier through the voltage proportional coefficient; Step 3: Feedback the physical side output current to the digital side controlled current source through the interface algorithm module; Step 4: According to step 2 and step 3, the interface algorithm module is optimized to complete the noise reduction process.

2. The interface method for a power hardware-in-the-loop system according to claim 1, characterized in that: In step 2, the digital side voltage is transferred to the physical side linear power amplifier through the voltage proportional coefficient, which specifically includes the following steps: Step 201: The real-time simulator converts the voltage signal collected in step 1 into a voltage proportional coefficient k. v Perform reduction processing to complete the adaptive adjustment of the signal amplitude and obtain a digital voltage signal with stable amplitude and accuracy; Step 202: The real-time simulator converts the digital voltage signal into a high-fidelity analog voltage signal through a high-precision digital-to-analog conversion module, and reliably transmits the processed signal to the voltage signal input terminal of the linear power amplifier; Step 203: After receiving the high-precision analog voltage signal, the linear power amplifier performs high-speed and high-precision amplification processing on the analog signal.

3. The interface method for a power hardware-in-the-loop system according to claim 1, characterized in that: In step 3, the physical side output current is fed back to the digital side controlled current source through the interface algorithm module, which specifically includes the following steps: Step 301: using a linear power amplifier to accurately transmit the analog current signal collected in step 1 to a real-time simulator; Step 302: Using a real-time simulator, the received analog signal is converted into a high-precision digital signal, and the digital signal is reliably transmitted to the FPGA high-speed computing unit to complete data processing and filtering; Step 303: The digital signal output by the FPGA high-speed operation unit is filtered through a second-order low-pass filter and a current proportional coefficient k. i After processing, it is fed back to the controlled current source.

4. The interface method for a power hardware-in-the-loop system according to claim 3, characterized in that: In step 302, for the noise generated by the linear power amplifier current sensor during the sampling or transmission of analog quantities, an RC first-order low-pass filter is added during the FPGA sampling process to filter out high-frequency interference signals; wherein, R i is the filter resistor of the simulation circuit in FPGA, C i is the filter capacitor of the simulation circuit in FPGA, and the bandwidth f of the first-order low-pass filter i for 5. The interface method for a power hardware-in-the-loop system according to claim 1, characterized in that: In step 303, the FPGA output is filtered through a second-order low-pass filter and a current proportional coefficient k i , specifically including the following steps: Step 3031: Filter the filtered current signal through a second-order low-pass filter GPL(s) GPL(s) is the transfer function of the second-order low-pass filter; ω n is the natural angular frequency of the filter; ζ is the damping ratio; s is the complex frequency variable; Step 3032: The current signal after being filtered by the second-order low-pass filter is filtered by the current proportional gain coefficient k. i After proportional amplification, it is fed back to the digital side controlled current source.

6. The interface method for a power hardware-in-the-loop system according to claim 1, characterized in that: The step 4 specifically includes the following steps: Step 401: The voltage signal outputted by the simulator port is collected in real time and transmitted to the linear power amplifier via the interface algorithm module, thereby achieving accurate and stable physical interaction between the simulator and the physical side. Step 402: The current signal on the physical side is collected in real time, and accurately transmitted to the controlled current source on the digital side through the optimized interface algorithm module. The digital side then performs precise calculations and updates to generate a voltage signal at the simulator output port.

Images