Time-interleaved ADC sampling method and system

Abstract

The invention provides a time-interleaved ADC sampling method and system. The method is applied to a time-interleaved ADC sampling system. The system comprises a pseudorandom sequence generator, a decoder, an analog multiplexer, a digital multiplexer and a plurality of analog-to-digital converter sub-ADCs. The pseudo-random sequence generator is connected with the analog multiplexer and is also connected with the digital multiplexer through the decoder; the analog multiplexer is connected with the digital multiplexer through a plurality of sub-ADCs (Analog to Digital Converters); the number of paths of the digital multiplexer is M, and the number of paths of the analog multiplexer and the number of the sub-ADCs are M + 1; and during sampling of each beat of signals, multi-channel random interleaving output is realized through the pseudo-random sequence generator, the analog multiplexer, the plurality of sub-ADCs, the decoder and the digital multiplexer. According to the invention, random sampling is realized through the plurality of sub-ADCs, the stray period is disrupted, the stray is converted into a noise floor, and the noise floor is dispersed in the whole Nyquist band, so that the residual stray is corrected.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a time-interleaved ADC sampling method and system. Background Art

[0002] The main function of a multi-channel time-interleaved ADC (Analog-to-digital converter) is to increase the overall ADC sampling rate (Fs) by using multiple sub-ADCs for parallel sampling. However, this process introduces interleaving spurs, which are mainly caused by three types of analog imperfections: 1) offset, 2) gain, and 3) timing skew. For multi-channel interleaved ADCs, although correction has been performed in the existing technology, residual interleaving spurs still exist. This is due to the limitation of correction accuracy, which makes it impossible to perfectly calibrate the mismatch in the analog domain. Interleaving spurs are very sensitive to mismatch, so the interleaving spurs are greatly reduced after correction, but residual spurs still exist. Summary of the Invention

[0003] The purpose of this application is to provide a time-interleaved ADC sampling method and system, which uses a randomization method to ensure that the sub-ADCs are sampled randomly rather than sequentially. This can disrupt the spurious period, convert the spurious into a noise floor, and disperse it throughout the Nyquist band, thereby correcting the residual spurious. Furthermore, it can also achieve timing skew correction for inputting special frequency points.

[0004] In a first aspect, the present application provides a time-interleaved ADC sampling method, which is applied to a time-interleaved ADC sampling system; the system includes: a pseudo-random sequence generator, a decoder, an analog multiplexer, a digital multiplexer, and multiple analog-to-digital converter sub-ADCs; the pseudo-random sequence generator is connected to the analog multiplexer and is also connected to the digital multiplexer through the decoder; the analog multiplexer is connected to the digital multiplexer through multiple sub-ADCs; the number of channels of the digital multiplexer is M, and the number of channels of the analog multiplexer and the number of sub-ADCs are both M+1; when sampling each signal, the following steps are performed: the pseudo-random sequence generator outputs a first pseudo-random signal to the analog multiplexer; the analog multiplexer selects a corresponding target sub-ADC to output the currently connected analog signal based on the first pseudo-random signal; the target sub-ADC converts the analog signal into a digital signal and sends it to the digital multiplexer; the decoder decodes the first pseudo-random signal to obtain a second pseudo-random signal and sends it to the digital multiplexer; the digital multiplexer selects a corresponding output channel based on the second pseudo-random signal and outputs the digital signal of the target sub-ADC.

[0005] Furthermore, the pseudo-random sequence generator includes: a pseudo-random binary sequence module, a RAM memory, and a FIFO queue; the FIFO queue pre-stores sub-ADC identifiers corresponding to M sub-ADCs; an address in the RAM memory corresponds to a binary sequence, and a preset sub-ADC identifier is stored in one address; the preset sub-ADC identifier is the sub-ADC identifier corresponding to the M+1th sub-ADC; the step of the pseudo-random sequence generator outputting a first pseudo-random signal to the analog multiplexer includes: if the current beat number is less than or equal to M, determining the sub-ADC identifier at the front end of the current array according to the order of the sub-ADC identifiers in the FIFO queue as the first pseudo-random signal and outputting it to the analog multiplexer; if the current beat number is greater than M, the pseudo-random binary sequence module inputs a random binary number into the RAM memory; the RAM memory selects the sub-ADC identifier at the corresponding target address based on the random binary number and adds it to the FIFO queue, outputs the sub-ADC identifier at the target address as the first pseudo-random signal to the analog multiplexer, and stores the first sub-ADC identifier in the FIFO queue at the target address in the RAM memory.

[0006] Furthermore, in the above-mentioned M+1 sub-ADCs, M is a regular number corresponding to the sub-ADCs, or M+1 is a regular number corresponding to the sub-ADCs; the regular number includes: 2, 4, 8 or 16.

[0007] Furthermore, the number M of sub-ADCs is determined as follows: obtain the total ADC sampling rate and the highest sampling rate that the current sub-ADC can achieve; and divide the total ADC sampling rate by the highest sampling rate of the current sub-ADC to obtain the quotient M.

[0008] Furthermore, the decoder is used to decode a sequence of 1 to M+1 into a sequence of 1 to M.

[0009] Furthermore, the above method also includes: aligning the timing deviation of the third designated sub-ADC with the sampling signal of the first designated sub-ADC and the sampling signal of the second designated sub-ADC as references; for the case of M+1=4, performing the timing deviation alignment three times according to the above steps: for the first time, the sampling signal of the first designated sub-ADC is the k-th sampling signal of the first sub-ADC; the sampling signal of the second designated sub-ADC is the k+1-th sampling signal of the first sub-ADC; the third designated sub-ADC is the third sub-ADC; for the second time, the sampling signal of the first designated sub-ADC is the k-th sampling signal of the first sub-ADC; the sampling signal of the second designated sub-ADC is the k-th sampling signal of the third sub-ADC; the third designated sub-ADC is the second sub-ADC; for the third time, the sampling signal of the first designated sub-ADC is the k-th sampling signal of the third sub-ADC; the sampling signal of the second designated sub-ADC is the k+1-th sampling signal of the first sub-ADC; and the third designated sub-ADC is the fourth sub-ADC.

[0010] Furthermore, the step of aligning the timing deviation of the third designated sub-ADC with the sampling signal of the first designated sub-ADC and the sampling signal of the second designated sub-ADC as a reference includes: searching, from the random interleaved sampling spectrum, for first sampling situations in which the third designated sub-ADC is immediately followed by all the first designated sub-ADCs; and for second sampling situations in which the first designated sub-ADC is immediately followed by all the third designated sub-ADCs; calculating a first correlation value based on the sampling signals of the first designated sub-ADC and the third designated sub-ADC in the first sampling situation; calculating a second correlation value based on the sampling signals of the third designated sub-ADC and the first designated sub-ADC in the second sampling situation; and aligning the timing deviation of the third designated sub-ADC based on the first correlation value and the second correlation value.

[0011] Furthermore, the step of calculating the first correlation value based on the sampled signals of the first designated sub-ADC and the third designated sub-ADC in the first sampling situation includes: performing a multiplication-accumulation operation according to the following formula to obtain the first correlation value vxcorr1:

[0012]

[0013] Wherein, y1(k) represents the sampling signal of the first designated sub-ADC; y3(k) represents the k-th sampling signal of the third designated sub-ADC; N represents the preset accumulation length;

[0014] The step of calculating the second correlation value based on the sampling signals of the third designated sub-ADC and the first designated sub-ADC in the second sampling situation includes: performing a multiplication-accumulation operation according to the following formula to obtain the second correlation value vxcorr2:

[0015]

[0016] Furthermore, the step of aligning the timing deviation of the third designated sub-ADC based on the first correlation value and the second correlation value includes: if the first correlation value is greater than the second correlation value, adjusting the delay of the third designated sub-ADC by increasing one step; if the first correlation value is less than the second correlation value, adjusting the delay of the third designated sub-ADC by decreasing one step; if the first correlation value is equal to the second correlation value, keeping the delay of the third designated sub-ADC unchanged.

[0017] In a second aspect, the present application also provides a time-interleaved ADC sampling system, which includes: a pseudo-random sequence generator, a decoder, an analog multiplexer, a digital multiplexer, and multiple analog-to-digital converter sub-ADCs; the pseudo-random sequence generator is connected to the analog multiplexer, and is also connected to the digital multiplexer through the decoder; the analog multiplexer is connected to the digital multiplexer through multiple sub-ADCs; the number of ways of the digital multiplexer is M, and the number of ways of the analog multiplexer and the number of sub-ADCs are both M+1; the time-interleaved ADC sampling system is used to perform the method described in any one of claims 1 to 9.

[0018] The present application provides a time-interleaved ADC sampling method and system, the method being applied to a time-interleaved ADC sampling system; the system comprising: a pseudo-random sequence generator, a decoder, an analog multiplexer, a digital multiplexer, and a plurality of analog-to-digital converter sub-ADCs; the pseudo-random sequence generator being connected to the analog multiplexer and also connected to the digital multiplexer through the decoder; the analog multiplexer being connected to the digital multiplexer through a plurality of sub-ADCs; the number of paths of the digital multiplexer being M, and the number of paths of the analog multiplexer and the number of sub-ADCs being M+1; and the following steps being performed during each signal sampling: the pseudo-random sequence generator outputting a first pseudo-random signal to the analog multiplexer; the analog multiplexer selecting a corresponding target sub-ADC to output the currently connected analog signal based on the first pseudo-random signal; the target sub-ADC converting the analog signal into a digital signal and sending it to the digital multiplexer; the decoder performing decoding processing based on the first pseudo-random signal to obtain a second pseudo-random signal and sending it to the digital multiplexer; and the digital multiplexer selecting a corresponding output path based on the second pseudo-random signal and outputting the digital signal of the target sub-ADC. This application uses a randomization method to ensure that the sub-ADC samples randomly instead of sequentially. This can disrupt the spurious period, convert the spurious into a noise floor, and disperse it throughout the Nyquist band, thereby correcting the residual spurious. On this basis, it can also achieve timing skew correction for inputting special frequency points. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0020] Figure 1 A flowchart of a time-interleaved ADC sampling method provided in an embodiment of the present application;

[0021] Figure 2A schematic diagram of the structure of a time-interleaved ADC sampling system provided in an embodiment of the present application;

[0022] Figure 3 A schematic diagram of the structure of a pseudo-random sequence generator provided in an embodiment of the present application;

[0023] Figure 4 A schematic diagram of a single-sided spectrum corresponding to the presence or absence of random interleaving provided in an embodiment of the present application;

[0024] Figure 5 Schematic diagram of the total ADC output and four sub-ADC output waveforms when sequential interleaving is performed, the analog input is a special single tone point (Fs / 4), and the sub-ADCs have timing skew;

[0025] Figure 6 A schematic diagram of a random interleaved sampling pattern provided in an embodiment of the present application;

[0026] Figure 7 This is a schematic diagram of the total ADC output and four sub-ADC output waveforms when random interleaving is provided in an embodiment of the present application, the analog input is a special single tone point (Fs / 4), and the sub-ADCs have timing skew;

[0027] Figure 8 A schematic structural diagram of another time-interleaved ADC sampling system provided in an embodiment of the present application;

[0028] Figure 9 A schematic diagram of the structure of another pseudo-random sequence generator provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] The following will clearly and completely describe the technical solutions of this application in conjunction with the embodiments. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0030] With respect to the multi-channel interleaved ADC in the prior art, although correction is performed, the problem of residual interleaved spurs still exists. The embodiments of the present application provide a time-interleaved ADC sampling method and system. By using a randomization method, the sub-ADCs are sampled randomly rather than sequentially. This can disrupt the spurious period, convert the spurs into a noise floor, and disperse them throughout the Nyquist band, thereby correcting the residual spurs.

[0031] To facilitate understanding of this embodiment, a time-interleaved ADC sampling method disclosed in an embodiment of the present application is first introduced in detail.

[0032] Figure 1 This is a flowchart of a time-interleaved ADC sampling method provided in an embodiment of the present application, which is applied to a time-interleaved ADC sampling system; see Figure 2 As shown, the system includes: a pseudo-random sequence generator, a decoder, an analog multiplexer, a digital multiplexer, and multiple analog-to-digital converter sub-ADCs; the pseudo-random sequence generator is connected to the analog multiplexer and is also connected to the digital multiplexer through the decoder; the analog multiplexer is connected to the digital multiplexer through multiple sub-ADCs; the number of paths of the digital multiplexer is M, and the number of paths of the analog multiplexer and the number of sub-ADCs are both M+1; when sampling each signal, the following steps are performed:

[0033] Step S102: the pseudo-random sequence generator outputs a first pseudo-random signal to the analog multiplexer;

[0034] See also Figure 3 As shown, the pseudo-random sequence generator includes: a pseudo-random binary sequence module (shown as prbs in the figure), a RAM memory (shown as ram in the figure), and a FIFO queue (shown as fifo in the figure); the FIFO queue pre-stores sub-ADC identifiers corresponding to M sub-ADCs (such as identifiers 1, 2, ..., M in the figure); the addresses in the RAM memory correspond to a binary sequence (such as 0 and 1 in the figure, and in some other embodiments, can also be 00, 01, 10, 11 to further improve randomness), and one address stores a preset sub-ADC identifier; the preset sub-ADC identifier is the sub-ADC identifier corresponding to the M+1th sub-ADC (such as identifier M+1 in the figure);

[0035] Based on the specific structure of the pseudo-random sequence generator, the step of the pseudo-random sequence generator outputting the first pseudo-random signal to the analog multiplexer includes:

[0036] (1) If the current beat number is less than or equal to M, the sub-ADC identifier at the front end of the current array is determined according to the sub-ADC identifier order in the FIFO queue as the first pseudo-random signal to be output to the analog multiplexer;

[0037] For example, the sub-ADC identification order in the FIFO queue is 1, 2, 3...M. When the current beat number is 1, the first pseudo-random signal output to the analog multiplexer is 1; when the current beat number is 2, the first pseudo-random signal output to the analog multiplexer is 2; when the current beat number is 3, the first pseudo-random signal output to the analog multiplexer is 3... When the current beat number is M, the first pseudo-random signal output to the analog multiplexer is M.

[0038] (2) If the current beat number is greater than M, the pseudo-random binary sequence module inputs a random binary number into the RAM memory; the RAM memory selects the sub-ADC identifier in the target address corresponding to the random binary number and adds it to the FIFO queue, and outputs the sub-ADC identifier in the target address as the first pseudo-random signal to the analog multiplexer, and stores the first sub-ADC identifier in the FIFO queue in the target address of the RAM memory.

[0039] Taking the binary sequences corresponding to the addresses in the RAM memory as 0 and 1 as an example, when the current beat number is M+1, the sub-ADC identifiers corresponding to the binary sequences 0 and 1 are M+1 and 1, respectively. When the pseudo-random binary sequence module inputs a random binary number of 0 to the RAM memory, the sub-ADC identifier M+1 corresponding to 0 is output as the first pseudo-random signal to the analog multiplexer, and the first sub-ADC identifier 2 in the FIFO queue is stored in the target address 0 of the RAM memory. If the pseudo-random binary sequence module inputs a random binary number of 1 to the RAM memory, the sub-ADC identifier 1 corresponding to 1 is output as the first pseudo-random signal to the analog multiplexer, and the first sub-ADC identifier 2 in the FIFO queue is stored in the target address 1 of the RAM memory.

[0040] In this embodiment, the PRBS module generates a pseudo-random sequence of 0s and 1s. This sequence selects a RAM address, and the sub-ADC number at that address is the sub-ADC to be activated at that moment. Upon activation, the sub-ADC number is entered into a FIFO queue, which simultaneously outputs a sub-ADC number into RAM (Random Access Memory). This cycle continues to generate a pseudo-random sequence between 1 and M+1.

[0041] Step S104: the analog multiplexer selects the corresponding target sub-ADC according to the first pseudo-random signal to output the currently connected analog signal;

[0042] For example, if the pseudo-random sequence generator outputs the first pseudo-random signal 1 to the analog multiplexer, the analog multiplexer selects the sub-ADC1 corresponding to the identifier 1 to output the currently connected analog signal.

[0043] Step S106 , the target sub-ADC converts the analog signal into a digital signal and sends it to the digital multiplexer;

[0044] Taking the above example again, the sub-ADC1 converts the analog signal into a digital signal and sends it to the digital multiplexer.

[0045] Step S108: The decoder performs decoding processing on the first pseudo-random signal to obtain a second pseudo-random signal and sends it to the digital multiplexer;

[0046] The decoder is used to decode the sequence of 1 to M+1 into a sequence of 1 to M. By decoding the first pseudo-random signal, the first pseudo-random signal identifier 1 is converted into a value in the sequence of 1 to M in chronological order. For example, if it is still 1, the identifier 1 is sent to the digital multiplexer.

[0047] Step S110 : The digital multiplexer selects a corresponding output path according to the second pseudo-random signal, and outputs the digital signal of the target sub-ADC.

[0048] The digital multiplexer outputs the digital signal converted by the sub-ADC1 through the output path number corresponding to the identifier 1.

[0049] For example, when 4-way interleaving is used, there are 4 sub-ADCs, but the digital multiplexer can only output 3 digital signals. The decoder maps the randomized outputs of the 4 sub-ADCs to the 3 outputs of the digital multiplexer in chronological order.

[0050] 1) At the Kth beat, the digital decoder connects the output of the sub-ADC4 to the first output of the digital multiplexer to output the digital signal of the sub-ADC4 through the first output pin;

[0051] 2) At the K+1th beat, the analog side selects sub-ADC1 between sub-ADC1 and sub-ADC2; the digital side connects the output of sub-ADC1 to the second output of the digital multiplexer;

[0052] 3) At the K+2th beat, the analog side selects sub-ADCx, and the digital side connects the output of the selected sub-ADCx to the third output of the digital multiplexer.

[0053] The above steps illustrate the output process of a single-beat sampling signal. After outputting multiple-beat signals, a randomly interleaved output sampling signal, i.e., a digital signal, can be obtained.

[0054] In this embodiment, there are two operation modes:

[0055] First, in the M+1 sub-ADCs, M is the regular number of sub-ADCs, i.e., M=2, 4, 8, or 16; equivalent to M+1=3, 5, 9, or 17;

[0056] The second type is that M+1 is the regular number of sub-ADCs; that is, M+1=2, 4, 8 or 16.

[0057] In practical applications, the specific number of sub-ADCs used can be calculated using the following method to calculate the M value in the number of sub-ADCs:

[0058] Obtain the total ADC sampling rate and the maximum sampling rate that the current sub-ADC can achieve. Divide the total ADC sampling rate by the maximum sampling rate of the current sub-ADC, and the resulting quotient is M.

[0059] For example, the total ADC sampling rate Fs is obtained, and based on the current sub-ADC design and chip process level, the maximum achievable sub-ADC sampling rate Fs_sub is given. Using Fs / Fs_sub, the number of sub-ADCs for traditional time-interleaved sampling is obtained, and one sub-ADC is added for random interleaving.

[0060] For example: Fs = 1000MHz,

[0061] 1) If the maximum sampling rate achieved by the sub-ADC is Fs_sub = 250 MHz, then 4 + 1 = 5 sub-ADCs are required to achieve random interleaving;

[0062] 2) If the highest sampling rate Fs_sub achieved by the sub-ADC is 333.33 MHz, 3+1=4 sub-ADCs are required to achieve random interleaving.

[0063] The time-interleaved ADC sampling method provided in the embodiment of the present application changes the sampling order of the time-interleaved ADC, and realizes the pseudo-random selection and sampling of each sub-ADC, such as Figure 2 Compared to traditional time-interleaved ADCs, this solution adds an additional sub-ADC to implement random interleaving of multiple sub-ADCs. For every fs clock, a pseudo-random sequence generator generates a pseudo-random sequence between 1 and M+1, which is used for multi-channel interleaving on the analog side and multi-channel deinterleaving on the digital side.

[0064] above Figure 2 and Figure 3 The first implementation structure is shown; Figure 8 and Figure 9 The second implementation is shown. For the case of random interleaving of four sub-ADCs, the first implementation uses three digital channels, operating at a clock rate of fs / 3. The second implementation uses four digital channels, operating at a clock rate of fs / 4. From a circuit design perspective, the second implementation is easier to implement. In practical applications, the first implementation is suitable when using 4+1 random sub-ADCs; the second implementation is suitable when using four random sub-ADCs.

[0065] The following uses 8-channel ADC time interleaving as an example to provide two application examples. For example, if the ADC module sampling rate is 10GHz, there are two implementation methods:

[0066] Method 1 uses 8+1 sub-ADCs, with each sub-ADC sampling at 10G / 8 = 1.25GHz. The default sub-ADC initialization interleaving order is 1-2-3-4-5-6-7-8, so:

[0067] On the 9th beat, the sub-ADC will randomly select between 1 and 9, determined by the prbs output on beat 9. Assume that 1 is selected.

[0068] At the 10th beat, the sub-ADC will randomly select between 2 and 9, determined by the prbs output of the 10th beat. Assume that 9 is selected.

[0069] On the 11th beat, the sub-ADC will randomly select between 2 and 3, determined by the prbs output on the 11th beat.

[0070] Beat 12, and so on.

[0071] Method 2 uses 7+1 sub-ADCs, with each sub-ADC sampling at 10G / 7≈1.43GHz. Compared to method 1, this saves one sub-ADC; however, the sampling rate of each ADC increases from 1.25GHz to 1.43GHz. This trade-off is a matter of practical consideration.

[0072] The preset sub-ADC initialization interleaving order is: 1-2-3-4-5-6-7, then:

[0073] On beat 8, the sub-ADC will randomly select between 1 and 8, determined by the prbs output on beat 8. Assume that 8 is selected.

[0074] On the 9th beat, the sub-ADC will randomly select between 1 and 9, determined by the prbs output on beat 9. Assume that 1 is selected.

[0075] On the 10th beat, the sub-ADC will randomly select between 2 and 9, determined by the prbs output on beat 10. Assume that 9 is selected.

[0076] Beat 11, and so on.

[0077] Without interleaving, the sampling points of the eight ADC channels are fixed in timing, resulting in fixed timing offsets between each ADC channel and the others. However, with randomization, the timing offsets of each ADC channel vary randomly, thus randomizing the spurious signals introduced by the timing offsets, effectively converting them into a noise floor. Enabling random interleaving disperses the remaining interleaved spurious signals into the noise floor, subtly increasing the noise floor and correcting for residual spurious signals.

[0078] In addition, a single-sided spectrum image is plotted based on the digital signals sampled during the multi-beat signal sampling. The horizontal axis of the single-sided spectrum image represents frequency, and the vertical axis represents normalized digital power. The spurious-free dynamic range (SFDR) can then be determined based on the single-sided spectrum image.

[0079] Compared with the prior art, the multi-channel interleaved sampling method provided in the embodiment of the present application can solve the residual interleaved spurious problem after multi-channel interleaved mismatch correction and improve SFDR. Figure 4 The left figure shows the SFDR after interleaving mismatch correction of the 8-way ADC, which is -71.5dBFs. Figure 4 The figure on the right shows the SFDR of the 8-channel ADC after random interleaving is turned on, and the SFDR is improved to -85.9dBFs.

[0080] In addition, the existing timing skew correction method cannot correct the single tone input at a special frequency point, such as Figure 5 The diagram shows the total ADC output waveform and the four ADC output waveforms without random interleaving. Because the four ADC output waveforms are essentially straight lines, correlation values cannot be obtained, and timing skew correction is also impossible. In this embodiment of the present application, the random interleaving method described above can solve the problem of being unable to correct timing skew when inputting at specific frequencies.

[0081] That is, the above method further includes:

[0082] Aligning the timing deviation of the third designated sub-ADC with the sampling signal of the first designated sub-ADC and the sampling signal of the second designated sub-ADC as references;

[0083] For the case where M+1=4, perform three timing skew alignments according to the above steps:

[0084] For the first time, the sampling signal of the first designated sub-ADC is the k-th sampling signal of the first sub-ADC; the sampling signal of the second designated sub-ADC is the k+1-th sampling signal of the first sub-ADC; the third designated sub-ADC is the third sub-ADC;

[0085] The second time, the sampling signal of the first designated sub-ADC is the k-th sampling signal of the first sub-ADC; the sampling signal of the second designated sub-ADC is the k-th sampling signal of the third sub-ADC; the third designated sub-ADC is the second sub-ADC;

[0086] For the third time, the sampling signal of the first designated sub-ADC is the kth sampling signal of the third sub-ADC; the sampling signal of the second designated sub-ADC is the k+1th sampling signal of the first sub-ADC; and the third designated sub-ADC is the fourth sub-ADC.

[0087] Take 4-way random interleaving as an example:

[0088] Step 1: Align the timing skew of ADC3 using sub-ADC1(k) and sub-ADC1(k+1) as references.

[0089] Step 2: Align the timing skew of sub-ADC2 using sub-ADC1(k) and sub-ADC3(k) as references.

[0090] Step 3: Align the timing skew of sub-ADC4 using sub-ADC3(k) and sub-ADC1(k+1) as references.

[0091] Furthermore, the step of aligning the timing deviation of the third designated sub-ADC using the sampling signal of the first designated sub-ADC and the sampling signal of the second designated sub-ADC as references includes:

[0092] (1) From the random interleaved sampling spectrum, find all first sampling situations where the first designated sub-ADC is followed by the third designated sub-ADC; and all second sampling situations where the third designated sub-ADC is followed by the first designated sub-ADC; the 4-way random interleaved sampling spectrum is as follows Figure 6 shown.

[0093] (2) calculating a first correlation value based on the sampling signals of the first designated sub-ADC and the third designated sub-ADC in the first sampling case; and calculating a second correlation value based on the sampling signals of the third designated sub-ADC and the first designated sub-ADC in the second sampling case;

[0094] The step of calculating the first correlation value based on the sampled signals of the first designated sub-ADC and the third designated sub-ADC in the first sampling situation includes: performing a multiplication-accumulation operation according to the following formula to obtain the first correlation value vxcorr1:

[0095]

[0096] Wherein, y1(k) represents the sampling signal of the first designated sub-ADC; y3(k) represents the k-th sampling signal of the third designated sub-ADC; N represents the preset accumulation length;

[0097] The step of calculating the second correlation value based on the sampling signals of the third designated sub-ADC and the first designated sub-ADC in the second sampling situation includes: performing a multiplication-accumulation operation according to the following formula to obtain the second correlation value vxcorr2:

[0098]

[0099] (3) Aligning the timing offset of the third designated sub-ADC based on the first correlation value and the second correlation value.

[0100] In a specific implementation, if the first correlation value is greater than the second correlation value, the delay of the third designated sub-ADC is adjusted to increase one step; if the first correlation value is less than the second correlation value, the delay of the third designated sub-ADC is adjusted to decrease one step; if the first correlation value is equal to the second correlation value, the delay of the third designated sub-ADC is kept unchanged.

[0101] Take the first step above as an example:

[0102] In the random interleaving graph, find all sampling situations where sub-ADC1 is followed by sub-ADC3. Multiply the outputs of sub-ADC1 and sub-ADC3 at these two moments and accumulate them for a fixed length N (this length is configurable). This is recorded as vxcorr1:

[0103]

[0104] Here, y1 represents the output of sub-ADC1, and y3 represents the output of sub-ADC3.

[0105] In the random interleaving graph, find all points where sub-ADC3 is immediately followed by sub-ADC1. Multiply the outputs of sub-ADC3 and sub-ADC1 at these two moments, add the same length N, and record it as vxcorr2. The calculation method of vxcorr2 is similar and will not be described here.

[0106] The calculation process for the second and third steps is similar. For example, when calculating the second step, in the random interleaving graph, find the sampling situation where sub-ADC1 is immediately followed by sub-ADC2, and calculate vx1; find the sampling situation where sub-ADC2 is immediately followed by sub-ADC3, and calculate vx2.

[0107] Figure 7 The figure shows the waveforms of the total ADC output and the outputs of the four sub-ADCs when timing deviation occurs. After adding a random input at a specific frequency (e.g., FS / 4 = 250 MHz), constrained random interleaving is performed, the timing deviation value is adjusted, and the corresponding correlation value is calculated. The correlation value can reflect the timing deviation, and the difference between vxcorr1 and vxcorr2 is calculated and compared with 0, which can be used as a basis for calibrating the timing deviation.

[0108] In the embodiments of this application, for single-tone correction scenarios at specific frequencies, randomization breaks the fixed sampling of identical data by each sub-ADC, allowing timing skew correction to be achieved through correlation methods. For example, with two-channel interleaving, the outputs of the two ADCs are y1(k) and y2(k). The correlation between y1(k) and y2(k) and the correlation between y1(k+1) and y2(k) are calculated and compared. The analog delay is adjusted so that the two correlation values are identical, completing the timing skew correction.

[0109] Compared with the prior art, the time-interleaved ADC sampling method provided by the embodiment of the present application can solve the residual interleaving spurious after multi-channel interleaving mismatch correction, improve SFDR, and accurately correct the timing skew for single-tone input at a specific frequency.

[0110] Based on the above method embodiment, the present application embodiment also provides a time interleaved ADC sampling system, see Figure 2 As shown, the system includes: a pseudo-random sequence generator, a decoder, an analog multiplexer, a digital multiplexer, and multiple analog-to-digital converter sub-ADCs; the pseudo-random sequence generator is connected to the analog multiplexer and is also connected to the digital multiplexer through the decoder; the analog multiplexer is connected to the digital multiplexer through multiple sub-ADCs; the number of ways of the digital multiplexer is M, and the number of ways of the analog multiplexer and the number of sub-ADCs are both M+1; the time-interleaved ADC sampling system is used to execute the method described in the above embodiment.

[0111] The system provided in the embodiment of the present application has the same implementation principle and technical effects as those in the aforementioned method embodiment. For the sake of brief description, for matters not mentioned in the embodiment of the system, reference can be made to the corresponding content in the aforementioned method embodiment.

[0112] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0113] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The scope of protection of the present application is not limited thereto. Although the present application has been described in detail with reference to the above-described embodiments, those skilled in the art should understand that any person skilled in the art can modify or easily conceive of changes to the technical solutions described in the above-described embodiments within the technical scope disclosed in the present application, or perform equivalent replacements for some of the technical features thereof. These modifications, changes, or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application shall be subject to the scope of protection of the claims.

Claims

1. A time-interleaved ADC sampling method, characterized in that: The method is applied to a time-interleaved ADC sampling system; the system comprises: a pseudo-random sequence generator, a decoder, an analog multiplexer, a digital multiplexer, and a plurality of analog-to-digital converter sub-ADCs; the pseudo-random sequence generator is connected to the analog multiplexer and is also connected to the digital multiplexer through the decoder; the analog multiplexer is connected to the digital multiplexer through a plurality of sub-ADCs; the number of ways of the digital multiplexer is M, and the number of ways of the analog multiplexer and the number of sub-ADCs are both M+1; When sampling each signal, the following steps are performed: The pseudo-random sequence generator outputs a first pseudo-random signal to the analog multiplexer; The analog multiplexer selects the corresponding target sub-ADC according to the first pseudo-random signal to output the currently connected analog signal; The target sub-ADC converts the analog signal into a digital signal and sends it to the digital multiplexer; The decoder performs decoding processing on the first pseudo-random signal to obtain a second pseudo-random signal and sends it to the digital multiplexer; The digital multiplexer selects a corresponding output path according to the second pseudo-random signal and outputs the digital signal of the target sub-ADC.

2. The method according to claim 1, characterized in that The pseudo-random sequence generator includes: a pseudo-random binary sequence module, a RAM memory, and a FIFO queue; the FIFO queue pre-stores sub-ADC identifiers corresponding to M sub-ADCs; the addresses in the RAM memory correspond to the binary sequence, and one address stores a preset sub-ADC identifier; the preset sub-ADC identifier is the sub-ADC identifier corresponding to the M+1th sub-ADC; The step of outputting a first pseudo-random signal from the pseudo-random sequence generator to the analog multiplexer comprises: If the current beat number is less than or equal to M, determine the front-end sub-ADC identifier of the current array according to the sub-ADC identifier order in the FIFO queue as the first pseudo-random signal to be output to the analog multiplexer; If the current beat number is greater than M, the pseudo-random binary sequence module inputs a random binary number into the RAM memory; the RAM memory selects a sub-ADC identifier in a corresponding target address based on the random binary number and adds the identifier to the FIFO queue, outputs the sub-ADC identifier in the target address as a first pseudo-random signal to the analog multiplexer, and stores the first sub-ADC identifier in the FIFO queue in the target address of the RAM memory.

3. The method according to claim 1, characterized in that Among the M+1 sub-ADCs, M is the normal number corresponding to the sub-ADCs, or M+1 is the normal number corresponding to the sub-ADCs; the normal number includes: 2, 4, 8 or 16.

4. The method according to claim 1, wherein The number of sub-ADCs, M, is determined as follows: Get the total ADC sampling rate and the maximum sampling rate that the current sub-ADC can achieve; The total ADC sampling rate is divided by the highest sampling rate of the current sub-ADC, and the quotient obtained is M.

5. The method according to claim 1, wherein The decoder is used to decode a sequence of 1 to M+1 into a sequence of 1 to M.

6. The method according to claim 1, characterized in that The method further comprises: Aligning the timing deviation of the third designated sub-ADC with the sampling signal of the first designated sub-ADC and the sampling signal of the second designated sub-ADC as references; For the case where M+1=4, perform three timing skew alignments according to the above steps: For the first time, the sampling signal of the first designated sub-ADC is the k-th sampling signal of the first sub-ADC; the sampling signal of the second designated sub-ADC is the k+1-th sampling signal of the first sub-ADC; and the third designated sub-ADC is the third sub-ADC; The second time, the sampling signal of the first designated sub-ADC is the k-th sampling signal of the first sub-ADC; the sampling signal of the second designated sub-ADC is the k-th sampling signal of the third sub-ADC; the third designated sub-ADC is the second sub-ADC; For the third time, the sampling signal of the first designated sub-ADC is the kth sampling signal of the third sub-ADC; the sampling signal of the second designated sub-ADC is the k+1th sampling signal of the first sub-ADC; and the third designated sub-ADC is the fourth sub-ADC.

7. The method according to claim 6, characterized in that The step of aligning the timing deviation of the third designated sub-ADC with the sampling signal of the first designated sub-ADC and the sampling signal of the second designated sub-ADC as references includes: From the random interleaved sampling spectrum, find all first sampling situations where the first designated sub-ADC is immediately followed by the third designated sub-ADC; and all second sampling situations where the third designated sub-ADC is immediately followed by the first designated sub-ADC; Calculating a first correlation value based on the sampled signals of the first designated sub-ADC and the third designated sub-ADC in the first sampling case; calculating a second correlation value based on the sampled signals of the third designated sub-ADC and the first designated sub-ADC in the second sampling case; The timing offset of the third designated sub-ADC is aligned based on the first correlation value and the second correlation value.

8. The method according to claim 7, characterized in that The step of calculating the first correlation value based on the sampled signals of the first designated sub-ADC and the third designated sub-ADC in the first sampling situation includes: performing a multiplication-accumulation operation according to the following formula to obtain the first correlation value vxcorrl: Wherein, y1(k) represents the sampling signal of the first designated sub-ADC; y3(k) represents the k-th sampling signal of the third designated sub-ADC; N represents the preset accumulation length; The step of calculating the second correlation value based on the sampling signals of the third designated sub-ADC and the first designated sub-ADC in the second sampling situation includes: performing a multiplication-accumulation operation according to the following formula to obtain the second correlation value vxcorr2:

9. The method according to claim 7, characterized in that The step of aligning the timing deviation of the third designated sub-ADC based on the first correlation value and the second correlation value includes: If the first correlation value is greater than the second correlation value, adjusting the delay of the third designated sub-ADC by increasing a step; If the first correlation value is less than the second correlation value, adjusting the delay of the third designated sub-ADC to decrease by one step; If the first correlation value is equal to the second correlation value, the delay of the third designated sub-ADC is kept unchanged.

10. A time-interleaved ADC sampling system, characterized in that: The system includes: a pseudo-random sequence generator, a decoder, an analog multiplexer, a digital multiplexer, and multiple analog-to-digital converter sub-ADCs; the pseudo-random sequence generator is connected to the analog multiplexer and is also connected to the digital multiplexer through the decoder; the analog multiplexer is connected to the digital multiplexer through multiple sub-ADCs; the number of ways of the digital multiplexer is M, and the number of ways of the analog multiplexer and the number of sub-ADCs are both M+1; the time-interleaved ADC sampling system is used to perform the method according to any one of claims 1 to 9.

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