Time synchronization method, device and system

Abstract

The invention relates to a time synchronization method and system, the method is applied to the time synchronization system, the system comprises a machine frame type device, a mainboard of the machine frame type device is electrically connected with a slot position plate, the mainboard comprises a first phase-locked loop and a second phase-locked loop which are electrically connected with a first FPGA, the slot position plate comprises a second FPGA, and the first FPGA is electrically connected with the second FPGA. The first phase-locked loop and the second phase-locked loop are electrically connected with the first FPGA, the third phase-locked loop and the fourth phase-locked loop are electrically connected with the second FPGA, the third phase-locked loop and the first phase-locked loop are homologous in clock and used for controlling a system clock, and the fourth phase-locked loop and the second phase-locked loop are homologous in clock and used for controlling system time. Determining the deviation between the slot position plate and the opposite terminal equipment according to the timestamp; and updating the main board system time and the slot position board system time according to the deviation through the second phase-locked loop and the fourth phase-locked loop.

Description

Technical Field

[0001] The present application relates to the field of time synchronization technology, and in particular to a time synchronization method and system. Background Art

[0002] With the rapid development of emerging technologies such as 5G, the Industrial Internet, and smart grids, network requirements for time synchronization accuracy have significantly increased. Traditional time synchronization technologies can no longer meet these demands.

[0003] Traditional time synchronization methods, when implemented based on transmission technologies such as Optical Transport Network (OTN), Slicing Packet Network (SPN), Packet Transport Network (PTN), and IP Radio Access Network (IPRAN), rely on clock synchronization, and the synchronization accuracy is affected by message delay, resulting in low time synchronization accuracy. Summary of the Invention

[0004] The embodiments of the present application provide a time synchronization method and system to at least solve the problem of insufficient clock synchronization accuracy in related technologies.

[0005] In a first aspect, an embodiment of the present application provides a time synchronization method, which is applied to a time synchronization system. The system includes a frame-type device, wherein a mainboard and a slot board of the frame-type device are electrically connected, the mainboard includes a first phase-locked loop and a second phase-locked loop electrically connected to a first FPGA, the slot board includes a second FPGA, and a third phase-locked loop and a fourth phase-locked loop electrically connected to the second FPGA, the third phase-locked loop and the first phase-locked loop have the same clock source and are used to control the system clock, and the fourth phase-locked loop and the second phase-locked loop have the same clock source and are used to control the system time. The method includes:

[0006] Acquire, by the second FPGA, a message timestamp generated at the Ethernet physical layer interface, and determine, based on the timestamp, a deviation between the slot board and the peer device;

[0007] The second phase-locked loop and the fourth phase-locked loop are used to update the main board system time and the slot board system time according to the deviation.

[0008] In one embodiment, the deviation includes a frequency deviation and a time deviation, and the obtaining, by the second FPGA, a message timestamp generated on the Ethernet physical layer interface and determining the deviation between the slot board and the peer device based on the timestamp includes:

[0009] An Ethernet port that enables a target synchronization protocol, wherein the slot board periodically communicates with the peer device via the Ethernet physical layer interface;

[0010] Calculating, by the second FPGA, a difference in timestamps when two adjacent messages are received, where the difference represents a frequency deviation between the opposite device and the fourth phase-locked loop;

[0011] The time offset between the opposite device and the slot board is calculated based on the timestamp when the target message is sent, the timestamp when the target message is received, the timestamp when the reply message is sent, and the timestamp when the reply message is received.

[0012] In one embodiment, the time deviation includes a second deviation and a nanosecond deviation, the mainboard system time includes first nanosecond information, and the slot board system time includes second information and second nanosecond information, and updating the mainboard system time and the slot board system time according to the deviation using the second phase-locked loop and the fourth phase-locked loop includes:

[0013] Update the second information in the slot board system time according to the second deviation;

[0014] preliminarily updating the first nanosecond information according to the nanosecond deviation, generating a first clock according to the preliminarily updated first nanosecond information through the second phase-locked loop, and preliminarily updating the second nanosecond information based on the first clock and the fourth phase-locked loop;

[0015] The frequency of the second phase-locked loop is updated according to the frequency deviation, the first nanosecond information is updated again according to the frequency of the second phase-locked loop, a second clock is generated by the second phase-locked loop according to the first nanosecond information after being updated again, and the second nanosecond information is updated again based on the second clock and the fourth phase-locked loop.

[0016] In one embodiment, the first clock and the second clock include nanosecond transition points, and updating the second nanosecond information includes:

[0017] Using the first clock or the second clock as a reference source of the fourth phase-locked loop;

[0018] parsing the nanosecond transition point according to the first clock or the second clock by the second FPGA;

[0019] The second nanosecond information is updated according to the nanosecond jump point through the fourth phase-locked loop.

[0020] In one embodiment, after updating the second nanosecond information, the method further includes:

[0021] Calculating a frequency deviation between the updated opposite-end device and the fourth phase-locked loop;

[0022] In response to the frequency deviation not being within the preset threshold range, the main board system time and the slot board system time continue to be updated according to the nanosecond deviation until the frequency deviation is within the preset threshold range.

[0023] In a second aspect, an embodiment of the present application provides a frame-type device, the device being configured to implement the time synchronization method described in the first aspect, wherein a mainboard and a slot board of the frame-type device are electrically connected, the mainboard including a first FPGA, and a first phase-locked loop and a second phase-locked loop electrically connected to the first FPGA, the slot board including a second FPGA, and a third phase-locked loop and a fourth phase-locked loop electrically connected to the second FPGA;

[0024] The third phase-locked loop and the first phase-locked loop have the same clock source, and are used to control the system clock;

[0025] The fourth phase-locked loop and the second phase-locked loop have the same clock source and are used to control system time.

[0026] In a third aspect, an embodiment of the present application provides a time synchronization system, the system being used to cooperate with a peer device to implement the time synchronization method described in the first aspect, the system including a frame-type device, the mainboard and the slot board of the frame-type device being electrically connected, the mainboard including a first FPGA, and a first phase-locked loop and a second phase-locked loop electrically connected to the first FPGA, the slot board including a second FPGA, and a third phase-locked loop and a fourth phase-locked loop electrically connected to the second FPGA, the third phase-locked loop and the first phase-locked loop having the same clock source and being used to control the system clock, the fourth phase-locked loop and the second phase-locked loop having the same clock source and being used to control the system time; the system further comprising:

[0027] Calculation module: used to obtain the message timestamp generated on the Ethernet physical layer interface through the second FPGA, and determine the deviation between the slot board and the opposite end device according to the timestamp;

[0028] Synchronization module: used to update the main board system time and the slot board system time according to the deviation through the second phase-locked loop and the fourth phase-locked loop.

[0029] In one embodiment, the deviation includes a frequency deviation and a time deviation, and the calculation module includes:

[0030] Enabling unit: used to enable the Ethernet port of the target synchronization protocol, the slot board periodically communicates with the opposite device through the Ethernet physical layer interface;

[0031] A first calculation unit: configured to calculate, through the second FPGA, a difference in timestamps when two adjacent messages are received, where the difference represents a frequency deviation between the opposite device and the fourth phase-locked loop;

[0032] The second calculation unit is used to calculate the time deviation between the opposite device and the slot board based on the timestamp when the target message is sent, the timestamp when the target message is received, the timestamp when the reply message is sent, and the timestamp when the reply message is received.

[0033] In one embodiment, the time deviation includes a second deviation and a nanosecond deviation, the mainboard system time includes first nanosecond information, the slot board system time includes second information and second nanosecond information, and the synchronization module includes:

[0034] Second synchronization unit: used to update the second information in the slot board system time according to the second deviation;

[0035] a coarse synchronization unit configured to preliminarily update the first nanosecond information according to the nanosecond deviation, generate a first clock according to the preliminarily updated first nanosecond information through the second phase-locked loop, and preliminarily update the second nanosecond information based on the first clock and the fourth phase-locked loop;

[0036] A fine synchronization unit is used to update the frequency of the second phase-locked loop according to the frequency deviation, update the first nanosecond information again according to the frequency of the second phase-locked loop, generate a second clock according to the updated first nanosecond information through the second phase-locked loop, and update the second nanosecond information again based on the second clock and the fourth phase-locked loop.

[0037] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the time synchronization method as described in the first aspect above.

[0038] The embodiments of the present application provide a time synchronization method and system, which have at least the following technical effects.

[0039] The system clock domain in this application relies on the control of the first and third phase-locked loops from the same clock source, while the time clock domain relies on the control of the second and fourth phase-locked loops from the same clock source. This decouples the system clock and the time clock, avoiding oscillation interference caused by asynchronous clock interaction during time synchronization and improving time synchronization accuracy. Timestamps are generated on the Ethernet physical layer interface, and deviations are determined based on the timestamps. Time synchronization is then performed based on the deviations, reducing protocol stack delay jitter and the impact of message delay, which is beneficial for improving time synchronization accuracy.

[0040] The details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0042] Figure 1 This is a flowchart of a time synchronization method according to an embodiment of the present application;

[0043] Figure 2 is a flow chart showing a method for updating system time according to an exemplary embodiment;

[0044] Figure 3 is a schematic diagram showing a first clock according to an exemplary embodiment;

[0045] Figure 4 This is a schematic structural diagram of a frame-type device according to an embodiment of the present application;

[0046] Figure 5 This is a structural block diagram of a time synchronization system according to an embodiment of the present application. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solutions and advantages of this application more clearly understood, the present application is described and illustrated below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely used to explain this application and are not intended to limit this application. Based on the embodiments provided in this application, all other embodiments obtained by those of ordinary skill in the art without making any creative efforts are within the scope of protection of this application.

[0048] Obviously, the drawings described below are merely examples or embodiments of the present application. Those skilled in the art can, without inventive effort, apply the present application to other similar scenarios based on these drawings. Furthermore, it is also understood that, although the effort involved in such a development process may be complex and lengthy, for those skilled in the art related to the content disclosed in this application, changes in design, manufacturing, or production based on the technical content disclosed in this application are merely conventional technical means and should not be construed as an insufficiency of the content disclosed in this application.

[0049] References to "embodiments" in this application mean that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it refer to independent or alternative embodiments that are mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described in this application may be combined with other embodiments unless there is a conflict.

[0050] Unless otherwise defined, the technical or scientific terms used in this application should have the ordinary meaning understood by a person of ordinary skill in the technical field to which this application belongs. The words "one", "a", "the" and the like used in this application do not indicate a limit on quantity and may indicate the singular or plural. The terms "include", "comprise", "have" and any variations thereof used in this application are intended to cover non-exclusive inclusions; for example, a process, method, system, product or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units that are not listed, or may also include other steps or units that are inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like used in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The word "multiple" used in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, "A and / or B" can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects before and after are in an "or" relationship. The terms "first", "second", "third", etc. involved in this application are only used to distinguish similar objects and do not represent a specific order for the objects.

[0051] (1) When implementing time synchronization based on OTN networks, OTN mainly uses wavelength / sub-wavelength scheduling, and the transparent transmission of time synchronization signals may cause delay asymmetry (such as fiber path asymmetry and internal delay differences in equipment). OTN's mapping / demapping process (such as ODUflex) may introduce jitter and drift, affecting high-precision clock recovery. Early OTN equipment did not support 1588v2 enough and needed to rely on external synchronization sources or upgrade hardware. (2) When implementing time synchronization based on SPN, SPN carries services such as eMBB and uRLLC at the same time. Low-latency slices may be preempted by high-traffic services, affecting synchronization stability. Dynamic adjustment of network topology in 5G scenarios (such as FlexE link bundling) may cause changes in synchronization paths and introduce delay fluctuations. uRLLC requires sub-microsecond synchronization, and SPN must strictly guarantee the priority and timestamp accuracy of 1588v2 messages. (3) When implementing time synchronization based on PTN, PTN is based on IP / MPLS, and there are problems such as queue jitter and congestion packet loss, which affect the transmission of 1588v2 messages. It also needs to rely on SyncE to provide frequency synchronization, but phase / time synchronization still requires 1588v2, and the coordination complexity of the two is high. In addition, PTN is mostly used for mobile backhaul, and boundary clocks or transparent clocks need to be configured hop by hop, which makes deployment scale and management difficult. (4) When implementing time synchronization based on IPRAN, IPRAN is based on traditional IP routing, and dynamic changes in paths lead to asymmetric delays, making it difficult to meet microsecond-level synchronization requirements. Differences in the implementation of 1588v2 by equipment from different manufacturers (such as the timestamp insertion position) may lead to the accumulation of synchronization errors. In addition, IPRAN needs to upgrade hardware that supports 1588v2 and SyncE (such as high-precision PHY chips), and the cost of existing network transformation is high.

[0052] Based on the above situation, the embodiments of the present application provide a time synchronization method, device and system.

[0053] In a first aspect, an embodiment of the present application provides a time synchronization method, which is applied to a time synchronization system, a system frame device, a mainboard and a slot board of the frame device are electrically connected, the mainboard includes a first phase-locked loop and a second phase-locked loop electrically connected to the first FPGA, the slot board includes a first FPGA, and a third phase-locked loop and a fourth phase-locked loop electrically connected to the second FPGA, the third phase-locked loop and the first phase-locked loop are of the same origin and are used to control the system clock, the fourth phase-locked loop and the second phase-locked loop are of the same origin and are used to control the system time.

[0054] Optionally, the main board and the slot board are connected via a backplane bus. The main board includes a first FPGA and a second phase-locked loop of the first phase-locked loop electrically connected to the first FPGA. The first phase-locked loop uses the recovered clock or crystal oscillator of a certain port as a reference source, and the first phase-locked loop is used to control the main board system clock. The system time includes the main board system time and the slot board system time. The main board system time is stored inside the first FPGA of the main board. The main board system time is divided into second information and nanosecond information, both of which are controlled by software. The software modifies the current second information and nanosecond information in the main board through the read-write bus. The second phase-locked loop oscillates freely and is controlled by the SPI controller. The frequency deviation is controlled by software. The second phase-locked loop generates and provides a working clock for the second information and nanosecond information. The second phase-locked loop generates an encoding clock with nanosecond information and uses the encoding clock as the reference source for the fourth phase-locked loop.

[0055] The reference source for the third phase-locked loop (PLL) electrically connected to the second FPGA is the motherboard's system clock. The reference source for the fourth phase-locked loop is the encoded clock containing nanosecond information generated and transmitted by the second phase-locked loop. FPGA2 internally stores the current slot board system time, which is divided into seconds and nanoseconds. The seconds information is controlled by software, while the nanosecond information is controlled by the encoded clock containing nanosecond information generated and transmitted by the second phase-locked loop.

[0056] In this way, the system clock domain relies on the control of the first and third phase-locked loops of the same clock source, and the time clock domain relies on the control of the second and fourth phase-locked loops of the same clock source, thereby decoupling the system clock domain and the time clock domain. This makes it easier to synchronize time directly according to the system time without relying on the system clock, avoiding oscillation interference caused by asynchronous clock interaction during the time synchronization process.

[0057] Figure 1 This is a flow chart of a time synchronization method according to an embodiment of the present application. Figure 1 As shown, the method includes:

[0058] Step S101: obtaining a message timestamp generated at the Ethernet physical layer interface through the second FPGA, and determining the deviation between the slot board and the opposite end device according to the timestamp.

[0059] Optionally, FPGA2 transmits the system time information of the current slot board to the Ethernet physical layer interface, generating a send and receive timestamp at the message start point. Based on the message timestamps, the time offset and path delay between interacting devices, as well as the frequency offset between the fourth phase-locked loop (PLL) and the peer device, are determined. This approach accounts for both the system time offset between the current device and the peer device, as well as the frequency offset between the fourth PLL and the peer device, providing accurate offset data for subsequent time synchronization.

[0060] In one example, the deviation includes frequency deviation and time deviation, and step S101 includes:

[0061] Step S1011: Enable the Ethernet port of the target synchronization protocol, and the slot board periodically communicates with the opposite device through the Ethernet physical layer interface.

[0062] Optionally, target synchronization protocols include IEEE 802.1AS, NTP, and 1588v2. For example, if the current device supports 1588v2, the Ethernet port with 1588 enabled periodically sends fixed messages, such as sync and follow_up messages. Generating timestamps on the Ethernet physical layer interface reduces protocol stack delay jitter and improves time synchronization accuracy.

[0063] Step S1012: Calculate, by the second FPGA, the difference between the timestamps of two adjacent messages when they are received, where the difference represents the frequency deviation between the opposite device and the fourth phase-locked loop.

[0064] Optionally, the time difference between two adjacent messages in the receiving direction is calculated. This difference can reflect the frequency deviation between the current peer device clock and the fourth phase-locked loop (PLL). Each message has a fixed frequency. Taking the sync message as an example, the frequency is 1 / 16, or 16 packets per second, corresponding to a frequency of 0.0625s. Assuming the frequency deviation between the peer device clock and the fourth PLL is 0.0635s, this indicates that the frequency of the fourth PLL is greater than the clock frequency of the first peer device. Furthermore, multiple frequency deviations can be calculated, filtered, and averaged to ensure frequency deviation accuracy, thereby improving time synchronization precision.

[0065] Step S1013: Calculate the time offset between the opposite device and the slot board based on the timestamp when the target message is sent, the timestamp when the target message is received, the timestamp when the reply message is sent, and the timestamp when the reply message is received.

[0066] Optionally, when the network transmission path is symmetric, assuming that the timestamp when the target message is sent is t1, the timestamp when the target message is received is t2, the timestamp when the reply message is sent is t3, and the timestamp when the reply message is received is t4, the path delay Delay is expressed as:

[0067]

[0068] The time deviation Offest is expressed as:

[0069] Offser = (t2 - t1) - Delay.

[0070] In this way, the influence of network delay is eliminated and the time offset is obtained. When the upstream and downstream delays of the network are asymmetric, the Delay Asymmetry Correction field in the 1588v2 protocol is used to compensate for the asymmetry.

[0071] Step S102: updating the main board system time and the slot board system time according to the deviation through the second phase-locked loop and the fourth phase-locked loop.

[0072] Optionally, the mainboard system time is first updated based on the deviation, and then the slot board system time is updated based on the mainboard system time and the second and fourth phase-locked loops (PLLs) of the same source, to synchronize the time and frequency of the current device with the peer device. This allows the current device to synchronize with the peer device directly based on the deviation, without relying on the system clock, achieving the same effect as the peer device's clock.

[0073] In one example, the time deviation includes a second deviation and a nanosecond deviation, the mainboard system time includes first nanosecond information, and the slot board system time includes second information and second nanosecond information. Step S102 includes:

[0074] Step S1021: Update the second information in the slot board system time according to the second deviation.

[0075] Optionally, accurate second information is determined based on the second deviation, and the second information in the mainboard system time and the slot board system time is directly modified to accurate second information through software to achieve correction of the second information.

[0076] Step S1022 , preliminarily updating the first nanosecond information according to the nanosecond deviation, generating a first clock according to the preliminarily updated first nanosecond information through the second phase-locked loop, and preliminarily updating the second nanosecond information based on the first clock and the fourth phase-locked loop.

[0077] Optionally, accurate nanosecond information is determined based on the nanosecond deviation, and the first nanosecond information in the mainboard system time is directly modified to the accurate nanosecond information through software to achieve correction of the first nanosecond information. As an example, assuming a nanosecond deviation of 5000100, the accurate nanosecond information is the first nanosecond information + 1000ns*m, where m is determined based on the nanosecond deviation and is 5000 in this example. In this way, the nanosecond information of the mainboard system time is initially adjusted, and then a first clock containing the first nanosecond information is generated through the second phase-locked loop. The first clock is used as the reference source for the fourth phase-locked loop, and the second nanosecond information in the slot board system is updated based on the fourth phase-locked loop and the first clock.

[0078] Step S1023: update the frequency of the second phase-locked loop according to the frequency deviation, update the first nanosecond information again according to the frequency of the second phase-locked loop, generate a second clock according to the updated first nanosecond information through the second phase-locked loop, and update the second nanosecond information again based on the second clock and the fourth phase-locked loop.

[0079] Optionally, under the premise that the system time of the current device and the system time of the peer device are nearly synchronized, the frequency deviation of the fourth phase-locked loop is fine-tuned in real time to keep the frequency deviation within an error range, achieving an effect equivalent to the clock of the peer device, thereby achieving precise time synchronization. During adjustment, the frequency of the second phase-locked loop is modified through software, thereby speeding up or slowing down the first nanosecond information and correcting the first nanosecond information. The second phase-locked loop then generates a second clock containing the first nanosecond information, and the second clock is used as the reference source for the fourth phase-locked loop. The second nanosecond information in the slot board system is controlled based on the fourth phase-locked loop and the second clock. The error range can be set according to actual needs and should generally not be too large. As an example, the error range is set to [-10pps, 10pps].

[0080] This method divides the time synchronization process into second-by-second adjustment, nanosecond coarse adjustment, and nanosecond fine adjustment, allowing for hierarchical adjustment. This prevents excessive frequency adjustments, which can cause the phase-locked loop to lose lock or require extended relocking times, or affect clock stability due to excessive frequency adjustments, leading to rapid accumulation of phase errors. It also prevents excessive time synchronization adjustments, which can prevent accurate estimation of network latency and cause cumulative synchronization errors.

[0081] In one example, after updating the second nanosecond information, the method also includes: calculating the frequency deviation between the updated opposite device and the fourth phase-locked loop; in response to the frequency deviation not being within a preset threshold range, continuing to update the second nanosecond information according to the frequency deviation until the frequency deviation is within the preset threshold range.

[0082] The system determines the frequency deviation between the updated peer device and the fourth phase-locked loop (PLL). If the frequency deviation is outside the preset threshold, the system continues to update the frequency of the second phase-locked loop based on the frequency deviation, speeding up or slowing down the first nanosecond information, thereby correcting the first nanosecond information. The second phase-locked loop then generates a second clock containing the first nanosecond information. This second clock serves as the reference source for the fourth phase-locked loop (PLL). The fourth phase-locked loop and the second clock control the second nanosecond information in the slot board system. In this way, the frequency deviation is stabilized within the preset error range, ensuring that the clocks of the current device and the peer device are as consistent as possible, achieving high-precision time synchronization.

[0083] Figure 2 FIG. 1 is a flow chart showing a method for updating system time according to an exemplary embodiment. Figure 2As shown, the system time is updated through software control. The idle state S1 represents the initial state, in which the current device does not have the 1588v2 protocol time synchronization function enabled. The 1588v2 negotiation state S2 indicates that the 1588v2 protocol has started negotiation. When the negotiation is normal, it enters the interaction state. If the negotiation times out or an exception occurs, it returns to the idle state. The interaction state S3 indicates that the 1588v2 protocol is interacting normally, sending periodic messages, and then entering the deviation calculation state. The deviation calculation state S4 calculates the frequency deviation and time deviation between the current device and the peer device based on the periodic messages of the 1588v2 protocol. After the calculation is complete, it enters the coarse adjustment state S5. The coarse adjustment state S5 performs accurate adjustment of the second information and coarse adjustment of the nanosecond information. After the adjustment is complete, it enters the fine adjustment state S6. If the 1588v2 protocol is abnormal at this time, it returns to the 1588v2 negotiation state S2. Fine adjustment state S6 performs fine adjustment of nanosecond information. This involves modifying the frequency offset of the motherboard's second phase-locked loop (PLL) to speed up or slow down the nanosecond information. Normally, the system remains stable in this state after adjustment. If the system time fluctuates significantly during this period, the system returns to the coarse adjustment state S5. If a 1588v2 protocol anomaly occurs, the system returns to the negotiation state S2.

[0084] In this way, during time synchronization, the frequency offset and time offset are calculated. Initial adjustments to the nanosecond information are made based on the second offset in the frequency offset, and fine-tuned using the frequency offset to adjust the nanosecond information. This prevents problems such as excessive frequency adjustments that can lead to error accumulation, ensuring time and frequency alignment between the current device and the peer device, thus achieving high-precision time synchronization that meets the 1588 Class C standard.

[0085] In one example, the first clock and the second clock include nanosecond transition points, and updating the second nanosecond information in steps S1022 and S1023 includes:

[0086] Step S201: Use the first clock or the second clock as a reference source of the fourth phase-locked loop.

[0087] Step S202: parsing the nanosecond transition point according to the first clock or the second clock by the second FPGA.

[0088] Step S203: updating the second nanosecond information according to the nanosecond jump point through the third phase-locked loop.

[0089] Optionally, in the first FPGA, a second phase-locked loop (PLL) on the motherboard generates and provides a working clock for the second and nanosecond information of the motherboard system time. The second PLL further generates a first clock and encodes a one-second reset signal into the first clock. As an example, the working clock can be a 500M clock, and the first clock can be a 25M clock. Figure 3is a schematic diagram showing a first clock according to an exemplary embodiment, such as Figure 3 As shown. The first clock's high-level duty cycle is adjusted to 75% in the first clock cycle where the nanosecond is zero, and to 50% in the remaining cycles, thereby encoding the nanosecond timing information. After receiving the 25M clock, the slot board decodes the nanosecond transition point and sends this clock as a reference source to the slot board's fourth phase-locked loop. Once the fourth phase-locked loop is locked, the main board's second phase-locked loop and the slot board's fourth phase-locked loop have the same clock source. Finally, the slot board clears the nanosecond information to 0 based on the nanosecond transition point and continues to accumulate it, thus updating and controlling the nanosecond information. The second clock is generated and transmitted in the same manner as the first clock.

[0090] In one example, the number of slot boards is greater than or equal to two. In this case, two phase-locked loops are configured on each slot board. For example, if the number of slot boards is equal to two, the first slot board includes the fifth and sixth phase-locked loops, and the second slot board includes the seventh and eighth phase-locked loops. The fifth and seventh phase-locked loops use the first phase-locked loop as their reference source, respectively, while the sixth and eighth phase-locked loops use the second phase-locked loop as their reference source. During time synchronization, the mainboard can simultaneously send a clock containing nanosecond information to multiple slot boards. For example, the mainboard sends a clock containing nanosecond information generated by the second phase-locked loop to the first and second slot boards, respectively. The first and second slot boards then analyze the nanosecond transition points in the clock for nanosecond control. The sixth and eighth phase-locked loops use the clock containing nanosecond information sent by the mainboard as their reference source.

[0091] In summary, the system clock domain in the present application relies on the control of the first phase-locked loop and the third phase-locked loop of the same clock source, and the time clock domain relies on the control of the second phase-locked loop and the fourth phase-locked loop of the same clock source, thereby decoupling the system clock domain and the time clock domain, avoiding oscillation interference caused by asynchronous clock interaction during the time synchronization process. Generating a timestamp at the Ethernet physical layer interface reduces protocol stack delay jitter, which is beneficial to improving the accuracy of time synchronization. When performing time synchronization, the frequency deviation and time deviation are calculated, and the nanosecond information is preliminarily adjusted according to the second deviation in the frequency deviation, and the nanosecond information is fine-tuned by the frequency deviation. Avoid problems such as excessive frequency adjustment amplitude leading to error accumulation, achieve time and frequency alignment between the current device and the opposite device, and thus achieve high-precision time synchronization. In addition, the frequency deviation is stabilized within a preset error range so that the clock effects of the current device and the opposite device are as consistent as possible, achieving high-precision time synchronization.

[0092] In a second aspect, an embodiment of the present application provides a frame-type device, which is used to implement the time synchronization method of the first aspect. Figure 4 is a structural diagram of a frame-type device according to an embodiment of the present application. Figure 4As shown, a mainboard 10 and a slot board 20 of a chassis-type device are electrically connected. The mainboard 10 includes a first FPGA 101, and a first phase-locked loop 102 and a second phase-locked loop 103 electrically connected to the first FPGA 101. The slot board includes a second FPGA 201, and a third phase-locked loop 202 and a fourth phase-locked loop 203 electrically connected to the second FPGA 201. The third phase-locked loop 202 and the first phase-locked loop 102 share the same clock source and are used to control the system clock. The fourth phase-locked loop 203 and the second phase-locked loop 103 share the same clock source and are used to control the system time.

[0093] Optionally, the mainboard 10 and the slot board 20 are connected via a backplane bus. The first phase-locked loop 102 uses the recovered clock or crystal oscillator of a certain port as a reference source and is used to control the mainboard system clock. The system time includes the mainboard system time and the slot board system time. The mainboard's first FPGA 101 contains the mainboard system time. The mainboard system time is divided into seconds and nanoseconds, both of which are controlled by software. The software modifies the current seconds and nanoseconds in the mainboard via the read-write bus. The second phase-locked loop 103 oscillates freely and is controlled by the SPI controller. The frequency deviation is controlled by software. The second phase-locked loop generates and provides a working clock for the seconds and nanoseconds. The second phase-locked loop 103 generates an encoding clock with nanosecond information and uses this encoding clock as the reference source for the fourth phase-locked loop 203.

[0094] The reference source for the third phase-locked loop (PLL) 202, electrically connected to the second FPGA 201, is the mainboard's system clock. The reference source for the fourth phase-locked loop (PLL) 203 is the encoded clock containing nanosecond information generated and transmitted by the second phase-locked loop 103. FPGA 2201 internally stores the current slot board system time, which is divided into seconds and nanoseconds. The seconds information is controlled by software, while the nanosecond information is controlled by the encoded clock containing nanosecond information generated and transmitted by the second phase-locked loop 103.

[0095] In this way, the system clock domain relies on the control of the first and third phase-locked loops of the same clock source, and the time clock domain relies on the control of the second and fourth phase-locked loops of the same clock source. The system clock domain and the time clock domain are decoupled through the phase-locked loops, making it easier to synchronize time directly according to the system time without relying on the system clock, avoiding oscillation interference caused by asynchronous clock interaction during the time synchronization process.

[0096] To sum up, in this application, a dual phase-locked loop is set up so that the system clock domain depends on the control of the first phase-locked loop and the third phase-locked loop of the same clock source, and the time clock domain depends on the control of the second phase-locked loop and the fourth phase-locked loop of the same clock source, thereby decoupling the system clock domain and the time clock domain, avoiding oscillation interference caused by asynchronous clock interaction during the time synchronization process, and is conducive to improving the accuracy of time synchronization.

[0097] In a third aspect, an embodiment of the present application provides a time synchronization system, which is used to cooperate with a peer device to implement the time synchronization method of the first aspect. Figure 5 is a structural block diagram of a time synchronization system according to an embodiment of the present application. Figure 5 As shown, the system includes a frame-type device, wherein the mainboard and slot board of the frame-type device are electrically connected. The mainboard includes a first FPGA, and a first phase-locked loop and a second phase-locked loop electrically connected to the first FPGA. The slot board includes a second FPGA, and a third phase-locked loop and a fourth phase-locked loop electrically connected to the second FPGA. The third phase-locked loop and the first phase-locked loop have the same clock source and are used to control the system clock. The fourth phase-locked loop and the second phase-locked loop have the same clock source and are used to control the system time. The system includes:

[0098] Calculation module 100: used to obtain the message timestamp generated at the Ethernet physical layer interface through the second FPGA, and determine the deviation between the slot board and the opposite end device according to the timestamp.

[0099] Synchronization module 200: used to update the main board system time and the slot board system time according to the deviation through the second phase-locked loop and the fourth phase-locked loop.

[0100] In one example, the deviation includes frequency deviation and time deviation, and the calculation module 100 includes:

[0101] Enabling unit: used to enable the Ethernet port of the target synchronization protocol. The slot board periodically communicates with the peer device through the Ethernet physical layer interface.

[0102] The first calculation unit is configured to calculate, through the second FPGA, a difference between time stamps when two adjacent messages are received, where the difference represents a frequency deviation between the opposite device and the fourth phase-locked loop.

[0103] The second calculation unit is used to calculate the time deviation between the opposite device and the slot board based on the timestamp when the target message is sent, the timestamp when the target message is received, the timestamp when the reply message is sent, and the timestamp when the reply message is received.

[0104] In one example, the time deviation includes a second deviation and a nanosecond deviation, the mainboard system time includes first nanosecond information, the slot board system time includes second information and second nanosecond information, and the synchronization module 200 includes:

[0105] Second synchronization unit: used to update the second information in the slot board system time according to the second deviation.

[0106] Coarse synchronization unit: used to preliminarily update the first nanosecond information according to the nanosecond deviation, generate the first clock according to the preliminarily updated first nanosecond information through the second phase-locked loop, and preliminarily update the second nanosecond information based on the first clock and the fourth phase-locked loop.

[0107] Fine synchronization unit: used to update the frequency of the second phase-locked loop according to the frequency deviation, update the first nanosecond information again according to the frequency of the second phase-locked loop, generate a second clock according to the updated first nanosecond information through the second phase-locked loop, and update the second nanosecond information again based on the second clock and the fourth phase-locked loop.

[0108] In one example, the first clock and the second clock in the coarse synchronization unit and the fine synchronization unit include nanosecond transition points, and the coarse synchronization unit and the fine synchronization unit update second nanosecond information. The system includes:

[0109] Used to use the first clock or the second clock as a reference source of the fourth phase-locked loop.

[0110] The nanosecond transition point is parsed by the second FPGA according to the first clock or the second clock.

[0111] The second nanosecond information is updated according to the nanosecond jump point through the fourth phase-locked loop.

[0112] In one example, after the second nanosecond information is updated by the coarse synchronization unit and the fine synchronization unit, the system further includes:

[0113] Calculate the updated frequency deviation between the opposite device and the fourth phase-locked loop.

[0114] In response to the frequency deviation not being within the preset threshold range, the main board system time and the slot board system time continue to be updated according to the nanosecond deviation until the frequency deviation is within the preset threshold range.

[0115] In summary, the system clock domain in the present application relies on the control of the first phase-locked loop and the third phase-locked loop of the same clock source, and the time clock domain relies on the control of the second phase-locked loop and the fourth phase-locked loop of the same clock source, thereby decoupling the system clock domain and the time clock domain, avoiding oscillation interference caused by asynchronous clock interaction during the time synchronization process. Generating a timestamp at the Ethernet physical layer interface reduces protocol stack delay jitter, which is beneficial to improving the accuracy of time synchronization. When performing time synchronization, the frequency deviation and time deviation are calculated, and the nanosecond information is preliminarily adjusted according to the second deviation in the frequency deviation, and the nanosecond information is fine-tuned by the frequency deviation. Avoid problems such as excessive frequency adjustment amplitude leading to error accumulation, achieve time and frequency alignment between the current device and the opposite device, and thus achieve high-precision time synchronization. In addition, the frequency deviation is stabilized within a preset error range so that the clock effects of the current device and the opposite device are as consistent as possible, achieving high-precision time synchronization.

[0116] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium having a program stored thereon, which, when executed by a processor, implements the time synchronization method provided in the first aspect.

[0117] The readable storage medium may include, but is not limited to, a portable disk, a hard disk, a random access memory, a read-only memory, an erasable programmable read-only memory, an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0118] In a possible implementation, the present invention may also be implemented in the form of a program product, which includes program code. When the program product is run on a terminal device, the program code is used to enable the terminal device to execute the steps of the time synchronization method provided in the first aspect.

[0119] The program code for executing the present invention may be written in any combination of one or more programming languages, and may be executed entirely on the user device, partially on the user device, as an independent software package, partially on the user device and partially on a remote device, or entirely on the remote device.

[0120] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0121] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A time synchronization method, characterized in that: The method is applied to a time synchronization system, the system including a frame-type device, a mainboard and a slot board of the frame-type device being electrically connected, the mainboard including a first phase-locked loop and a second phase-locked loop electrically connected to a first FPGA, the slot board including a second FPGA, and a third phase-locked loop and a fourth phase-locked loop electrically connected to the second FPGA, the third phase-locked loop and the first phase-locked loop having the same clock source and being used to control the system clock, the fourth phase-locked loop and the second phase-locked loop having the same clock source and being used to control the system time, the method comprising: Acquire, by the second FPGA, a message timestamp generated at the Ethernet physical layer interface, and determine, based on the timestamp, a deviation between the slot board and the peer device; The second phase-locked loop and the fourth phase-locked loop are used to update the main board system time and the slot board system time according to the deviation.

2. A time synchronization method according to claim 1, characterized in that: The deviation includes a frequency deviation and a time deviation. The obtaining, by the second FPGA, a message timestamp generated at the Ethernet physical layer interface and determining the deviation between the slot board and the opposite device according to the timestamp include: An Ethernet port that enables a target synchronization protocol, wherein the slot board periodically communicates with the peer device via the Ethernet physical layer interface; Calculating, by the second FPGA, a difference in timestamps when two adjacent messages are received, where the difference represents a frequency deviation between the opposite device and the fourth phase-locked loop; The time offset between the opposite device and the slot board is calculated based on the timestamp when the target message is sent, the timestamp when the target message is received, the timestamp when the reply message is sent, and the timestamp when the reply message is received.

3. A time synchronization method according to claim 2, characterized in that: The time deviation includes a second deviation and a nanosecond deviation, the mainboard system time includes first nanosecond information, and the slot board system time includes second information and second nanosecond information, and updating the mainboard system time and the slot board system time according to the deviation by using the second phase-locked loop and the fourth phase-locked loop includes: Update the second information in the slot board system time according to the second deviation; preliminarily updating the first nanosecond information according to the nanosecond deviation, generating a first clock according to the preliminarily updated first nanosecond information through the second phase-locked loop, and preliminarily updating the second nanosecond information based on the first clock and the fourth phase-locked loop; The frequency of the second phase-locked loop is updated according to the frequency deviation, the first nanosecond information is updated again according to the frequency of the second phase-locked loop, a second clock is generated by the second phase-locked loop according to the first nanosecond information after being updated again, and the second nanosecond information is updated again based on the second clock and the fourth phase-locked loop.

4. A time synchronization method according to claim 3, characterized in that: The first clock and the second clock include nanosecond transition points, and updating the second nanosecond information includes: Using the first clock or the second clock as a reference source of the fourth phase-locked loop; parsing the nanosecond transition point according to the first clock or the second clock by the second FPGA; The second nanosecond information is updated according to the nanosecond jump point through the fourth phase-locked loop.

5. A time synchronization method according to claim 3, characterized in that: After updating the second nanosecond information, the method further includes: Calculating a frequency deviation between the updated opposite-end device and the fourth phase-locked loop; In response to the frequency deviation not being within the preset threshold range, the main board system time and the slot board system time continue to be updated according to the nanosecond deviation until the frequency deviation is within the preset threshold range.

6. A frame-type device, characterized in that: The device is used to implement the time synchronization method according to any one of claims 1 to 5, wherein a mainboard and a slot board of the frame-type device are electrically connected, the mainboard includes a first FPGA, and a first phase-locked loop and a second phase-locked loop electrically connected to the first FPGA, and the slot board includes a second FPGA, and a third phase-locked loop and a fourth phase-locked loop electrically connected to the second FPGA; The third phase-locked loop and the first phase-locked loop have the same clock source, and are used to control the system clock; The fourth phase-locked loop and the second phase-locked loop have the same clock source and are used to control system time.

7. A time synchronization system, characterized in that: The system is used to cooperate with a peer device to implement the time synchronization method according to any one of claims 1 to 5. The system includes a frame-type device, a mainboard and a slot board of the frame-type device are electrically connected, the mainboard includes a first FPGA, and a first phase-locked loop and a second phase-locked loop electrically connected to the first FPGA, the slot board includes a second FPGA, and a third phase-locked loop and a fourth phase-locked loop electrically connected to the second FPGA, the third phase-locked loop and the first phase-locked loop have the same clock source and are used to control the system clock, and the fourth phase-locked loop and the second phase-locked loop have the same clock source and are used to control the system time; The system further comprises: Calculation module: used to obtain the message timestamp generated on the Ethernet physical layer interface through the second FPGA, and determine the deviation between the slot board and the opposite end device according to the timestamp; Synchronization module: used to update the main board system time and the slot board system time according to the deviation through the second phase-locked loop and the fourth phase-locked loop.

8. A time synchronization system according to claim 7, characterized in that: The deviation includes frequency deviation and time deviation, and the calculation module includes: Enabling unit: used to enable the Ethernet port of the target synchronization protocol, the slot board periodically communicates with the opposite device through the Ethernet physical layer interface; A first calculation unit: configured to calculate, through the second FPGA, a difference in timestamps when two adjacent messages are received, where the difference represents a frequency deviation between the opposite device and the fourth phase-locked loop; The second calculation unit is used to calculate the time deviation between the opposite device and the slot board based on the timestamp when the target message is sent, the timestamp when the target message is received, the timestamp when the reply message is sent, and the timestamp when the reply message is received.

9. A time synchronization system according to claim 7, characterized in that: The time deviation includes a second deviation and a nanosecond deviation, the mainboard system time includes first nanosecond information, the slot board system time includes second information and second nanosecond information, and the synchronization module includes: Second synchronization unit: used to update the second information in the slot board system time according to the second deviation; a coarse synchronization unit configured to preliminarily update the first nanosecond information according to the nanosecond deviation, generate a first clock according to the preliminarily updated first nanosecond information through the second phase-locked loop, and preliminarily update the second nanosecond information based on the first clock and the fourth phase-locked loop; A fine synchronization unit is used to update the frequency of the second phase-locked loop according to the frequency deviation, update the first nanosecond information again according to the frequency of the second phase-locked loop, generate a second clock according to the updated first nanosecond information through the second phase-locked loop, and update the second nanosecond information again based on the second clock and the fourth phase-locked loop.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the time synchronization method according to any one of claims 1 to 5 is implemented.

Images