High-speed serial signal test method, system and semiconductor test equipment

Abstract

The application is suitable for the technical field of signal testing, and provides a high-speed serial signal testing method, system and semiconductor testing equipment. The high-speed serial signal testing method adjusts the timing of a testing signal through a clock reference with adjustable phase, actively introduces controllable jitter, and is used for jitter margin testing. A target testing signal is sent to a receiving end through transmission driving, after a receiving signal is obtained, a target sampling timing is extracted based on clock recovery, a programmable receiving delay chain is controlled to perform time scanning, and receiving data at multiple sampling time points is obtained. By comparing each sampling data with the testing signal, the bit error rate under each delay setting is counted, and signal quality evaluation is completed. The above scheme has the advantages of modularity, high precision, low cost and the like, and improves the comprehensive testing efficiency and reliability of the semiconductor testing equipment on the high-speed serial signal.

Description

Technical Field

[0001] This application belongs to the field of semiconductor testing technology, and in particular relates to a high-speed serial signal testing method, system and semiconductor testing equipment. Background Technology

[0002] As integrated circuits and electronic systems evolve towards higher speeds, lower power consumption, and miniaturization, high-speed serial interfaces are increasingly widely used in chip interconnects and system communication. These interfaces employ high-speed serial transmission, utilizing differential signals and embedded clocks to achieve higher data transmission rates with a limited number of channels, significantly improving signal channel utilization. However, high-speed serial signals are highly susceptible to noise, jitter, crosstalk, and distortion during transmission, leading to decreased signal integrity and consequently affecting system stability and protocol compatibility. Therefore, testing high-speed serial signals has become a critical task in chip design verification, system debugging, and mass production testing.

[0003] Currently, mass production testing of high-speed serial signals mainly relies on ATE (Automatic Test Equipment). However, existing ATE equipment has significant shortcomings in meeting the testing requirements of high-speed serial signals. On the one hand, the testing resources of the ATE itself are limited, making it difficult to support key functions required by high-speed serial interfaces, such as high-speed data driving, clock recovery, and bit error rate statistics. On the other hand, its closed structure and outdated updates make it difficult to adapt to the constantly evolving high-speed protocol standards and complex debugging mechanisms. Especially in mass production environments, the requirements for test stability, consistency, and throughput efficiency are extremely high, while traditional ATE lacks effective test paths and strategies for high-speed serial signal links. Summary of the Invention

[0004] In view of this, embodiments of this application provide a high-speed serial signal testing method, system, and semiconductor testing equipment. Through modularization, high precision, and low cost, it achieves comprehensive testing of the electrical characteristics, protocol behavior, and jitter tolerance of high-speed serial signals, and is applied in semiconductor testing equipment, thereby improving the testing efficiency of semiconductor testing equipment for high-speed serial signals.

[0005] A first aspect of this application provides a high-speed serial signal testing method, applied to a high-speed serial signal testing system, the high-speed serial signal testing method comprising:

[0006] The timing of the test signal is adjusted using an adjustable phase clock reference to obtain the target test signal;

[0007] The target test signal is transmitted to the receiving end via a transmission driver, and the received signal is obtained.

[0008] Based on clock recovery, the target sampling timing is extracted from the received signal, and the programmable receiving delay chain is controlled to adjust the delay of the received signal. Time scanning is performed within one signal period to obtain the sampling data of the received signal at multiple sampling times.

[0009] The sampled data at the multiple sampling times are compared with the target test signal, and the bit error rate under each delay setting is calculated to complete the signal quality assessment.

[0010] This application embodiment uses an adjustable-phase clock reference to adjust the timing of the test signal, actively introducing controllable jitter for jitter tolerance testing. The target test signal is sent to the receiver via a transmit driver. After acquiring the received signal, the target sampling timing is extracted based on clock recovery, and a programmable receive delay chain is controlled to perform time scanning to acquire received data at multiple sampling moments. By comparing each sampled data with the test signal, the bit error rate under each delay setting is calculated to complete the signal quality assessment. This scheme has advantages such as modularity, high precision, and low cost, and can improve the overall testing efficiency and reliability of semiconductor testing equipment for high-speed serial signals.

[0011] In one possible implementation, before timing the test signal using an adjustable-phase clock reference to obtain the target test signal, the method further includes:

[0012] Based on preset test configuration parameters, a test signal conforming to the target protocol format is generated. The test configuration parameters include at least the protocol type, transmission rate, and voltage swing parameter. The valid data field of the test signal is generated based on a pseudo-random number generator to simulate actual business data.

[0013] In one possible implementation, the step of timing-adjusting the test signal using an adjustable-phase clock reference to obtain the target test signal includes:

[0014] Based on preset phase transition control commands, the reference clock is phase-switched to obtain multiple phase-switched clocks;

[0015] Based on the timing of the test signal transmission driven by the multiple phase switching clocks and the reference clock, a jitter-controlled target test signal is generated.

[0016] In one possible implementation, the step of extracting the target sampling timing from the received signal based on clock recovery includes:

[0017] Based on the high and low level switching information in the received signal, clock recovery is performed to obtain the embedded recovered clock of the received signal;

[0018] The target sampling timing is determined based on the embedded recovery clock of the received signal.

[0019] In one possible implementation, with the target sampling timing as the sampling reference, the controllable programmable receive delay chain adjusts the delay of the received signal, performs time scanning within one signal period, and acquires sampling data of the received signal at multiple sampling times, including:

[0020] According to a preset fixed delay step, multiple different delay configuration values ​​are set for the programmable receiving delay chain to evenly distribute multiple sampling moments within a receiving signal period;

[0021] At each sampling time, the received signal is sampled to obtain the sampled data of the received signal at the multiple sampling times.

[0022] In one possible implementation, the step of comparing the sampled data at the plurality of sampling times with the test signal, calculating the bit error rate under each delay setting, and determining the target sampling time based on the bit error rate to complete the signal quality assessment includes:

[0023] The sampled data at each sampling time point are compared with the test signal one by one, and the bit error rate corresponding to each delay setting is calculated.

[0024] An eye diagram of the received signal is constructed based on the bit error rate distribution;

[0025] Based on the eye diagram of the received signal, a signal quality assessment is performed.

[0026] In one possible implementation, the step of comparing the received data at each sampling time with the test signal one by one and calculating the bit error rate corresponding to each delay setting includes:

[0027] The sampled data at each sampling time is parsed according to the protocol, the preamble field and the synchronization sequence field are identified, and the effective data start position of each sampled data is determined.

[0028] Based on the effective data start position of each sampled data, extract the effective data fields from the sampled data at each sampling time;

[0029] The valid data field is compared with the valid data field of the test signal, and the bit error rate corresponding to each delay setting is calculated.

[0030] In one possible implementation, the method further includes:

[0031] Parallel testing was performed on multiple high-speed serial channels, and the sampling timing and receiving delay configuration values ​​for each channel were set respectively.

[0032] A second aspect of this application provides a high-speed serial signal testing system, the system being built on an FPGA, the system comprising:

[0033] The transmit jitter module is used to adjust the timing of the test signal using an adjustable phase clock reference to obtain the target test signal;

[0034] The transmission driver module is used to send the target test signal to the receiving end via the transmission driver and to obtain the received signal;

[0035] The receiving scanning module is used to extract the target sampling timing of the received signal based on clock recovery, and control the programmable receiving delay chain to adjust the delay of the received signal, perform time scanning within one signal period, and obtain the sampling data of the received signal at multiple sampling times;

[0036] The signal testing module is used to compare the sampled data at the multiple sampling times with the target test signal, calculate the bit error rate under each delay setting, and complete the signal quality assessment.

[0037] A third aspect of this application provides a semiconductor testing device, which includes at least a control device and a high-speed serial signal testing system as described in the second aspect above; the control device is used to control the activation of the testing function of the high-speed serial signal testing system.

[0038] A fourth aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the high-speed serial signal testing method described in the first aspect.

[0039] A fifth aspect of this application provides a computer program product that, when run on a semiconductor testing device, causes the semiconductor testing device to execute the high-speed serial signal testing method described in the first aspect.

[0040] The beneficial effects of the second to fifth aspects mentioned above can all be referred to the beneficial effects described in the first aspect above, and will not be repeated here. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1This is a schematic diagram of the structure of a high-speed serial signal testing system provided in an embodiment of this application;

[0043] Figure 2 This is a schematic diagram of another high-speed serial signal testing system provided in an embodiment of this application;

[0044] Figure 3 This refers to the specific implementation process of CDR;

[0045] Figure 4 This is a flowchart illustrating a high-speed serial signal testing method provided in an embodiment of this application;

[0046] Figure 5 This is a schematic diagram of the serial-to-parallel conversion module and the low-speed jitter clock generation module based on DDS;

[0047] Figure 6 This is a diagram illustrating the jitter of a low-speed clock;

[0048] Figure 7 This is a schematic diagram of the output driver;

[0049] Figure 8 This is a schematic diagram of clock recovery for different channels;

[0050] Figure 9 This is a flowchart illustrating another high-speed serial signal testing method provided in an embodiment of this application;

[0051] Figure 10 This is a schematic diagram of the structure of a semiconductor testing device provided in an embodiment of this application;

[0052] Figure 11 This is a schematic diagram of another semiconductor testing device provided in an embodiment of this application. Detailed Implementation

[0053] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0054] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0055] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0056] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0057] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0058] It should be understood that the sequence number of each step in this embodiment does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of this application embodiment.

[0059] As integrated circuits and electronic systems evolve towards higher speeds, lower power consumption, and miniaturization, high-speed serial interfaces are increasingly widely used in chip interconnects and system communication. These interfaces employ high-speed serial transmission, utilizing differential signals and embedded clocks to achieve higher data transmission rates with a limited number of channels, significantly improving signal channel utilization. However, high-speed serial signals are highly susceptible to noise, jitter, crosstalk, and distortion during transmission, leading to a decline in signal integrity and timing characteristics, which in turn affects system stability and protocol compatibility. Therefore, testing high-speed serial signals has become a critical task in chip design verification, system debugging, and mass production testing.

[0060] Currently, mass production testing of high-speed serial signals mainly relies on ATE (Automatic Test Equipment). However, existing ATE equipment has significant shortcomings in meeting the testing requirements of high-speed serial signals. On the one hand, the testing resources of the ATE itself are limited, making it difficult to support key functions required by high-speed serial interfaces, such as high-speed data driving, clock recovery, and bit error rate statistics. On the other hand, its closed structure and outdated updates make it difficult to adapt to the constantly evolving high-speed protocol standards and complex debugging mechanisms. Especially in mass production environments, the requirements for test stability, consistency, and throughput efficiency are extremely high, while traditional ATE lacks effective test paths and strategies for high-speed serial signal links.

[0061] To address the aforementioned issues, this application proposes a high-speed serial signal testing method, system, semiconductor testing equipment, and storage medium. The method involves timing the test signal using a programmable transmit delay chain, actively introducing controllable jitter for jitter tolerance testing. The target test signal is transmitted to the receiver via a transmit driver. After acquiring the received signal, the sampling timing is extracted based on clock recovery, and the programmable receive delay chain is controlled to perform time scanning, acquiring received data at multiple sampling moments. By comparing each sampled data point with the test signal, the bit error rate under each delay setting is calculated, completing the signal quality assessment. This solution offers advantages such as modularity, high precision, and low cost, improving the overall testing efficiency and reliability of semiconductor testing equipment for high-speed serial signals.

[0062] The high-speed serial signal testing method, system, semiconductor testing equipment, storage medium, and computer program provided in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0063] Figure 1 A schematic diagram of a high-speed serial signal testing system provided in an embodiment of this application is shown. This high-speed serial signal testing system is built on an FPGA, and its overall structure may include a transmit jitter module, a transmit drive module, a receive scan module, and a signal testing module.

[0064] The transmit jitter module is used to adjust the timing of the test signal using an adjustable phase clock reference to obtain the target test signal;

[0065] The transmit driver module is used to send the target test signal to the receiver via the transmit driver and to acquire the received signal;

[0066] The receiving scanning module is used to extract the target sampling timing of the received signal based on clock recovery, and control the programmable receiving delay chain to adjust the delay of the received signal. It performs time scanning within one signal period to obtain the sampling data of the received signal at multiple sampling times.

[0067] The signal testing module is used to compare the sampled data at multiple sampling times with the test signal, calculate the bit error rate under each delay setting, and complete the signal quality assessment.

[0068] The transmit jitter module can adjust the timing of the test signal using an internally adjustable phase clock reference. Specifically, by changing the phase shift of the test signal, the output edge of the test signal is controllably offset, thereby generating a target test signal with controllable jitter characteristics. This signal contains a deliberately designed phase drift, which is beneficial for subsequent jitter tolerance testing and eye diagram evaluation.

[0069] It should be noted that the high-speed serial signal test system in this application is applied to existing semiconductor test equipment to improve the comprehensive testing capabilities of semiconductor test equipment for the electrical characteristics, protocol behavior, and jitter tolerance of high-speed serial signals, and to improve the testing efficiency of high-speed serial signals.

[0070] It should also be noted that the timing adjustment of the test signal by the adjustable phase clock reference in this application can be achieved by a programmable phase-agile clock reference. Specifically, it can be achieved by a combination of phase-locked loop and delay phase-locked loop, or by using the MMCM (mixed-mode clock manager) inside the FPGA. This application does not limit the specific implementation of this method.

[0071] like Figure 1 As shown, the target test signal, after being output by the transmit jitter module, is sent to the receiver by the transmit drive module to acquire the received signal, which is then sent to the receive scan module. Upon receiving the signal, the receive scan module first extracts the embedded clock information through a clock recovery (CDR) mechanism to obtain the target sampling timing. Then, it controls the programmable receive delay chain to perform a time scan operation within one signal period at preset steps, acquiring sampling data at multiple sampling moments to construct the bit error rate distribution and eye diagram image. Next, the sampling data acquired at multiple sampling moments is compared bit-by-bit with the effective data field of the test signal, and the bit error rate under each delay setting is calculated to form an eye diagram for signal quality assessment, including eye diagram opening analysis and jitter tolerance analysis.

[0072] As one possible implementation, see Figure 2 The diagram shows a structural schematic of another high-speed serial signal testing system provided in an embodiment of this application. (See attached diagram.) Figure 2 As shown, the system includes multiple modules integrated inside the FPGA, as well as a transmit driver module and a receive comparison module connected to the outside of the FPGA.

[0073] Protocol processing module: This module generates test data based on user-defined test configuration parameters and packages the test data into data frames conforming to the target high-speed serial communication protocol format, supporting MIPI, PCIe, USB, SATA, and other protocol formats. This module is also used for frame header addition, synchronization sequence embedding, and pseudo-random code generation for use by the signal transmission module. Simultaneously, it identifies the received signal, pinpointing valid data fields and comparing them one-to-one with the valid data fields in the test signal to determine the bit error rate and output the final signal quality index.

[0074] Signal transmission module: Receives test data frames output by the protocol processing module, controls the data rhythm and logic level conversion, and transmits them to the transmission jitter module.

[0075] Transmit jitter module: It injects jitter into the test signal through an adjustable phase clock reference, changes the edge timing of the test signal, and thus generates a target test signal containing controllable jitter.

[0076] Transmitting driver module (external): Receives the target test signal from the FPGA and drives the voltage swing, then transmits the voltage-swept target test signal to the receiving end (i.e., the receiving comparison module) through the physical link.

[0077] Receiver Comparison Module: This module compares the analog target test signal with a set voltage threshold, converting the analog received signal into a digital signal for output to the data receiving module. It typically consists of a high-speed comparator that determines whether the signal is high or low based on a threshold voltage (such as VOH or VOL).

[0078] Data receiving module: Used to receive digital signals from the receiving comparison module, serving as the basis for subsequent clock recovery and sampling processing.

[0079] Clock recovery module: This module recovers the clock signal from the digital signal output by the data receiving module, extracts the embedded clock signal, and generates the target sampling timing sequence. This module can be implemented using CDR (Clock and Data Recovery) logic based on data flip points. For details on the implementation of CDR, please refer to [link to relevant documentation]. Figure 3 That is, based on the received signal ( Figure 3 The system takes input data and determines the phase of the signal, extracts clock information from it, and determines the correct target sampling position.

[0080] Receive Scan Module: Under the clock reference output by the clock recovery module, the received signal is scanned in time. By configuring a programmable receive delay chain, different delays are introduced into the received signal to obtain received data at multiple sampling times; delayed step sampling is completed within one signal period to form a mapping relationship between bit error rate and time (which can be used for eye diagram analysis).

[0081] In this embodiment, the signal transmission module, data reception module, and clock recovery module can all be implemented using the SERDES IP built into the FPGA, such as Xilinx's GTH.

[0082] For example, taking the test of MIPI C-PHY three-level differential signal as an example, the user can first input test configuration parameters in the host computer interface, including protocol type (MIPI C-PHY), transmit rate (e.g., 16.3Gbps), differential swing (e.g., 200mV), and pseudo-random code mode (e.g., PRBS7). The system's protocol processing module generates a data frame containing a preamble and synchronization sequence based on this, and maps it into a logic bit stream (low level V_L, middle level V_M, high level V_H) that conforms to the C-PHY three-level specification. Then, under the rhythm control of the signal transmission module, it is output to the transmit jitter module inside the FPGA.

[0083] The transmit jitter module applies periodic (±5ps) and random (±2ps) phase offsets at each bit period interval (UI) using an adjustable-phase clock reference (e.g., a programmable phase-agile clock reference), generating a target test signal with controllable jitter. This signal is then transmitted to the receiver after differential voltage swing by an external transmit driver module. At the receiver, the comparator module converts the incoming analog three-level signal into a digital bitstream according to a preset threshold. The data receiving module buffers the bitstream and sends it to the clock recovery (CDR) module to extract the embedded clock and determine the target sampling point. Based on this target sampling point, the receive scanning module adjusts the signal phase in 2ps steps within a range of ±UI / 2, acquiring sampled data at multiple phases.

[0084] The protocol processing module compares the sampled data under different phase signals with the original PRBS7 data bit by bit, calculates and summarizes the bit error rate-timing offset mapping curve, and generates an eye diagram based on this. By observing the critical point of the bit error rate changing with the jitter amplitude, the timing tolerance and signal quality of the receiver under the MIPI C-PHY three-level protocol can be accurately evaluated.

[0085] In the embodiments of this application, the above system does not require an expensive oscilloscope and has the advantages of high precision, low cost and high automation in testing.

[0086] See Figure 4 This diagram illustrates a flowchart of a high-speed serial signal testing method provided in an embodiment of this application; this high-speed serial signal testing method is applied to... Figure 1 The high-speed serial signal test system shown is illustrated. Figure 4 As shown, the method may include the following steps:

[0087] Step 401: The timing of the test signal is adjusted using an adjustable phase clock reference to obtain the target test signal.

[0088] Among them, an adjustable phase clock reference refers to a reference clock source that can dynamically change the phase of the output clock through control logic.

[0089] By way of example and not limitation, the timing adjustment of the test signal using an adjustable-phase clock reference in this application can be implemented using a phase-locked loop (PLL), mixed-mode clock manager (MMCM), delay phase-locked loop (DLL) module integrated in an FPGA, or a direct digital frequency synthesizer (DDFS). PLL and MMCM modules typically achieve discrete phase selection through multi-phase outputs, while DDFS performs continuous phase control based on the phase accumulator principle, offering higher phase adjustment accuracy. For example, in a DDFS structure using a 10-bit phase accumulator, the minimum phase step can reach 360° / 1024, meeting the requirements for high-precision jitter simulation.

[0090] This type of clock reference can jump between multiple preset phases or adjust the phase in fine-grained steps to drive the test signal generation module, thereby achieving controllable offset of the signal edge position and forming output waveforms with different jitter characteristics. Programmable phase-agile clock references are a type of clock control mechanism that supports rapid phase switching and jump configuration, suitable for constructing test signal systems with adjustable timing and adjustable jitter characteristics.

[0091] Timing adjustment refers to time offsetting of the rising or falling edge of the test signal. Specifically, it can be achieved by phase switching and jumping through a programmable phase-agile clock reference to generate a target test signal with controllable jitter.

[0092] Specifically, the high-speed serial signal testing system first uses a programmable phase-agile clock reference to adjust the timing of the test signal, achieving precise control over the test signal timing. The programmable phase-agile clock reference consists of a clock management module with multi-phase output capability. This module can rapidly switch between multiple preset phases via configuration registers or control commands. Each phase state corresponds to a clock output with a fixed phase offset relative to the reference clock. By dynamically switching the output clocks of different phases, the timing of the test signal's edge emission can be adjusted without changing the clock frequency, achieving precise control over the rising and falling edge timings, thereby generating a target test signal with controllable jitter characteristics.

[0093] For example, a programmable phase-agile clock reference can be constructed from a clock management module (such as an MMCM or PLL (phase-locked loop) in an FPGA) with multi-phase output capability. It supports switching the output clock in fixed-phase steps within a range of 0° to 360°, achieving a phase resolution of 5° and a corresponding time accuracy of approximately 10 ps (taking a 200MHz clock as an example). By loading configuration registers or sending digital control commands, rapid transitions between multiple preset phases can be achieved, thereby realizing dynamic adjustment of the reference clock phase for driving edge control of test signals and achieving high-precision, jitter-controlled timing generation.

[0094] In one possible implementation, the system is based on a serial-to-parallel converter module that, driven by a reference clock, can combine multiple low-speed digital signals into a single high-speed serial signal for output. Before the test signal is generated, a low-speed reference clock signal is first processed by a clock management module with multi-phase output capability to generate multiple low-speed clock signals with fixed phase differences. These phase-staggered low-speed clocks are used to drive multiple low-speed parallel data streams, ensuring that the parallel data is sent to the serial-to-parallel converter according to a set time relationship, thereby realizing the construction of high-speed signals and fine timing control.

[0095] To further simulate the jitter characteristics of real signals in the time domain, the system can integrate a low-speed jitter clock generation module based on a DDS (Direct Digital Synthesizer). This DDS module internally includes a phase accumulator, a waveform lookup table, a digital-to-analog converter (DAC), and a filtering module to output a continuous, frequency-controllable clock waveform. By dynamically providing the step value for each DDS phase accumulation through a random codeword generator, the phase of the output clock can be modulated, achieving controllable jitter injection into the low-speed reference clock. Its serial-to-parallel conversion module and the low-speed jitter clock generation module based on a DDS can be found in [reference needed]. Figure 5 A diagram illustrating the jitter of a low-speed clock can be found in [reference needed]. Figure 6 The jitter is ultimately inherited by the serial-to-parallel conversion module and reflected in the final target test signal, providing a real and adjustable source of timing disturbance for subsequent signal quality scanning and bit error rate analysis.

[0096] Ultimately, under the further control of the adjustable-phase clock reference, the target test signal possesses the required rising / falling edge timing characteristics and artificially injected phase jitter, which is used to accurately simulate signal changes in actual high-speed transmission systems, providing ideal test input for reception analysis in subsequent steps.

[0097] In one possible implementation, the test signal is time-adjusted using an adjustable-phase clock reference to obtain the target test signal, including:

[0098] Based on preset phase transition control commands, the reference clock is phase-switched to obtain multiple phase-switched clocks;

[0099] Based on the timing of the test signal transmission driven by multiple phase switching clocks and a reference clock, a target test signal with controllable jitter is generated.

[0100] The controllable jitter can be achieved by presetting the jitter amplitude, jitter frequency, and jitter waveform type, among which the waveform type includes sine wave, triangle wave, or random jitter mode.

[0101] Specifically, the clock control module dynamically configures the reference clock according to preset phase transition control commands, causing it to periodically switch between multiple discrete phase values, generating multiple phase-switching clocks with different phase offsets. The driving timing of the test signal is jointly determined by these phase-switching clocks and the original reference clock, forming a controllable edge offset trajectory, thereby achieving dynamic adjustment of the test signal timing. This phase switching process is equivalent to superimposing periodic time offsets at the signal edge positions, thus constructing a target test signal with a set jitter mode. For example, when the phase transition control command cycles within a ±10-degree phase offset range at a frequency of 1 kHz, the corresponding test signal will exhibit deterministic jitter with an amplitude of approximately 20 ps and a frequency of 1 kHz. The entire adjustment process is executed in real time through the clock management logic embedded in the FPGA, ensuring that the stability and resolution of the phase switching meet the accuracy requirements of high-speed timing control.

[0102] In one possible implementation, if the test signal is a three-level signal, such as for MIPI C-PHY multilevel transmission protocol testing, the target test signal generation process in step 401 may include the following refinement operations:

[0103] The output voltage can be set to low level, intermediate level, and high level using a digital-to-analog converter;

[0104] The control transmit driver circuit maps logic bits to corresponding levels;

[0105] Controllable timing jitter is introduced by using an adjustable phase clock reference to achieve timing adjustment of multi-level test signals.

[0106] In this embodiment, the low, medium, and high levels can be set to 150mV, 300mV, and 450mV, respectively. The transmit delay chain adds periodic jitter of 5% peak value in 10ps steps, thereby generating a target test signal that has both level diversity and controllable jitter characteristics, significantly enhancing the test coverage for receiver protocol compatibility and jitter robustness.

[0107] Step 402: The target test signal is sent to the receiver via the transmit driver to obtain the received signal.

[0108] In this embodiment, the target test signal is transmitted to the receiver via a transmit driver circuit. The transmit driver circuit converts the digital logic level into a voltage swing and impedance matching characteristic that conforms to the target protocol requirements.

[0109] For example, refer to Figure 7 The schematic diagram of the output drive shown shows that the output drive circuit can adopt a two-stage structure, including a low-speed driver and a high-speed driver, which are responsible for the reference setting of the output voltage and the rapid conversion of the relative level, respectively.

[0110] The low-speed driver is used to output a stable voltage reference level. Its output voltage is determined by control bit 1 and can be configured to multiple reference values ​​(e.g., 1V or 2.5V). The high-speed driver, based on the voltage reference provided by the low-speed driver, outputs a high-speed voltage variation within a range of ±ΔV, where ΔV is a preset level variation amplitude (e.g., ±0.5V). Its output is driven by control bit 0 to achieve high-speed signal modulation.

[0111] For example, if the voltage reference is 1V or 2.5V and the voltage variation is ±0.5V, the overall output drive can achieve four different level combinations.

[0112] bit1=0, bit0=0; reference voltage 1V + 0.5V = 1.5V.

[0113] bit1=0, bit0=1; reference 1V - 0.5V = 0.5V.

[0114] bit1=1, bit0=0; reference voltage 2.5V + 0.5V = 3.0V.

[0115] bit1=1, bit0=1; reference voltage 2.5V - 0.5V = 2.0V.

[0116] By combining different configurations of bit1 and bit0, the output driver circuit can quickly and stably generate multiple high-speed levels to support the high-speed signal transmission requirements under different protocols or voltage standards. This structure achieves a decoupled design between the voltage reference and the fast switching, improving the integrity and adjustability of the drive signal. It also facilitates coordination with the comparator threshold at the receiving end, enhancing the overall testing flexibility and robustness of the system.

[0117] Step 403: Based on clock recovery, extract the target sampling timing of the received signal, and control the programmable receiving delay chain to adjust the delay of the received signal. Perform time scanning within one signal period to obtain the sampling data of the received signal at multiple sampling times.

[0118] Clock recovery refers to extracting clock information synchronized with the data from the received signal. Specifically, a phase-locked loop or digital clock manager can be used to track the edge transitions of the received signal to determine the reference timing for sampling at the receiving end.

[0119] Among them, the programmable receiver delay chain refers to a receiver time adjustment circuit, which can be implemented using a programmable digital delay line in an FPGA. It is used to continuously adjust the position of the sampling point within a signal cycle to achieve time scanning.

[0120] Time scanning refers to changing the sampling time in fixed steps within a single signal period. Specifically, it can be achieved by gradually increasing or decreasing the delay value of the receiving delay chain, and is used to obtain the distribution of sampled data of the received signal at different time points.

[0121] Specifically, after acquiring the received signal, the receiving end first extracts the target sampling timing of the received signal based on clock recovery technology. The clock recovery circuit reconstructs a sampling clock synchronized with the data by tracking the data transition edges of the received signal. Secondly, it controls a programmable receive delay chain to adjust the delay of the received signal. The programmable receive delay chain consists of multiple adjustable delay units, with different delay configuration values ​​set via digital control signals. Within one signal period, the receive delay chain changes the delay setting in fixed steps, achieving high-density time scanning of the received signal. Under each delay setting, the received signal is sampled, acquiring sampled data at multiple sampling moments.

[0122] For example, the high-speed comparator at the receiving end (i.e., the receive comparator module) can convert differential signals into single-ended digital signals. The comparator's threshold voltages are set by the digital-to-analog converter, including a high threshold voltage VOH and a low threshold voltage VOL. Its clock recovery module can employ a digital phase-locked loop (PLL) structure, reconstructing a sampling clock synchronized with the data by tracking the data transition edges of the received signal. The sampling clock frequency matches the data rate, and its phase is aligned with the data center. The programmable receive delay chain can consist of 32 adjustable delay units. The delay time of each delay unit can be adjusted within the range of 0-5 ps, with a delay resolution of 0.05 ps. Within one signal cycle, the receive delay chain changes the delay setting in fixed steps of 0.5 ps, achieving 32 uniformly distributed sampling moments. The sampled data from these 32 sampling moments is then processed by the protocol processing module.

[0123] In one possible implementation, based on clock recovery, the target sampling timing is extracted from the received signal, including:

[0124] Based on the high and low level switching information in the received signal, clock recovery is performed to obtain the embedded recovered clock of the received signal;

[0125] The target sampling timing is determined based on the embedded recovery clock of the received signal.

[0126] Among them, the high-low level switching information is obtained by detecting the transition point of the logic state in the received signal from high to low or low to high, and the transition point carries clock phase information; the embedded recovery clock can be generated by periodically tracking the transition point interval through a phase-locked loop, and its frequency is consistent with the actual transmission rate of the received signal; the determination of the target sampling timing is achieved by using the rising edge or falling edge of the recovery clock as a reference point and superimposing a fixed phase offset.

[0127] Specifically, during signal transmission, the high-speed comparator continuously monitors the signal level. When it detects that the interval between two consecutive transition points equals a preset signal period, it triggers the clock recovery module to start the phase-locked loop (PLL) circuit. The PLL circuit adjusts the internal oscillator frequency to align the edge of the recovered clock with the transition point, ultimately outputting a phase-synchronized embedded recovered clock. Subsequently, the digital control logic divides the clock period into multiple equally spaced sampling windows based on the edge position of the recovered clock, with each sampling window corresponding to a sampling moment. For example, in PCIe 5.0 protocol testing, the recovered clock frequency is 16 GHz, and the sampling window is based on the rising edge of the recovered clock, with a sampling point set every 6.25 ps, covering the signal variation area within the entire bit period.

[0128] In one possible implementation, with the target sampling timing as the sampling reference, a programmable receive delay chain is controlled to adjust the delay of the received signal, and a time scan is performed within one signal period to acquire sampled data of the received signal at multiple sampling times, including:

[0129] According to the preset fixed delay step, multiple different delay configuration values ​​are set for the programmable receiving delay chain to evenly distribute multiple sampling moments within a receiving signal period;

[0130] At each sampling time, the received signal is sampled to obtain the sampled data of the received signal at multiple sampling times.

[0131] The fixed delay step size is set to the equal interval of the received signal period. For example, in a 200ps signal period at a rate of 5Gbps, 20 delay configuration values ​​are set with a step size of 10ps. The delay configuration values ​​are written into the programmable receive delay chain through registers, and each configuration value corresponds to a specific phase offset within the received signal period. The uniform distribution of sampling times is achieved through fixed-step accumulation, ensuring that the time interval between adjacent sampling points remains consistent.

[0132] Specifically, the delay of the programmable receive delay chain is linearly controlled by a configuration value; each step increases the delay by a fixed value. During time scanning, the delay configuration value is loaded sequentially in step increments, gradually moving the sampling point from the beginning to the end of the signal period. For example, with the initial configuration value, the sampling point is located at 0 ps of the signal period; when the configuration value increases by one step, the sampling point is delayed by 10 ps; when the configuration value reaches its maximum value, the sampling point is located at 190 ps. Because the step size is fixed and accumulates uniformly, the sampling points are evenly distributed within the signal period. This method ensures that the sampled data covers the rising edge, falling edge, and steady-state range of the signal, avoiding errors in eye diagram opening region identification due to uneven sampling point distribution. By traversing all delay configuration values, the voltage changes of the received signal within a complete period are fully captured, providing a high-resolution data foundation for bit error rate statistics.

[0133] Step 404: Compare the sampled data at multiple sampling times with the test signal, calculate the bit error rate under each delay setting, and complete the signal quality assessment.

[0134] Bit error rate statistics refer to comparing the received signal with the test signal bit by bit and calculating the error ratio. Specifically, a real-time comparison counter can be implemented using hardware logic to quantify the signal quality differences under different delay settings.

[0135] Specifically, the sampled data at multiple sampling times are compared with the test signal, and the bit error rate (BER) is calculated for each delay setting. By analyzing the BER distribution, the eye diagram characteristics of the received signal can be constructed. Based on the characteristics of the eye diagram's opening region, signal quality is assessed. This evaluation method based on high-density scanning can accurately reflect the timing margin and voltage noise tolerance of the received signal.

[0136] In one possible implementation, sampled data from multiple sampling times are compared with the test signal, and the bit error rate is calculated for each delay setting to complete the signal quality assessment, including:

[0137] The sampled data at each sampling time point is compared with the test signal one by one, and the bit error rate corresponding to each delay setting is calculated.

[0138] Construct an eye diagram of the received signal based on the bit error rate distribution;

[0139] Based on the eye diagram of the received signal, complete the signal quality assessment.

[0140] The bit error rate (BER) statistics are achieved by comparing the received data with the original test sequence bit by bit, with each delay setting corresponding to a specific sampling phase. The eye diagram is constructed by mapping the BER onto the time axis to form a two-dimensional distribution, with the horizontal axis representing the sampling time offset and the vertical axis representing the BER value. The opening region identification uses a threshold comparison algorithm to filter continuous regions with a BER of less than one in a million. The center position calculation determines the midpoint of the time interval through linear interpolation.

[0141] For example, the received data at each sampling time is compared with the test signal one by one, and the bit error rate (BER) corresponding to each delay setting is calculated. Specifically, multiple sampling times can be set, such as 16 sampling points evenly distributed within one signal period. For each sampling point, the sampled data is compared with the data at the corresponding position in the original test signal to calculate the number of bit errors. Then, the BER corresponding to each sampling point is calculated based on the total number of bits. An eye diagram of the received signal is constructed based on the BER distribution. The BER data of each sampling point is plotted as a two-dimensional graph, with the horizontal axis representing the sampling time and the vertical axis representing the BER. An eye diagram contour is formed by connecting adjacent points. Based on the eye diagram contour, signal quality assessment is completed. Similarly, BER testing, jitter analysis, and other quality assessments can be performed.

[0142] In one possible implementation, the received data at each sampling time is compared with the test signal one by one, and the bit error rate corresponding to each delay setting is calculated, including:

[0143] The protocol is parsed for the sampled data at each sampling time, the preamble field and the synchronization sequence field are identified, and the effective data start position of each sampled data is determined.

[0144] Based on the effective data start position of each sampled data, extract the effective data fields from the sampled data at each sampling time.

[0145] The valid data field is compared with the valid data field of the test signal, and the bit error rate corresponding to each delay setting is calculated.

[0146] Protocol parsing is implemented through hardware logic or firmware. The preamble field is a fixed bit sequence defined by a specific protocol, used to indicate the start of a data frame. The synchronization sequence field is used for clock alignment and symbol boundary calibration. The start position of valid data is determined by detecting the offset between the end position of the preamble and the end position of the synchronization sequence. After the valid data field is extracted, the bit error rate is calculated through bit-by-bit comparison or block check.

[0147] Specifically, after the received signal is sampled and timed according to the target, it is input into the protocol parsing module. The preamble detection circuit matches a fixed bit sequence, and the preamble is considered to have ended when the number of consecutive matches exceeds a preset threshold. The synchronization sequence detection circuit performs symbol boundary search based on the symbol interval specified in the protocol to determine the symbol alignment point. The start position of the valid data is calculated by the relative offset between the end position of the preamble and the synchronization sequence alignment point. The valid data field is truncated from the received signal according to the start position and a preset length, and then sent to the bit error rate (BER) statistics module for bit-by-bit comparison with the original data of the test signal. The BER calculation result is used to evaluate signal quality and ensure that the test results reflect the true transmission performance.

[0148] In one possible implementation, the high-speed serial signal testing method further includes: performing parallel testing on multiple high-speed serial channels, and setting the sampling timing and receiving delay configuration values ​​for each channel respectively.

[0149] Because different trace delays and device delays will cause different timings in different lanes, different lanes require different clock recovery methods (CDRs) to independently recover the clock and determine their respective optimal sampling times. See details in [link to documentation]. Figure 8 .

[0150] In this embodiment, steps 401 to 404 adjust the timing of the test signal using a programmable transmit delay chain, actively introducing controllable jitter for jitter tolerance testing. The target test signal is sent to the receiver via a transmit driver. After receiving the signal, the sampling timing is extracted based on clock recovery, and the programmable receive delay chain is controlled to perform time scanning to acquire received data at multiple sampling times. By comparing each sampled data with the test signal, the bit error rate under each delay setting is calculated to complete the signal quality assessment. This scheme has advantages such as modularity, high precision, and low cost, improving the overall testing efficiency and accuracy of high-speed serial signals.

[0151] See Figure 9 The diagram illustrates a flowchart of another high-speed serial signal testing method provided in an embodiment of this application. Figure 9 As shown, the method may include the following steps:

[0152] Step 901: Generate a test signal that conforms to the target protocol format based on the preset test configuration parameters.

[0153] In this embodiment of the application, the preset test configuration parameters can be set by the control device of the semiconductor test equipment.

[0154] The test configuration parameters include at least the protocol type, transmission rate, and voltage swing parameter. The valid data field of the test signal is generated based on a pseudo-random number generator to simulate actual business data.

[0155] Specifically, the protocol type parameter ensures the test signal conforms to the target interface specification, the transmit rate parameter controls the signal timing frequency, and the voltage swing parameter defines the signal amplitude range. The valid data field generated by the pseudo-random number generator contains randomized 0 / 1 sequences, covering various data combination patterns, and can simulate real business data streams. The test configuration parameters are set through configuration registers: the protocol type parameter selects the frame structure of different interfaces such as MIPI, PCIe, or USB; the transmit rate parameter sets the signal baud rate; and the voltage swing parameter adjusts the driver's output amplitude. The pseudo-random number generator uses an LFSR structure to generate PRBS7 or PRBS31 sequences to fill the valid data field, simulating the random data distribution in real transmission scenarios. The resulting test signal not only meets the target protocol format requirements but also possesses statistical characteristics similar to actual business data, ensuring that subsequent timing adjustments and bit error rate statistics accurately reflect the performance of the system under test in business scenarios.

[0156] Step 902: The timing of the test signal is adjusted using an adjustable phase clock reference to obtain the target test signal.

[0157] Step 903: The target test signal is sent to the receiver via the transmit driver to obtain the received signal.

[0158] Step 904: Based on clock recovery, extract the target sampling timing of the received signal, and control the programmable receiving delay chain to adjust the delay of the received signal. Perform time scanning within one signal period to obtain the sampling data of the received signal at multiple sampling times.

[0159] Step 905: Compare the sampled data at multiple sampling times with the test signal, calculate the bit error rate under each delay setting, and complete the signal quality assessment.

[0160] The implementation of steps 902 to 905 in this embodiment is the same as that of steps 401 to 404 in the above embodiment, and they can be referred to each other. This application will not repeat them here.

[0161] Compared to the above embodiments, the embodiments of this application can flexibly generate test signals conforming to various high-speed serial interface protocols, improving the versatility and configurability of the test system applied to semiconductor test equipment. By using pseudo-random data to simulate actual business data, the realism of the test is enhanced, which helps to discover potential signal integrity issues. In addition, the preset test configuration parameters allow the test process to quickly adapt to different application scenarios and test requirements, improving test efficiency.

[0162] Figure 10 This is a schematic diagram of the structure of a semiconductor testing device provided in an embodiment of this application, as shown below. Figure 10As shown, the semiconductor testing equipment of this embodiment includes at least a control device and a high-speed serial signal testing system. The control device is used to control the activation of the testing function of the high-speed serial signal testing system. For example, when it is necessary to test the high-speed serial signal of the chip, the high-speed serial signal testing function of the semiconductor testing equipment can be activated by the control device.

[0163] The high-speed serial signal test system includes at least a transmit jitter module, a transmit drive module, a receive scan module, and a signal test module.

[0164] In this embodiment of the application, the high-speed serial signal testing system further includes:

[0165] The test signal generation module is used to generate a test signal conforming to the target protocol format based on preset test configuration parameters. The test configuration parameters include at least the protocol type, transmission rate, and voltage swing parameter. The effective data field of the test signal is generated based on a pseudo-random number generator to simulate actual business data.

[0166] In this embodiment of the application, the transmit jitter module may further include:

[0167] The phase switching unit is used to switch the phase of the reference clock based on a preset phase transition control command to obtain multiple phase-switched clocks.

[0168] The driving unit is used to drive the timing of the test signal transmission according to the plurality of phase switching clocks and the reference clock, so as to generate a jitter-controllable target test signal.

[0169] In this embodiment of the application, the receiving scanning module may specifically include:

[0170] A clock recovery unit is used to perform clock recovery based on the high-low level toggling information in the received signal, and to obtain the embedded recovered clock of the received signal;

[0171] The target sampling determination unit is used to determine the target sampling timing based on the embedded recovery clock of the received signal.

[0172] In this embodiment of the application, when the target sampling timing is used as the sampling reference, the receiving scanning module may further include:

[0173] The delay value configuration unit is used to set multiple different delay configuration values ​​for the programmable receiving delay chain according to a preset fixed delay step size, so as to evenly distribute multiple sampling moments within a receiving signal period;

[0174] The sampling acquisition unit is used to sample the received signal at each sampling time to acquire the sampling data of the received signal at the multiple sampling times.

[0175] In this embodiment of the application, the signal testing module may specifically include:

[0176] The comparison unit is used to compare the sampled data at each sampling time with the test signal one by one, and to calculate the bit error rate corresponding to each delay setting.

[0177] An eye diagram construction unit is used to construct an eye diagram of the received signal based on the bit error rate distribution;

[0178] The quality assessment unit is used to perform signal quality assessment based on the eye diagram of the received signal.

[0179] In this embodiment of the application, the sampling acquisition unit can specifically be used for:

[0180] The sampled data at each sampling time is parsed according to the protocol, the preamble field and the synchronization sequence field are identified, and the effective data start position of each sampled data is determined.

[0181] Based on the effective data start position of each sampled data, extract the effective data fields from the sampled data at each sampling time;

[0182] The valid data field is compared with the valid data field of the test signal, and the bit error rate corresponding to each delay setting is calculated.

[0183] In this embodiment of the application, the high-speed serial signal testing system further includes:

[0184] The parallel testing module is used to perform parallel testing on multiple high-speed serial channels and set the sampling timing and receiving delay configuration values ​​for each channel.

[0185] Figure 11 This is a schematic diagram of another semiconductor testing device provided in an embodiment of this application. Figure 11 As shown, the semiconductor testing equipment 1100 of this embodiment includes: at least one processor 1110 ( Figure 11 (Only one is shown in the diagram) a processor, a memory 1120, and a computer program 1121 stored in the memory 1120 and executable on the at least one processor 1110, wherein the processor 1110 executes the computer program 1121 to implement the steps in the above-described high-speed serial signal testing method embodiment.

[0186] The semiconductor testing equipment 1100 can be a server, physical server, or computing device, etc. This semiconductor testing equipment may include, but is not limited to, a processor 1110 and a memory 1120. Those skilled in the art will understand that... Figure 11This is merely an example of semiconductor test equipment 1100 and does not constitute a limitation on semiconductor test equipment 1100. It may include more or fewer components than shown, or combine certain components, or different components, such as input / output devices, network access devices, etc.

[0187] The processor 1110 may be a Central Processing Unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0188] In some embodiments, the memory 1120 may be an internal storage unit of the semiconductor testing equipment 1100, such as a hard disk or memory of the semiconductor testing equipment 1100. In other embodiments, the memory 1120 may be an external storage device of the semiconductor testing equipment 1100, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on the semiconductor testing equipment 1100. Furthermore, the memory 1120 may include both internal storage units and external storage devices of the semiconductor testing equipment 1100. The memory 1120 is used to store operating systems, applications, boot loaders, data, and other programs, such as the program code of computer programs. The memory 1120 can also be used to temporarily store data that has been output or will be output.

[0189] In specific implementations, the processor 1110, memory 1120, and computer program 1121 described in the embodiments of this application can execute the embodiments of the high-speed serial signal testing method of this application, which will not be repeated here.

[0190] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0191] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0192] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0193] In the embodiments provided in this application, it should be understood that the disclosed apparatus / semiconductor testing equipment and methods can be implemented in other ways. For example, the apparatus / semiconductor testing equipment embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0194] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0195] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0196] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0197] The implementation of all or part of the processes in the methods of the above embodiments can also be accomplished by a computer program product. When the computer program product is run on a semiconductor testing device, the semiconductor testing device can implement the steps in the various method embodiments described above.

[0198] The embodiments described above are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for testing high-speed serial signals, characterized in that, The method, applied to a high-speed serial signal testing system, includes: The timing of the test signal is adjusted using an adjustable phase clock reference to obtain the target test signal; The target test signal is transmitted to the receiving end via a transmission driver, and the received signal is obtained. Based on clock recovery, the target sampling timing is extracted from the received signal, and the programmable receiving delay chain is controlled to adjust the delay of the received signal. Time scanning is performed within one signal period to obtain the sampling data of the received signal at multiple sampling times. The sampled data at the multiple sampling times are compared with the test signal, and the bit error rate under each delay setting is calculated to complete the signal quality assessment. The controllable programmable receive delay chain adjusts the delay of the received signal, performs time scanning within one signal period, and acquires sampled data of the received signal at multiple sampling times, including: Using the target sampling timing as the sampling reference, and according to a preset fixed delay step, multiple different delay configuration values ​​are set for the programmable receiving delay chain to evenly distribute multiple sampling times within a receiving signal period. At each sampling time, the received signal is sampled to obtain the sampled data of the received signal at the multiple sampling times.

2. The method as described in claim 1, characterized in that, Before timing the test signal using an adjustable-phase clock reference to obtain the target test signal, the method further includes: Based on preset test configuration parameters, a test signal conforming to the target protocol format is generated. The test configuration parameters include at least the protocol type, transmission rate, and voltage swing parameter. The valid data field of the test signal is generated based on a pseudo-random number generator to simulate actual business data.

3. The method as described in claim 2, characterized in that, The step of timing the test signal using an adjustable-phase clock reference to obtain the target test signal includes: Based on preset phase transition control commands, the reference clock is phase-switched to obtain multiple phase-switched clocks; Based on the timing of the test signal transmission driven by the multiple phase switching clocks and the reference clock, a jitter-controlled target test signal is generated.

4. The method as described in claim 1, characterized in that, The step of extracting the target sampling timing from the received signal based on clock recovery includes: Based on the high and low level switching information in the received signal, clock recovery is performed to obtain the embedded recovered clock of the received signal; The target sampling timing is determined based on the embedded recovery clock of the received signal.

5. The method as described in claim 1, characterized in that, The step of comparing the sampled data at the multiple sampling times with the test signal, calculating the bit error rate under each delay setting, and completing the signal quality assessment includes: The sampled data at each sampling time point are compared with the test signal one by one, and the bit error rate corresponding to each delay setting is calculated. An eye diagram of the received signal is constructed based on the bit error rate distribution; Based on the eye diagram of the received signal, a signal quality assessment is performed.

6. The method as described in claim 5, characterized in that, The step of comparing the received data at each sampling time with the test signal one by one, and calculating the bit error rate corresponding to each delay setting, includes: The sampled data at each sampling time is parsed according to the protocol, the preamble field and the synchronization sequence field are identified, and the effective data start position of each sampled data is determined. Based on the effective data start position of each sampled data, extract the effective data fields from the sampled data at each sampling time; The valid data field is compared with the valid data field of the test signal, and the bit error rate corresponding to each delay setting is calculated.

7. The method as described in claim 1, characterized in that, The method further includes: Parallel testing was performed on multiple high-speed serial channels, and the sampling timing and receiving delay configuration values ​​for each channel were set respectively.

8. A high-speed serial signal testing system, characterized in that, The system is built on an FPGA and includes: The transmit jitter module is used to adjust the timing of the test signal using an adjustable phase clock reference to obtain the target test signal; The transmission driver module is used to send the target test signal to the receiving end via the transmission driver and to obtain the received signal; The receiving scanning module is used to extract the target sampling timing of the received signal based on clock recovery, and control the programmable receiving delay chain to adjust the delay of the received signal, perform time scanning within one signal period, and obtain the sampling data of the received signal at multiple sampling times; The signal testing module is used to compare the sampled data at the multiple sampling times with the test signal, calculate the bit error rate under each delay setting, and complete the signal quality assessment. The receiving scanning module is further configured to use the target sampling timing as a sampling reference and set multiple different delay configuration values ​​for the programmable receiving delay chain according to a preset fixed delay step size, so as to evenly distribute multiple sampling times within a receiving signal period; and to sample the received signal at each sampling time to obtain the sampling data of the received signal at the multiple sampling times.

9. A semiconductor testing device, characterized in that, The semiconductor testing equipment includes at least a control device and the high-speed serial signal testing system as described in claim 8; The control device is used to control the activation of the test function of the high-speed serial signal test system.

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