Method, device, equipment and storage medium for correcting delay between channels of optical interconnection links

Abstract

The present disclosure provides a method, apparatus, device, and storage medium for correcting inter-channel delay in an optical interconnect link. During PCIe link training, the transmission delay of each channel upon reaching a receiving device is determined based on the training sequence transmitted between the channels of the PCIe link. Based on the transmission delay of each channel, the inter-channel delay of the PCIe link is corrected using the optical microring resonator of each channel. The present disclosure can correct the transmission delay of PCIe signals in a PCIe optical interconnect link and achieve delay alignment between channels. This method can avoid the drawbacks of using serpentine winding or other methods on the PCB end to compensate for transmission delay, maximize savings in PCB wiring space, and improve PCB wiring density, signal integrity, and link training success rate.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, in particular to optical communications, and more particularly to a method, apparatus, device, and storage medium for correcting inter-channel delay in an optical interconnection link. Background Art

[0002] PCIe (Peripheral Component Interconnect Express), a key implementation of a high-speed serial bus protocol, is widely used in servers, storage systems, and artificial intelligence computing platforms, enabling high-speed data interconnection between high-performance computing devices. PCIe is a high-speed serial bus protocol, and a PCIe link typically consists of multiple channels (a link contains multiple lanes) to provide greater bandwidth.

[0003] In current PCB link designs, to minimize latency differences between PCIe channels, the routing lengths of different channels within the same link are typically kept as close as possible. For example, PCIe channels that could otherwise have shorter routing are deliberately routed in a serpentine pattern to approximate the transmission delay of the longest routing channel. However, this serpentine routing approach consumes significant PCB routing space and reduces routing density. Furthermore, the routing process creates numerous bends in the channel, which can lead to impedance discontinuities and cause signal quality issues such as reflections and ringing. Furthermore, the actual propagation delay of high-frequency signals in serpentine routing can deviate from the designed value due to skin effect and dielectric loss. Summary of the Invention

[0004] The present disclosure provides a method, apparatus, device, and storage medium for correcting inter-channel delay in an optical interconnect link. These methods can correct PCIe signal transmission delay in a PCIe optical interconnect link, avoid the drawbacks of compensating for transmission delay using methods such as serpentine winding on the PCB end, maximize PCB wiring space savings, and improve PCB wiring density.

[0005] In a first aspect, an embodiment of the present disclosure provides a method for correcting inter-channel delay in an optical interconnection link, comprising:

[0006] During PCIe link training, determining the transmission delay of each channel when the training sequence is transmitted between the channels of the PCIe link and reaches the receiving device;

[0007] According to the transmission delay of each channel, the optical microring resonator of each channel is used to correct the inter-channel delay of the PCIe link.

[0008] In a second aspect, an embodiment of the present disclosure provides a device for correcting delay between channels of an optical interconnection link, comprising:

[0009] A determination module, configured to determine, during a PCIe link training process, the transmission delay of each channel of the PCIe link when the training sequence is transmitted between the channels, when the training sequence reaches the receiving end device;

[0010] The correction module is used to correct the inter-channel delay of the PCIe link using the optical microring resonator of each channel according to the transmission delay of each channel.

[0011] In a third aspect, an embodiment of the present disclosure provides an optical transceiver device, including:

[0012] An optical delay component for controlling the delay of the training sequence optical signal transmitted by each channel of the PCIe link;

[0013] an optical receiving component connected to the optical delay component, the optical receiving component being configured to convert the training sequence optical signal output by the optical delay component into a differential electrical signal;

[0014] A detection controller is connected to the optical delay component and the optical receiving component, respectively. The detection controller is used to detect the arrival time of the training sequence of each channel in the differential electrical signal, determine the transmission delay of each channel, and use the optical microring resonator of each channel to correct the inter-channel delay of the PCIe link based on the transmission delay of each channel.

[0015] In a fourth aspect, an embodiment of the present disclosure provides a receiving end device, comprising the optical transceiver device as described in the third aspect above.

[0016] In a fifth aspect, an embodiment of the present disclosure provides a storage medium storing instructions. When the instructions are executed on a receiving-end device, the receiving-end device executes the method described in the first aspect above.

[0017] In a sixth aspect, an embodiment of the present disclosure provides a program product, comprising at least one of a program and an instruction, wherein when the at least one of the program and the instruction is executed by a receiving device, the steps of the method described in the first aspect are implemented.

[0018] In the seventh aspect, an embodiment of the present disclosure provides a resource pooling system based on the PCIe protocol, including a first computing device and a second computing device, wherein the first computing device and the second computing device are optically interconnected through the optical transceiver equipment and optical fiber as described in the third aspect above.

[0019] According to the technical solution disclosed in the present invention, it is possible to correct the PCIe signal transmission delay in the PCIe optical interconnection link and achieve delay alignment between channels. This can avoid the defects of using serpentine winding and other methods on the PCB end to compensate for transmission delay, maximize the savings in PCB wiring space, and improve PCB wiring density, signal integrity, and link training success rate.

[0020] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings are provided to facilitate a better understanding of the present invention and do not constitute a limitation of the present disclosure.

[0022] Figure 1 1 is a flow chart of a method for correcting inter-channel delay in an optical interconnection link according to an embodiment of the present disclosure;

[0023] Figure 2 1 is a flow chart of a method for correcting inter-channel delay in an optical interconnection link according to an embodiment of the present disclosure;

[0024] Figure 3 is a block diagram of an optical interconnect link inter-channel delay correction device provided according to an embodiment of the present disclosure;

[0025] Figure 4 is a block diagram of an optical transceiver device provided according to an embodiment of the present disclosure;

[0026] Figure 5 An example diagram of a PCIe protocol optical interconnect link receiving end channel delay correction solution provided by an embodiment of the present disclosure;

[0027] Figure 6 For Figure 5 The PCIe protocol optical interconnect link receiving end channel delay correction scheme shown in the figure implements the control flow chart of channel delay correction;

[0028] Figure 7 is a schematic diagram of an optical transceiver device provided according to an embodiment of the present disclosure;

[0029] Figure 8 is a block diagram of a receiving device provided according to an embodiment of the present disclosure;

[0030] Figure 9 is a schematic diagram of a remote GPU interconnection system provided according to an embodiment of the present disclosure;

[0031] Figure 10 Schematic diagram of a resource pooling system based on the PCIe protocol provided according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] The following description of exemplary embodiments of the present disclosure is made in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding. These details should be considered as merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0033] The following describes the method, apparatus, device, and storage medium for correcting inter-channel delay in an optical interconnection link according to embodiments of the present disclosure with reference to the accompanying drawings.

[0034] It should be noted that the execution entity of the optical interconnection link channel delay correction method of the embodiment of the present disclosure may be an optical interconnection link channel delay correction device, which may be implemented by software and / or hardware. The device may be configured in an electronic device, which may be a receiving end device, and the receiving end device may include but is not limited to a terminal, a server end, etc.

[0035] Figure 1 FIG. 1 is a flow chart of a method for correcting delay between optical interconnection links according to an embodiment of the present disclosure, as shown in FIG. Figure 1 As shown, the method may include but is not limited to the following steps.

[0036] In step 101, during the PCIe link training process, the transmission delay of each channel when reaching the receiving end device is determined based on the training sequence transmitted between each channel of the PCIe link.

[0037] In some embodiments, the training sequences transmitted between lanes of a PCIe link may be sent by a transmitting device. In one possible implementation, the PCIe link lanes enter a link training process, and the transmitting device sends the training sequences to the receiving device. The receiving device can determine the transmission delay of each lane before the training sequences reach the receiving device based on the training sequences transmitted between the lanes of the PCIe link.

[0038] In some embodiments, the training sequence may include, but is not limited to, one or more of the following: a TS1 symbol sequence; a TS2 symbol sequence; a symbol sequence used to identify a training phase during PCIe link training, the symbol sequence being different from the TS1 symbol sequence and the TS2 symbol sequence. Exemplarily, the training sequence may be used to confirm the transmission delay of a PCIe link channel. For example, the training sequence may use the TS1 symbol sequence, but is not limited thereto. For example, the training sequence may also use the TS2 symbol sequence, or may use other symbol sequences that need to be transmitted during link training, the symbol sequence being different from the TS1 symbol sequence and the TS2 symbol sequence.

[0039] In some embodiments, the PCIe link training process may include, but is not limited to, one or more of the following: an initial training process when a PCIe link is first established; and a training process when a PCIe channel re-enters a recovery state after exiting a low-power state (L0s). Exemplarily, the PCIe link training process may include the initial training process when a PCIe link is first established, and may also include a link training process when a PCIe link channel re-enters a recovery state after exiting a low-power state (L0s).

[0040] In step 102, according to the transmission delay of each channel, the optical microring resonator of each channel is used to correct the inter-channel delay of the PCIe link.

[0041] In some embodiments, a maximum transmission delay may be determined from the transmission delays of the various channels, and the inter-channel delay of the PCIe link may be corrected based on the difference between the maximum transmission delay and the transmission delays of the various channels.

[0042] In one possible implementation, based on the difference between the maximum transmission delay and the transmission delay of each channel, the optical microring resonator corresponding to each channel can continue to transmit the training sequence of the corresponding channel after a specific delay, thereby correcting the inter-channel delay of the PCIe link.

[0043] By implementing the embodiments of the present disclosure, it is possible to correct the PCIe signal transmission delay in the PCIe optical interconnect link and achieve delay alignment between channels. This can avoid the defects of using serpentine winding and other methods on the PCB end to compensate for transmission delay, maximize the savings in PCB wiring space, and improve PCB wiring density, signal integrity, and link training success rate.

[0044] Figure 2 FIG. 1 is a flow chart of a method for correcting delay between optical interconnection links according to an embodiment of the present disclosure, as shown in FIG. Figure 2 As shown, the method may include but is not limited to the following steps.

[0045] In step 201, during the PCIe link training process, a training sequence optical signal received by a receiving end device is converted into a differential electrical signal.

[0046] In some embodiments, the training sequence transmitted between the various channels of a PCIe link may be sent by a transmitting device. In one possible implementation, a PCIe link channel enters a link training process, and the transmitting device sends a training sequence to a receiving device. The receiving device includes an optical receiving component that can convert the training sequence optical signal received by the receiving device into a differential electrical signal. Exemplarily, each channel of the PCIe link corresponds to an optical receiving component. When the receiving device receives the training sequence, the optical receiving component of each channel converts the training sequence optical signal of the respective channel into a differential electrical signal.

[0047] In some embodiments, the training sequence may include, but is not limited to, one or more of the following: a TS1 symbol sequence; a TS2 symbol sequence; a symbol sequence used to identify a training phase during PCIe link training, the symbol sequence being different from the TS1 symbol sequence and the TS2 symbol sequence. Exemplarily, the training sequence may be used to confirm the transmission delay of a PCIe link channel. For example, the training sequence may use the TS1 symbol sequence, but is not limited thereto. For example, the training sequence may also use the TS2 symbol sequence, or may use other symbol sequences that need to be transmitted during link training, the symbol sequence being different from the TS1 symbol sequence and the TS2 symbol sequence.

[0048] In some embodiments, the PCIe link training process may include, but is not limited to, one or more of the following: an initial training process when a PCIe link is first established; and a training process when a PCIe channel re-enters a recovery state after exiting a low-power state (L0s). Exemplarily, the PCIe link training process may include the initial training process when a PCIe link is first established, and may also include a link training process when a PCIe link channel re-enters a recovery state after exiting a low-power state (L0s).

[0049] In step 202, the arrival time of the training sequence of each channel in the differential electrical signal is detected to determine the transmission delay of each channel.

[0050] In an embodiment of the present disclosure, a training sequence optical signal may include, but is not limited to, the sending time of the training sequence. The training sequence optical signal is converted into a differential electrical signal so that the differential electrical signal carries information about the sending time of the training sequence of each channel. The differential electrical signal can be parsed and detected to determine the arrival time and sending time of the training sequence of each channel in the differential electrical signal. The transmission delay of each channel is determined based on the arrival time and sending time.

[0051] In step 203, the maximum transmission delay is determined from the transmission delays of the various channels.

[0052] In an embodiment of the present disclosure, the transmission delays (also called latency or transmission delay) of various channels may be compared to determine the maximum transmission delay and the corresponding channel.

[0053] In step 204 , according to the difference between the maximum transmission delay and the transmission delay of each channel, the optical microring resonator of each channel is used to correct the inter-channel delay of the PCIe link.

[0054] In some embodiments, each channel can be associated with multiple optical microring resonators, which can be arranged in series. In some embodiments, the nominal adjustable delay of a single optical microring resonator can range from 80 to 120 ps. The nominal adjustable delay of an optical microring resonator is primarily achieved by varying the resonance conditions, which are typically related to the free spectral range (FSR) and the coupling coefficient. By adjusting the coupling coefficient (e.g., changing the spacing or width between the straight waveguide and the ring waveguide) or the temperature (thermo-optical effect), the optical microring resonator can dynamically adjust the resonant wavelength, thereby varying the number of light cycles within the ring waveguide and the delay. For example, increasing the coupling coefficient couples more light into the ring waveguide, resulting in increased delay; decreasing the coupling coefficient reduces it. The number of optical microring resonators can be selected based on system requirements and the number of control ports. For example, four to eight optical microring resonators can be designed for a single channel to compensate for PCB trace length differences of up to approximately 150 mm. Exemplarily, each channel is associated with an optical waveguide device for transmitting optical signals and multiple optical microring resonators for delaying optical signals. Multiple optical microring resonators are connected in series to regulate the transmission delay of the training sequence inside the optical waveguide device.

[0055] In some embodiments, the difference between the maximum transmission delay and the transmission delay of each channel can be used as a target to control the resonance of the optical microring resonator in each channel. The resonant optical microring resonator can be used to continue transmitting the training sequence of the corresponding channel after a specific delay. Exemplarily, the difference between the maximum transmission delay and the transmission delay of each channel is used as a target to control the resonance of each optical microring resonator in each channel. The training sequence optical signal first enters the optical microring resonator at the resonant optical microring resonator and then re-enters the optical waveguide device for continued transmission after a specific delay, completing inter-channel delay correction.

[0056] Optionally, in some embodiments, the arrival time of subsequent training sequences transmitted between channels can be detected to determine the maximum difference in transmission delays across the channels. When the maximum difference in transmission delays across the channels is less than the rated adjustable delay of a single optical microring resonator, a confirmation message is sent to the receiving device, indicating that inter-channel delay correction is complete. Exemplarily, the arrival time of subsequent training sequences can be detected, and when the maximum difference in transmission delays across all channels is less than the rated adjustable delay of a single optical microring resonator, inter-channel delay correction is considered complete, and confirmation of the completion of inter-channel delay correction can be sent to the receiving device or a PCIe chip of the receiving device via a communication link.

[0057] In the above-described embodiment, an optical delay correction mechanism is introduced into the receiving device, utilizing an optical microring resonator to controllably adjust the delay of the optical signal, thereby achieving dynamic inter-channel delay matching and precise inter-channel delay correction. This avoids serpentine PCB wiring and eliminates the need to increase wiring length to adjust delay, saving PCB wiring space and increasing wiring density. The optical delay correction method avoids signal reflections, ringing, and other signal quality issues caused by bends and impedance discontinuities in traditional wiring methods, thereby improving signal integrity. The method is applicable not only to the training process during initial link establishment but also supports delay correction when a PCIe channel re-enters the Recovery state after exiting a low-power state, enabling dynamic delay adjustment. Multiple optical microrings can be independently configured for each channel to achieve precise inter-channel delay matching. Replacing traditional wiring with optical delay correction simplifies the PCB design process and reduces material and process costs. After inter-channel delay alignment, link training success rates are improved, bit error rates are reduced, and overall system performance and stability are enhanced, thereby improving system interconnect performance and reliability.

[0058] Figure 3 FIG is a block diagram of an optical interconnect link channel delay correction device provided according to an embodiment of the present disclosure. Figure 3 As shown, the optical interconnect link inter-channel delay correction device may include: a determination module 301 and a correction module 302.

[0059] The determination module 301 is configured to determine the transmission delay of each channel when the training sequence reaches the receiving device according to the training sequence transmitted between each channel of the PCIe link during the PCIe link training process.

[0060] The correction module 302 is configured to correct the inter-channel delay of the PCIe link using the optical microring resonator of each channel according to the transmission delay of each channel.

[0061] In some embodiments, the determination module 301 is configured to: convert the training sequence optical signal received by the receiving device into a differential electrical signal; detect the arrival time of the training sequence of each channel in the differential electrical signal, and determine the transmission delay of each channel.

[0062] In some embodiments, the correction module 302 is configured to: determine a maximum transmission delay from the transmission delays of the channels; and correct the inter-channel delay of the PCIe link using the optical microring resonator of each channel based on the difference between the maximum transmission delay and the transmission delay of each channel.

[0063] In some embodiments, the correction module 302 is configured to control the optical microring resonator of each channel to resonate, with the difference between the maximum transmission delay and the transmission delay of each channel as a target. The resonant optical microring resonator is configured to continue transmitting the training sequence of the corresponding channel after a specific delay.

[0064] In some embodiments, the determination module 301 is further configured to detect the arrival time of subsequent training sequences transmitted between the channels and determine the maximum difference in transmission delays between the channels. The correction module 302 is further configured to send a confirmation message to a receiving device if the maximum difference in transmission delays between the channels is less than the rated adjustable delay of a single optical microring resonator. The confirmation message indicates that inter-channel delay correction is complete.

[0065] In some embodiments, each channel is associated with multiple optical microring resonators, and the multiple optical microring resonators are arranged in series. In some embodiments, the rated adjustable delay of a single optical microring resonator ranges from 80 to 120 ps.

[0066] In some embodiments, the training sequence includes one or more of the following: a TS1 symbol sequence; a TS2 symbol sequence; a symbol sequence used to identify a training phase during PCIe link training, the symbol sequence being different from the TS1 symbol sequence and the TS2 symbol sequence.

[0067] In some embodiments, the PCIe link training process includes one or more of the following: an initial training process when the PCIe link is first established; a training process when the PCIe channel exits a low power state and re-enters a recovery state.

[0068] Regarding the apparatus in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0069] Figure 4 FIG is a block diagram of an optical transceiver device provided according to an embodiment of the present disclosure. Figure 4 As shown, the optical transceiver device may include: an optical delay component 11, an optical receiving component 12, and a detection controller 13. The optical delay component 11 can be used to controllably adjust the delay of the training sequence optical signal transmitted by each channel of the PCIe link. The optical receiving component 12 is connected to the optical delay component 11 and can be used to convert the training sequence optical signal output by the optical delay component 11 into a differential electrical signal. The detection controller 13 is connected to the optical delay component 11 and the optical receiving component 12 respectively and can be used to detect the arrival time of the training sequence of each channel in the differential electrical signal, determine the transmission delay of each channel, and use the optical microring resonator of each channel to correct the inter-channel delay of the PCIe link based on the transmission delay of each channel.

[0070] In some embodiments, as Figure 5 As shown, 10 is a symbol sequence (such as a training sequence) transmitted by the PCIe protocol, 11 is an optical delay component, 12 is an optical receiving component, and 13 is a detection controller. The optical delay component 11 may include various channels (such as Figure 5The optical waveguides 111 (four channels, but not limited thereto) and optical microring resonators 112 connected to the optical waveguides 111 are shown. Each channel is associated with a set of optical waveguides 111 and optical microring resonators 112 for transmission and delay correction of symbol sequence optical signals. Exemplarily, each channel is associated with multiple optical microring resonators 112, which are arranged in series. The optical receiving component 12 may include a photodiode 121 and an amplifier 122. Each channel is associated with a set of photodiodes 121 and amplifiers 122 for converting the symbol sequence optical signals into differential electrical signals for transmission to a receiving device. The optical microring resonator 112 and amplifier 122 are both connected to a detection controller 13. The detection controller 13 can control the optical microring resonator 112 to resonate with the optical waveguide 111, allowing the optical signal of the symbol sequence 10 transmitted within the optical waveguide 111 to enter the optical microring resonator 112 and then enter the optical waveguide 111. The detection controller 13 is connected to the amplifier 122 to identify the symbol sequence 10, confirm the link training process (if the symbol sequence 10 is identified as the aforementioned training sequence, the link training process is confirmed), and the transmission delay of the symbol sequence 10 within each channel to the receiving device. The detection controller 13 interacts with the receiving device or its PCIe chip via a communication link 133. After completing and confirming channel delay matching, the detection controller 13 sends a confirmation message to the receiving device or its PCIe chip via the communication link 133.

[0071] In some embodiments, the detection controller 13 is used to: determine the maximum transmission delay from the transmission delays of each channel; and correct the inter-channel delay of the PCIe link using the optical microring resonator of each channel according to the difference between the maximum transmission delay and the transmission delay of each channel.

[0072] In some embodiments, the detection controller 13 is used to control the optical microring resonator of each channel to resonate with the difference between the maximum transmission delay and the transmission delay of each channel as a target, and the resonant optical microring resonator is used to continue to transmit the training sequence of the corresponding channel after a specific delay.

[0073] In some embodiments, the detection controller 13 is further configured to: detect the arrival time of subsequent training sequences transmitted between the channels, and determine the maximum difference in transmission delays of the channels; if the maximum difference in transmission delays of the channels is less than the rated adjustable delay of a single optical microring resonator, a confirmation message is sent to a receiving device, where the confirmation message is used to indicate that the inter-channel delay correction is complete.

[0074] Figure 6 For Figure 5 The PCIe protocol optical interconnect link receiving end channel delay correction scheme shown in the figure implements the control flow chart of channel delay correction. Figure 6As shown, the control flow may include but is not limited to the following steps.

[0075] In step 601, the PCIe channel enters the link training process, and the transmitting end device sends a TS1 symbol sequence to the receiving end device.

[0076] In step 602, the TS1 symbol sequence 10 arrives at the photodiode 121 and the amplifier 122 in the optical receiving component 12 of the receiving end device and is converted into a differential electrical signal.

[0077] In step 603 , the detection controller 13 detects the differential electrical signal output by the amplifier 122 and records the delay Tn corresponding to each channel according to the arrival time of the symbol sequence 10 of each channel TS1.

[0078] In step 604 , the detection controller 13 compares the delay Tn corresponding to each channel, identifies the maximum delay Tmax and the corresponding channel, and controls the optical microring resonator 112 of each channel in the optical delay component 11 to resonate, taking the difference (Tmax-Tn) between the maximum delay Tmax and the transmission delay Tn corresponding to each channel as the target.

[0079] In step 605, the symbol sequence optical signal entering the optical delay component 11 will first enter the optical microring resonator 112 at the optical microring resonator 112 where the resonance occurs, and then re-enter the optical waveguide 111 after a specific delay TL to continue transmission, completing the inter-channel delay correction.

[0080] In step 606, the detection controller 13 detects the arrival time of the subsequent PCIe symbol sequence. If the maximum difference among all channel delays is less than the rated adjustable delay of the single optical microring resonator 112, the inter-channel delay correction is completed. The inter-channel delay correction completion information is transmitted to the receiving device or the PCIe chip of the receiving device through the communication link 113.

[0081] like Figure 7 As shown in FIG, it is a schematic diagram of an optical transceiver device provided according to an embodiment of the present disclosure, which can realize PCIe protocol optical interconnect link channel delay correction. Figure 7As shown, the optical transceiver 2 may include an optical delay component 21, an optical receiving component 22, and a detection controller 23. Optionally, the optical transceiver 2 may also include an optical transmitting component 24. The optical delay component 21 may be used to delay a first optical signal 201 (e.g., a training optical signal) transmitted from a peer end (e.g., a transmitting end device) by channel to correct for differences in each channel. The optical delay component 21 primarily includes an optical microring resonator for delaying the optical signal and an optical waveguide device for transmitting the optical signal. The optical receiving component 22 may be used to convert the optical signal into an electrical signal. The detection controller 23 may be used to detect the arrival time of the symbol sequence TS1 in each channel of the optical receiving component 22, which identifies the link training process, through a first detection electrical signal 231, and to control the resonance of the optical microring resonator in each channel of the optical delay component 21 through a first control electrical signal 232 to delay the optical signal of the corresponding channel, thereby eliminating delay variations between the channels of the second optical signal 211 after passing through the optical delay component 21. The optical transmitting component 24 may be used to convert an uplink electrical signal 242 into an optical signal 202 and transmit it. The detection controller 23 can interactively communicate with the receiving device or the PCIe chip of the receiving device through the control link 233 to confirm the delay correction information.

[0082] Regarding the optical transceiver device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0083] Figure 8 is a block diagram of a receiving device provided according to an embodiment of the present disclosure. Figure 8 As shown, the receiving end device may include an optical transceiver device 801. The optical transceiver device 801 may be the optical transceiver device shown in any of the above embodiments. The function and structure of the optical transceiver device 801 may refer to the function and structure of the optical transceiver device shown in any of the above embodiments, and will not be repeated here.

[0084] In an exemplary embodiment, the optical transceiver device 801 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the above methods.

[0085] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory including instructions. The instructions can be executed by the optical transceiver device 801 of the receiving device to perform the above method. For example, the non-transitory computer-readable storage medium can be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, optical data storage device, etc.

[0086] In an exemplary embodiment, a program product is further provided, including at least one of a program and an instruction, wherein the at least one of the program and the instruction implements the steps of the above method when executed by a receiving device.

[0087] Figure 9 Schematic diagram of a remote GPU interconnection system provided according to an embodiment of the present disclosure. Figure 9 As shown, the remote GPU interconnection system applies the optical interconnection link channel delay correction method provided by the present disclosure. Among them, the remote GPU interconnection system may include a first server 31 and a second server 32. The main chip of the first server 31 may be a CPU chip 311; the main chip of the second server 32 may be a GPU chip 322; the first server 31 and the second server 32 are interconnected over long distances through a PCIe signal optical interconnection link composed of a first delay matching optical transceiver 312, an optical fiber 331, and a second delay matching optical transceiver 321. The first delay matching optical transceiver 312 and the second delay matching optical transceiver 321 can correct the transmission delay caused by the PCB trace difference between the CPU chip 311 and the GPU chip 322. The optional implementation of the correction method can refer to the optional implementation of the method shown in any of the above embodiments, which will not be repeated here. The functions and structures of the first delay matching optical transceiver 312 and the second delay matching optical transceiver 321 can refer to the functions and structures of the optical transceivers shown in any of the above embodiments, which will not be repeated here. Among them, as Figure 9 As shown, when the first server 31 can serve as both a sending end device and a receiving end device, and the second server 32 can also serve as both a sending end device and a receiving end device, illustratively, when the first server 31 serves as a sending end device, the second server 32 can serve as a receiving end device, and delay correction between optical interconnection link channels can be achieved through the second delay matching optical transceiver 321 in the second server 32. Exemplarily, when the first server 31 serves as a receiving end device, the second server 32 can serve as a sending end device, and delay correction between optical interconnection link channels can be achieved through the first delay matching optical transceiver 312 in the first server 31.

[0088] The embodiment of the present disclosure provides a GPU resource pooling system based on the PCIe protocol, including a first computing device and a second computing device, wherein the first computing device and the second computing device can be optically interconnected via an optical transceiver device and an optical fiber. The function and structure of the optical transceiver device can refer to the function and structure of the optical transceiver device shown in any of the above embodiments, and will not be repeated here. For example, the first computing device can be a GPU server, and the second computing device can be a general server, but is not limited thereto. For example, Figure 10Schematic diagram of a resource pooling system based on the PCIe protocol according to an embodiment of the present disclosure. The resource pooling system based on the PCIe protocol can be a large-scale AI cluster system that applies PCIe protocol optical interconnect link channel delay correction. Figure 10 As shown, the system may include a GPU resource pool 4, a PCIe switch 5, and a general server 6. At least one GPU server 41 ( Figure 10 The GPU chip 411 in the figure (showing four GPU servers, but not limited to these) is connected to the PCIe switch chip 51 via a delay-matching optical transceiver 412, optical fiber 425, a PCIe switch 5 port, and a delay-matching optical transceiver 52, forming a PCIe optical link. The PCIe switch chip 51 is connected to the CPU chip 62 in the general server 6 via a delay-matching optical transceiver 53, optical fiber 526, and a delay-matching optical transceiver 61. The delay-matching optical transceiver can correct for transmission delay differences from the PCB traces at the other end of the link. Optional implementations of this correction method can be found in the optional implementations of the method shown in any of the above embodiments and will not be repeated here. The functions and structures of the delay-matching optical transceiver 412, delay-matching optical transceiver 52, delay-matching optical transceiver 53, and delay-matching optical transceiver 61 can be found in the functions and structures of the optical transceivers shown in any of the above embodiments and will not be repeated here.

[0089] For example, the GPU server 41 can serve as a transmitting device, and the PCIe Switch chip 51 can serve as a receiving device. Delay correction between the optical interconnection link channels between the GPU server 41 and the PCIe Switch chip 51 can be achieved through a delay matching optical transceiver 52 on the PCIe Switch chip 51. The PCIe Switch chip 51 can serve as a transmitting device, and the general server 6 can serve as a receiving device. Delay correction between the optical interconnection link channels between the PCIe Switch chip 51 and the general server 6 can be achieved through a delay matching optical transceiver 61 on the general server 6.

[0090] For example, the general server 6 can serve as a transmitting device, and the PCIe Switch chip 51 can serve as a receiving device. The delay matching optical transceiver 53 on the PCIe Switch chip 51 can be used to implement delay correction between the optical interconnection link channels between the PCIe Switch chip 51 and the general server 6. The PCIe Switch chip 51 can serve as a transmitting device, and the GPU server 41 can serve as a receiving device. The delay matching optical transceiver 412 on the GPU server 41 can be used to implement delay correction between the optical interconnection link channels between the GPU server 41 and the PCIe Switch chip 51.

[0091] In summary, the technical solution of the embodiments of the present disclosure adopts an optical microring resonance delayed optical signal transmission method to correct the PCIe signal transmission delay caused by chip packaging differences and PCB trace length differences in the PCIe optical interconnection link, avoiding the shortcomings of using serpentine winding and other methods on the PCB end to compensate for transmission delay, maximizing the savings in PCB wiring space and improving PCB wiring density.

[0092] An embodiment of the present disclosure further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of any of the above-mentioned embodiments of the method for correcting delay between channels of an optical interconnect link are implemented.

[0093] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.

[0094] The above is a detailed introduction to a target detection method provided by the present disclosure. Specific examples are used herein to illustrate the principles and implementation methods of the present disclosure. The description of the above embodiments is only used to help understand the method of the present disclosure and its core ideas. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present disclosure, several improvements and modifications can be made to the present disclosure, and these improvements and modifications also fall within the scope of protection of the claims of the present disclosure.

Claims

1. A method for correcting delay between channels of an optical interconnection link, characterized in that: include: During PCIe link training, determining the transmission delay of each channel when the training sequence is transmitted between the channels of the PCIe link and reaches the receiving device; Correcting the inter-channel delay of the PCIe link using the optical microring resonators of the channels according to the transmission delays of the channels, including: determining a maximum transmission delay from the transmission delays of the channels; According to the difference between the maximum transmission delay and the transmission delay of each channel, the training sequence of the corresponding channel is continuously transmitted after the characteristic delay through the optical microring resonator corresponding to each channel, so as to correct the inter-channel delay of the PCIe link.

2. The method according to claim 1, characterized in that The determining, based on the training sequences transmitted between the channels of the PCIe link, the transmission delay of each channel when the training sequence reaches the receiving end device, includes: Converting the training sequence optical signal received by the receiving end device into a differential electrical signal; The arrival time of the training sequence of each channel in the differential electrical signal is detected to determine the transmission delay of each channel.

3. The method according to claim 1, characterized in that The correcting the inter-channel delay of the PCIe link using the optical microring resonator of each channel according to the difference between the maximum transmission delay and the transmission delay of each channel includes: Taking the difference between the maximum transmission delay and the transmission delay of each channel as a target, the optical microring resonator of each channel is controlled to resonate, and the resonated optical microring resonator is used to continue transmitting the training sequence of the corresponding channel after a specific delay.

4. The method according to claim 3, characterized in that The method further comprises: detecting arrival times of subsequent training sequences transmitted between the channels, and determining a maximum difference in transmission delays of the channels; If the maximum difference among the transmission delays of the channels is less than the rated adjustable delay of a single optical microring resonator, confirmation information is sent to the receiving device, where the confirmation information is used to indicate that the inter-channel delay correction is completed.

5. The method according to claim 3, characterized in that Each of the channels is associated with a plurality of the optical microring resonators, and the plurality of the optical microring resonators are arranged in series.

6. The method according to claim 5, characterized in that The rated adjustable delay of a single optical microring resonator ranges from 80 to 120 ps.

7. The method according to any one of claims 1 to 6, characterized in that The training sequence includes one or more of the following: TS1 symbol sequence; TS2 symbol sequence; A symbol sequence used to identify a training phase during the PCIe link training process, wherein the symbol sequence is different from the TS1 symbol sequence and the TS2 symbol sequence.

8. The method according to any one of claims 1 to 6, characterized in that The PCIe link training process includes one or more of the following: The initial training process when the PCIe link is first established; The training process of the PCIe channel after exiting the low-power state and re-entering the recovery state.

9. An optical interconnect link channel delay correction device, characterized in that: include: A determination module, configured to determine, during a PCIe link training process, the transmission delay of each channel of the PCIe link when the training sequence is transmitted between the channels, when the training sequence reaches the receiving end device; A correction module is configured to correct the inter-channel delay of the PCIe link using the optical microring resonator of each channel according to the transmission delay of each channel, including: determining a maximum transmission delay from the transmission delays of each channel; According to the difference between the maximum transmission delay and the transmission delay of each channel, the training sequence of the corresponding channel is continuously transmitted after the characteristic delay through the optical microring resonator corresponding to each channel, so as to correct the inter-channel delay of the PCIe link.

10. An optical transceiver device, characterized in that: include: An optical delay component for controlling the delay of the training sequence optical signal transmitted by each channel of the PCIe link; an optical receiving component connected to the optical delay component, the optical receiving component being configured to convert the training sequence optical signal output by the optical delay component into a differential electrical signal; a detection controller, connected to the optical delay component and the optical receiving component, respectively, and configured to detect the arrival time of the training sequence of each channel in the differential electrical signal, determine the transmission delay of each channel, and perform correction processing on the inter-channel delay of the PCIe link using the optical microring resonator of each channel according to the transmission delay of each channel, including: determining a maximum transmission delay from the transmission delays of each channel; According to the difference between the maximum transmission delay and the transmission delay of each channel, the training sequence of the corresponding channel is continuously transmitted after the characteristic delay through the optical microring resonator corresponding to each channel, so as to correct the inter-channel delay of the PCIe link.

11. The optical transceiver device according to claim 10, wherein: The optical delay component includes an optical waveguide of each channel and an optical microring resonator connected to the optical waveguide.

12. The optical transceiver device according to claim 11, characterized in that: Each of the channels is associated with a plurality of the optical microring resonators, and the plurality of the optical microring resonators are arranged in series.

13. The optical transceiver device according to claim 10, wherein: The detection controller is used to: Determining a maximum transmission delay from the transmission delays of the respective channels; According to the difference between the maximum transmission delay and the transmission delay of each channel, the optical microring resonator of each channel is used to correct the inter-channel delay of the PCIe link.

14. The optical transceiver device according to claim 13, wherein: The detection controller is used to: Taking the difference between the maximum transmission delay and the transmission delay of each channel as a target, the optical microring resonator of each channel is controlled to resonate, and the resonated optical microring resonator is used to continue transmitting the training sequence of the corresponding channel after a specific delay.

15. The optical transceiver device according to claim 14, characterized in that: The detection controller is also used for: detecting arrival times of subsequent training sequences transmitted between the channels, and determining a maximum difference in transmission delays of the channels; If the maximum difference among the transmission delays of the channels is smaller than the rated adjustable delay of a single optical microring resonator, confirmation information is sent to a receiving device, where the confirmation information is used to indicate that the inter-channel delay correction is completed.

16. A receiving device, characterized in that: The optical transceiver comprises the optical transceiver according to any one of claims 10 to 15.

17. A storage medium storing instructions, characterized in that: When the instruction is executed on the receiving-end device, the receiving-end device is caused to execute the method according to any one of claims 1 to 8.

18. A program product, comprising at least one of a program and instructions, characterized in that: When at least one of the program and the instruction is executed by the receiving device, the steps of the method according to any one of claims 1 to 8 are implemented.

19. A resource pooling system based on PCIe protocol, characterized in that: The device comprises a first computing device and a second computing device, wherein the first computing device and the second computing device are optically interconnected via the optical transceiver device and the optical fiber according to any one of claims 10 to 15.

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