Detection device

Abstract

A detection device is provided with: a substrate; a plurality of photoelectric conversion elements arranged on the substrate; a plurality of transistors including a semiconductor layer and a gate electrode facing the semiconductor layer, the plurality of transistors being provided corresponding to the plurality of photoelectric conversion elements, respectively; and a first electrode and a second electrode that are provided between the substrate and the photoelectric conversion element in a direction perpendicular to the substrate and face each other with the insulating film interposed therebetween, the first electrode having a plurality of main parts that overlap each of the photoelectric conversion elements and connecting parts that connect adjacent main parts. The second electrode is formed in an island shape in each of the plurality of photoelectric conversion elements, the first electrode is in the same layer as the gate electrode, and the second electrode is in the same layer as the semiconductor layer.

Description

[0001] This application is a divisional application of the invention patent application with a priority date of December 23, 2019, an application date of November 26, 2020, an application number of 2020800880109, and an invention name of "Detection Device". All contents of this application are incorporated herein by reference. Technical Field

[0002] The present invention relates to a detection device. Background Art

[0003] Patent Document 1 describes a detection device (referred to as a photoelectric conversion device in Patent Document 1) that includes multiple photoelectric conversion elements, such as PIN photodiodes, arranged on a substrate. The photoelectric conversion element in Patent Document 1 is driven by a drive circuit comprising three transistors and a capacitor. The signal (charge) generated by the photoelectric conversion device is accumulated in the capacitor. A voltage signal corresponding to the signal accumulated in the capacitor is output from an output transistor.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Laid-Open No. 2013-12696 Summary of the Invention

[0007] Technical problem to be solved by the invention

[0008] The detection device is required to suppress variations in the signal output from the transistor.

[0009] An object of the present invention is to provide a detection device capable of suppressing variations in output signals.

[0010] Solutions for solving technical problems

[0011] A detection device according to one embodiment of the present invention comprises: a substrate; a plurality of photoelectric conversion elements arranged on the substrate; a plurality of transistors including a semiconductor layer and a gate electrode opposite to the semiconductor layer, which are respectively arranged corresponding to the plurality of photoelectric conversion elements; and a first electrode and a second electrode, which are arranged between the substrate and the photoelectric conversion elements in a direction perpendicular to the substrate and opposite to each other via an insulating film, the first electrode having a plurality of main portions respectively overlapping with the photoelectric conversion elements and a connecting portion connecting adjacent main portions, the second electrode being formed in an island shape on each of the plurality of photoelectric conversion elements, the first electrode being on the same layer as the gate electrode, and the second electrode being on the same layer as the semiconductor layer.

[0012] A detection device according to one embodiment of the present invention comprises: a substrate; a plurality of photoelectric conversion elements arranged on the substrate; a plurality of transistors, including a semiconductor layer, a gate electrode opposite to the semiconductor layer, and a source electrode connected to the semiconductor layer, which are respectively arranged corresponding to the plurality of photoelectric conversion elements; and a first electrode and a second electrode, which are arranged between the substrate and the photoelectric conversion elements in a direction perpendicular to the substrate and opposite to each other with an insulating film therebetween, the first electrode having a plurality of main portions respectively overlapping with the photoelectric conversion elements and a connecting portion connecting adjacent main portions, the second electrode being formed in an island shape on each of the plurality of photoelectric conversion elements, the first electrode being on the same layer as the gate electrode, and the second electrode being on the same layer as the source electrode.

[0013] A detection device according to one embodiment of the present invention comprises: a substrate; a plurality of photoelectric conversion elements arranged on the substrate; a plurality of transistors arranged corresponding to the plurality of photoelectric conversion elements, respectively; and a first electrode and a second electrode, which, when viewed from above, are arranged in a region overlapping with the photoelectric conversion elements and the plurality of transistors, and are opposed to each other via an insulating film in a direction perpendicular to the substrate, the first electrode being arranged above the photoelectric conversion element, and the second electrode being arranged above the first electrode via the insulating film. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a cross-sectional view schematically showing a cross-sectional structure of a detection device with an illumination device including the detection device according to the first embodiment.

[0015] Figure 2 It is a plan view showing the detection device according to the first embodiment.

[0016] Figure 3 This is a block diagram showing a configuration example of a detection device according to the first embodiment.

[0017] Figure 4 is a circuit diagram showing a detection element.

[0018] Figure 5 It is a top view showing the detection element.

[0019] Figure 6 It is a top view of the array substrate that constitutes the detection element.

[0020] Figure 7 yes Figure 6 VII-VII' cross-sectional view.

[0021] Figure 8 It is a plan view of an array substrate constituting a detection element according to a second embodiment.

[0022] Figure 9 yes Figure 8 IX-IX' cross-section diagram.

[0023] Figure 10 It is a plan view showing a detection element according to a third embodiment.

[0024] Figure 11 It is a plan view of an array substrate constituting a detection element according to a third embodiment.

[0025] Figure 12 yes Figure 11 XII-XII' cross-section. DETAILED DESCRIPTION

[0026] The methods (embodiments) for implementing the invention are described in detail with reference to the accompanying drawings. The present invention is not limited to the contents described in the following embodiments. In addition, the constituent elements described below include elements that can be easily thought of by those skilled in the art and substantially the same elements. Furthermore, the constituent elements described below can be appropriately combined. It should be noted that the disclosure is only an example, and appropriate changes that maintain the gist of the invention that can be easily thought of by those skilled in the art are of course included in the scope of the present invention. In addition, in order to make the description clearer, the drawings sometimes schematically indicate the width, thickness, shape, etc. of each part compared to the actual method, but this is only an example and does not limit the interpretation of the present invention. In addition, in this specification and the drawings, the same reference numerals are marked for the elements that are the same as those described in the drawings that have already appeared, and detailed descriptions are sometimes appropriately omitted.

[0027] In this specification and claims, when expressing the manner in which another structure is arranged on a certain structure, when simply expressed as "on", unless otherwise specified, it includes both the case in which the other structure is arranged directly above the certain structure in a manner of contact with the certain structure and the case in which the other structure is arranged above the certain structure with another structure further between them.

[0028] (First embodiment)

[0029] Figure 1 1 is a cross-sectional view showing a schematic cross-sectional structure of a detection device with an illumination device having a detection device according to the first embodiment. Figure 1 As shown, the detection device 120 with an illumination device includes a detection device 1, an illumination device 121, an adhesive layer 125, and a cover member 122. In a direction perpendicular to the surface of the detection device 1, the illumination device 121, the detection device 1, the adhesive layer 125, and the cover member 122 are stacked in this order.

[0030] The lighting device 121 has a light irradiation surface 121a for irradiating light, and irradiates light L1 from the light irradiation surface 121a toward the detection device 1. The lighting device 121 is a backlight source. The lighting device 121 may be, for example, a so-called side-light type backlight source having a light guide plate provided at a position corresponding to the detection area AA and a plurality of light sources arranged at one end or both ends of the light guide plate. As the light source, for example, a light emitting diode (LED) emitting light of a prescribed color is used. In addition, the lighting device 121 may also be a so-called directly below type backlight source having a light source (for example, LED) provided directly below the detection area AA. In addition, the lighting device 121 is not limited to a backlight source, and may also be provided on the side or above the detection device 1, and may also irradiate light L1 from the side or above the finger Fg.

[0031] The detection device 1 is arranged to be opposite to the light irradiation surface 121a of the lighting device 121. The light L1 irradiated from the lighting device 121 passes through the detection device 1 and the cover part 122. The detection device 1 can detect the unevenness of the surface of the finger Fg (such as a fingerprint) by detecting the light L2 reflected by the finger Fg. Alternatively, in addition to detecting fingerprints, the detection device 1 can also detect information related to the organism by detecting the light L2 reflected inside the finger Fg. Information related to the organism is, for example, a blood vessel image such as a vein, a pulse, a pulse wave, etc. The color of the light L1 from the lighting device 121 may also be different depending on the detection object.

[0032] The cover member 122 is a member that protects the detection device 1 and the lighting device 121 and covers the detection device 1 and the lighting device 121. The cover member 122 is, for example, a glass substrate. However, the cover member 122 is not limited to a glass substrate and may also be a resin substrate, etc. Alternatively, the cover member 122 may not be provided. In this case, a protective layer such as an insulating film is provided on the surface of the detection device 1, and the finger Fg is in contact with the protective layer of the detection device 1.

[0033] The detection device 120 with an illumination device may also be provided with a display panel instead of the illumination device 121. The display panel may be, for example, an organic EL display panel (OLED: Organic Light Emitting Diode) or an inorganic EL display (micro LED, mini LED). Alternatively, the display panel may be a liquid crystal display panel (LCD: Liquid Crystal Display) using a liquid crystal element as a display element or an electrophoretic display panel (EPD: Electrophoretic Display) using an electrophoretic element as a display element. Even in this case, the display light (light L1) irradiated from the display panel passes through the detection device 1, and based on the light L2 reflected by the finger Fg, the fingerprint of the finger Fg and information related to the biological body can be detected. In addition, the stacking order of the display panel and the detection device 1 may also be reversed. That is, the display panel may also be stacked on the detection device 1.

[0034] Figure 2 FIG. 1 is a top view showing the detection device according to the first embodiment. Figure 2 As shown, the detection device 1 includes an array substrate 2 (substrate 21 ), a sensor unit 10 , a scanning line driving circuit 15 , a signal line selecting circuit 16 , a detection circuit 48 , a control circuit 102 , and a power supply circuit 103 .

[0035] The control substrate 101 is electrically connected to the substrate 21 via the wiring substrate 110. The wiring substrate 110 is, for example, a flexible printed circuit board or a rigid substrate. A detection circuit 48 is provided on the wiring substrate 110. A control circuit 102 and a power supply circuit 103 are provided on the control substrate 101. The control circuit 102 is, for example, an FPGA (Field Programmable Gate Array). The control circuit 102 supplies control signals to the sensor unit 10, the scan line driving circuit 15, and the signal line selecting circuit 16 to control the detection operation of the sensor unit 10. The power supply circuit 103 generates a power supply potential VDD and a reference potential VCOM (refer to Figure 4 ) are supplied to the sensor unit 10, the scan line driver circuit 15, and the signal line selection circuit 16. Furthermore, while this embodiment illustrates a case where the detection circuit 48 is disposed on the wiring substrate 110, this is not limiting. The detection circuit 48 may also be disposed on the substrate 21.

[0036] The substrate 21 has a detection area AA and a peripheral area GA. The detection area AA is the area where the multiple detection elements 3 of the sensor unit 10 are located. The peripheral area GA is the area outside the detection area AA and is not provided with any detection elements 3. Specifically, the peripheral area GA is the area between the outer periphery of the detection area AA and the outer edge of the substrate 21. The scan line drive circuit 15 and the signal line selection circuit 16 are provided in the peripheral area GA.

[0037] The multiple detection elements 3 of the sensor unit 10 are light sensors each having a photoelectric conversion element 30 as a sensor element. The photoelectric conversion element 30 is a photodiode that outputs an electrical signal corresponding to the light irradiated thereon. More specifically, the photoelectric conversion element 30 is a PIN (Positive Intrinsic Negative) photodiode. In addition, the photoelectric conversion element 30 can also be referred to as an OPD (Organic Photo Diode). The detection elements 3 are arranged in a matrix in the detection area AA. The photoelectric conversion elements 30 of the multiple detection elements 3 perform detection based on the gate drive signal (for example, the reset control signal RST, the readout control signal RD) supplied from the scanning line drive circuit 15. The multiple photoelectric conversion elements 30 output the electrical signal corresponding to the light irradiated thereon as a detection signal Vdet to the signal line selection circuit 16. The detection device 1 detects information related to the biological body based on the detection signal Vdet from the multiple photoelectric conversion elements 30.

[0038] The scan line driver circuit 15 and the signal line selection circuit 16 are provided in the peripheral area GA. Specifically, the scan line driver circuit 15 is provided in a region of the peripheral area GA extending along the second direction Dy. The signal line selection circuit 16 is provided in a region of the peripheral area GA extending along the first direction Dx, and is provided between the sensor unit 10 and the detection circuit 48.

[0039] Furthermore, the first direction Dx is a direction within a plane parallel to the substrate 21. The second direction Dy is a direction within a plane parallel to the substrate 21 and is perpendicular to the first direction Dx. Furthermore, the second direction Dy does not necessarily intersect the first direction Dx. Furthermore, the third direction Dz is a direction perpendicular to the first and second directions Dx and is the normal direction to the substrate 21.

[0040] Figure 3 : is a block diagram showing an example of the configuration of the detection device according to the first embodiment. Figure 3 As shown, the detection device 1 further includes a detection control circuit 11 and a detection unit 40. Part or all of the functions of the detection control circuit 11 are included in the control circuit 102. In addition, part or all of the functions of the detection unit 40 other than the detection circuit 48 are included in the control circuit 102.

[0041] The detection control circuit 11 supplies control signals to the scan line driver circuit 15, the signal line selection circuit 16, and the detection unit 40, thereby controlling their operations. The detection control circuit 11 supplies various control signals, such as a start signal STV and a clock signal CK, to the scan line driver circuit 15. Furthermore, the detection control circuit 11 supplies various control signals, such as a selection signal ASW, to the signal line selection circuit 16.

[0042] The scanning line driving circuit 15 drives a plurality of scanning lines (the readout control scanning line GLrd, the reset control scanning line GLrst (see FIG. Figure 4 The scanning line driving circuit 15 selects a plurality of scanning lines sequentially or simultaneously and supplies gate driving signals (e.g., reset control signal RST, readout control signal RD) to the selected scanning lines. Thus, the scanning line driving circuit 15 selects a plurality of photoelectric conversion elements 30 connected to the scanning lines.

[0043] The signal line selection circuit 16 selects a plurality of output signal lines SL in sequence or simultaneously (see Figure 4 ) switching circuit. Signal line selection circuit 16 is, for example, a multiplexer. Based on selection signal ASW supplied from detection control circuit 11, signal line selection circuit 16 connects the selected output signal line SL to detection circuit 48. Thus, signal line selection circuit 16 outputs detection signal Vdet from photoelectric conversion element 30 to detection unit 40.

[0044] The detection unit 40 includes a detection circuit 48, a signal processing circuit 44, a coordinate extraction circuit 45, a storage circuit 46, and a detection timing control circuit 47. The detection timing control circuit 47 controls the detection circuit 48, the signal processing circuit 44, and the coordinate extraction circuit 45 to operate synchronously based on a control signal supplied from the detection control circuit 11.

[0045] Detection circuit 48 is, for example, an analog front end (AFE). Detection circuit 48 is a signal processing circuit that includes at least the functions of detection signal amplifier circuit 42 and A / D converter circuit 43. Detection signal amplifier circuit 42 is a circuit that amplifies detection signal Vdet and is, for example, an integrator circuit. A / D converter circuit 43 converts the analog signal output from detection signal amplifier circuit 42 into a digital signal.

[0046] The signal processing circuit 44 is a logic circuit that detects a predetermined physical quantity input to the sensor unit 10 based on the output signal of the detection circuit 48. When the finger Fg contacts or approaches the detection surface, the signal processing circuit 44 can detect the surface irregularities of the finger Fg or the palm based on the signal from the detection circuit 48. Furthermore, the signal processing circuit 44 can also detect biological information based on the signal from the detection circuit 48. Examples of biological information include a vascular image of the finger Fg or the palm, a pulse wave, a pulse rate, and blood oxygen saturation.

[0047] The storage circuit 46 temporarily stores the signal calculated by the signal processing circuit 44. The storage circuit 46 may be, for example, a RAM (Random Access Memory) or a register circuit.

[0048] The coordinate extraction circuit 45 is a logic circuit that determines the detected coordinates of the concave and convex surfaces of the finger Fg or other object when the signal processing circuit 44 detects contact or proximity with the finger Fg. Furthermore, the coordinate extraction circuit 45 determines the detected coordinates of blood vessels in the finger Fg or palm. The coordinate extraction circuit 45 combines the detection signals Vdet output by the detection elements 3 of the sensor unit 10 to generate two-dimensional information representing the shape of the concave and convex surfaces of the finger Fg or other object. Alternatively, the coordinate extraction circuit 45 may output the detection signal Vdet as the sensor output Vo without calculating the detected coordinates.

[0049] Next, a circuit configuration example of the detection device 1 will be described. Figure 4 FIG. 1 is a circuit diagram showing a detection element. Figure 4 As shown, the detection element 3 includes a photoelectric conversion element 30, a reset transistor Mrst, a readout transistor Mrd, and a source follower transistor Msf. Furthermore, the detection element 3 includes a reset control scan line GLrst and a readout control scan line GLrd as detection drive lines (scan lines), and an output signal line SL as a signal readout wiring.

[0050] In addition, Figure 4 , one detection element 3 is shown, but the reset control scan line GLrst, the readout control scan line GLrd, and the output signal line SL are connected to a plurality of detection elements 3. Specifically, the reset control scan line GLrst and the readout control scan line GLrd are connected in the first direction Dx (refer to FIG. Figure 2 ) and connected to the plurality of detection elements 3 arranged in the first direction Dx. In addition, the output signal line SL extends in the second direction Dy and connected to the plurality of detection elements 3 arranged in the second direction Dy.

[0051] The reset transistor Mrst, readout transistor Mrd, and source follower transistor Msf are provided for each photoelectric conversion element 30. The multiple transistors included in the detection element 3 are each formed of an n-type TFT (Thin Film Transistor). However, this is not limiting; each transistor may also be formed of a p-type TFT.

[0052] A reference potential VCOM is applied to the anode of the photoelectric conversion element 30. The cathode of the photoelectric conversion element 30 is connected to the node N1. The node N1 is connected to the capacitor Cs, the capacitor Cad, one of the source and the drain of the reset transistor Mrst, and the gate of the source follower transistor Msf. In addition, a parasitic capacitor Cp exists in the node N1. One end side of the capacitor Cs and the capacitor Cad is connected to the node N1, and the other end side is connected to the reference potential VCOM. When light is irradiated to the photoelectric conversion element 30, the signal (charge) output from the photoelectric conversion element 30 is accumulated in the capacitor Cs and the capacitor Cad. Here, the capacitor Cs is, for example, an upper electrode 34 and a lower electrode 35 (see Figure 7 ) is formed between the first electrode 81 and the second electrode 82 (see Figure 7 ) forms a capacitance between them.

[0053] The gate of the reset transistor Mrst is connected to the reset control scan line GLrst. A reset potential Vrst is supplied to the other of the source and drain of the reset transistor Mrst. When the reset transistor Mrst is turned on (conductive state) in response to the reset control signal RST, the potential of the node N1 is reset to the reset potential Vrst. The reference potential VCOM is lower than the reset potential Vrst, and the photoelectric conversion element 30 is reverse biased.

[0054] Source follower transistor Msf is connected between a terminal supplied with power supply potential VDD and readout transistor Mrd (node N2). The gate of source follower transistor Msf is connected to node N1. The signal (charge) generated by photoelectric conversion element 30 is supplied to the gate of source follower transistor Msf. Consequently, source follower transistor Msf outputs a signal (voltage) corresponding to the signal (charge) generated in photoelectric conversion element 30 to readout transistor Mrd.

[0055] The readout transistor Mrd is connected between the source of the source follower transistor Msf (node N2) and the output signal line SL (node N3). The gate of the readout transistor Mrd is connected to the readout control scan line GLrd. When the readout transistor Mrd is turned on in response to the readout control signal RD, the signal output from the source follower transistor Msf, that is, the signal voltage corresponding to the signal (charge) generated in the photoelectric conversion element 30, is output to the output signal line SL as the detection signal Vdet.

[0056] In this embodiment, by adding capacitor Cad in addition to capacitor Cs, it is possible to suppress a decrease in the potential of node N1 during the exposure period, between the reset period (the period during which the potential of node N1 is reset to the reset potential Vrst) and the read period (the period during which the read transistor Mrd is turned on). This suppresses variations in the potential of node N1, and consequently, suppresses variations in the signal (voltage) output from source follower transistor Msf.

[0057] In addition, Figure 4 In the example shown, the reset transistor Mrst and the readout transistor Mrd each have a so-called dual-gate structure, consisting of two transistors connected in series. However, this is not limiting. The reset transistor Mrst and the readout transistor Mrd may each have a single-gate structure, or three or more transistors may be connected in series. Furthermore, the circuit of a single detection element 3 is not limited to a configuration consisting of only three transistors: the reset transistor Mrst, the source follower transistor Msf, and the readout transistor Mrd. The detection element 3 may have two transistors or may have four or more transistors.

[0058] Next, the planar structure and cross-sectional structure of the detection element 3 will be described. Figure 5 FIG is a top view showing the detection element. Figure 5 As shown, one detection element 3 is formed in a region surrounded by two reset control scanning lines GLrst and two output signal lines SL.

[0059] The plurality of reset control scan lines GLrst extend in the first direction Dx and are arranged in the second direction Dy. The plurality of output signal lines SL extend in the second direction Dy and are arranged in the first direction Dx.

[0060] The photoelectric conversion element 30 is provided in an area surrounded by two reset control scan lines GLrst adjacent to each other in the second direction Dy and two output signal lines SL adjacent to each other in the first direction Dx. The upper electrode 34 and the lower electrode 35 are opposed to each other in the third direction Dz, with the photoelectric conversion element 30 interposed therebetween. Specifically, the photoelectric conversion element 30 is arranged on the array substrate 2, which is provided with various wirings and various transistors, with the lower electrode 35 interposed therebetween.

[0061] The lower electrode 35 has a larger area than the photoelectric conversion element 30 and the upper electrode 34. The lower electrode 35 is electrically connected to the reset transistor Mrst and the source follower transistor Msf via the contact hole H2 in the portion that does not overlap with the photoelectric conversion element 30 and the upper electrode 34. The upper electrode 34 is provided to cover the photoelectric conversion element 30 and is electrically connected to the photoelectric conversion element 30 via the contact hole H1. The upper electrode 34 is connected to the reference potential supply line via the connection wiring 36, and supplies the reference potential VCOM to the photoelectric conversion element 30. Although not shown in the figure, the reference potential supply line is extended in the second direction Dy, for example, overlapping with the output signal line SL.

[0062] A first electrode 81 and a second electrode 82 are provided in a region overlapping the photoelectric conversion element 30. A capacitor Cad is formed between the first electrode 81 and the second electrode 82. The detailed configurations of the photoelectric conversion element 30, the first electrode 81, and the second electrode 82 will be described later.

[0063] Figure 6 It is a top view of the array substrate that constitutes the detection element. Figure 6 It is a plan view schematically showing a portion of the detection element 3 , that is, a portion above the photoelectric conversion element 30 , with a portion removed.

[0064] like Figure 6 As shown, the detection element 3 also includes a readout control scan line GLrd and two signal lines: a power signal line SLsf and a reset signal line SLrst. The readout control scan line GLrd extends in the first direction Dx and is arranged in a second direction Dy with the reset control scan line GLrst. In one detection element 3, a photoelectric conversion element 30, a plurality of transistors, and a capacitor Cad are provided between the reset control scan line GLrst and the readout control scan line GLrd, which are adjacent in the second direction Dy. In addition, the power signal line SLsf and the reset signal line SLrst each extend in the second direction Dy and are arranged in the first direction Dx with the output signal line SL.

[0065] Figure 5 The photoelectric conversion element 30 shown is arranged on an array substrate 2 provided with various wirings and various transistors, and is arranged to overlap with at least a portion of the various transistors. In addition, it is arranged in an area overlapping with at least a portion of the power signal line SLsf, the reset signal line SLrst and the readout control scan line GLrd.

[0066] like Figure 6As shown, the reset transistor Mrst includes a semiconductor layer 61, a source electrode 62, a drain electrode 63, and a gate electrode 64. One end of the semiconductor layer 61 is connected to the reset signal line SLrst. The other end of the semiconductor layer 61 is connected to the connection wiring SLcn. The portion of the reset signal line SLrst connected to the semiconductor layer 61 functions as the source electrode 62, and the portion of the connection wiring SLcn connected to the semiconductor layer 61 functions as the drain electrode 63. The gate electrode 64 faces the semiconductor layer 61. More specifically, the reset control scan line GLrst is provided with two branch portions that branch in the second direction Dy. The semiconductor layer 61 intersects the two branch portions of the reset control scan line GLrst. The two branch portions are adjacent to each other in the first direction Dx. The portions of the two branch portions of the reset control scan line GLrst that overlap with the semiconductor layer 61 function as the gate electrode 64. The portion of the semiconductor layer 61 that overlaps with the two branch portions of the reset control scan line GLrst forms a channel region.

[0067] The connection wiring SLcn is formed in an inverted L shape and includes a portion extending in the first direction Dx and a portion extending in the second direction Dy. The end portion of the portion extending in the first direction Dx of the connection wiring SLcn is connected to the contact hole H2 (see Figure 5 ) is connected to the cathode (n-type semiconductor layer 33) of the photoelectric conversion element 30. In addition, the reset transistor Mrst is connected to the gate of the source follower transistor Msf via the portion of the connection wiring SLcn extending in the second direction Dy. That is, the connection wiring SLcn is connected to Figure 4 Corresponding to node N1.

[0068] Source-follower transistor Msf includes a semiconductor layer 65, a source electrode 67, a drain electrode 66, and a gate electrode 68. One end of semiconductor layer 65 is connected to power supply signal line SLsf. The other end of semiconductor layer 65 is connected to readout transistor Mrd via connection wiring SLcna. The portion of power supply signal line SLsf connected to semiconductor layer 65 functions as drain electrode 66, and the portion of connection wiring SLcna connected to semiconductor layer 65 functions as source electrode 67.

[0069] One end of the gate electrode 68 is connected to the connection wiring SLcn via a contact hole. The semiconductor layer 65 intersects the gate electrode 68. A channel region is formed in a portion of the semiconductor layer 65 intersecting the gate electrode 68.

[0070] With such a configuration, the cathode (n-type semiconductor layer 33 ) of the photoelectric conversion element 30 is electrically connected to the reset transistor Mrst and the source follower transistor Msf via the connection wiring SLcn.

[0071] The readout transistor Mrd has a semiconductor layer 71, a source electrode 73, a drain electrode 72, and a gate electrode 74. One end of the semiconductor layer 71 is connected to the source follower transistor Msf via the connection wiring SLcna. The other end of the semiconductor layer 71 is connected to the output signal line SL. The portion of the output signal line SL connected to the semiconductor layer 71 functions as the source electrode 73. The portion of the connection wiring SLcna connected to the semiconductor layer 71 functions as the drain electrode 72. Two branches extending in the second direction Dy are connected to the readout control scan line GLrd. The two branches are arranged adjacent to each other in the first direction Dx. The semiconductor layer 71 intersects with the two branches branched from the readout control scan line GLrd. The two branches of the readout control scan line GLrd function as the gate electrodes 74. In such a configuration, the source follower transistor Msf and the readout transistor Mrd are connected to the output signal line SL.

[0072] In a plan view, the first electrode 81 and the second electrode 82 are located in a region that overlaps with the photoelectric conversion element 30 and does not overlap with the reset transistor Mrst, the source follower transistor Msf, and the readout transistor Mrd. The first electrode 81 includes a main portion 81a, a connecting portion 81b, a secondary portion 81c, and a connecting portion 81d. The second electrode 82 includes a main portion 82a, a connecting portion 82b, and a secondary portion 82c. The main portion 81a overlaps with the main portion 82a, the connecting portion 81b overlaps with the connecting portion 82b, and the secondary portion 81c overlaps with the secondary portion 82c.

[0073] The main portion 81a and the main portion 82a are formed to have the largest area of the various portions constituting the first electrode 81 and the second electrode 82, and are provided in the region surrounded by the output signal line SL, the connection wiring SLcn, the source follower transistor Msf, and the readout transistor Mrd. The end of the second electrode 82a on the second direction Dy side of the main portion 82a is connected to the portion of the connection wiring SLcn extending in the first direction Dx via four contact holes H3. Thus, the second electrode 82 is electrically connected to the cathode of the photoelectric conversion element 30, the reset transistor Mrst, and the gate of the source follower transistor Msf via the connection wiring SLcn (node N1).

[0074] The connecting portion 81b and the connecting portion 82b are arranged to intersect the portion of the connecting wiring SLcn extending in the second direction Dy. The connecting portion 81b connects the main portion 81a and the secondary portion 81c, which are adjacent in the first direction Dx. The connecting portion 82b connects the main portion 82a and the secondary portion 82c, which are adjacent in the first direction Dx. The width of the connecting portion 81b and the connecting portion 82b in the second direction Dy is smaller than the width of the main portion 81a and the main portion 82a in the second direction Dy.

[0075] The auxiliary portions 81c and 82c are provided between the reset signal line SLrst and the power signal line SLsf, and are wider in the second direction Dy than the connecting portions 81b and 82b.

[0076] The connecting portion 81d connects the main portion 81a and the auxiliary portion 81c of the detection element 3 adjacent to each other in the first direction Dx. In other words, the first electrode 81 overlaps with the plurality of detection elements 3 arranged in the first direction Dx and extends in the first direction Dx. The first electrode 81 is connected to the reference potential VCOM at an arbitrary position. In addition, the second electrode 82 is provided separately per detection element 3. That is, when viewed from above, the first electrode 81 and the second electrode 82 overlap with the photoelectric conversion element 30. The first electrode 81 has a plurality of main portions 81a that overlap with the photoelectric conversion elements 30, respectively, and a connecting portion 81d that connects the adjacent main portions 81a. In addition, the second electrode 82 is formed in an island shape on each of the plurality of photoelectric conversion elements 30.

[0077] With this configuration, the first electrode 81 and the second electrode 82 form capacitance between the opposing main portions 81a and 82a, respectively. Furthermore, capacitance is also formed between the opposing connecting portions 81b and 82b, and between the opposing auxiliary portions 81c and 82c, resulting in a relatively large capacitance Cad as a whole. However, this is not limiting, and the first electrode 81 and the second electrode 82 may not have the connecting portions 81b and 82b, or the auxiliary portions 81c and 82c.

[0078] Furthermore, the first electrode 81 and the second electrode 82 have chamfered corners 81e and 82e. That is, the ends of the first electrode 81 and the second electrode 82 do not have sharp corners. Therefore, compared to a case where the corners of the first electrode 81 and the second electrode 82 are formed at right angles, the concentration of the electric field at the ends of the first electrode 81 and the second electrode 82 can be suppressed. Consequently, the detection device 1 can suppress the generation of ESD (electrostatic discharge) during the manufacturing process of the array substrate 2.

[0079] also, Figure 5 as well as Figure 6 The planar configuration of the photoelectric conversion element 30, capacitor Cad, and each transistor shown is merely an example and can be modified as appropriate. For example, the configuration of the multiple transistors may also be different. For example, in this embodiment, the semiconductor layer 65 and the semiconductor layer 71 are separately configured, but this is not limiting. The source follower transistor Msf and the readout transistor Mrd may also be formed from a common semiconductor layer.

[0080] In addition, the configuration of the first electrode 81 and the second electrode 82 may be appropriately changed according to the configuration of each transistor. Figure 5 and Figure 6 In the embodiment, the area of the second electrode 82 is set larger than the area of the first electrode 81, and the outer periphery of the second electrode 82 is arranged so as to surround the periphery of the first electrode 81. However, this is not limited to this, and the relationship between the areas of the second electrode 82 and the first electrode 81 may be reversed or the areas may be the same.

[0081] Figure 7 yes Figure 6 VII-VII' cross-section. In addition, Figure 7 , the cross-sectional structure of the reset transistor Mrst among the three transistors included in the detection element 3 is shown, but the cross-sectional structures of the source follower transistor Msf and the read transistor Mrd are also the same as that of the reset transistor Mrst.

[0082] The substrate 21 is an insulating substrate, for example, a glass substrate such as quartz or alkali-free glass. The substrate 21 has a first principal surface S1 and a second principal surface S2 opposite the first principal surface S1. Various transistors including the reset transistor Mrst, various wirings (scanning lines and signal lines), a first electrode 81, a second electrode 82, and an insulating film are provided on the first principal surface S1 of the substrate 21 to form the array substrate 2. The photoelectric conversion element 30 is arranged on the array substrate 2, that is, on the first principal surface S1 side of the substrate 21.

[0083] The undercoat film 22 is provided on the first main surface S1 of the substrate 21. The undercoat film 22, the insulating films 23, 24, 25, and the insulating films 27, 28 are inorganic insulating films such as silicon oxide (SiO2) or silicon nitride (SiN).

[0084] In the cross-sectional structure of the reset transistor Mrst, a semiconductor layer 61 is provided on the undercoat film 22. The semiconductor layer 61 is made of, for example, polysilicon. However, the semiconductor layer 61 is not limited thereto and may also be made of, for example, a microcrystalline oxide semiconductor, an amorphous oxide semiconductor, or low-temperature polysilicon (LTPS).

[0085] The insulating film 23 covers the semiconductor layer 61 and is provided on the primer film 22. The gate electrode 64 is provided on the insulating film 23. In addition, the gate electrode 68 of the source follower transistor Msf is also provided on the insulating film 23 in the same layer as the gate electrode 64. The insulating film 23 is a gate insulating film. As the material of the insulating film 23, TEOS (Tetra Ethyl Ortho Silicate) can be used. The reset control scan line GLrst and the readout control scan line GLrd (see Figure 6) are also provided in the same layer as the gate electrode 64. The insulating film 24 is provided on the insulating film 23 to cover the gate electrodes 64 and 68.

[0086] The reset transistor Mrst has a top gate structure in which the gate electrode 64 is located on the upper side of the semiconductor layer 61 , but can also be a bottom gate structure in which the gate electrode 64 is located on the lower side of the semiconductor layer 61 , or a double gate structure in which the gate electrodes 64 are located on both the upper and lower sides of the semiconductor layer 61 .

[0087] Insulating films 24 and 25 cover gate electrode 64 and are provided on insulating film 23. Source electrode 62 and drain electrode 63 are provided on insulating film 25. Source electrode 62 and drain electrode 63 are connected to semiconductor layer 61 via contact holes penetrating insulating films 23, 24, and 25, respectively. Source electrode 62 and drain electrode 63 are formed of, for example, a stacked film of TiAlTi or TiAl, which is a stacked structure of titanium and aluminum.

[0088] In addition, various signal lines (output signal line SL (see Figure 5 ), power signal line SLsf and reset signal line SLrst) and connection wiring SLcn are provided in the same layer as source electrode 62 and drain electrode 63. Connection wiring SLcn is connected to gate electrode 68 of source follower transistor Msf via a contact hole penetrating insulating films 24 and 25.

[0089] The first electrode 81 and the second electrode 82 forming the capacitor Cad are arranged using two layers in each layer constituting a transistor (for example, a reset transistor Mrst). In the present embodiment, the first electrode 81 and the second electrode 82 are arranged between the substrate 21 and the photoelectric conversion element 30 in the third direction Dz. The second electrode 82 is arranged on the primer film 22 and is opposite to the first electrode 81 across the insulating film 23 in the third direction Dz. The first electrode 81 is in the same layer as the gate electrode 64 and is formed of the same material as the gate electrode 64. The second electrode 82 is in the same layer as the semiconductor layer 61 and is formed of the same material as the semiconductor layer 61. The second electrode 82 has an area larger than the first electrode 81 and extends to a region overlapping with the connection wiring SLcn. The second electrode 82 is connected to the connection wiring SLcn via four contact holes H3 that penetrate the insulating films 23, 24, and 25.

[0090] Since the first electrode 81 and the second electrode 82 are provided in the same layer as the reset transistor Mrst, the manufacturing process is simpler than forming the capacitor Cad in a layer different from the reset transistor Mrst, and the detection device 1 (array substrate 2) can be made thinner.

[0091] Insulating film 26 is provided on insulating film 25, covering various transistors such as reset transistor Mrst and capacitor Cad. Insulating film 26 is an organic insulating film made of an organic material such as photosensitive acrylic. Insulating film 26 is thicker than insulating film 25. Compared to inorganic insulating materials, insulating film 26 has better coverage of height differences and can flatten the height differences formed by various transistors and wiring.

[0092] Next, the cross-sectional structure of the photoelectric conversion element 30 is described. The photoelectric conversion element 30 is provided on the insulating film 26. Specifically, the lower electrode 35 is provided on the insulating film 26 and is electrically connected to the connection wiring SLcn via the contact hole H2. The photoelectric conversion element 30 is connected to the lower electrode 35. The lower electrode 35 can, for example, have a stacked structure of titanium (Ti) and titanium nitride (TiN). The lower electrode 35 is provided between the substrate 21 and the photoelectric conversion element 30. Therefore, the lower electrode 35 functions as a light shielding layer, which can suppress the intrusion of light from the second main surface S2 side of the substrate 21 into the photoelectric conversion element 30.

[0093] Photoelectric conversion element 30 is configured to include semiconductor layers that exhibit a photovoltaic effect. Specifically, the semiconductor layers of photoelectric conversion element 30 include an i-type semiconductor layer 31, a p-type semiconductor layer 32, and an n-type semiconductor layer 33. i-type semiconductor layer 31, p-type semiconductor layer 32, and n-type semiconductor layer 33 are, for example, amorphous silicon (a-Si). The materials of the semiconductor layers are not limited to these and may also be polycrystalline silicon, microcrystalline silicon, or the like.

[0094] The p-type semiconductor layer 32 is formed by doping a-Si with impurities to form a p+ region. The n-type semiconductor layer 33 is formed by doping a-Si with impurities to form an n+ region. The i-type semiconductor layer 31 is, for example, an undoped intrinsic semiconductor and has lower conductivity than the p-type semiconductor layer 32 and the n-type semiconductor layer 33.

[0095] In the direction perpendicular to the surface of substrate 21 (third direction Dz), i-type semiconductor layer 31 is provided between n-type semiconductor layer 33 and p-type semiconductor layer 32. In this embodiment, n-type semiconductor layer 33, i-type semiconductor layer 31, and p-type semiconductor layer 32 are stacked in this order on lower electrode 35.

[0096] Thus, the n-type semiconductor layer 33 of the photoelectric conversion element 30 is electrically connected to the reset transistor Mrst and the source follower transistor Msf via the lower electrode 35 and the connection wiring SLcn.

[0097] Upper electrode 34 is provided on p-type semiconductor layer 32. Upper electrode 34 is made of a light-transmitting conductive material such as ITO (Indium Tin Oxide). Insulating film 27 is provided on insulating film 26, covering photoelectric conversion element 30 and upper electrode 34. Contact hole H1 is provided in the region of insulating film 27 that overlaps with upper electrode 34.

[0098] The connection wiring 36 is provided on the insulating film 27 and is electrically connected to the upper electrode 34 via the contact hole H1. The reference potential VCOM (see FIG. 1 ) is supplied to the p-type semiconductor layer 32 via the connection wiring 36. Figure 4 ).

[0099] The photoelectric conversion element 30 is disposed on the insulating film 26, that is, above the multiple transistors and capacitor Cad. In other words, the first electrode 81 and second electrode 82 that constitute capacitor Cad are less restricted by the placement and shape of the photoelectric conversion element 30. Therefore, they can be formed over a large area, utilizing an area that does not overlap with the multiple transistors. This increases the capacitance of capacitor Cad.

[0100] Insulating film 28 is provided on insulating film 27, covering upper electrode 34 and connection wiring 36. Insulating film 28 serves as a protective layer to prevent moisture from entering photoelectric conversion element 30. Furthermore, insulating film 29 is provided on insulating film 28, covering the plurality of photoelectric conversion elements 30. Insulating film 29 is a hard coating film formed of an organic material. Insulating film 29 flattens the height differences on the surface of insulating film 28 formed by photoelectric conversion elements 30 and connection wiring 36.

[0101] The cover member 122 is provided so as to cover the various transistors and the photoelectric conversion element 30 via the adhesive layer 125. The adhesive layer 125 bonds the insulating film 29 to the cover member 122. The adhesive layer 125 is, for example, a light-transmitting optical clear adhesive sheet (OCA).

[0102] As described above, the detection device 1 of this embodiment includes: a substrate 21; a plurality of photoelectric conversion elements 30 arranged on the substrate 21; a plurality of transistors (source follower transistor Msf, reset transistor Mrst, and readout transistor Mrd) including a semiconductor layer 61 and a gate electrode 64 opposing the semiconductor layer 61, and provided corresponding to the plurality of photoelectric conversion elements 30; and a first electrode 81 and a second electrode 82 provided between the substrate 21 and the photoelectric conversion elements 30 in a direction perpendicular to the substrate 21, opposing each other via the insulating film 23. The first electrode 81 and the gate electrode 64 are in the same layer, and the second electrode 82 is in the same layer as the semiconductor layer 61.

[0103] As a result, a capacitor Cad is formed between the first electrode 81 and the second electrode 82, thereby suppressing the decrease in the potential of the node N1 (the cathode of the photoelectric conversion element 30, the gate of the source follower transistor Msf, and the source or drain of the reset transistor Mrst) during the exposure period. As a result, the detection device 1 can suppress the deviation of the signal output from the source follower transistor Msf. In addition, the first electrode 81 and the second electrode 82 are formed on the same layer as the transistor, so that the detection device 1 (array substrate 2) can be thinned compared to a structure provided on a layer different from the transistor.

[0104] (Second embodiment)

[0105] Figure 8 It is a top view of an array substrate constituting a detection element according to Embodiment 2. In the following description, components identical to those described in the above embodiments are denoted by the same reference numerals, and duplicate descriptions are omitted.

[0106] like Figure 8 As shown, in the detection element 3A of the second embodiment, the configuration of the first electrode 81A and the second electrode 82A constituting the capacitor Cad differs from that of the first embodiment described above. Specifically, the first electrode 81A includes a main portion 81Aa and a connecting portion 81Ab. The main portion 81Aa is provided in the region surrounded by the output signal line SL, the power supply signal line SLsf, the reset control scan line GLrst, the source follower transistor Msf, and the readout transistor Mrd. The connecting portion 81Ab extends in the first direction Dx, intersecting the signal lines, and connects adjacent main portions 81Aa in the first direction Dx.

[0107] The second electrode 82A is provided overlapping the main portion 81Aa of the first electrode 81A. The second electrode 82A also serves as the connection wiring SLcn. That is, one end side of the second electrode 82A in the second direction Dy is connected to the semiconductor layer 61 of the reset transistor Mrst. In addition, one end side of the second electrode 82A in the second direction Dy is connected to the semiconductor layer 61 of the reset transistor Mrst via the contact hole H2 (see Figure 5 ) is electrically connected to the cathode of the photoelectric conversion element 30. Furthermore, the other end side of the second electrode 82A in the second direction Dy is electrically connected to the gate electrode 68 of the source follower transistor Msf.

[0108] In the second embodiment, the first electrode 81A is also connected to the reference potential VCOM. The second electrode 82A functions as the node N1. The first electrode 81A is provided with a chamfered portion 81Ae. Alternatively, the second electrode 82A may also be formed with a chamfered portion.

[0109] Figure 9 yes Figure 8 IX-IX' cross-section diagram. Figure 9 As shown, in the detection device 1A of the second embodiment, the first electrode 81A and the second electrode 82A are opposed to each other via the insulating films 24 and 25. The first electrode 81A is formed in the same layer as the gate electrode 64 and is made of the same material as the gate electrode 64. The second electrode 82A is formed in the same layer as the source electrode 62 and the drain electrode 63 and is made of the same material as the source electrode 62 and the drain electrode 63.

[0110] In this embodiment, the first electrode 81A and the second electrode 82A are also provided in the third direction Dz between the substrate 21 and the photoelectric conversion element 30. In a plan view, the first electrode 81A and the second electrode 82A are provided in a region that does not overlap with the plurality of transistors.

[0111] Furthermore, the second embodiment can also be combined with the configuration of the first embodiment. Figure 9 In the embodiment, the primer film 22 and the insulating film 23 are stacked between the first electrode 81A and the substrate 21, and no electrodes are provided. However, as in the first embodiment, the first electrode 81 can be provided on the same layer as the semiconductor layer 61, facing the first electrode 81A. In this case, in the capacitance Cad, the capacitance formed between the first electrode 81A and the second electrode 82A and the capacitance formed between the first electrode 81A and the first electrode 81 are connected in parallel. Thus, even when the area of the detection element 3A is small, the capacitance Cad can be ensured.

[0112] (Third embodiment)

[0113] Figure 10 FIG is a top view showing a detection element of the third embodiment. Figure 10 As shown in FIG. 1 , the detection element 3B of the third embodiment has a second electrode 82B. Figure 10 In FIG. 8 , the second electrode 82B is indicated by a two-dot chain line for easier viewing of the drawing.

[0114] The second electrode 82B is arranged to overlap with the upper electrode 34, and the capacitor Cad is formed by the opposing second electrode 82B and the upper electrode 34. That is, the upper electrode 34 corresponds to the first electrodes 81 and 81A in the above-mentioned first embodiment and the second embodiment. The upper electrode 34 is connected to the reference potential VCOM in the same manner as the first electrodes 81 and 81A. In addition, the second electrode 82B is formed in a rectangular shape in such a way as to occupy most of the area surrounded by the two adjacent output signal lines SL and the two adjacent reset control scanning lines GLrst. In addition, when viewed from above, the second electrode 82B is formed with an area larger than that of the photoelectric conversion element 30, and is connected to the connection wiring SLcn (refer to Figure 11 )connect.

[0115] Figure 11 FIG. 1 is a top view of an array substrate constituting a detection element according to the third embodiment. Figure 11 In FIG, the positional relationship between the second electrode 82B and the upper electrode 34 is indicated by a two-dot chain line. Figure 11 As shown, the second electrode 82B and the upper electrode 34 are provided in a region overlapping with the source follower transistor Msf, the readout transistor Mrd, and the reset transistor Mrst. In other words, the electrode forming the capacitor Cad is provided on a different layer from the plurality of transistors and is not provided on the array substrate 2 side. The second electrode 82B and the upper electrode 34 are provided separately from each other in each region surrounded by the output signal line SL and the reset control scan line GLrst.

[0116] Figure 12 yes Figure 11 XII-XII' cross-section diagram. Figure 12 As shown, the upper electrode 34 is provided on the photoelectric conversion element 30, and the second electrode 82B is provided on the upper electrode 34 via the insulating film 28. The second electrode 82B extends to a region that does not overlap with the photoelectric conversion element 30 and is connected to the connection wiring SLcn via a contact hole H2A that penetrates the insulating films 27 and 28. The second electrode 82B, like the upper electrode 34, is formed of a light-transmitting conductive material such as ITO.

[0117] The second electrode 82B is located in an area that overlaps with multiple transistors, including the reset transistor Mrst, minimizing the constraints imposed by the multiple transistors and various wiring patterns. Therefore, in this embodiment, the area of the second electrode 82B can be increased compared to the first and second embodiments described above. This allows for a larger capacitor Cad.

[0118] This embodiment can be combined with at least one of the first and second embodiments. That is, a first electrode and a second electrode facing each other with an insulating film interposed therebetween may be provided between the photoelectric conversion element 30 and the substrate 21 and in a region not overlapping with the plurality of transistors.

[0119] While preferred embodiments of the present invention have been described above, the present invention is not limited to such embodiments. The contents disclosed in the embodiments are merely examples, and various changes can be made without departing from the scope of the present invention. Appropriate changes made without departing from the scope of the present invention naturally also fall within the technical scope of the present invention.

[0120] Description of Reference Numerals

[0121] 1. 1A: detection device; 2: array substrate; 3. 3A, 3B: detection element; 10: sensing part; 15: scan line driving circuit; 16: signal line selection circuit; 21: substrate; 22: primer film; 23, 24, 25, 26, 27, 28, 29: insulating film; 30: photoelectric conversion element; 81: first electrode; 82: second electrode; AA: detection area; Cs, Cad: capacitance; Cp: parasitic capacitance; GA: peripheral area; GLrst: reset control scan line; GLrd: readout control scan line; SL: output signal line; SLsf: power supply signal line; SLrst: reset signal line; Mrst: reset transistor; Msf: source follower transistor; Mrd: readout transistor.

Claims

1. A detection device comprising: substrate; a plurality of diodes having optical characteristics, arranged on the substrate; a plurality of transistors including a semiconductor layer and a gate electrode facing the semiconductor layer, wherein the plurality of transistors are respectively provided corresponding to the plurality of diodes having optical characteristics; as well as The first electrode and the second electrode are provided between the substrate and the diode having optical characteristics in a direction perpendicular to the substrate and are opposed to each other with an insulating film interposed therebetween. The first electrode includes: a plurality of main portions overlapping the diodes having optical characteristics; and a connecting portion connecting adjacent main portions. The second electrode is formed in an island shape on each of the plurality of diodes having optical characteristics. The first electrode and the gate electrode are in the same layer, The second electrode is in the same layer as the semiconductor layer, At least one of the first electrode and the second electrode has a chamfered portion having a chamfered corner in a plan view.

2. A detection device comprising: substrate; a plurality of diodes having optical characteristics, arranged on the substrate; a plurality of transistors including a semiconductor layer, a gate electrode opposite to the semiconductor layer, and a source electrode connected to the semiconductor layer, wherein the plurality of transistors are respectively provided corresponding to the plurality of diodes having optical characteristics; as well as The first electrode and the second electrode are provided between the substrate and the diode having optical characteristics in a direction perpendicular to the substrate and are opposed to each other with an insulating film interposed therebetween. The first electrode includes: a plurality of main portions overlapping the diodes having optical characteristics; and a connecting portion connecting adjacent main portions. The second electrode is formed in an island shape on each of the plurality of diodes having optical characteristics. The first electrode and the gate electrode are in the same layer, The second electrode is in the same layer as the source electrode, At least one of the first electrode and the second electrode has a chamfered portion having a chamfered corner in a plan view.

3. The detection device according to claim 1 or 2, wherein: In a plan view, the first electrode and the second electrode are provided in a region that does not overlap with the plurality of transistors. In a plan view, the first electrode and the second electrode overlap with the diode having optical characteristics.

4. The detection device according to claim 1 or 2, wherein: A plurality of diodes having optical characteristics are arranged side by side in a first direction, The connecting portion of the first electrode electrically connects the main portions adjacent to each other in the first direction.

5. A detection device comprising: substrate; a plurality of diodes having optical characteristics, arranged on the substrate; a plurality of transistors, respectively provided corresponding to the plurality of diodes having optical characteristics; as well as The first electrode and the second electrode are provided in a region overlapping with the plurality of diodes having optical characteristics and the plurality of transistors in a plan view, and are opposed to each other with an insulating film interposed therebetween in a direction perpendicular to the substrate. The first electrode is provided on the diode having optical characteristics, The second electrode is provided on the first electrode via the insulating film.

6. The detection device according to claim 5, wherein: The detection device has: an organic insulating film covering the plurality of transistors; and a lower electrode provided between the organic insulating film and the diode having optical characteristics in a direction perpendicular to the substrate and electrically connected to the diode having optical characteristics; The second electrode extends in a region that does not overlap with the diode having optical characteristics, and is electrically connected to the lower electrode via a contact hole penetrating the insulating film.

7. The detection device according to claim 5 or 6, wherein: The detection device includes a plurality of signal lines and a plurality of scanning lines connected to the plurality of transistors. The diode having optical characteristics, the first electrode, and the second electrode are provided in each region surrounded by the plurality of the signal lines and the plurality of the scanning lines.

8. The detection device according to any one of claims 1, 2 and 5, wherein: The first electrode is connected to a reference potential, The second electrode is electrically connected to the transistor and the diode having optical characteristics.

9. The detection device according to any one of claims 1, 2 and 5, wherein: The plurality of transistors include a source follower transistor, a reset transistor, and a readout transistor, The second electrode is electrically connected to one of a source and a drain of the reset transistor and a gate of the source follower transistor.

10. The detection device according to any one of claims 1, 2 and 5, wherein: The diode having optical characteristics includes an n-type semiconductor layer, an i-type semiconductor layer, and a p-type semiconductor layer stacked on the substrate.

11. A detection device comprising: substrate; a plurality of diodes having optical characteristics, arranged on the substrate; a plurality of transistors including a semiconductor layer and a gate electrode facing the semiconductor layer, wherein the plurality of transistors are respectively provided corresponding to the plurality of diodes having optical characteristics; as well as The first electrode and the second electrode are provided between the substrate and the diode having optical characteristics in a direction perpendicular to the substrate and are opposed to each other with an insulating film interposed therebetween. The first electrode includes: a plurality of main portions overlapping the diodes having optical characteristics; and a connecting portion connecting adjacent main portions. The second electrode is formed in an island shape on each of the plurality of diodes having optical characteristics. The first electrode and the gate electrode are in the same layer, The second electrode is in the same layer as the semiconductor layer, A plurality of diodes having optical characteristics are arranged side by side in a first direction, The connecting portion of the first electrode electrically connects the main portions adjacent to each other in the first direction.

12. A detection device comprising: substrate; a plurality of diodes having optical characteristics, arranged on the substrate; a plurality of transistors including a semiconductor layer and a gate electrode facing the semiconductor layer, wherein the plurality of transistors are respectively provided corresponding to the plurality of diodes having optical characteristics; as well as The first electrode and the second electrode are provided between the substrate and the diode having optical characteristics in a direction perpendicular to the substrate and are opposed to each other with an insulating film interposed therebetween. The first electrode includes: a plurality of main portions overlapping the diodes having optical characteristics; and a connecting portion connecting adjacent main portions. The second electrode is formed in an island shape on each of the plurality of diodes having optical characteristics. The first electrode and the gate electrode are in the same layer, The second electrode is in the same layer as the semiconductor layer, The first electrode is connected to a reference potential, The second electrode is electrically connected to the transistor and the diode having optical characteristics.

13. A detection device comprising: substrate; a plurality of diodes having optical characteristics, arranged on the substrate; a plurality of transistors including a semiconductor layer and a gate electrode facing the semiconductor layer, wherein the plurality of transistors are respectively provided corresponding to the plurality of diodes having optical characteristics; as well as The first electrode and the second electrode are provided between the substrate and the diode having optical characteristics in a direction perpendicular to the substrate and are opposed to each other with an insulating film interposed therebetween. The first electrode includes: a plurality of main portions overlapping the diodes having optical characteristics; and a connecting portion connecting adjacent main portions. The second electrode is formed in an island shape on each of the plurality of diodes having optical characteristics. The first electrode and the gate electrode are in the same layer, The second electrode is in the same layer as the semiconductor layer, The plurality of transistors include a source follower transistor, a reset transistor, and a readout transistor, The second electrode is electrically connected to one of a source and a drain of the reset transistor and a gate of the source follower transistor.

14. A detection device comprising: substrate; a plurality of diodes having optical characteristics, arranged on the substrate; a plurality of transistors including a semiconductor layer and a gate electrode facing the semiconductor layer, wherein the plurality of transistors are respectively provided corresponding to the plurality of diodes having optical characteristics; as well as The first electrode and the second electrode are provided between the substrate and the diode having optical characteristics in a direction perpendicular to the substrate and are opposed to each other with an insulating film interposed therebetween. The first electrode includes: a plurality of main portions overlapping the diodes having optical characteristics; and a connecting portion connecting adjacent main portions. The second electrode is formed in an island shape on each of the plurality of diodes having optical characteristics. The first electrode and the gate electrode are in the same layer, The second electrode is in the same layer as the semiconductor layer, The diode having optical characteristics includes an n-type semiconductor layer, an i-type semiconductor layer, and a p-type semiconductor layer stacked on the substrate.

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