Semiconductor device and method for detecting process change

Abstract

The invention relates to a semiconductor device and a method for detecting process changes. A semiconductor device includes: a comparison circuit configured to generate a flag signal by comparing a voltage level of a reference voltage with a voltage level of a process voltage after a process change detection operation is started; and a process information signal generation circuit configured to generate a process information signal indicating a process change based on a count detection signal generated based on the flag signal and based on a timing of a pulse included in the periodic signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2024-0023845 filed on February 19, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The present disclosure relates to a semiconductor system for detecting process variations. Background Art

[0004] As the integration level of semiconductor systems increases, the operating speed of semiconductor systems also continues to increase. As the integration level and speed of semiconductor systems increase, when internal process variations occur, they may cause operational errors in the semiconductor systems. Summary of the Invention

[0005] In an embodiment, a semiconductor device may include: a comparison circuit configured to generate a flag signal by comparing a voltage level of a reference voltage with a voltage level of a process voltage after a process variation detection operation starts; and a process information signal generation circuit configured to generate a process information signal indicating a process variation based on a count detection signal, the count detection signal being generated based on the flag signal and timing of pulses included in a period signal.

[0006] In an embodiment, a semiconductor device may include: a periodic signal generating circuit configured to generate a periodic signal having pulses generated at a timing that varies according to process variations; a count detection signal generating circuit configured to generate a count detection signal by comparing a target count signal with a count signal that counts pulses of the periodic signal; and a process information signal generating circuit configured to generate a process information signal indicating a process variation based on the count detection signal and a flag signal.

[0007] In an embodiment, a semiconductor device may include: a comparison circuit configured to generate a plurality of flag signals in response to detecting a voltage level of a process voltage having a voltage level that varies according to process variations; a count detection signal generation circuit configured to generate a plurality of count detection signals by comparing the count signals with a first target count signal, a second target count signal, a third target count signal, and a fourth target count signal, wherein the count signals count pulses of a periodic signal having a pulse timing that varies according to process variations; and a process information signal generation circuit configured to generate a plurality of process information signals indicating process variations based on the plurality of count detection signals and the plurality of flag signals.

[0008] In an embodiment, a method may include: generating a plurality of flag signals in response to detecting a process voltage that varies according to process variations of a semiconductor device; generating a count signal that counts pulses of a periodic signal having a pulse timing that varies according to the process variations; generating a plurality of count detection signals by comparing the count signal with each of a plurality of target count signals; and generating a process information signal indicating the process variations based on the plurality of count detection signals and the plurality of flag signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram illustrating a semiconductor system according to an embodiment of the present disclosure.

[0010] Figure 2 is a block diagram illustrating a semiconductor device included in a semiconductor system according to an embodiment of the present disclosure.

[0011] Figure 3 is a diagram illustrating a periodic signal generating circuit of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 4 is a diagram illustrating a comparison circuit of a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 5 is a block diagram illustrating a flag signal generating circuit according to an embodiment of the present disclosure.

[0014] Figure 6 is a diagram illustrating a comparison voltage signal generating circuit according to an embodiment of the present disclosure.

[0015] Figure 7 is a voltage diagram illustrating process voltages generated according to process variations and a reference voltage according to an embodiment of the present disclosure.

[0016] Figure 8 is a circuit diagram illustrating a flag signal decoding circuit according to an embodiment of the present disclosure.

[0017] Figure 9 is a table including data output during operation of a flag signal decoding circuit according to an embodiment of the present disclosure.

[0018] Figure 10 is a block diagram illustrating a count detection signal generating circuit according to an embodiment of the present disclosure.

[0019] Figure 11 is a diagram illustrating a count comparison circuit of a count detection signal generating circuit according to an embodiment of the present disclosure.

[0020] Figure 12 is a table including data output during operation of a counting comparator according to an embodiment of the present disclosure.

[0021] Figure 13 is a table of data output during operation of a logic circuit including a counter comparison circuit according to an embodiment of the present disclosure.

[0022] Figure 14 is a circuit diagram illustrating a process information signal generating circuit according to an embodiment of the present disclosure.

[0023] Figure 15 is a table including data output during operation of the process information signal generating circuit according to an embodiment of the present disclosure.

[0024] Figure 16 is a diagram illustrating an embodiment of an electronic system including a semiconductor system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] Methods are needed to detect internal process variations, such as process variations during semiconductor manufacturing or variations due to process variations that degrade performance or semiconductor aging (e.g., due to circuit mismatches), and methods for modifying process variations in semiconductor systems. Typically, process variations can be detected by comparing a voltage that varies according to the process variation with a reference voltage level that remains constant despite the process variation. Methods are needed to accurately detect process variations.

[0026] Terms such as "first" and "second" are used to distinguish various components, but the components are not limited by these terms. For example, a first component can be called a second component, and vice versa.

[0027] When a component is referred to as being “connected” to another component, the components may be directly connected to each other or connected to each other through another component interposed therebetween. When a component is referred to as being “directly connected” to another component, the components are directly connected to each other without another component interposed therebetween.

[0028] "Logic high" and "logic low" are used to describe the logic levels of a signal. A signal at a "logic high" is different from a signal at a "logic low." For example, while a signal at a first voltage corresponds to a signal at a "logic high," a signal at a second voltage may correspond to a signal at a "logic low." Depending on the embodiment, a "logic high" is a voltage that is higher than a "logic low." Depending on the embodiment, the logic levels of a signal may be different or opposite logic levels. For example, a signal at a logic high may be at a logic low in some embodiments, while a signal at a logic low may be at a logic high in some embodiments.

[0029] The present disclosure is described in more detail by way of examples, which are only used to illustrate the present disclosure and are not intended to limit the scope of the present disclosure.

[0030] like Figure 1 As shown, a semiconductor system 1 according to an embodiment of the present disclosure includes a controller 10 and a semiconductor device 20 .

[0031] The controller 10 includes a first control pin 11_1, a second control pin 11_2, and a third control pin 11_3. The semiconductor device 20 includes a first device pin 21_1, a second device pin 21_2, and a third device pin 21_3. A first transmission line L11 is connected between the first control pin 11_1 and the first device pin 21_1. A second transmission line L12 is connected between the second control pin 11_2 and the second device pin 21_2. A third transmission line L13 is connected between the third control pin 11_3 and the third device pin 21_3. The controller 10 transmits a clock signal CLK to the semiconductor device 20 via the first transmission line L11. The controller 10 transmits a process detection enable signal PD_EN to the semiconductor device 20 via the second transmission line L12. The controller 10 receives a process information signal PINF from the semiconductor device 20 via the third transmission line L13. The clock signal CLK is a periodically switching signal that synchronizes the operations of the controller 10 and the semiconductor device 20. The process detection enable signal PD_EN is a signal that is enabled to initiate a process operation. The process information signal PINF, used to indicate process variations, including deviations in process variations, is a signal comprising multiple bits generated based on a periodic signal having pulse generation timing that varies according to process variations. The process information signal PINF is generated after the process inspection operation begins and is based on a voltage level of a process voltage that varies according to process variations.

[0032] The semiconductor device 20 includes a comparison circuit CMP CIR 230 and a process information signal generation circuit PINF GEN 250 .

[0033] When the process detection enable signal PD_EN is enabled, the comparison circuit 230 generates a flag signal based on the voltage levels of the reference voltage and the process voltage after the process variation detection operation starts. After the process variation detection operation starts, the comparison circuit 230 generates a flag signal by comparing the voltage levels of the reference voltage and the process voltage PV.

[0034] After the process variation detection operation starts, the process information signal generation circuit 250 generates the process information signal PINF based on the periodic signal and the flag signal. After the process variation detection operation starts, the process information signal generation circuit 250 generates the process information signal PINF based on the flag signal, which is generated based on the periodic signal having pulse generation timing that varies according to process variation and the voltage level of the process voltage. After the process variation detection operation starts, the process information signal generation circuit 250 generates the process information signal PINF based on the count detection signal, which is generated based on the flag signal and the pulse timing within the periodic signal.

[0035] After the process variation detection operation starts, when the process detection enable signal PD_EN is enabled, the semiconductor device 20 generates a flag signal by comparing a reference voltage with a voltage level of a process voltage having a voltage level that varies according to process variations. After the process variation detection operation starts, the semiconductor device 20 generates a process information signal PINF indicating process variations based on the flag signal and a count detection signal generated based on the timing of pulses of the periodic signal.

[0036] Figure 2 is a block diagram showing an embodiment of a semiconductor device 20. Figure 2 As shown, the semiconductor device 20 includes a control circuit CTR CIR 210 , a period signal generating circuit VCO GEN 220 , a comparison circuit CMP CIR 230 , a count detection signal generating circuit CD GEN 240 , and a process information signal generating circuit PINF GEN 250 .

[0037] The control circuit 210 generates a voltage enable signal VEN, a cycle enable signal OEN, a comparison enable signal SEN, and a count enable signal CEN based on a process detection enable signal PD_EN that is synchronized with the clock signal CLK. The control circuit 210 generates the voltage enable signal VEN, which is enabled at a logic high level when the process detection enable signal PD_EN is enabled in synchronization with the clock signal CLK. For example, when the process detection enable signal PD_EN is enabled at a logic high level, the rising edge of the voltage enable signal VEN occurs in synchronization with the clock signal CLK. The control circuit 210 generates the cycle enable signal OEN, which is enabled at a logic high level when the process detection enable signal PD_EN is enabled in synchronization with the clock signal CLK. For example, when the process detection enable signal PD_EN is enabled at a logic high level, the rising edge of the cycle enable signal OEN occurs in synchronization with the clock signal CLK. The control circuit 210 generates a comparison enable signal SEN, which is enabled at a logic high level at the time when the process detection enable signal PD_EN is enabled in synchronization with the clock signal CLK. For example, at the time when the process detection enable signal PD_EN is enabled at a logic high level, the rising edge of the comparison enable signal SEN occurs in synchronization with the clock signal CLK. The control circuit 210 generates a count enable signal CEN, which is enabled at a logic high level during an interval starting from the time when the process detection enable signal PD_EN is enabled in synchronization with the clock signal CLK. For example, at the time when the process detection enable signal PD_EN is enabled at a logic high level, the rising edge of the count enable signal CEN occurs in synchronization with the clock signal CLK, and the count enable signal CEN maintains a logic high level during the interval. This interval is the time when the count signal ( Figure 10 CNT<1:8> in FIG. 8 is a period of time during which pulses of the periodic signal VCO generated during this interval are counted.

[0038] When the voltage enable signal VEN is enabled, the periodic signal generating circuit 220 supplies the oscillator ROD ( Figure 3 223) provides a first supply voltage ( Figure 3 VSUP1 in) and the second supply voltage ( Figure 3 When the period enable signal OEN is enabled, the period signal generating circuit 220 generates the period signal VCO in the form of a pulse, which is generated from the first supply voltage ( Figure 3 VSUP1 in) and the second supply voltage ( Figure 3 The periodic signal VCO is a signal including pulses generated at timings that vary according to process variations.

[0039] The comparison circuit 230 is based on the reference voltage ( Figure 4 The voltage levels of VREF1, VREF2, VREF3, and VREF4 in FIG. 1 and the process voltage ( Figure 4 When the comparison enable signal SEN is enabled, the comparison circuit 230 generates the flag signal FLAG<1:5> by adjusting the voltage level of the reference voltage ( Figure 4 The voltage levels of VREF1, VREF2, VREF3, and VREF4 in FIG. 1 and the process voltage ( Figure 4 The flag signals FLAG<1:5> are generated by comparing the voltage level of the process voltage PV with the voltage level of the process voltage PV. The flag signals FLAG<1:5> are signals including five (5) bits, but may be generated to include a different number of bits according to embodiments.

[0040] The count detection signal generating circuit CD GEN 240 generates a count detection signal based on the count signal ( Figure 10 The count detection signal generating circuit 240 generates the count detection signal CD<1:5> based on the count of the pulses of the periodic signal VCO and the first target count signal TTF<1:8>, the second target count signal TFF<1:8>, the third target count signal TSS<1:8> and the fourth target count signal TFT<1:8>. The count detection signal generating circuit 240 generates the count detection signal CD<1:5> based on the pulses of the periodic signal VCO when the count enable signal CEN is enabled. Figure 10 The count detection signal CD<1:5> is generated by comparing the first target count signal TTF<1:8>, the second target count signal TFF<1:8>, the third target count signal TSS<1:8>, and the fourth target count signal TFT<1:8>. The count detection signal CD<1:5> is a signal including five (5) bits, but may be generated to include a different number of bits according to embodiments. The count signal ( Figure 10 Each of the first target count signal CNT<1:8>, the second target count signal TFF<1:8>, the third target count signal TSS<1:8> and the fourth target count signal TFT<1:8> is a signal including eight (8) bits, but can be generated to include a different number of bits according to the embodiment.

[0041] The process information signal generation circuit 250 generates a process information signal PINF<1:9> indicating a process variation based on the count detection signals CD<1:5> and the flag signals FLAG<1:5>. The process information signal generation circuit 250 generates the process information signal PINF<1:9> based on a combination of logic levels of the bits of the count detection signals CD<1:5> and the flag signals FLAG<1:5>. The process information signal PINF<1:9> is a signal including nine (9) bits, but may be generated to include a different number of bits depending on the embodiment.

[0042] After the process variation detection operation starts when the process detection enable signal PD_EN is enabled, the semiconductor device 20 compares the reference voltage ( Figure 4 The voltage levels of VREF1, VREF2, VREF3, and VREF4 in FIG. 1 and the process voltage ( Figure 4 After the process variation detection operation starts, the semiconductor device 20 generates the flag signals FLAG<1:5> based on the voltage level of the PV in the periodic signal VCO. The process variation detection operation starts, and the semiconductor device 20 generates the process information signals PINF<1:9> indicating the process variation based on the flag signals FLAG<1:5> and the count detection signals CD<1:5>. The count detection signals CD<1:5> are generated based on the pulse timing of the periodic signal VCO.

[0043] Figure 3 1 is a diagram showing a periodic signal generating circuit 220 included in the semiconductor device 20 according to an embodiment of the present disclosure, for example. Figure 3 As shown, the periodic signal generating circuit 220 includes an enable signal generating circuit 221 and a voltage supply circuit 222 .

[0044] The enable signal generating circuit 221 is composed of an inverter 221 <1> and 221 <2> The enable signal generation circuit 221 generates the inverted enable signal ENB by inverting the voltage enable signal VEN. The enable signal generation circuit 221 generates the enable signal END by inverting the inverted enable signal ENB. When the voltage enable signal VEN is enabled at a logic high level, the enable signal generation circuit 221 generates the inverted enable signal ENB at a logic low level and the enable signal END at a logic high level. When the voltage enable signal VEN is disabled at a logic low level, the enable signal generation circuit 221 generates the inverted enable signal ENB at a logic high level and the enable signal END at a logic low level.

[0045] The voltage supply circuit 222 includes a first supply voltage generating circuit 222_1 , a second supply voltage generating circuit 222_2 , a connecting circuit 222_3 , a charge discharging circuit 222_4 , and an oscillator ROD 223 .

[0046] The first supply voltage generating circuit 222_1 includes a PMOS transistor 222 <1> , which is provided between the power supply voltage VDD and the node nd221 and is turned on when the enable signal END is generated at a logic low level; the PMOS transistor 222 <2> , which is provided between the power supply voltage VDD and the node nd221 and is turned on when the voltage level of the node nd221 is at the voltage level of the ground voltage VSS; the PMOS transistor 222 <3> , which is provided between the power supply voltage VDD and the node nd222 and is turned on when the voltage level of the node nd221 is at the voltage level of the ground voltage VSS; the PMOS transistor 222 <4> , which is provided between the power supply voltage VDD and the node nd222 and is turned on when the enable signal END is generated at a logic low level; and the PMOS transistor 222 <5> , which is provided between the power supply voltage VDD and the node nd223, and is turned on when the voltage level of the node nd221 is at the voltage level of the ground voltage VSS.

[0047] The PMOS transistor 222 of the first supply voltage generating circuit 222_1 <1> and PMOS transistor 222 <4> The PMOS transistor 222 is turned on when the enable signal END is generated at a logic low level. <1> and PMOS transistor 222 <4> When the enable signal END is generated at a logic low level and turned on, the first supply voltage generating circuit 222_1 drives nodes nd221 and nd222 to the voltage level of the power supply voltage VDD. As the charge in node nd221 is discharged, driving node nd221 to the voltage level of the ground voltage VSS, the first supply voltage generating circuit 222_1 drives node nd223 to the voltage level of the power supply voltage VDD. When node nd221 is driven at the voltage level of the ground voltage VSS, the first supply voltage generating circuit 222_1 generates the first supply voltage VSUP1 by driving node nd223 to the voltage level of the power supply voltage VDD.

[0048] When the process variation is low, the PMOS transistor 222 <1> , PMOS transistor 222 <2> , PMOS transistor 222 <3> , PMOS transistor 222 <4> and PMOS transistor 222 <5> When the driving force of the PMOS transistor 222 is reduced, the first supply voltage generating circuit 222_1 generates the first supply voltage VSUP1 at a low voltage level. <1> , PMOS transistor 222 <2> , PMOS transistor 222 <3> , PMOS transistor 222 <4> and PMOS transistor 222 <5> When the driving force increases, the first supply voltage generating circuit 222_1 generates the first supply voltage VSUP1 at a high voltage level.

[0049] The second supply voltage generating circuit 222_2 includes an NMOS transistor 222 <6> , which is provided between the node nd225 and the ground voltage VSS and is turned on when the inverted enable signal ENB is generated at a logic high level; the NMOS transistor 222 <7> , which is provided between the node nd225 and the ground voltage VSS, and is turned on when the voltage level of the node nd225 is the voltage level of the power supply voltage VDD; and the NMOS transistor 222 <8> , which is provided between the node nd226 and the ground voltage VSS, and is turned on when the voltage level of the node nd225 is the voltage level of the power supply voltage VDD.

[0050] When the inverted enable signal ENB is generated at a logic high level, the NMOS transistor 222 of the second supply voltage generating circuit 222_2 <6> When the NMOS transistor 222 <6> When the inverted enable signal ENB is generated at a logic high level and is turned on, the second supply voltage generating circuit 222_2 drives the node nd225 to the voltage level of the ground voltage VSS. When the node nd225 is driven at the voltage level of the power supply voltage VDD, the NMOS transistor 222 of the second supply voltage generating circuit 222_2 <7> and NMOS transistor 222 <8> When the NMOS transistor 222 <8> When node nd225 is driven at the power supply voltage VDD and is turned on, the second supply voltage generating circuit 222_2 drives node nd226 to the ground voltage VSS. When node nd225 is driven at the power supply voltage VDD, the second supply voltage generating circuit 222_2 generates the second supply voltage VSUP2 by driving node nd226 at the ground voltage VSS.

[0051] When the process variation is low, the NMOS transistor 222 <6> , NMOS transistor 222 <7> and NMOS transistor 222 <8> When the driving force of the NMOS transistor 222 is reduced, the second supply voltage generating circuit 222_2 generates the second supply voltage VSUP2 of a high voltage level. <6> , NMOS transistor 222 <7> and NMOS transistor 222 <8> When the driving force increases, the second supply voltage generating circuit 222_2 generates the second supply voltage VSUP2 at a low voltage level.

[0052] The connecting circuit 222_3 includes a switch 222 <9> , the switch 222 <9> The switch 222 is provided between the node nd222 and the node nd225, and when the enable signal END is generated at a logic high level and the inverted enable signal ENB is generated at a logic low level, the switch 222 is <9> is turned on.

[0053] When switch 222 <9> When the enable signal END is generated at a logic high level and the inverted enable signal ENB is generated at a logic low level, the connection circuit 222_3 is turned on and connects the current path of the node nd222 and the node nd225. <9> When the enable signal END is generated at a logic low level and the inverted enable signal ENB is generated at a logic high level, the connection circuit 222_3 blocks the current path between the nodes nd222 and nd225. For example, the current path includes a path or route for current flowing from the power supply voltage VDD through the nodes nd222 and nd225 to the ground voltage VSS.

[0054] The charge discharging circuit 222_4 includes a resistor 222 disposed between a node nd221 and a node nd224. <10> and an NMOS transistor 222 provided between a node nd224 and a ground voltage VSS. <11> , NMOS transistor 222 <11> It is turned on when the enable signal END is generated at a logic high level.

[0055] When the enable signal END is generated at a logic high level, the charge discharging circuit 222_4 discharges the charge of the node nd221 to the ground voltage VSS.

[0056] Oscillator 223 is provided between node nd223 and node nd226 and is supplied with a first supply voltage VSUP1 and a second supply voltage VSUP2. Oscillator 223 generates a periodic signal VCO, which includes pulses that are periodically generated when a period enable signal OEN is enabled at a logic high level. Oscillator 223 can be implemented as a ring oscillator, in which an odd number of inverters are connected in series when the period enable signal OEN is enabled at a logic high level. Oscillator 223 generates a periodic signal VCO having a period or frequency that generates pulses. When process variation is low, oscillator 223 increases the period or frequency of the pulse generation when the first supply voltage VSUP1 is generated at a low level and the second supply voltage VSUP2 is generated at a high level. When process variation is high, oscillator 223 decreases the period or frequency of the pulse generation when the first supply voltage VSUP1 is generated at a high level and the second supply voltage VSUP2 is generated at a low level.

[0057] Figure 4 FIG. 2 is a diagram showing a comparison circuit 230 included in, for example, the semiconductor device 20 according to an embodiment of the present disclosure. Figure 4 As shown, the comparison circuit 230 includes a process voltage generating circuit 231 , a reference voltage generating circuit VREF GEN 232 , and a flag signal generating circuit FLAG GEN 233 .

[0058] The process voltage generating circuit 231 includes a PMOS transistor 231 provided between a power supply voltage VDD and a node nd231. <1> and an NMOS transistor 231 provided between the node nd231 and the ground voltage VSS. <2> When the process voltage PV is driven at the voltage level of the ground voltage VSS, the PMOS transistor 231 <1> When the process voltage PV is driven at the voltage level of the power supply voltage VDD, the NMOS transistor 231 <2> conduction.

[0059] When the PMOS transistor 231 <1> When the process voltage PV is driven at the voltage level of the ground voltage VSS, the process voltage generating circuit 231 can drive the process voltage PV to the voltage level of the power supply voltage VDD. <2> When the process voltage PV is driven at the voltage level of the power supply voltage VDD, the process voltage generating circuit 231 is turned on and may drive the process voltage PV to the voltage level of the ground voltage VSS.

[0060] When the process variation is low, the process voltage generating circuit 231 generates the process voltage PV driven at a low level. When the process variation is high, the process voltage generating circuit 231 generates the process voltage PV driven at a high level.

[0061] The reference voltage generation circuit 232 generates a first reference voltage VREF1, a second reference voltage VREF2, a third reference voltage VREF3, and a fourth reference voltage VREF4 by dividing the power supply voltage VDD through a plurality of resistors. The first reference voltage VREF1, the second reference voltage VREF2, the third reference voltage VREF3, and the fourth reference voltage VREF4 are all generated at a constant voltage level that is not affected by process variations. The first reference voltage VREF1 is generated at a higher voltage level than the second reference voltage VREF2. The second reference voltage VREF2 is generated at a higher voltage level than the third reference voltage VREF3. The third reference voltage VREF3 is generated at a higher voltage level than the fourth reference voltage VREF4.

[0062] When the comparison enable signal SEN is enabled at a logic high level, the flag signal generation circuit 233 generates flag signals FLAG<1:5> by comparing the voltage level of the process voltage PV with the first reference voltage VREF1, the second reference voltage VREF2, the third reference voltage VREF3, and the fourth reference voltage VREF4 based on the voltage level of the process voltage PV. When the comparison enable signal SEN is enabled at a logic high level, the flag signal generation circuit 233 generates flag signals FLAG<1:5> by comparing the voltage level of the process voltage PV with each of the first reference voltage VREF1, the second reference voltage VREF2, the third reference voltage VREF3, and the fourth reference voltage VREF4. When the comparison enable signal SEN is disabled at a logic low level, the flag signal generation circuit 233 generates flag signals FLAG<1:5> with all bits disabled at a logic low level.

[0063] Figure 5 2 is a block diagram showing a flag signal generating circuit 233 included in, for example, the comparison circuit 230 according to an embodiment of the present disclosure. Figure 5 As shown, the flag signal generating circuit 233 includes a comparison voltage signal generating circuit VCMP GEN 310 and a flag signal decoding circuit FLAG DEC CIR 320 .

[0064] The comparison voltage signal generating circuit 310 generates comparison voltage signals VCMP<1:4> based on the voltage level of the process voltage PV and the first reference voltage VREF1, the second reference voltage VREF2, the third reference voltage VREF3, and the fourth reference voltage VREF4 when the comparison enable signal SEN is enabled at a logic high level. The comparison voltage signal generating circuit 310 generates comparison voltage signals VCMP<1:4> by comparing the voltage level of the process voltage PV with the first reference voltage VREF1, the second reference voltage VREF2, the third reference voltage VREF3, and the fourth reference voltage VREF4 when the comparison enable signal SEN is enabled at a logic high level. When the comparison enable signal SEN is disabled at a logic low level, the comparison voltage signal generating circuit 310 generates comparison voltage signals VCMP<1:4> in which all bits are generated at a logic high level. The comparison voltage signals VCMP<1:4> are signals including four (4) bits, but may be generated to include a different number of bits according to embodiments.

[0065] The flag signal decoding circuit 320 generates the flag signal FLAG<1:5> based on the logic level combination of the bits of the comparison voltage signal VCMP<1:4>. The flag signal decoding circuit 320 generates the selectively enabled flag signal FLAG<1:5> by decoding the comparison voltage signal VCMP<1:4>. Figure 9The operation including generating the selectively enabled flag signals FLAG<1:5> based on the logic level combination of the bits of the comparison voltage signals VCMP<1:4> by the flag signal decoding circuit 320 is described in detail.

[0066] Figure 6 1 is a diagram showing a comparison voltage signal generating circuit 310 included in, for example, the flag signal generating circuit 233 according to an embodiment of the present disclosure. Figure 6 As shown, the comparison voltage signal generating circuit 310 includes a comparison signal generating circuit 311 and a comparison voltage signal output circuit 312 .

[0067] The comparison signal generating circuit 311 includes a first comparator 311 <1> , the second comparator 311 <2> , the third comparator 311 <3> and the fourth comparator 311 <4> .

[0068] First comparator 311 <1> The first bit CMP of the comparison signal is generated by comparing the process voltage PV with the first reference voltage VREF1. <1> When the voltage level of the process voltage PV is higher than the voltage level of the first reference voltage VREF1, the first comparator 311 <1> Generates the first bit CMP of the logic high level of the comparison signal <1> When the voltage level of the process voltage PV is equal to or lower than the voltage level of the first reference voltage VREF1, the first comparator 311 <1> Generates the first bit CMP of the logic low level of the comparison signal <1> .

[0069] Second comparator 311 <2> The second bit CMP of the comparison signal is generated by comparing the process voltage PV with the second reference voltage VREF2. <2> When the voltage level of the process voltage PV is higher than the voltage level of the second reference voltage VREF2, the second comparator 311 <2> Generates the second bit CMP of the logic high level of the comparison signal <2> When the voltage level of the process voltage PV is equal to or lower than the voltage level of the second reference voltage VREF2, the second comparator 311 <2> Generates the second bit CMP of the logic low level of the comparison signal <2> .

[0070] The third comparator 311 <3> The third bit CMP of the comparison signal is generated by comparing the process voltage PV with the third reference voltage VREF3. <3> When the voltage level of the process voltage PV is higher than the voltage level of the third reference voltage VREF3, the third comparator 311 <3> Generates the third bit CMP of the comparison signal with a logic high level <3> When the voltage level of the process voltage PV is equal to or lower than the voltage level of the third reference voltage VREF3, the third comparator 311 <3> The third bit CMP that generates the logic low level of the comparison signal <3> .

[0071] Fourth comparator 311 <4> The fourth bit CMP of the comparison signal is generated by comparing the process voltage PV with the fourth reference voltage VREF4. <4> When the voltage level of the process voltage PV is higher than the voltage level of the fourth reference voltage VREF4, the fourth comparator 311 <4> Generates the fourth bit CMP of the comparison signal with a logic high level <4> When the voltage level of the process voltage PV is equal to or lower than the voltage level of the fourth reference voltage VREF4, the fourth comparator 311 <4> Generates the fourth bit CMP of the comparison signal at a logic low level <4> .

[0072] The comparison voltage signal output circuit 312 uses an inverter 312 <1> 、312 <2> 、312 <3> and 312 <4> and NAND gate 312 <5> 、312 <6> 、312 <7> and 312 <8> to achieve.

[0073] When the comparison enable signal SEN is enabled at a logic high level, the inverter 312 <1> AND NAND gate 312 <5> By buffering the first bit CMP of the comparison signal <1> To generate the first bit of the comparison voltage signal VCMP <1> When the comparison enable signal SEN is disabled at a logic low level, the NAND gate 312 <5> Generates the first bit VCMP of the logic high level of the comparison voltage signal <1> .

[0074] When the comparison enable signal SEN is enabled at a logic high level, the inverter 312 <2> AND NAND gate 312 <6> By buffering the second bit CMP of the comparison signal <2> To generate the second bit VCMP of the comparison voltage signal <2> When the comparison enable signal SEN is disabled at a logic low level, the NAND gate 312 <6> Generates the second bit VCMP of the logic high level of the comparison voltage signal <2> .

[0075] When the comparison enable signal SEN is enabled at a logic high level, the inverter 312 <3> AND NAND gate 312 <7> By buffering the third bit CMP of the comparison signal <3> To generate the third bit VCMP of the comparison voltage signal <3> When the comparison enable signal SEN is disabled at a logic low level, the NAND gate 312 <7> Generates the third bit VCMP of the logic high level of the comparison voltage signal <3> .

[0076] When the comparison enable signal SEN is enabled at a logic high level, the inverter 312 <4> AND NAND gate 312 <8> By buffering the fourth bit CMP of the comparison signal <4> To generate the fourth bit VCMP of the comparison voltage signal <4> When the comparison enable signal SEN is disabled at a logic low level, the NAND gate 312 <8> Generates the fourth bit VCMP of the logic high level of the comparison voltage signal <4> .

[0077] Figure 7 FIG. 1 is a voltage diagram showing process voltages and reference voltages generated according to process variations according to an embodiment of the present disclosure. Figure 7 The voltage levels of the process voltage PV and the reference voltages VREF1 , VREF2 , VREF3 , and VREF4 generated according to process variations are described.

[0078] When the process variation is within the first deviation SF, the voltage level of the process voltage PV is higher than the voltage level of the first reference voltage VREF1 .

[0079] When the process variation is at the second deviation TF or the third deviation ST, the voltage level of the process voltage PV is lower than that of the first reference voltage VREF1 and higher than that of the second reference voltage VREF2. The second deviation TF is a process variation that is smaller than the first deviation SF and larger than the third deviation ST. In the example of the second deviation TF, the process voltage PV is generated to have a voltage level lower than that of the process voltage PV when the process variation is at the first deviation SF, and to have a voltage level higher than that of the process voltage PV when the process variation is at the third deviation ST. In the example of the third deviation ST, the process voltage PV is generated to have a voltage level lower than that of the process voltage PV when the process variation is at the second deviation TF, and to have a voltage level higher than that of the process voltage PV when the process variation is at the fourth deviation FF.

[0080] When the process variation is within the first deviation SF, the second deviation TF, or the third deviation ST, the PMOS transistor 231 of the process voltage generating circuit 231 <1> The driving force is greater than that of the NMOS transistor 231 of the process voltage generating circuit 231 <2> driving force.

[0081] When the process variation is at the fourth deviation FF, the fifth deviation TT, or the sixth deviation SS, the voltage level of the process voltage PV is lower than the voltage level of the second reference voltage VREF2 and higher than the voltage level of the third reference voltage VREF3. The fourth deviation FF is a process variation that is smaller than the third deviation ST and larger than the fifth deviation TT. The fifth deviation TT is a process variation that is smaller than the fourth deviation FF and larger than the sixth deviation SS. In the case of the fourth deviation FF, the process voltage PV is generated at a voltage level lower than the voltage level of the process voltage PV when the process variation is at the third deviation ST and higher than the voltage level of the process voltage PV when the process variation is at the fifth deviation TT. In the case of the fifth deviation TT, the process voltage PV is generated at a voltage level lower than the voltage level of the process voltage PV when the process variation is at the fourth deviation FF and higher than the voltage level of the process voltage PV when the process variation is at the sixth deviation SS. In the case of the sixth deviation SS, the process voltage PV is generated at a voltage level lower than the voltage level of the process voltage PV when the process variation is at the fifth deviation TT and higher than the voltage level of the process voltage PV when the process variation is at the seventh deviation FT.

[0082] When the process variation is in the fourth deviation FF, the fifth deviation TT, or the sixth deviation SS, the PMOS transistor 231 of the process voltage generating circuit 231 <1> and NMOS transistor 231 <2> The driving forces are the same or similar.

[0083] When the process variation is at the seventh deviation FT or the eighth deviation TS, the voltage level of the process voltage PV is lower than the voltage level of the third reference voltage VREF3 and higher than the voltage level of the fourth reference voltage VREF4. The seventh deviation FT is a process variation that is smaller than the sixth deviation SS and larger than the eighth deviation TS. The eighth deviation TS is a process variation that is smaller than the seventh deviation SS and larger than the ninth deviation FS. In the example of the seventh deviation FT, the process voltage PV is generated to have a voltage level lower than the voltage level of the process voltage PV when the process variation is at the sixth deviation SS and to have a voltage level higher than the voltage level of the process voltage PV when the process variation is at the eighth deviation TS. In the example of the eighth deviation TS, the process voltage PV is generated to have a voltage level lower than the voltage level of the process voltage PV when the process variation is at the seventh deviation FT and to have a voltage level higher than the voltage level of the process voltage PV when the process variation is at the ninth deviation FS.

[0084] When the process variation is at the ninth deviation FS, the voltage level of the process voltage PV is lower than that of the fourth reference voltage VREF4. In the example of the ninth deviation FS, the process voltage PV is generated to have a voltage level lower than that of the process voltage PV when the process variation is at the eighth deviation TS.

[0085] When the process variation is in the seventh deviation FT, the eighth deviation TS, or the ninth deviation FS, the PMOS transistor 231 of the process voltage generating circuit 231 <1> The driving force of the NMOS transistor 231 is smaller than that of the process voltage generating circuit 231. <2> driving force.

[0086] Figure 8 1 is a circuit diagram showing a flag signal decoding circuit 320 included in, for example, the flag signal generating circuit 233 according to an embodiment of the present disclosure. Figure 8 As shown, the flag signal decoding circuit 320 can use an inverter 320 <1> , 320 <2> , 320 <3> , 320 <4> , 320 <10> , 320 <11> , 320 <12> , 320 <13> and 320 <14> and NAND gate 320 <5> , 320 <6> , 320 <7> , 320 <8> and 320 <9> to achieve.

[0087] Inverter 320 <1> The fourth bit of the comparison voltage signal VCMP <4> Invert and output the result.

[0088] Inverter 320 <2> The third bit of the comparison voltage signal VCMP <3> Invert and output the result.

[0089] Inverter 320 <3> The second bit of the comparison voltage signal VCMP <2> Invert and output the result.

[0090] Inverter 320 <4> The first bit of the comparison voltage signal VCMP <1> Invert and output the result.

[0091] When the fourth bit of the comparison voltage signal VCMP <4> At logic high, inverter 320 <2> The output signal of inverter 320 is at a logic high level. <3> The output signal of the inverter 320 is at a logic high level, and <4> When the output signal of the NAND gate 320 is at a logic high level, <5> and inverter 320 <10> Generates the first bit FLAG of the flag signal of logic high level <1> . NAND gate 320 <5> All other combinations of inputs will result in inverter 320 <10> Generates the first bit FLAG of the logic low level of the flag signal <1> .

[0092] When the inverter 320 <1> The output signal is at a logic high level, and the third bit of the comparison voltage signal VCMP <3> At a logic high level, the second bit of the comparison voltage signal VCMP <2> The first bit VCMP of the comparison voltage signal is at a logic high level. <1> When at logic high, NAND gate 320 <6> and inverter 320 <11> Generates the second bit FLAG of the logic high level of the flag signal <2> . NAND gate 320 <6> All other combinations of inputs will result in inverter 320 <11> Generates the second bit FLAG of the logic low level of the flag signal <2> .

[0093] When the inverter 320 <1> The output signal of inverter 320 is at a logic high level. <2> The output signal is at a logic high level, and the second bit of the comparison voltage signal VCMP <2> The first bit VCMP of the comparison voltage signal is at a logic high level. <1> When at logic high, NAND gate 320 <7> and inverter 320 <12> The third bit FLAG of the logic high level of the flag signal is generated <3> . NAND gate 320 <7> All other combinations of inputs will result in inverter 320 <12> The third bit FLAG generates a logic low level flag signal <3> .

[0094] When the inverter 320 <1> The output signal of inverter 320 is at a logic high level. <2> The output signal of inverter 320 is at a logic high level. <3> The output signal is at a logic high level and the first bit of the comparison voltage signal VCMP <1> When at logic high, NAND gate 320 <8> and inverter 320 <13> The fourth bit FLAG of the logic high level that can generate the flag signal <4> . NAND gate 320 <8> All other combinations of inputs result in inverter 320 <13> The fourth bit FLAG generates a logic low level flag signal <4> .

[0095] When the inverter 320 <1> The output signal of inverter 320 is at a logic high level. <2> The output signal of inverter 320 is at a logic high level. <3> The output signal of the inverter 320 is at a logic high level and <4> When the output signal of the NAND gate 320 is at a logic high level, <9> and inverter 320 <14> The fifth bit FLAG of the logic high level of the flag signal is generated <5> . NAND gate 320 <9> All other combinations of inputs will result in inverter 320 <14> The fifth bit FLAG of the logic low level of the flag signal is generated <5> .

[0096] Figure 9 is included in, for example, Figure 8 The table shows the data output during the operation of the flag signal decoding circuit. Figure 9Operations including generating the selectively enabled flag signals FLAG<1:5> based on the logic level combination of the bits of the comparison voltage signals VCMP<1:4> by the flag signal decoding circuit 320 are described.

[0097] When the first bit of the comparison voltage signal VCMP <1> At the logic high level H, the second bit of the comparison voltage signal VCMP <2> At the logic high level H, the third bit of the comparison voltage signal VCMP <3> The fourth bit VCMP of the comparison voltage signal is at a logic high level H and <4> When at a logic high level H, the flag signal decoding circuit 320 generates bits FLAG<1:5> of the flag signal in which all bits are disabled and set to a logic low level L.

[0098] When the first bit of the comparison voltage signal VCMP <1> At the logic high level H, the second bit of the comparison voltage signal VCMP <2> At logic low level L, the third bit of the comparison voltage signal VCMP <3> The fourth bit VCMP of the comparison voltage signal is at a logic low level L. <4> When the flag signal decoding circuit 320 is at a logic low level L, it generates the first bit FLAG of the flag signal which is enabled to be a logic high level H. <1> , and the second bit FLAG of the flag signal is disabled as logic low level L <2> To the fifth bit FLAG <5> .

[0099] When the first bit of the comparison voltage signal VCMP <1> At the logic low level L, the second bit of the comparison voltage signal VCMP <2> At the logic high level H, the third bit of the comparison voltage signal VCMP <3> The fourth bit VCMP of the comparison voltage signal is at a logic high level H and <4> When the flag signal decoding circuit 320 is at a logic high level H, the flag signal decoding circuit 320 generates the second bit FLAG of the flag signal which is enabled to be a logic high level H. <2> , and the first bit FLAG of the flag signal is disabled as logic low level L <1> And the third bit FLAG <3> To the fifth bit FLAG <5> .

[0100] When the first bit of the comparison voltage signal VCMP <1> At the logic low level L, the second bit of the comparison voltage signal VCMP <2> At logic low level L, the third bit of the comparison voltage signal VCMP <3> The fourth bit VCMP of the comparison voltage signal is at a logic high level H and <4> When the flag signal decoding circuit 320 is at a logic high level H, the flag signal decoding circuit 320 generates the third bit FLAG of the flag signal that is enabled to be a logic high level H. <3> , and the first bit FLAG of the flag signal is disabled as logic low level L <1> , the second bit FLAG <2> 、The fourth bit FLAG <4> And the fifth bit FLAG <5> .

[0101] When the first bit of the comparison voltage signal VCMP <1> At the logic low level L, the second bit of the comparison voltage signal VCMP <2> At logic low level L, the third bit of the comparison voltage signal VCMP <3> The fourth bit VCMP of the comparison voltage signal is at a logic low level L. <4> When the flag signal decoding circuit 320 is at a logic high level H, the flag signal decoding circuit 320 generates the fourth bit FLAG of the flag signal that is enabled to be a logic high level H. <4> , and the first bit FLAG of the flag signal is disabled as logic low level L <1> , the second bit FLAG <2> 、The third bit FLAG <3> And the fifth bit FLAG <5> .

[0102] When the first bit of the comparison voltage signal VCMP <1> At the logic low level L, the second bit of the comparison voltage signal VCMP <2> The third bit VCMP of the comparison voltage signal has a logic low level L. <3> The fourth bit VCMP of the comparison voltage signal is at a logic low level L. <4> When the flag signal decoding circuit 320 is at a logic low level L, it generates the fifth bit FLAG of the flag signal which is enabled to be a logic high level H. <5> , and the first bit FLAG of the flag signal is disabled as logic low level L <1> To the fourth bit FLAG <4> .

[0103] Figure 10 1 is a block diagram showing a count detection signal generating circuit 240 included in, for example, the semiconductor device 20 according to an embodiment of the present disclosure. Figure 10 As shown, the count detection signal generating circuit 240 includes a counting circuit CNT CIR 241 and a counting comparison circuit CNT CMP CIR 242 .

[0104] The counting circuit 241 generates a counting signal CNT<1:8> including bits that are sequentially counted based on the counting enable signal CEN and the periodic signal VCO. The counting circuit 241 generates the counting signal CNT<1:8> including bits that are sequentially counted each time a pulse of the periodic signal VCO is input during an interval in which the counting enable signal CEN is enabled.

[0105] For example, when a pulse of the periodic signal VCO is input for the first time during an interval in which the count enable signal CEN is enabled, the counting circuit 241 generates a first bit CNT of the counting signal. <1> When the pulse of the periodic signal VCO is input for the second time during the interval in which the count enable signal CEN is enabled, the counting circuit 241 generates the first bit CNT of the counting signal. <1> and the second bit CNT of the counting signal <2> The first bit transitions from a logic high level to a logic low level, and the second bit transitions from a logic low level to a logic high level. The eight bits CNT<1:8> of the count signal are generated in a similar manner as each subsequent pulse of the periodic signal VCO is input to the count circuit 241.

[0106] The count comparison circuit 242 generates the count detection signal CD<1:5> based on the flag signal FLAG<2:4>, the count signal CNT<1:8>, the first target count signal TTF<1:8>, the second target count signal TFF<1:8>, the third target count signal TSS<1:8> and the fourth target count signal TFT<1:8>. <2> When enabled, the counting comparison circuit 242 generates the first bit CD of the counting detection signal by comparing the counting signal CNT<1:8> with the first target counting signal TTF<1:8>. <1> When the third bit of the flag signal FLAG <3> When enabled, the count comparison circuit 242 generates the second to fourth bits CD<2:4> of the count detection signal by comparing the count signal CNT<1:8>, the second target count signal TFF<1:8> and the third target count signal TSS<1:8>. <4> When enabled, the counting comparison circuit 242 generates the fifth bit CD of the counting detection signal by comparing the counting signal CNT<1:8> with the fourth target counting signal TFT<1:8>. <5> .

[0107] Figure 11 1 is a diagram showing a count comparison circuit 242 included in the count detection signal generating circuit 240 according to an embodiment of the present disclosure. Figure 11 As shown, the counting and comparing circuit 242 includes a first counting and comparing circuit 1 st COM 242_1, second counter comparator 2 nd COM 242_2, third counter comparator 3 rd COM 242_3, fourth counter comparator 4 th COM 242_4 , a first logic circuit 242_5 , a second logic circuit 242_6 , and a third logic circuit 242_7 .

[0108] The first counting comparator 242_1 generates a first bit IC of the internal counting signal by comparing the counting signal CNT<1:8> with the first target counting signal TTF<1:8>. <1> When the counting signal CNT<1:8> has a bit-by-bit value higher than the first target counting signal TTF<1:8>, the first counting comparator 242_1 generates the first bit IC of the internal counting signal enabled to a logic high level. <1> As reference Figure 7 As described above, the first target count signal TTF<1:8> is a signal having a logic level combination indicating when the process variation is within the first deviation SF.

[0109] The second counting comparator 242_2 generates a second bit IC of the internal counting signal by comparing the counting signal CNT<1:8> with the second target counting signal TFF<1:8>. <2> When the counting signal CNT<1:8> has a higher bit-by-bit value than the second target counting signal TFF<1:8>, the second counting comparator 242_2 generates the second bit IC of the internal counting signal enabled to be a logic high level. <2> As reference Figure 7 As described above, the second target count signals TFF<1:8> are signals having a combination of logic levels indicating when the process variation is at one of the second deviation TF and the third deviation ST.

[0110] The third counting comparator 242_3 generates a third bit IC of the internal counting signal by comparing the counting signal CNT<1:8> with the third target counting signal TSS<1:8>. <3> When the counting signal CNT<1:8> has a higher bit-by-bit value than the third target counting signal TSS<1:8>, the third counting comparator 242_3 generates a third bit IC of the internal counting signal enabled to a logic high level. <3> As reference Figure 7 As described above, the third target count signal TSS<1:8> is a signal having a logic level combination indicating when the process variation is in one of the fourth deviation FF, the fifth deviation TT, and the sixth deviation SS.

[0111] The fourth counting comparator 242_4 generates a fourth bit IC of the internal counting signal by comparing the counting signal CNT<1:8> with the fourth target counting signal TFT<1:8>. <4> When the counting signal CNT<1:8> has a bit-by-bit value higher than the fourth target counting signal TFT<1:8>, the fourth counting comparator 242_4 generates a fourth bit IC of the internal counting signal enabled to a logic high level. <4> As reference Figure 7 As described above, the fourth target count signal TFT<1:8> is a signal having a logic level combination indicating when the process variation is in one of the seventh deviation FT, the eighth deviation TS, and the ninth deviation FS.

[0112] The first logic circuit 242_5 uses a NAND gate 242 <51> and inverter 242 <52> to achieve.

[0113] When the second bit of the flag signal FLAG <2> When enabled to a logic high level, the first logic circuit 242_5 buffers the first bit IC of the internal counting signal. <1> To generate the first bit CD of the counting detection signal <1> When the second bit of the flag signal FLAG <2> The first bit of the internal counting signal is generated at a logic high level IC <1> When the first logic circuit 242_5 generates the first bit CD of the count detection signal enabled to be a logic high level, <1> When the second bit of the flag signal FLAG <2> When the first logic circuit 242_5 generates the first bit CD of the count detection signal which is prohibited to be a logic low level, <1> .

[0114] The second logic circuit 242_6 uses a NAND gate 242 <61> , 242 <62> , 242 <63> , 242 <64> , XOR gate 242 <65> , NOR gate 242 <66> and inverter 242 <67> , 242 <68> , 242 <69> and 242 <70> to achieve.

[0115] When the third bit of the flag signal FLAG <3> The third bit of the internal counting signal IC is enabled to a logic high level <3> When enabled to a logic high level, the second logic circuit 242_6 buffers the second bit IC of the internal counting signal. <2> To generate the second bit CD of the count detection signal <2> When the third bit of the flag signal FLAG <3> The third bit of the internal counting signal IC is generated at a logic high level <3> The second bit of the internal counting signal IC is generated at a logic high level <2> When the second logic circuit 242_6 generates the second bit CD of the count detection signal enabled to be a logic high level, <2> When the third bit of the flag signal FLAG <3> When the second logic circuit 242_6 generates the second bit CD of the count detection signal which is prohibited to be at a logic low level, <2> .

[0116] When the third bit of the flag signal FLAG <3> When the second logic circuit 242_6 is enabled to a logic high level, the second logic circuit 242_6 generates a counter signal based on the second bit IC of the internal counting signal. <2> and the third bit of the internal counting signal IC <3> The logic level generates the third bit CD of the count detection signal <3> When the third bit of the flag signal FLAG <3> is generated as a logic high level, the third bit of the internal count signal IC <3> is generated as a logic high level and the second bit of the internal counting signal IC <2> When the count detection signal is generated as a logic low level, the second logic circuit 242_6 generates the third bit CD of the count detection signal which is enabled as a logic high level. <3> When the third bit of the flag signal FLAG <3> When the third bit CD of the count detection signal is disabled and is at a logic low level, the second logic circuit 242_6 generates the third bit CD of the count detection signal which is disabled and is at a logic low level. <3> .

[0117] When the third bit of the flag signal FLAG <3> The third bit of the internal counting signal IC is enabled to a logic high level <3> When the second logic circuit 242_6 is disabled and is at a logic low level, the second logic circuit 242_6 controls the second bit IC of the internal counting signal. <2> The fourth bit CD of the count detection signal is generated by inverting and buffering <4> When the third bit of the flag signal FLAG <3> is generated as a logic high level, the third bit of the internal count signal IC <3> is generated as a logic low level, and the second bit of the internal counting signal IC <2> When the fourth bit CD of the count detection signal is enabled to be a logic high level, the second logic circuit 242_6 generates the fourth bit CD of the count detection signal. <4> When the third bit of the flag signal FLAG <3> When the fourth bit CD of the count detection signal is disabled and is at a logic low level, the second logic circuit 242_6 generates the fourth bit CD of the count detection signal which is disabled and is at a logic low level. <4> .

[0118] The third logic circuit 242_7 uses a NAND gate 242 <71> and inverter 242 <72> to achieve.

[0119] When the fourth bit of the flag signal FLAG <4> When the logic level is high, the third logic circuit 242_7 buffers the fourth bit IC of the internal counting signal. <4> To generate the fifth bit CD of the count detection signal <5> When the fourth bit of the flag signal FLAG <4> The fourth bit of the internal counting signal IC is generated as a logic high level <4> When the fifth bit CD of the count detection signal is enabled to be a logic high level, the third logic circuit 242_7 generates the fifth bit CD of the count detection signal. <5> When the fourth bit of the flag signal FLAG <4> When the third logic circuit 242_7 is disabled as a logic low level, the fifth bit CD of the count detection signal is disabled as a logic low level. <5> .

[0120] Figure 12 This includes, for example, Figure 11 The table shows the data output during the operation of the counting comparators 242_1, 242_2, 242_3 and 242_4. Figure 12 Described is an operation of generating the internal counting signal IC<1:4> by the counting comparators 242_1 , 242_2 , 242_3 , and 242_4 by comparing the counting signal CNT<1:8> with the first, second, third, and fourth target counting signals TTF<1:8>, TFF<1:8>, TSS<1:8>, and TFT<1:8>.

[0121] In an example when the process variation is in the first deviation SF, the counting signal CNT<1:8> has a higher bit-by-bit value than the first target counting signal TTF<1:8>.

[0122] The first counting comparator 242_1 generates a first bit IC of the internal counting signal enabled to be a logic high level H by comparing the counting signal CNT<1:8> with the first target counting signal TTF<1:8>. <1> , resulting in that when the process variation is in the first deviation SF, the counting signal CNT<1:8> has a higher bit-by-bit value than the first target counting signal TTF<1:8>.

[0123] In an example where the process variation is in one of the second deviation TF and the third deviation ST, the count signal CNT<1:8> has a higher bit-by-bit value than the second target count signal TFF<1:8>.

[0124] The second counting comparator 242_2 generates a second bit IC of the internal counting signal enabled to be a logic high level H by comparing the counting signal CNT<1:8> with the second target counting signal TFF<1:8>. <2> , resulting in that when the process variation is at one of the second deviation TF and the third deviation ST, the count signal CNT<1:8> has a bit-by-bit value higher than the second target count signal TFF<1:8>. The third counting comparator 242_3 generates a third bit IC of the internal count signal enabled to be a logic high level H by comparing the count signal CNT<1:8> with the third target count signal TSS<1:8>. <3> , resulting in that when the process variation is at one of the second deviation TF and the third deviation ST, the count signal CNT<1:8> has a higher bit-by-bit value than the third target count signal TSS<1:8>.

[0125] In an example where the process variation is one of the fourth deviation FF, the fifth deviation TT, and the sixth deviation SS, the count signal CNT<1:8> has a lower bit-by-bit value than the second target count signal TFF<1:8> and has a higher bit-by-bit value than the third target count signal TSS<1:8>.

[0126] The second counting comparator 242_2 generates a second bit IC of the internal counting signal that is disabled to a logic low level L by comparing the counting signal CNT<1:8> with the second target counting signal TFF<1:8>. <2> , resulting in that when the process variation is at one of the fourth deviation FF, the fifth deviation TT, and the sixth deviation SS, the count signal CNT<1:8> has a bit-by-bit value lower than the second target count signal TFF<1:8>. The third counting comparator 242_3 generates a third bit IC of the internal count signal enabled to be a logic high level H by comparing the count signal CNT<1:8> with the third target count signal TSS<1:8>. <3> , resulting in that when the process variation is in one of the fourth deviation FF, the fifth deviation TT, and the sixth deviation SS, the counting signal CNT<1:8> has a higher bit-by-bit value than the third target counting signal TSS<1:8>.

[0127] In an example where the process variation is one of the seventh deviation FT and the eighth deviation TS, the count signal CNT<1:8> has a lower bit-by-bit value than the third target count signal TSS<1:8>.

[0128] The second counting comparator 242_2 generates a second bit IC of the internal counting signal that is disabled to a logic low level L by comparing the counting signal CNT<1:8> with the second target counting signal TFF<1:8>. <2> , resulting in that when the process variation is at one of the seventh deviation FT and the eighth deviation TS, the count signal CNT<1:8> has a bit-by-bit value lower than the second target count signal TFF<1:8>. The third counting comparator 242_3 generates a third bit IC of the internal count signal that is disabled to a logic low level L by comparing the count signal CNT<1:8> with the third target count signal TSS<1:8>. <3> , resulting in that when the process variation is in one of the seventh deviation FT and the eighth deviation TS, the count signal CNT<1:8> has a lower bit-by-bit value than the third target count signal TSS<1:8>.

[0129] In an example where the process variation is at a ninth deviation FS, the count signal CNT<1:8> has a higher bit-by-bit value than the fourth target count signal TFT<1:8>.

[0130] The fourth counting comparator 242_4 generates a fourth bit IC of the internal counting signal enabled to be a logic high level H by comparing the counting signal CNT<1:8> with the fourth target counting signal TFT<1:8>. <4> , resulting in that when the process variation is at the ninth deviation FS, the counting signal CNT<1:8> has a higher bit-by-bit value than the first target counting signal TTF<1:8>.

[0131] Figure 13 This includes, for example, Figure 11 The table shows the data output during the operation of the logic circuits 242_5, 242_6 and 242_7. Figure 13 An operation of generating the count detection signals CD<1:5> based on the logic levels of the flag signals FLAG<2:4> and the internal count signals IC<1:4> by the logic circuits 242_5 , 242_6 , and 242_7 is described.

[0132] When the second bit of the flag signal FLAG <2> is enabled as logic high H and the first bit of the internal counting signal IC <1> When the first logic circuit 242_5 generates the first bit CD of the count detection signal at the logic high level H, <1> .

[0133] When the third bit of the flag signal FLAG <3> The third bit of the internal counting signal IC is generated as a logic high level H. <3> The second bit of the internal counting signal IC is generated as a logic high level H <2> When the second logic circuit 242_6 generates the second bit CD of the count detection signal at the logic high level H, <2> .

[0134] When the third bit of the flag signal FLAG <3> The third bit of the internal counting signal IC is generated as a logic high level H. <3> is generated as a logic high level H, and the second bit of the internal counting signal IC <2> When the second logic circuit 242_6 generates the second bit CD of the count detection signal at a logic high level H, the second logic circuit 242_6 generates the second bit CD of the count detection signal at a logic high level H. <3> .

[0135] When the third bit of the flag signal FLAG <3> The third bit of the internal counting signal IC is generated as a logic high level H. <3> is generated as a logic low level L, and the second bit of the internal counting signal IC <2> When the fourth bit CD of the count detection signal is generated as a logic low level L, the second logic circuit 242_6 generates a fourth bit CD of the count detection signal at a logic high level H. <4> .

[0136] When the fourth bit of the flag signal FLAG <4> The fourth bit of the internal counting signal IC is generated as a logic high level H and <4> When the logic high level H is generated, the third logic circuit 242_7 generates the fifth bit CD of the count detection signal at the logic high level H. <5> .

[0137] Figure 14 FIG. 2 is a circuit diagram showing a process information signal generating circuit 250 included in, for example, a semiconductor device 20 according to an embodiment of the present disclosure. Figure 14 As shown, the process information signal generating circuit 250 includes a first process information signal generating circuit 251, a second process information signal generating circuit 252, a third process information signal generating circuit 253, a fourth process information signal generating circuit 254, a fifth process information signal generating circuit 255, a sixth process information signal generating circuit 256, a seventh process information signal generating circuit 257, an eighth process information signal generating circuit 258 and a ninth process information signal generating circuit 259.

[0138] The first process information signal generating circuit 251 is composed of an inverter 251 <1> and 251 <2> The first process information signal generating circuit 251 buffers the first bit FLAG of the flag signal <1> To generate the first bit PINF of the process information signal <1> When the first bit of the flag signal FLAG <1> When the first process information signal generating circuit 251 is at a logic high level, it generates the first bit PINF of the process information signal at a logic high level. <1> When the first bit of the flag signal FLAG <1> When the first process information signal generating circuit 251 is at a logic low level, it generates the first bit PINF of the process information signal at a logic low level. <1> .

[0139] The second process information signal generating circuit 252 is composed of a NAND gate 252 <1> and inverter 252 <2> When the second bit of the flag signal FLAG <2> When the second process information signal generating circuit 252 is at a logic high level, the first bit CD of the buffered count detection signal <1> To generate the second bit PINF of the process information signal <2> When the second bit of the flag signal FLAG <2> The first bit CD of the counting detection signal is at a logic high level. <1> When the second process information signal generating circuit 252 is at a logic high level, it generates the second bit PINF of the process information signal at a logic high level. <2> When the second bit of the flag signal FLAG <2> When the second process information signal generating circuit 252 is at a logic low level, it generates the second bit PINF of the process information signal at a logic low level. <2> .

[0140] The third process information signal generating circuit 253 is composed of an inverter 253 <1> and 253 <2> and NAND gate 253 <3> When the second bit of the flag signal FLAG <2> When the third process information signal generating circuit 253 is at a logic high level, it inverts and buffers the first bit CD of the count detection signal. <1> To generate the third bit PINF of the process information signal <3> When the second bit of the flag signal FLAG <2> The first bit CD of the counting detection signal is at a logic high level. <1> When the third process information signal generating circuit 253 is at a logic low level, it generates a third bit PINF of the process information signal at a logic high level. <3> When the second bit of the flag signal FLAG <2> When the third process information signal generating circuit 253 is at a logic low level, it generates a third bit PINF of the process information signal at a logic low level. <3> .

[0141] The fourth process information signal generating circuit 254 is composed of an inverter 254 <1> and 254 <2> The fourth process information signal generating circuit 254 detects the second bit CD of the buffer count signal by <2> To generate the fourth bit PINF of the process information signal <4> When the second bit of the counting detection signal CD <2> When the fourth process information signal generating circuit 254 is at a logic high level, it generates a fourth bit PINF of the process information signal at a logic high level. <4> When the second bit of the counting detection signal CD <2> When the fourth process information signal generating circuit 254 is at a logic low level, it generates the fourth bit PINF of the process information signal at a logic low level. <4> .

[0142] The fifth process information signal generating circuit 255 is composed of an inverter 255 <1> and 255 <2> The fifth process information signal generating circuit 255 detects the third bit CD of the buffer count signal by <3> To generate the fifth bit PINF of the process information signal <5> When the third bit of the counting detection signal CD <3> When the fifth process information signal generating circuit 255 is at a logic high level, it generates the fifth bit PINF of the process information signal at a logic high level. <5> When the third bit of the counting detection signal CD <3> When the fifth process information signal generating circuit 254 is at a logic low level, it generates the fifth bit PINF of the process information signal at a logic low level. <5> .

[0143] The sixth process information signal generating circuit 256 is composed of an inverter 256 <1> and 256 <2> The sixth process information signal generating circuit 256 detects the fourth bit CD of the buffer count signal by <4> To generate the sixth bit PINF of the process information signal <6> . In the fourth bit of the counting detection signal CD <4> When the sixth process information signal generating circuit 256 is at a logic high level, it generates the sixth bit PINF of the process information signal at a logic high level. <6> . In the fourth bit of the counting detection signal CD <4> When the sixth process information signal generating circuit 256 is at a logic low level, the sixth bit PINF of the process information signal is generated at a logic low level. <6> .

[0144] The seventh process information signal generating circuit 257 is composed of a NAND gate 257 <1> and inverter 257 <2> In the fourth bit of the flag signal FLAG <4> When the seventh process information signal generating circuit 257 is at a logic high level, the fifth bit CD of the buffered count detection signal <5> To generate the seventh bit PINF of the process information signal <7> In the fourth bit of the flag signal FLAG <4> The fifth bit CD of the counting detection signal is at a logic high level. <5> When the seventh process information signal generating circuit 257 is at a logic high level, it generates the seventh bit PINF of the process information signal at a logic high level. <7> In the fourth bit of the flag signal FLAG <4> When the seventh process information signal generating circuit 257 is at a logic low level, it generates the seventh bit PINF of the process information signal at a logic low level. <7> .

[0145] The eighth process information signal generating circuit 258 is composed of an inverter 258 <1> and 258 <2> and NAND gate 258 <3> When the fourth bit of the flag signal FLAG <4> When the eighth process information signal generating circuit 258 is at a logic high level, it inverts and buffers the fifth bit CD of the count detection signal. <5> To generate the eighth bit PINF of the process information signal <8> When the fourth bit of the flag signal FLAG <4> The fifth bit CD of the counting detection signal is at a logic high level. <5> When the eighth process information signal generating circuit 258 is at a logic low level, it generates the eighth bit PINF of the process information signal at a logic high level. <8> When the fourth bit of the flag signal FLAG <4> When the eighth process information signal generating circuit 258 is at a logic low level, it generates the eighth bit PINF of the process information signal at a logic low level. <8> .

[0146] The ninth process information signal generating circuit 259 is composed of an inverter 259 <1> and 259 <2> The ninth process information signal generating circuit 259 buffers the fifth bit FLAG of the flag signal. <5> To generate the ninth bit PINF of the process information signal <9> When the fifth bit of the flag signal FLAG <5> When the ninth process information signal generating circuit 259 is at a logic high level, it generates the ninth bit PINF of the process information signal at a logic high level. <9> In the fifth bit of the flag signal FLAG <5> When the ninth process information signal generating circuit 259 is at a logic low level, it generates the ninth bit PINF of the process information signal at a logic low level. <9> .

[0147] Figure 15 It includes Figure 14 FIG2 is a table showing data output during operation of the process information signal generating circuit 250. Figure 15 Operations including generation of the process information signal PINF<1:9> based on the logic levels of the flag signal FLAG<1:5> and the count detection signal CD<1:5> by the process information signal generation circuit 250 are described.

[0148] The first process information signal generating circuit 251 generates a first bit PINF of the process information signal. <1> , when the first bit of the flag signal FLAG <1> When the logic level is high, the first bit PINF <1> At logic high level H.

[0149] When the second bit of the flag signal FLAG <2> The first bit CD of the counting detection signal is at a logic high level H. <1> When the second process information signal generating circuit 252 is at a logic high level H, it generates the second bit PINF of the process information signal at a logic high level H. <2> .

[0150] When the second bit of the flag signal FLAG <2> The first bit CD of the counting detection signal is at a logic high level H and <1> When the third process information signal generating circuit 253 is at a logic low level L, it generates a third bit PINF of the process information signal at a logic high level H. <3> .

[0151] When the second bit of the counting detection signal CD <2> When the fourth process information signal generating circuit 254 is at a logic high level H, it generates the fourth bit PINF of the process information signal at a logic high level H. <4> .

[0152] When the third bit of the count detection signal is CD <3> When the fifth process information signal generating circuit 255 is at a logic high level H, it generates the fifth bit PINF of the process information signal at a logic high level H. <5> .

[0153] When the fourth bit of the count detection signal is CD <4> When the sixth process information signal generating circuit 256 is at a logic high level H, it generates the sixth bit PINF of the process information signal at a logic high level H. <6> .

[0154] When the fourth bit of the flag signal FLAG <4> The fifth bit CD of the counting detection signal is at a logic high level H and <5> When the seventh process information signal generating circuit 257 is at a logic high level H, it generates the seventh bit PINF of the process information signal at a logic high level H. <7> .

[0155] When the fourth bit of the flag signal FLAG <4> The fifth bit CD of the counting detection signal is at a logic high level H and <5> When the eighth process information signal generating circuit 258 is at a logic low level L, it generates the eighth bit PINF of the process information signal at a logic high level H. <8> .

[0156] When the fifth bit of the flag signal FLAG <5> When the ninth process information signal generating circuit 259 is at a logic high level H, the ninth bit PINF of the process information signal is generated at a logic high level H. <9> .

[0157] refer to Figures 1 to 15 The process operation of the semiconductor system 1 according to the embodiment of the present disclosure is described. An example in which the process variation is a first deviation SF, an example in which the process variation is a third deviation ST, and an example in which the process variation is a fifth deviation TT are described.

[0158] An example is described when the process variation is in the first deviation SF.

[0159] The controller 10 transmits the clock signal CLK to the semiconductor device 20 through the first transmission line L11. The controller 10 transmits the process detection enable signal PD_EN to the semiconductor device 20 through the second transmission line L12.

[0160] The control circuit 210 generates a voltage enable signal VEN, a cycle enable signal OEN, and a comparison enable signal SEN, each of which is enabled at a logic high level when the process detection enable signal PD_EN is enabled in synchronization with the clock signal CLK. The control circuit 210 generates a count enable signal CEN enabled at a logic high level for the duration of an interval starting from the time when the process detection enable signal PD_EN is enabled in synchronization with the clock signal CLK.

[0161] When the voltage enable signal VEN is enabled, the period signal generating circuit 220 provides the first supply voltage VSUP1 and the second supply voltage VSUP2 to the oscillator 223. When the period enable signal OEN is enabled, the period signal generating circuit 220 generates the period signal VCO in the form of pulses that are periodically generated from the first supply voltage VSUP1 and the second supply voltage VSUP2.

[0162] When the comparison enable signal SEN is enabled, the comparison circuit 230 generates flag signals FLAG<1:5> as a result of comparing the voltage levels of the first reference voltage VREF1, the second reference voltage VREF2, the third reference voltage VREF3, and the fourth reference voltage VREF4 with a process voltage PV having a voltage level that varies according to process variations. In this example, since the process variations are within a first deviation SF, the voltage level of the generated process voltage PV is higher than the first reference voltage VREF1. Therefore, all bits of the flag signals FLAG<1:5> are disabled at a logic low level.

[0163] When the count signal CNT<1:8> counting pulses of the period signal VCO has a higher bit-by-bit value than the first target count signal TTF<1:8>, the count detection signal generating circuit 240 generates the count detection signal CD<1:5> with all bits disabled to a logic low level.

[0164] The process information signal generating circuit 250 generates the process information signal PINF<1:9> having all bits at a logic low level by decoding the flag signal FLAG<1:5> having all bits disabled at a logic low level and the count detection signal CD<1:5> having all bits disabled at a logic low level.

[0165] The controller 10 receives the process information signal PINF<1:9>, all of which are logic low, from the semiconductor device 20 via the third transmission line L13. When all bits of the process information signal PINF<1:9> are generated at logic low, the controller 10 detects that the process variation of the semiconductor device 20 is in the first deviation SF.

[0166] An example will be described where the process variation is at the third deviation ST.

[0167] The controller 10 transmits a clock signal CLK to the semiconductor device 20 through the first transmission line L11. The controller 10 transmits a process detection enable signal PD_EN to the semiconductor device 20 through the second transmission line L12.

[0168] At the time when the process detection enable signal PD_EN is enabled in synchronization with the clock signal CLK, the control circuit 210 generates a voltage enable signal VEN, a cycle enable signal OEN, and a comparison enable signal SEN, each of which is enabled at a logic high level. For the duration of an interval starting from the time when the process detection enable signal PD_EN is enabled in synchronization with the clock signal CLK, the control circuit 210 generates a count enable signal CEN enabled at a logic high level.

[0169] When the voltage enable signal VEN is enabled, the period signal generating circuit 220 provides the first supply voltage VSUP1 and the second supply voltage VSUP2 to the oscillator 223. When the period enable signal OEN is enabled, the period signal generating circuit 220 generates the period signal VCO in the form of pulses that are periodically generated from the first supply voltage VSUP1 and the second supply voltage VSUP2.

[0170] When the comparison enable signal SEN is enabled, the comparison circuit 230 generates the second bit FLAG of the flag signal enabled to be a logic high level. <2> As a result of comparing the voltage levels of the first reference voltage VREF1, the second reference voltage VREF2, the third reference voltage VREF3, and the fourth reference voltage VREF4 with the process voltage PV having a voltage level that varies according to process variations. In this example, since the process variations are at a third deviation ST, the process voltage PV is generated to have a voltage level between the first reference voltage VREF1 and the second reference voltage VREF2.

[0171] In this example, when the count signal CNT<1:8> counting the pulses of the period signal VCO has a lower bit-by-bit value than the first target count signal TTF<1:8>, the count detection signal generating circuit 240 generates the first bit CD of the count detection signal which is disabled to a logic low level. <1> .

[0172] When the second bit of the flag signal FLAG <2> The first bit CD of the counting detection signal is at a logic high level. <1> When the process information signal generating circuit 250 is disabled and is at a logic low level, it generates the third bit PINF of the process information signal at a logic high level. <3> .

[0173] The controller 10 receives the third bit PINF of the process information signal at a logic high level from the semiconductor device 20 through the third transmission line L13. <3> When the third bit of the process information signal PINF <3> When φ is generated as a logic high level, the controller 10 detects that the process variation of the semiconductor device 20 is in the third deviation ST.

[0174] An example will be described where the process variation is at the fifth deviation TT.

[0175] The controller 10 transmits the clock signal CLK to the semiconductor device 20 through the first transmission line L11. The controller 10 transmits the process detection enable signal PD_EN to the semiconductor device 20 through the second transmission line L12.

[0176] At the time when the process detection enable signal PD_EN is enabled in synchronization with the clock signal CLK, the control circuit 210 generates a voltage enable signal VEN, a cycle enable signal OEN, and a comparison enable signal SEN, each of which is enabled at a logic high level. For the duration of an interval starting from the time when the process detection enable signal PD_EN is enabled in synchronization with the clock signal CLK, the control circuit 210 generates a count enable signal CEN enabled at a logic high level.

[0177] When the voltage enable signal VEN is enabled, the period signal generating circuit 220 provides the first supply voltage VSUP1 and the second supply voltage VSUP2 to the oscillator 223. When the period enable signal OEN is enabled, the period signal generating circuit 220 generates the period signal VCO in the form of pulses that are periodically generated from the first supply voltage VSUP1 and the second supply voltage VSUP2.

[0178] When the comparison enable signal SEN is enabled, the comparison circuit 230 generates the third bit FLAG of the flag signal enabled to be a logic high level. <3> As a result of comparing the voltage levels of the first reference voltage VREF1, the second reference voltage VREF2, the third reference voltage VREF3, and the fourth reference voltage VREF4 with the process voltage PV, whose voltage level varies according to process variations. In this example, since the process variations are at a fifth deviation TT, the process voltage PV is generated to a voltage level between the second reference voltage VREF2 and the third reference voltage VREF3.

[0179] When the count signal CNT<1:8> counting the pulses of the period signal VCO has a lower bit-by-bit value than the second target count signal TFF<1:8> and a higher bit-by-bit value than the third target count signal TSS<1:8>, the count detection signal generating circuit 240 generates the third bit CD of the count detection signal enabled to a logic high level. <3> .

[0180] When the third bit of the count detection signal is CD <3> When the process information signal generating circuit 250 is enabled at a logic high level, it generates the fifth bit PINF of the process information signal at a logic high level. <5> .

[0181] The controller 10 receives the fifth bit PINF of the process information signal at a logic high level from the semiconductor device 20 through the third transmission line L13. <5> When the fifth bit of the process information signal PINF <5> When generated at a logic high level, the controller 10 detects that the process variation of the semiconductor device 20 is at a fifth deviation TT.

[0182] After the process variation detection operation begins, the semiconductor system 1 according to an embodiment of the present disclosure can detect deviations in process variations in various ways by generating process information signals PINF<1:9> based on the voltage level of a process voltage PV generated according to the process variation and the pulse timing of a periodic signal VCO. After the process variation detection operation begins, the semiconductor system 1 can accurately detect deviations in process variations from the process information signals PINF<1:9> indicating the process variation based on flag signals FLAG<1:5> generated based on the process voltage PV, whose voltage level varies with the process variation, and count detection signals CD<1:5> generated based on the periodic signal VCO, whose pulse timing varies with the process variation.

[0183] Figure 16 1 is a block diagram illustrating an electronic system 1000 according to an embodiment of the present disclosure. Figure 16 As shown, the electronic system 1000 includes a host 1100 and a semiconductor system 1200 .

[0184] The host 1100 and the semiconductor system 1200 use an interface protocol to transmit or communicate signals to each other in two directions. The interface protocol used between the host 1100 and the semiconductor system 1200 may include MultiMediaCard (MMC), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Peripheral Component Interconnect Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), and Universal Serial Bus (USB).

[0185] Semiconductor system 1200 includes a controller 1300 and K semiconductor devices 1400(1:K). Controller 1300 controls a process variation detection operation for each of semiconductor devices 1400(1:K), where K is a positive integer. After the process variation detection operation begins, each semiconductor device 1400(1:K) generates a process information signal PINF<1:9> based on the voltage level of a process voltage PV generated according to process variation and the timing of pulses of a periodic signal VCO. After the process variation detection operation begins, each semiconductor device 1400(1:K) generates a process information signal PINF<1:9> indicating process variation based on a flag signal FLAG<1:5> and a count detection signal CD<1:5>. The flag signal FLAG<1:5> is generated based on the process voltage PV, whose voltage level varies according to process variation, and the count detection signal CD<1:5> is generated based on the periodic signal VCO, whose pulse timing varies according to process variation. Each semiconductor device 1400(1:K) provides process information signals PINF<1:9> to the controller 1300. After receiving the process information signals PINF<1:9> from the semiconductor devices 1400(1:K), the controller 1300 detects process variations in various ways. The controller 1300 can accurately detect process variations from the process information signals PINF<1:9> received from each semiconductor device 1400(1:K).

[0186] The controller 1300 can be used with Figure 1 The semiconductor device 1400 (1:K) can be implemented similarly to the controller 10 shown in FIG. Figure 1 and Figure 2 The semiconductor device 20 shown in FIG is similarly implemented. According to an embodiment, the semiconductor device 1400 (1:K) can be implemented using one of a dynamic random access memory (DRAM), a phase change random access memory (PRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), and a ferroelectric random access memory (FRAM).

[0187] Although detailed embodiments of the present disclosure are disclosed in this disclosure, those skilled in the art will appreciate that various modifications, additions, and substitutions may be made to these embodiments without departing from the scope and technical spirit of the present disclosure. Therefore, the scope of the present disclosure should not be limited to the aforementioned embodiments. All variations within the meaning and scope of the equivalents of the claims are intended to be included within their scope.

Claims

1. A semiconductor device comprising: a comparison circuit that: generates a flag signal by comparing a voltage level of a reference voltage with a voltage level of a process voltage after a process variation detection operation starts; and A process information signal generating circuit generates a process information signal indicating a process variation based on a count detection signal generated based on the flag signal and based on timings of pulses included in a periodic signal.

2. The semiconductor device according to claim 1, in, The process voltage is a voltage having a voltage level that varies according to the process variation, and Here, the periodic signal is a signal having pulses generated at timings that vary according to the process variation.

3. The semiconductor device according to claim 1, wherein The comparison circuit comprises: a process voltage generating circuit comprising: a PMOS transistor and an NMOS transistor; and driving the process voltage based on a driving force of the PMOS transistor and a driving force of the NMOS transistor; and A flag signal generating circuit generates the flag signal by comparing the process voltage and the reference voltage during an interval in which a comparison enable signal is enabled.

4. The semiconductor device according to claim 3, wherein The process voltage generating circuit includes: the PMOS transistor being disposed between a power supply voltage and a first node and driving the process voltage to a voltage level of the power supply voltage when the process voltage is driven at a voltage level of a ground voltage; and The NMOS transistor is provided between the first node and the ground voltage and drives the process voltage to the voltage level of the ground voltage when the process voltage is driven at the voltage level of the power supply voltage.

5. The semiconductor device according to claim 3, wherein The flag signal generating circuit includes: a comparison voltage signal generating circuit, which: generates a comparison voltage signal by comparing the process voltage and the reference voltage during the interval in which the comparison enable signal is enabled; and A flag signal decoding circuit generates the flag signal based on a logic level combination of bits of the comparison voltage signal. The semiconductor device according to claim 5 , wherein: The comparison voltage signal generating circuit includes: a comparison signal generating circuit that generates a comparison signal by comparing the process voltage and the reference voltage; and A comparison voltage signal output circuit generates the comparison voltage signal by buffering the comparison signal during the interval in which the comparison enable signal is enabled; and generates the disabled comparison voltage signal during the interval in which the comparison enable signal is disabled.

7. A semiconductor device comprising: a periodic signal generating circuit that: generates a periodic signal having pulses generated at timings varying according to process variations; a count detection signal generating circuit that generates a count detection signal by comparing a target count signal with a count signal that counts pulses of the periodic signal; and A process information signal generating circuit generates a process information signal indicating a process variation based on the count detection signal and the flag signal.

8. The semiconductor device according to claim 7, wherein The periodic signal generating circuit: When the process variation is low, increasing the pulse generation frequency of the periodic signal, and When the process variation is high, the pulse generation frequency of the periodic signal is reduced.

9. The semiconductor device according to claim 7, wherein The counting detection signal generating circuit comprises: a counting circuit that: generates the counting signal including sequentially counted bits based on pulses of the periodic signal received during an interval in which a count enable signal is enabled; and A count comparison circuit generates the count detection signal by comparing the count signal with the target count signal.

10. The semiconductor device according to claim 7, further comprising a comparison circuit configured to generate the flag signal by comparing a reference voltage with a process voltage having a voltage level that varies according to the process variation.

11. The semiconductor device according to claim 10, wherein The comparison circuit comprises: a process voltage generating circuit comprising: a PMOS transistor and an NMOS transistor; and driving the process voltage based on a driving force of the PMOS transistor and a driving force of the NMOS transistor; and A flag signal generating circuit generates the flag signal by comparing the process voltage and the reference voltage during an interval in which a comparison enable signal is enabled.

12. The semiconductor device according to claim 11, wherein The process voltage generating circuit includes: the PMOS transistor being disposed between a power supply voltage and a first node and driving the process voltage to a voltage level of the power supply voltage when the process voltage is driven at a voltage level of a ground voltage; and The NMOS transistor is provided between the first node and the ground voltage and drives the process voltage to the voltage level of the ground voltage when the process voltage is driven at the voltage level of the power supply voltage.

13. The semiconductor device according to claim 11, wherein The flag signal generating circuit includes: a comparison voltage signal generating circuit, which: generates a comparison voltage signal by comparing the process voltage and the reference voltage during the interval in which the comparison enable signal is enabled; and A flag signal decoding circuit generates the flag signal based on a logic level combination of bits of the comparison voltage signal.

14. The semiconductor device according to claim 13, wherein The comparison voltage signal generating circuit includes: a comparison signal generating circuit, which: generates a comparison signal by comparing the process voltage and the reference voltage; and A comparison voltage signal output circuit generates the comparison voltage signal by buffering the comparison signal during the interval in which the comparison enable signal is enabled; and generates the disabled comparison voltage signal during the interval in which the comparison enable signal is disabled.

15. A semiconductor device comprising: a comparison circuit that: generates a plurality of flag signals in response to detecting a voltage level of a process voltage having a voltage level that varies according to process variations; a count detection signal generating circuit that: generates a plurality of count detection signals by comparing a count signal with a first target count signal, a second target count signal, a third target count signal, and a fourth target count signal, wherein the count signal counts pulses of a periodic signal having a pulse timing that varies according to the process variation; and A process information signal generating circuit generates a plurality of process information signals indicating the process variation based on the plurality of count detection signals and the plurality of flag signals.

16. The semiconductor device according to claim 15, wherein The comparison circuit generates the plurality of flag signals by comparing the process voltage with first, second, third, and fourth reference voltages, wherein each reference voltage is at a constant voltage level that is not affected by process variations.

17. The semiconductor device according to claim 15, wherein The comparison circuit generates the plurality of flag signals based on variations in driving strength of a PMOS transistor and a driving strength of an NMOS transistor, wherein the PMOS transistor and the NMOS transistor drive the process voltage.

18. The semiconductor device according to claim 15, wherein The comparison circuit comprises: a process voltage generating circuit comprising: a PMOS transistor and an NMOS transistor; and driving the process voltage based on a driving force of the PMOS transistor and a driving force of the NMOS transistor; and The flag signal generating circuit generates the plurality of flag signals by comparing the process voltage with a plurality of reference voltages during an interval in which a comparison enable signal is enabled.

19. The semiconductor device according to claim 18, wherein The process voltage generating circuit includes: the PMOS transistor being disposed between a power supply voltage and a first node and driving the process voltage to a voltage level of the power supply voltage when the process voltage is driven at a voltage level of a ground voltage; and The NMOS transistor is provided between the first node and the ground voltage and drives the process voltage to the voltage level of the ground voltage when the process voltage is driven at the voltage level of the power supply voltage.

20. The semiconductor device according to claim 18, wherein The flag signal generating circuit includes: a comparison voltage signal generating circuit, which: generates a plurality of comparison voltage signals by comparing the process voltage with the plurality of reference voltages during the interval in which the comparison enable signal is enabled; and A flag signal decoding circuit generates the plurality of flag signals based on a logic level combination of the plurality of comparison voltage signals.

21. The semiconductor device according to claim 15, wherein The counting detection signal generating circuit comprises: a counting circuit that: generates the counting signal including sequentially counted bits based on pulses of the periodic signal received during an interval in which a count enable signal is enabled; and A count comparison circuit generates the plurality of count detection signals by comparing the count signal with the first target count signal, the second target count signal, the third target count signal, and the fourth target count signal.

22. A method comprising: generating a plurality of flag signals in response to detecting a process voltage that varies according to process variations of a semiconductor device; generating a count signal that counts pulses of a periodic signal having a pulse timing that varies according to the process variation; generating a plurality of count detection signals by comparing the count signal with each of a plurality of target count signals; as well as A process information signal indicating the process variation is generated based on the plurality of count detection signals and the plurality of flag signals.

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