FIFO buffer and working mode switching method of FIFO buffer

Abstract

The invention relates to the technical field of chips, and discloses an FIFO buffer and a working mode switching method of the FIFO buffer, and the FIFO buffer comprises a frequency decoding module, a mode selection logic module and a data array module which are connected in sequence; a frequency decoding module outputs a working mode selection parameter based on a frequency phase relationship between a source clock domain and a target clock domain, specifically, the working mode selection parameter is used for indicating a working mode of an FIFO buffer; therefore, the mode selection logic module can control the FIFO buffer to be switched to the synchronous working mode or the asynchronous working mode based on the working mode selection parameters so as to operate the data array module in the synchronous working mode or the asynchronous working mode, and dynamic selection of the optimal working mode is achieved. The data transmission delay is reduced when the source clock domain and the target clock domain are synchronous, and the data transmission reliability is ensured when the source clock domain and the target clock domain are asynchronous.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a FIFO buffer and a method for switching an operating mode of the FIFO buffer. Background Art

[0002] In multi-clock domain digital circuit systems, dynamic frequency scaling (DFS) technology is widely used to dynamically adjust the operating frequency of a specific clock domain to meet the power consumption and performance requirements of different application scenarios. To achieve cross-clock domain data and command synchronization, asynchronous FIFO (First-In-First-Out) is a mature technology solution. It uses a Gray Code-encoded read and write pointer synchronization mechanism to ensure reliable data transmission between different clock domains.

[0003] The asynchronous FIFO design method in the related art has certain limitations after the physical design of the chip is solidified after tape-out. Therefore, it is urgent to propose a new FIFO buffer. Summary of the Invention

[0004] The present application provides a FIFO buffer and a method for switching the working mode of the FIFO buffer, which solves the technical problem of the need to optimize the data transmission delay of a multi-clock domain digital circuit system, achieves the technical effect of eliminating unnecessary delay cycles, and can improve the data transmission rate and the performance of the overall system.

[0005] In order to achieve the above objectives, the main technical solutions adopted in this application include:

[0006] In a first aspect, an embodiment of the present application provides a FIFO buffer used as a connection component between a source clock domain and a destination clock domain during cross-clock domain data transmission, the FIFO buffer comprising a frequency decoding module, a mode selection logic module, and a data array module connected in sequence;

[0007] The frequency decoding module is configured to output an operating mode selection parameter based on a frequency phase relationship between the source clock domain and the destination clock domain; wherein the operating mode selection parameter is used to indicate a target operating mode of the FIFO buffer;

[0008] The mode selection logic module is configured to control the FIFO buffer to switch to the target working mode to operate the data array module in the target working mode, and the target working mode is a synchronous working mode or an asynchronous working mode.

[0009] The FIFO buffer proposed in the embodiment of the present application outputs an operating mode selection parameter based on the frequency phase relationship between the source clock domain and the destination clock domain through a frequency decoding module. Specifically, the operating mode selection parameter is used to indicate the operating mode of the FIFO buffer, so that the mode selection logic module can control the FIFO buffer to switch to a synchronous operating mode or an asynchronous operating mode based on the operating mode selection parameter, so as to operate the data array module in the synchronous operating mode or the asynchronous operating mode, thereby realizing dynamic selection of the optimal operating mode. This implementation method not only reduces data transmission delay when the source clock domain and the destination clock domain are synchronized, but also ensures data transmission reliability when the source clock domain and the destination clock domain are asynchronous.

[0010] Optionally, the mode selection logic module is further configured to control the FIFO buffer to switch to a synchronous operating mode when the operating mode selection parameter indicates that the frequency and phase relationship is a co-frequency and co-phase relationship, so as to operate the data array module in the synchronous operating mode. In the synchronous operating mode, the control logic is simplified by directly passing the read and write pointers, which not only eliminates unnecessary delay cycles but also eliminates encoding conversion overhead, thereby improving the data transmission rate and overall system performance.

[0011] Optionally, the mode selection logic module is further configured to control the FIFO buffer to switch to an asynchronous operating mode when the operating mode selection parameter indicates that the frequency-phase relationship is not a co-frequency and co-phase relationship, so as to operate the data array module in the asynchronous operating mode. In the asynchronous operating mode, in order to prevent abnormal situations such as full-time full write and empty-time empty read, Gray code encoding is adopted. The single-bit jump characteristic of Gray code reduces the risk of cross-clock domain transmission, can solve the metastable problem in asynchronous scenarios, and facilitate secure data transmission.

[0012] Optionally, the mode selection logic module is further configured to, when the FIFO buffer switches to the synchronous operating mode, use natural binary-encoded read and write pointers and directly generate a first empty and full flag based on the natural binary-encoded read and write pointer values to indicate the storage status of the data array module. Directly using natural binary values to operate the read and write pointers in the synchronous operating mode reduces the computational overhead associated with encoding conversion. By comparing the read and write pointer differences in real time, the buffer status can be quickly determined, thereby ensuring the real-time and accuracy of the status signal.

[0013] Optionally, the mode selection logic module is further configured to, when the FIFO buffer switches to the asynchronous operating mode, use Gray code-encoded read and write pointers, perform two-level synchronization of the Gray code-encoded read and write pointers across clock domains, and generate a second empty and full flag based on the read and write pointer values after the two-level synchronization to indicate the storage status of the data array module. In the asynchronous operating mode, by converting Gray code and comparing the pointer difference, the buffer status is dynamically fed back to accurately control the start and stop conditions of read and write operations to ensure data integrity.

[0014] Optionally, the mode selection logic module includes a selection circuit and a configuration register; the configuration register is connected to the frequency decoding module and is configured to receive and store the operating mode selection parameters; the selection circuit is connected to the configuration register and the data array module respectively, and is configured to control the FIFO buffer to switch to the target operating mode based on the operating mode selection parameters, so as to operate the data array module under the target operating mode. By introducing the configuration register and the selection circuit, the FIFO buffer can be allowed to dynamically adjust the operating mode according to the real-time clock domain status, so that the system can adapt to more diverse application scenarios. Furthermore, by using a single FIFO design to meet the requirements of both synchronous and asynchronous operating modes, the complexity of the system design is reduced, and the special cases and additional logic design that need to be considered in the system design are reduced.

[0015] Optionally, the frequency decoding module is connected to a frequency cutting control module; the frequency cutting control module is configured to send a frequency cutting command operation code to the frequency decoding module; the frequency cutting command operation code carries the source clock domain frequency and the destination clock domain frequency; the frequency decoding module is further configured to parse based on the source clock domain frequency and the destination clock domain frequency to obtain the frequency phase relationship between the source clock domain and the destination clock domain. The frequency decoding module receives the frequency cutting command operation code, and parses the frequency cutting command operation code to obtain the frequency phase relationship, thereby using this frequency phase relationship to provide a decision basis for switching working modes, which is conducive to achieving precise control of dynamic frequency adjustment; seamlessly switching working modes when the system frequency changes, taking into account both efficiency and reliability.

[0016] Optionally, the frequency cutting control module is connected to a frequency cutting execution module; the frequency cutting command operation code also carries a command type; the frequency decoding module is further configured to compare the encoded value of the source clock domain frequency and the encoded value of the destination clock domain frequency when the command type indicates that the frequency cutting execution module has completed the frequency cutting action, thereby obtaining the frequency phase relationship between the source clock domain and the destination clock domain. If the frequency cutting execution module completes the frequency cutting action, the frequency decoding module determines the frequency phase relationship based on the encoded value of the source clock domain frequency and the encoded value of the destination clock domain frequency, thereby using this frequency phase relationship to provide a decision-making basis for switching the working mode, which is conducive to achieving precise control of dynamic frequency adjustment; seamlessly switching the working mode when the system frequency changes, taking into account both efficiency and reliability.

[0017] Optionally, the frequency cutting control module is further configured to, if a frequency cutting request issued by the frequency cutting control module passes arbitration, send a clear control signal to the FIFO buffer to suspend writing data into the data array module, thereby gradually clearing the data array module. When the data array module is cleared, the frequency cutting control module issues the frequency cutting command opcode. This not only ensures data integrity but also clears any remaining data before switching, preventing data loss due to transmission interruptions.

[0018] In a second aspect, an embodiment of the present application provides a method for switching the working mode of a FIFO buffer. The FIFO buffer is used as a connecting component between a source clock domain and a destination clock domain during cross-clock domain data transmission, and the FIFO buffer includes a frequency decoding module, a mode selection logic module, and a data array module connected in sequence; the method further includes: outputting a working mode selection parameter based on the frequency phase relationship between the source clock domain and the destination clock domain through the frequency decoding module; wherein the working mode selection parameter is used to indicate a target working mode of the FIFO buffer; and controlling the FIFO buffer to switch to the target working mode through the mode selection logic module to operate the data array module in the target working mode, wherein the target working mode is a synchronous working mode or an asynchronous working mode.

[0019] In a third aspect, an embodiment of the present application provides a microprocessor architecture, comprising a processor core, a memory, and a FIFO buffer of any of the above items; the memory is communicatively connected to the processor core; the processor core and the memory are respectively connected to the FIFO buffer.

[0020] In a fourth aspect, an embodiment of the present application provides a chip comprising the above-mentioned microprocessor architecture. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0022] Figure 1 A schematic diagram of a FIFO buffer framework provided in an embodiment of the present application;

[0023] Figure 2 A schematic diagram of a FIFO buffer framework provided in an embodiment of the present application;

[0024] Figure 3 A schematic diagram of a FIFO buffer framework provided in an embodiment of the present application;

[0025] Figure 4 A schematic diagram of a FIFO buffer framework provided in an embodiment of the present application;

[0026] Figure 5 A schematic diagram of a FIFO buffer framework provided in an embodiment of the present application;

[0027] Figure 6 A schematic diagram of a FIFO buffer framework provided in an embodiment of the present application;

[0028] Figure 7 This is a signal timing diagram in the synchronous working mode provided by the embodiment of the present application;

[0029] Figure 8 This is a signal timing diagram in the asynchronous working mode provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] To make the purpose, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of this application.

[0031] As mentioned in the background art, the asynchronous FIFO design approach in the related art is solidified in the physical design after chip tape-out, which has certain limitations. For example, when the clock frequency and phase of the source clock domain and the destination clock domain are completely consistent, the related art still needs to perform read and write pointer synchronization operations based on Gray code. The synchronization operation of the read and write pointers requires at least two stages of triggers to introduce a fixed delay of at least two cycles, thereby affecting the transmission efficiency of data and commands. Therefore, in order to eliminate this unnecessary delay and improve the efficiency of data transmission and the overall performance of the system, an embodiment of the present application proposes a FIFO buffer. The FIFO buffer is configured with a synchronous operating mode and an asynchronous operating mode. When the frequency and phase relationship between the source clock domain and the destination clock domain is the same frequency and phase relationship, the FIFO buffer adopts a low-latency synchronous operating mode. When the frequency and phase relationship between the source clock domain and the destination clock domain is not the same frequency and phase relationship, the FIFO buffer adopts an asynchronous operating mode. In the asynchronous operating mode, it is necessary to synchronize multi-bit signals between clock domains with different frequencies and phases. It can be seen that the FIFO buffer adopts a dual-mode design, which can automatically switch the working mode of the FIFO buffer through a hardware mechanism according to the frequency phase relationship between the source clock domain and the destination clock domain to reduce system latency without the need for software intervention.

[0032] According to an embodiment of the present application, an embodiment of a FIFO buffer is provided. The FIFO buffer 100 is used as a connecting component between a source clock domain and a destination clock domain during cross-clock domain data transmission. Figure 1 The FIFO buffer 100 includes a frequency decoding module 110, a mode selection logic module 120 and a data array module 130 which are connected in sequence.

[0033] The frequency decoding module 110 is configured to output an operating mode selection parameter based on the frequency phase relationship between the source clock domain and the destination clock domain, wherein the operating mode selection parameter is used to indicate a target operating mode of the FIFO buffer 100 .

[0034] The mode selection logic module 120 is configured to control the FIFO buffer 100 to switch to a target working mode, so as to operate the data array module 130 in the target working mode. The target working mode is a synchronous working mode or an asynchronous working mode.

[0035] In this embodiment, the FIFO buffer 100 is a first-in-first-out (FIFO) storage device for implementing cross-clock domain data transmission, which serves as a connecting component between the source clock domain and the destination clock domain. By buffering data and coordinating the read and write operations of different clock domains, the complete transmission of data in asynchronous or synchronous scenarios is ensured. Specifically, the core function of the FIFO buffer is to receive data from the source clock domain and output the data in sequence under the control of the destination clock domain. For example, when a processor communicates with a peripheral device, the frequency of the source clock domain (such as the CPU clock) and the destination clock domain (such as the peripheral clock) may be different or the same. At this time, the FIFO buffer achieves efficient data transmission through dynamic mode switching.

[0036] In this embodiment, the frequency decoding module 110 is one of the core components of the FIFO buffer 100, which is configured to parse the frequency phase relationship between the source clock domain and the destination clock domain in real time, and generate an operating mode selection parameter based on the frequency phase relationship. The operating mode selection parameter is a digital signal generated by the frequency decoding module, and its encoding value directly determines the target operating mode of the FIFO buffer. The operating mode selection parameter can be a 1-bit flag bit, for example, "0" represents asynchronous operating mode and "1" represents synchronous operating mode. The operating mode selection parameter can be a multi-bit field to support more complex mode configurations (such as mixed mode). Furthermore, the operating mode selection parameter is stored in a hardware register to ensure the stability of mode switching. For example, when the frequency decoding module detects the same frequency and phase relationship, the corresponding position in the register is set to "1", and the mode selection logic module can switch to the synchronous operating mode accordingly.

[0037] In this embodiment, the mode selection logic module 120 is a functional unit for controlling the switching of the FIFO buffer's operating modes. It receives operating mode selection parameters from the frequency decoding module. Based on these operating mode selection parameters, the mode selection logic module 120 configures the FIFO buffer 100 to either synchronous or asynchronous operating mode. Specifically, in synchronous operating mode, the mode selection logic module 120 disables the cross-clock domain synchronization circuitry, allowing the read and write pointers to interact directly using natural binary encoding, thereby eliminating synchronization delays. In asynchronous operating mode, the mode selection logic module 120 enables Gray code encoding and two-stage synchronization triggers to ensure the security of cross-clock domain transmission.

[0038] In this embodiment, the data array module 130 is the physical structure that actually stores and manipulates data within the FIFO buffer. It performs data write, storage, and read operations in the target operating mode (synchronous operating mode or asynchronous operating mode). Specifically, in the synchronous operating mode, the read and write addresses of the data array module 130 are directly generated by local counters in the source and destination clock domains, eliminating the need for cross-clock domain synchronization. It should be noted that, regardless of whether the synchronous or asynchronous operating mode is used, the read addresses of the data array module 130 are natural binary coded addresses generated in the destination clock domain, and the write addresses are natural binary coded addresses generated in the source clock domain. However, in the asynchronous operating mode, although the read and write addresses of the data array module 130 remain in natural binary code, to ensure cross-clock error protection, the natural binary code must be converted to Gray code and synchronized to the other clock domain via two-stage flip-flops. For example, when the FIFO is in asynchronous mode, the binary write pointer in the source clock domain is converted to Gray code and synchronized to the destination clock domain via two-stage flip-flops, thereby avoiding data errors caused by metastability.

[0039] In this embodiment, the source clock domain may represent the clock signal region of the initiator of data transmission. The destination clock domain may represent the clock signal region of the receiver of data transmission. For example, the source clock domain is controlled by the clock signal of the data sender (such as a CPU core), and the destination clock domain is controlled by the clock signal of the data receiver (such as a memory controller).

[0040] Specifically, the frequency decoding module 110 detects the source clock domain and the destination clock domain to obtain the frequency phase relationship between the source clock domain and the destination clock domain. The frequency decoding module 110 outputs an operating mode selection parameter based on the detected frequency phase relationship. The operating mode selection parameter indicates the target operating mode of the FIFO buffer. The mode selection logic module 120 passes the operating mode selection parameter to the control FIFO buffer to switch to the target operating mode, configures the hardware logic according to the parameter, and realizes seamless mode switching. The data array module 130 executes the read and write logic corresponding to the target operating mode to ensure that the data is correctly transmitted in the selected target operating mode, achieving safe and efficient transmission, and improving the data transmission efficiency and stability of the system.

[0041] Furthermore, the target operating mode is a synchronous operating mode or an asynchronous operating mode. The synchronous operating mode may refer to a low-latency operating mode adopted by the FIFO buffer when the frequency and phase of the source clock domain are consistent with those of the destination clock domain. In the synchronous operating mode, the read and write pointers can use natural binary encoding, and the read and write operations do not require synchronization across clock domains, and data transmission can be completed in only one clock cycle. The asynchronous operating mode may refer to a safe transmission mode adopted by the FIFO buffer when the frequency or phase of the source clock domain is different from that of the destination clock domain. In the asynchronous operating mode, the read and write pointers need to be converted into Gray code and synchronized to the other clock domain through two-stage triggers to avoid metastable problems.

[0042] In some embodiments, see Figure 2 The mode selection logic module 120 includes a selection circuit 210 and a configuration register 220. The configuration register 220 is connected to the frequency decoding module 110 and is configured to receive and store an operating mode selection parameter. The selection circuit 210 is connected to the configuration register 220 and the data array module 130, respectively, and is configured to control the FIFO buffer to switch to a target operating mode based on the operating mode selection parameter, thereby operating the data array module 130 in the target operating mode.

[0043] The selection circuit 210 is an electronic circuit component within the mode selection logic module 120 that dynamically switches the hardware logic path based on the operating mode selection parameters. The configuration register 220 is a hardware storage unit within the mode selection logic module 120 that stores the operating mode selection parameters. It is connected to the frequency decoding module 110. The configuration register 220 captures the operating mode selection parameters generated by the frequency decoding module 110 through a hardware interface and stores them in an internal storage unit.

[0044] Specifically, the frequency decoding module 110 transmits the working mode selection parameter to the configuration register 220 and locks the storage content through the write enable signal. The selection circuit 210 activates the corresponding hardware logic module to reconstruct the operation mode of the data array module based on the parameter value of the working mode selection parameter stored in the configuration register 220. For example, when the parameter value of the working mode selection parameter indicates the synchronous working mode, the selection circuit can turn off the Gray code encoder and enable direct transmission of the natural binary address; when the parameter value of the working mode selection parameter indicates the asynchronous working mode, the selection circuit can enable Gray code conversion and a two-stage synchronous trigger link. In this embodiment, on the one hand, the safe storage of the working mode selection parameter is achieved through the hardware interface to ensure the accuracy and stability of the mode switching. On the other hand, by dynamically reconstructing the hardware connection relationship, seamless switching between the synchronous working mode and the asynchronous working mode is achieved to improve efficiency in the synchronous working mode and ensure reliability in the asynchronous working mode.

[0045] In the above embodiment, the frequency decoding module outputs an operating mode selection parameter based on the frequency phase relationship between the source clock domain and the destination clock domain. Specifically, the operating mode selection parameter is used to indicate the operating mode of the FIFO buffer, so that the mode selection logic module can control the FIFO buffer to switch to the synchronous operating mode or the asynchronous operating mode based on the operating mode selection parameter, so as to operate the data array module in the synchronous operating mode or the asynchronous operating mode, thereby realizing dynamic selection of the optimal operating mode, not only reducing the data transmission delay when the source clock domain and the destination clock domain are synchronized, but also ensuring the data transmission reliability when the source clock domain and the destination clock domain are asynchronous.

[0046] In some embodiments, the mode selection logic module 120 is further configured to control the FIFO buffer to switch to the synchronous working mode when the working mode selection parameter indicates that the frequency-phase relationship is the same frequency and phase relationship, so as to operate the data array module in the synchronous working mode.

[0047] In the synchronous operating mode, a natural binary-coded read / write pointer can be used to operate the data array module. Natural binary-coded read / write pointers refer to an encoding method that uses continuous binary values to represent the write position (write pointer) and read position (read pointer) of data in the FIFO buffer. In the synchronous operating mode, the read / write pointers do not need to be converted into Gray code and can be directly transferred between the source clock domain and the destination clock domain. Specifically, the frequency decoding module analyzes the signal characteristics of the source clock domain and the destination clock domain and determines that the frequency and phase relationship between the source clock domain and the destination clock domain is the same frequency and phase relationship when the two frequencies are exactly the same and the phase difference is zero. Furthermore, if the frequency decoding module detects the same frequency and phase relationship, the operating mode selection parameter is set to a specific encoding value to indicate that the synchronous mode switching condition is currently met. Therefore, the mode selection logic module controls the FIFO buffer to switch to the synchronous operating mode. Dynamically reconfiguring the hardware logic through the mode selection logic module eliminates the need to design redundant circuits and can optimize cross-clock domain delays.

[0048] In this embodiment, in synchronous mode, the data array module executes data write and read operations based on natural binary-encoded read and write pointers. Directly passing read and write pointers simplifies control logic, eliminating unnecessary delay cycles and encoding conversion overhead, thereby improving data transfer rates and overall system performance.

[0049] Furthermore, the mode selection logic module 120 is further configured to use a natural binary-coded read / write pointer if the FIFO buffer switches to the synchronous working mode, and directly generate a first empty / full flag based on the natural binary-coded read / write pointer value to indicate the storage status of the data array module.

[0050] Specifically, in the synchronous working mode, the mode selection logic module does not need to perform Gray code conversion or cross-clock domain synchronization processing on the read and write pointers, but directly uses the original values ​​encoded in natural binary to perform logical operations. The read and write pointer values are generated in real time by the local counters of the source clock domain and the destination clock domain, and are directly input into the empty and full flag generation circuit. The mode selection logic module directly compares the natural binary coded read pointer value and the natural binary coded write pointer value to generate a first empty and full flag. The storage status of the data array module is indicated by the first empty and full flag. For example, the first empty and full flag feeds back the real-time data capacity information of the data array module in the form of a logic level or a digital signal.

[0051] In this embodiment, the first empty / full flag includes an empty flag and a full flag. The empty flag indicates that there is no valid data to read from the data array module. The full flag indicates that the data array module is full. When the write pointer value and the read pointer value are equal, the empty flag is set. The empty flag is used to prevent the destination clock domain from performing an invalid read operation when there is no data. When the write pointer value exceeds the read pointer value and exceeds the total capacity of the data array module, the full flag is set. The full flag is used to prevent the source clock domain from performing a write operation when the buffer is full. This process eliminates the Gray code conversion required in asynchronous mode, reducing cross-clock domain synchronization delay.

[0052] In the above embodiment, synchronous operation mode directly uses natural binary values to manipulate read and write pointers, reducing the computational overhead associated with encoding conversion. By comparing the read and write pointer differences in real time, the buffer status can be quickly determined, ensuring the real-time and accuracy of the status signal, thereby avoiding data transmission conflicts and maintaining data integrity and system stability.

[0053] In some embodiments, the mode selection logic module 120 is further configured to control the FIFO buffer to switch to the asynchronous working mode when the working mode selection parameter indicates that the frequency-phase relationship is not the same frequency and phase relationship, so as to operate the data array module in the asynchronous working mode.

[0054] It's important to note that while read and write operations in the data array module always use the natural binary address pointers of the source and destination clock domains, in asynchronous mode, Gray code read and write pointers are used for cross-clock domain transfer to ensure accurate data transmission. This Gray code synchronization encoding method accurately generates the FIFO buffer's empty and full flags, effectively preventing abnormal situations such as full write operations when the FIFO buffer is full and empty read operations when the FIFO buffer is empty.

[0055] Among them, the read and write pointers encoded in Gray code refer to the use of an encoding method in which only one bit of adjacent numerical values changes to represent the write position (write pointer) and read position (read pointer) of the data in the FIFO buffer. In the asynchronous working mode, the natural binary read and write pointers must first be converted into Gray code, and then synchronized to the other clock domain through a two-stage trigger. Specifically, the frequency decoding module detects the signal characteristics of the source clock domain and the destination clock domain. If it is determined that the frequencies of the two are different or the phases are not aligned, it is determined that the frequency and phase relationship between the source clock domain and the destination clock domain is not the same frequency and phase relationship. Furthermore, if the frequency decoding module detects that the frequency and phase relationship is not the same frequency and phase relationship, the working mode selection parameter is set to a specific encoding value to indicate that the asynchronous mode switching condition is currently met. Therefore, the mode selection logic module controls the FIFO buffer to switch to the asynchronous working mode. Dynamically reconstructing the hardware logic through the mode selection logic module does not require the design of redundant circuits and can optimize the cross-clock domain delay.

[0056] In this embodiment, in the asynchronous working mode, cross-clock synchronization is achieved through Gray code encoding to generate reliable empty and full flags. For example, the write pointer is generated by the counter of the source clock domain and converted into Gray code, which is transmitted to the destination clock domain through the synchronization circuit; the read pointer is generated by the counter of the destination clock domain and reversely synchronized to the source clock domain. When performing a read operation, the destination clock domain must first detect the non-empty state of the FIFO buffer. The generation of this non-empty state depends on the Gray code write pointer being synchronized from the source clock domain to the destination clock domain through two levels. Therefore, the destination clock domain must wait for the two-level synchronization to be completed before reading the corresponding address data, ensuring the reliability of cross-clock domain transmission.

[0057] In the above embodiment, the frequency decoding module monitors clock signal differences in real time, ensuring that asynchronous mode is triggered when frequencies or phases are inconsistent, thereby ensuring the reliability of cross-clock domain data transmission, eliminating the risk of metastability, and preventing data loss or corruption.

[0058] Furthermore, the mode selection logic module 120 is further configured to use the Gray code-encoded read and write pointers, perform two-level synchronization on the Gray code-encoded read and write pointers across clock domains if the FIFO buffer switches to the asynchronous working mode, and generate a second empty and full flag based on the read and write pointer values after the two-level synchronization to indicate the storage status of the data array module.

[0059] Specifically, in asynchronous operation, the mode selection logic module transfers Gray-coded read and write pointers to the other clock domain via a two-stage flip-flop chain to eliminate the effects of metastability. For example, the Gray-coded write pointer in the source clock domain is first sampled by the first-stage flip-flop into the intermediate clock domain, then synchronized to the destination clock domain via the second-stage flip-flop. The Gray-coded read pointer in the destination clock domain is synchronized back to the source clock domain in the same manner.

[0060] In this embodiment, the mode selection logic module, operating in asynchronous mode, generates a signal indicating the storage status of the data array module by comparing the difference between the two synchronized Gray code read and write pointer values. The second empty / full flag includes an empty flag and a full flag, and its generation logic must consider the encoding characteristics of the Gray code and the synchronized pointer values. For example, the synchronized write pointer Gray code value and read pointer Gray code value are compared, and the second empty / full flag is generated based on the total capacity of the data array module.

[0061] In the above embodiment, Gray code is used in asynchronous operation mode. The single-bit transition characteristics of Gray code reduce the risk of cross-clock domain transmission, addressing metastability issues in asynchronous scenarios and facilitating secure data transmission. Furthermore, by converting Gray code and comparing pointer differences, dynamic feedback of buffer status is provided to precisely control the start and stop conditions of read and write operations, ensuring data integrity.

[0062] In some embodiments, see Figure 3 The frequency decoding module 110 is connected to the frequency cutting control module 310. The frequency cutting control module 310 is configured to send a frequency cutting command operation code to the frequency decoding module 110; the frequency cutting command operation code carries the source clock domain frequency and the destination clock domain frequency. The frequency decoding module 110 is further configured to perform analysis based on the source clock domain frequency and the destination clock domain frequency to obtain the frequency phase relationship between the source clock domain and the destination clock domain.

[0063] In this embodiment, the frequency cutting control module 310 can be a functional unit for generating and managing frequency switching instructions, which is connected to the frequency decoding module 110 via a control signal line or a data bus. The frequency cutting control module 310 can receive a system-level frequency cutting request (such as a dynamic voltage frequency adjustment instruction) and encode it into a specific frequency cutting command operation code. The frequency cutting command operation code is a digitally encoded signal generated by the frequency cutting control module, which contains configuration information of the source clock domain frequency and the destination clock domain frequency. For example, the operation code adopts a multi-field structure. The clock domain frequency can refer to the specific frequency value or predefined frequency point number of the clock signal at the initiator of the data transmission. The destination clock domain frequency can refer to the specific frequency value or predefined frequency point number of the clock signal at the receiving end of the data transmission.

[0064] Specifically, the frequency cutting control module sends a frequency cutting command opcode to the frequency decoding module, converting the system-level frequency switching requirements into hardware-parseable encoding instructions, facilitating precise control of dynamic frequency adjustment. Furthermore, the frequency cutting control module sends a frequency cutting command opcode to the frequency decoding module to trigger frequency-phase relationship analysis. The frequency decoding module performs analysis based on the source clock domain frequency and the destination clock domain frequency, determining the frequency-phase relationship between the source clock domain and the destination clock domain through frequency point mapping and frequency calculation, providing a decision basis for operating mode switching.

[0065] In some embodiments, see Figure 4 The frequency cutting control module 310 is connected to the frequency cutting execution module 410. The frequency cutting command opcode also carries a command type. The frequency decoding module 110 is further configured to, when the command type indicates that the frequency cutting execution module 410 has completed the frequency cutting action, compare the encoded value of the source clock domain frequency with the encoded value of the destination clock domain frequency to obtain the frequency phase relationship between the source clock domain and the destination clock domain.

[0066] Among them, the frequency cutting execution module 410 can be a hardware circuit or logic unit for executing the actual clock frequency switching operation according to the frequency cutting command operation code, which is connected to the frequency cutting control module 310. The command type can be a field in the frequency cutting command operation code, which is used to identify the execution stage or operation type of the current command. The command type distinguishes different instructions through different encoding values. 2'b00 indicates a frequency cutting request; 2'b01 indicates that the frequency cutting is completed and the FIFO working mode needs to be switched; 2'b10 indicates that it is reserved and unused; 2'b11 indicates that it is reserved and unused. For example, when the frequency cutting execution module completes the frequency switching, the frequency cutting control module updates the command type field and passes it to the frequency decoding module through the frequency cutting command operation code to trigger the subsequent frequency phase relationship analysis.

[0067] Specifically, after receiving the frequency switching completion instruction, the frequency decoding module 110 parses the encoded value of the source clock domain frequency and the encoded value of the destination clock domain frequency, and calculates their frequency ratio and phase difference to determine whether the synchronous operating mode condition or the asynchronous operating mode condition is met. Furthermore, the frequency decoding module 110 outputs a logic signal representing the synchronization status of the two clock domains, which is used by the mode selection logic module 120 to switch the operating mode of the FIFO buffer 100. If the comparison result is a same-frequency and same-phase relationship, the synchronous operating mode parameter is output, indicating that the frequency and phase relationship is the same-frequency and same-phase relationship. If the frequency or phase is inconsistent, the asynchronous operating mode parameter is output, indicating that the frequency and phase relationship is not the same-frequency and same-phase relationship.

[0068] In the above embodiment, the frequency cutting command operation code is generated and sent by the frequency cutting control module, and the frequency cutting command operation code is parsed by the frequency decoding module to obtain the frequency phase relationship between the source clock domain and the destination clock domain, thereby providing a decision basis for switching the working mode and facilitating the precise control of dynamic frequency adjustment; the working mode is seamlessly switched when the system frequency changes, taking into account both efficiency and reliability.

[0069] In some embodiments, the frequency cutting control module is further configured to send a clear control signal to the FIFO buffer if the frequency cutting request issued by the frequency cutting control module passes arbitration, so as to suspend writing data into the data array module, so that the data array module is gradually cleared; wherein, when the data array module is cleared, the frequency cutting control module issues a frequency cutting command operation code.

[0070] Specifically, the arbitration mechanism is implemented through hardware logic or firmware algorithm, for example, by adopting polling scheduling or fixed priority strategy. When the frequency cutting request is arbitrated, the frequency cutting control module obtains execution authority and enters the subsequent operation process. The frequency cutting control module sends an instruction to the control logic of the FIFO buffer to suspend new data writing operations and allow existing data to be read out gradually. Exemplarily, the clearing control signal is implemented by pulling the level high or setting a specific bit to trigger the write enable mask logic of the FIFO buffer. For example, when the dfs_ctl_full signal is set, the write enable signal of the source clock domain is forced to be pulled low, preventing new data from entering the data array module, and the read operation continues until the data array module is cleared.

[0071] If all valid data in the data array module has been read and the FIFO buffer is in an idle state, the data array module is cleared. At this point, the FIFO buffer no longer holds any data to be transmitted, and the frequency switching operation can be performed safely. The frequency switching control module generates a frequency switching command opcode and sends it to the frequency decoding module to initiate the frequency switching process.

[0072] In the above embodiment, by sending a clear control signal to the FIFO buffer to suspend writing data into the data array module, not only can data integrity be guaranteed, but also remaining data can be cleared before switching to prevent data loss caused by transmission interruption.

[0073] According to an embodiment of the present application, an embodiment of a method for switching the working mode of a FIFO buffer is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0074] In this embodiment, a method for switching the working mode of a FIFO buffer is provided. The FIFO buffer is used as a connecting component between a source clock domain and a destination clock domain during cross-clock domain data transmission. The FIFO buffer includes a frequency decoding module, a mode selection logic module, and a data array module connected in sequence. Figure 5 FIFO buffer operation mode switching method according to an embodiment of the present application is a flowchart, such as Figure 5 As shown, the method includes the following steps:

[0075] S510. Outputting an operating mode selection parameter based on a frequency phase relationship between a source clock domain and a destination clock domain through a frequency decoding module; wherein the operating mode selection parameter is used to indicate a target operating mode of the FIFO buffer;

[0076] S520 , controlling the FIFO buffer to switch to a target operating mode through the mode selection logic module to operate the data array module in the target operating mode, where the target operating mode is a synchronous operating mode or an asynchronous operating mode.

[0077] For the specific definition of a method for switching the working mode of a FIFO buffer, please refer to the definition of a FIFO buffer above, which will not be repeated here. It should be understood that although the various steps in the above flowchart are displayed in sequence as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there are no strict order restrictions for the execution of these steps, and these steps can be executed in other orders. Moreover, at least part of the steps in the above flowchart may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0078] The embodiment of the present application also proposes a method for switching working modes based on a FIFO buffer. Figure 6 The FIFO buffer adopts a dual-mode FIFO, which includes a frequency decoding module, a mode selection logic module and a data array module. The mode selection logic module includes a selection circuit and a configuration register ( Figure 6 (not shown), the frequency decoding module is connected to the mode selection logic module, and the mode selection logic module is connected to the data array module. Figure 6 The frequency decoding module is connected to the frequency cutting control module, and the frequency cutting control module is connected to the frequency cutting execution module and the task arbitration module.

[0079] Based on this, the specific steps of the proposed FIFO buffer-based working mode switching method are introduced below through an example scenario of this application:

[0080] (1) When the system needs to change the frequency, the frequency cutting control module will send a frequency cutting request to the task arbitration module.

[0081] (2) If there are no system tasks with a higher priority than the frequency cutting request (such as data transmission interruption or emergency data processing) that need to be executed, the task arbitration module will return an arbitration response, granting the frequency cutting control module the right to execute. At this time, the frequency cutting control module wins the arbitration and sends a clear control signal dfs_ctl_full to the FIFO buffer control logic to suspend new data writing operations and allow existing data to be read out gradually, thereby causing the data array module to enter the "emptying" state.

[0082] (3) If all valid data in the data array module has been read and the FIFO buffer is in an idle state, it indicates that the data array module has been cleared. When the data array module is cleared, if the frequency cutting control module detects that the empty flag fifo_empty from the FIFO buffer is set, it will send a frequency cutting command valid signal and a frequency cutting command operation code dfs_cmd_opcode[9:0] to the frequency cutting execution module, and the frequency cutting execution module will perform the actual clock frequency switching operation according to the frequency cutting command operation code. At the same time, the frequency cutting control module will also send a frequency cutting command valid signal and a frequency cutting command operation code dfs_cmd_opcode[9:0] to the frequency decoding module so that the frequency decoding module can determine the frequency relationship between the destination clock domain and the source clock domain after the switch.

[0083] (4) The frequency decoding module parses the frequency switching command opcode dfs_cmd_opcode[9:0] to determine the frequency relationship between the destination clock domain and the source clock domain and writes it into the configuration register to control the operating mode of the FIFO buffer. The signal output by the configuration register is the operating mode selection parameter param_fifo_sync_type, which the mode selection logic module uses to switch between different target operating modes.

[0084] The coding information of the frequency cutting command operation code dfs_cmd_opcode[9:0] may be shown in the following Table 1:

[0085] Table 1 Command operation code encoding information

[0086]

[0087]

[0088] As can be seen from Table 1, the command type ([1:0]) is used to determine the type of switching operation (frequency switching request / completion). For example, when the frequency decoding module parses the command type dfs_cmd_opcode[1:0] as 2'b01, it means that the frequency switching execution module has completed the frequency switching. The next step is to switch the target working mode of the FIFO buffer. The different encoding values of the source clock domain frequency and the destination clock domain frequency ([5:2] and [9:6]) are used to correspond to different system operating frequencies, and there are a total of 16 levels of configurable frequencies. For example, for example, frequency 0 represents an operating frequency of 100MHz, and frequency 1 represents 200Mhz. When the encoding values of the source clock domain frequency dfs_cmd_opcode[5:2] and the destination clock domain frequency dfs_cmd_opcode[9:6] are both 4'b0000, it means that the source clock frequency and the destination clock frequency are both 100MHz. At this time, the two clock domains are in the same frequency and phase relationship.

[0089] Furthermore, when the encoding values of the source clock frequency dfs_cmd_opcode[5:2] and the destination clock frequency dfs_cmd_opcode[9:6] are equal, the operating mode selection parameter param_fifo_sync_type output by the frequency decoding module will be set to 1'b1, that is, the target operating mode of the FIFO buffer is set to the synchronous operating mode, so that the mode selection logic module can switch to the synchronous operating mode accordingly.

[0090] (5) The mode selection logic receives the working mode selection parameter param_fifo_sync_type from the frequency decoding module and parses it. Among them, the working mode selection parameter param_fifo_sync_type specifically includes the generation of signals such as the source clock src_clk, the destination clock dst_clk, the read pointer, the read address, the write pointer, the write address, and the empty flag fifo_empty and the full flag fifo_full. In the synchronous working mode, natural binary encoding can be used, and the read and write operations do not need to be synchronized across clock domains. Data transmission can be completed in only one clock cycle. In the asynchronous working mode, the read and write pointers need to be converted into Gray code and synchronized to the other clock domain through two-stage triggers to avoid metastable problems. (6) When the frequency cutting execution module completes the frequency switching of the source clock and the destination clock domain, it will feed back a frequency cutting completion signal to the frequency cutting control module to indicate that the frequency cutting is completed, so that the frequency cutting control module pulls down the clear control signal dfs_ctl_full, and the FIFO buffer reopens the write data entrance and starts to receive write data, thus entering the normal working state.

[0091] Please continue reading Figure 6 If the source clock domain src_clk and the target clock domain dst_clk are in a synchronous relationship, the workflow of the FIFO buffer when the target working mode is the synchronous working mode is exemplified as follows:

[0092] (1) Write operation: First, a write enable check is performed. When the write enable flag wr_en is high and the full flag fifo_full is low, data is allowed to be written. Then, data is written. The data wr_data is written to the write pointer wr_ptr_n of the data array module. Then, the write pointer wr_ptr_n is incremented to point to the next write address. Where wr_addr is the write address.

[0093] (2) Read operation: Similarly, the read enable check is first performed. When the read enable flag rd_en is high and the empty flag fifo_empty is low, data is allowed to be read. Then, data is read from the read pointer rd_ptr_n in the data array module to the data rd_data. Then, the read pointer rd_ptr_n is incremented to point to the next read address. Here, rd_addr is the read address.

[0094] (3) Empty and full judgment: If the read pointer rd_ptr_n and the write pointer wr_ptr_n are equal, the data array module is judged to be in an empty state at this time, and the empty flag fifo_empty is correspondingly high. If the highest bits of the read pointer rd_ptr_n and the write pointer wr_ptr_n are opposite, and the other bits are equal, the data array module is judged to be in a full state at this time, and the full flag fifo_full is correspondingly high.

[0095] Further, please refer to Figure 7 , Figure 7 The target working mode is the signal timing diagram of the synchronous working mode, based on Figure 7 It can be seen that:

[0096] It's important to note that in digital circuit systems, flip-flops typically sample on the rising edge of the clock, and the output signal value is updated in the next cycle. At time t1, the full flag, fifo_full, is low, and the write pointers wr_ptr_n and read pointers rd_ptr_n have the same values (000 and 000). Therefore, the empty flag, fifo_empty, is high (indicating that the data array module is now empty), indicating that the next write operation can proceed.

[0097] At time t2, a write enable check is performed, and the write enable flag wr_en is pulled high. The first data (data0) is written to the location corresponding to the write pointer wr_ptr_n (000) in the data array, and wr_ptr_n is updated to 001 in the next beat. At the same time, the values of the write pointer wr_ptr_n and the read pointer rd_ptr_n in the next beat are different (001 and 000), so the empty flag fifo_empty is pulled low.

[0098] At time t3, the second data (data1) is written into the address corresponding to the write pointer wr_ptr_n.

[0099] At time t4, the third piece of data (data2) is written to the address corresponding to the write pointer wr_ptr_n.

[0100] At time t5, the address corresponding to the write pointer wr_ptr_n is written with the fourth data (data3). At the same time, the value of the write pointer wr_ptr_n at this moment will be updated to 100 in the next beat.

[0101] At time t6, the value of the write pointer wr_ptr_n and the read pointer rd_ptr_n are opposite in all respects except the first bit. At this time, the data array is full, so the full flag fifo_full is pulled high (indicating full), and the write enable wr_en is pulled low to stop writing data, and the read enable rd_en is pulled high so that data can be read at the next moment.

[0102] At the same time, at time t6, the read enable signal rd_en is pulled high, and the data (data0) corresponding to the read pointer rd_ptr_n in the data array module is read out. The read pointer rd_ptr_n will be updated to (001) in the next cycle, no longer meeting the full flag generation condition. Therefore, the full flag fifo_full is pulled low (indicating that it is not full).

[0103] At time t7, the read pointer rd_ptr_n continues to read the second data (data1) at the corresponding position.

[0104] At time t8, the read pointer rd_ptr_n continues to read the third piece of data (data2) at the corresponding position.

[0105] At time t9, the read pointer rd_ptr_n continues to read the last piece of data (data3). In the next cycle, the values of the write pointer wr_ptr_n and the read pointer rd_ptr_n will be equal (100 and 100), so the empty flag fifo_empty is pulled high (that is, the data array module is now empty). The read enable rd_en is also pulled low to stop data reading.

[0106] Please continue reading Figure 6 If the source clock domain src_clk and the target clock domain dst_clk are in an asynchronous relationship, the workflow of the FIFO buffer when the target working mode is the asynchronous working mode is exemplified as follows:

[0107] (1) Write operation (source clock domain src_clk is regarded as write clock domain src_clk): First, the write pointer is updated. When the write enable wr_en is high and the full flag fifo_full is low, data is allowed to be written. At this time, the data wr_data is written to the data array module, and the binary write pointer wr_ptr_n is incremented to point to the next write address. At the same time, the binary write pointer wr_ptr_n at each moment will generate the corresponding Gray code write pointer wr_ptr_g through the Gray code conversion logic. It should be noted that the characteristic of Gray code is that only one bit changes between two adjacent values, which reduces the metastable problem during cross-clock domain transmission. Next, the write pointer is synchronized to the read clock domain. The Gray code write pointer wr_ptr_g is synchronized from the write clock domain src_clk to the read clock domain dst_clk through a two-stage synchronizer (which can be two flip-flops), thereby generating the synchronized write pointer wr_ptr_g_sync.

[0108] (2) Read operation (destination clock domain dst_clk is regarded as read clock domain dst_clk): Similarly, the read pointer is updated first. When the read enable rd_en is high and the empty flag fifo_empty is low, data is allowed to be read. At this time, the data rd_data is read from the read address rd_addr of the data array module, and the binary read pointer rd_ptr_n is incremented to point to the next read address. At the same time, the binary pointer rd_ptr_n at each moment generates the corresponding Gray code read pointer rd_ptr_g through the Gray code conversion logic. Then, the read pointer is synchronized to the write clock domain. The Gray code read pointer rd_ptr_g is synchronized to the write clock domain src_clk through a two-stage synchronizer (which can also be two flip-flops) to generate the synchronized read pointer rd_ptr_g_sync.

[0109] (3) Empty / Full Judgment: In the read clock domain dst_clk, compare the values of the synchronized write pointer wr_ptr_g_sync and the current Gray code read pointer rd_ptr_g. If they are equal, the data array module is judged to be empty. In the write clock domain, compare the values of the synchronized read pointer rd_ptr_g_syn and the current Gray code write pointer wr_ptr_g. If the upper two bits are opposite and the lower bits are equal, the data array module is judged to be full.

[0110] Further, please refer to Figure 8 , Figure 8 The target working mode is the signal timing diagram of asynchronous working mode, based on Figure 8 It can be seen that:

[0111] First, at time t0, the write enable signal wr_en in the write clock domain is low, indicating that a write operation has not yet been initiated. The binary write pointer wr_ptr_n and the Gray code write pointer wr_ptr_g both have an initial value of 000. After the first-level synchronization, the write pointer wr_ptr_g_sync1, and the write pointer wr_ptr_g_sync2, are both 000. In the read clock domain, the read enable signal rd_en is low, indicating that a read operation has not yet been initiated. The binary read pointer rd_ptr_n and the Gray code read pointer rd_ptr_g both have an initial value of 000. After the first-level synchronization, the read pointer rd_ptr_g_sync1, and the read pointer rd_ptr_g_sync2, are both 000. At this point, the Gray code write pointer wr_ptr_g and the Gray code read pointer rd_ptr_g are equal (000 and 000), satisfying the empty condition. Therefore, the empty flag fifo_empty is high, indicating that the data array module is not full. Therefore, the full flag fifo_full is low, indicating that the data array module is not full.

[0112] At time t1, the write enable wr_en in the write clock domain is pulled high, indicating the start of the write operation. The binary write pointer wr_ptr_n is updated to 001 in the next cycle, and the first data (data0) is written to its corresponding address. The Gray code write pointer wr_ptr_g is also converted to the corresponding Gray code 001;

[0113] At time t2, the write pointer wr_ptr_g_sync1 synchronizes with the Gray code write pointer wr_ptr_g and updates to 001, completing primary synchronization. Since the write pointer wr_ptr_g_sync2 remains at 000 after secondary synchronization (secondary synchronization not yet completed), the read clock domain remains unchanged, the read enable rd_en remains low, and the read pointer state remains unchanged. Similarly, the full flag fifo_full and the empty flag fifo_empty remain unchanged.

[0114] At time t3, the write pointer wr_ptr_g_sync2 synchronizes the value of the write pointer wr_ptr_g_sync1 after the first-level synchronization at the previous moment, and is updated to 001 in the next cycle to complete the second-level synchronization. At this time, the write pointer wr_ptr_g_sync2 after the second-level synchronization representing the Gray code pointer becomes 001, which no longer meets the empty judgment condition, so the empty flag fifo_empty is pulled low.

[0115] At time t4, the write operation continues in the write clock domain, the binary write pointer wr_ptr_n is incremented to 010 in the next cycle, and the second data (data1) is written to its corresponding address.

[0116] At time t5, the write operation continues in the write clock domain. The binary write pointer wr_ptr_n increments to 011 in the next cycle, and the third data (data2) is written to its corresponding address. The Gray code write pointer wr_ptr_g changes to 010.

[0117] At time t6, the write operation continues in the write clock domain. The binary write pointer wr_ptr_n in the write clock domain increments to 100 in the next cycle. The fourth data (data3) is written to its corresponding address, and the Gray code write pointer wr_ptr_g changes to 110. At this time, the full condition is met. That is, after comparing the read pointer rd_ptr_g_sync2 (000) after secondary synchronization with the current Gray code write pointer wr_ptr_g (110), it is found that the upper two bits of the two are opposite and the lower bits are equal. Therefore, the full flag fifo_full is pulled high, and the write enable wr_en is pulled low, stopping the write operation.

[0118] Correspondingly, at time t7, in the read clock domain, the read enable rd_en is pulled high to start the read operation; the binary read pointer rd_ptr_n increments to 001 in the next cycle, the Gray code read pointer rd_ptr_g converts to 001, and the first data data0 is read out.

[0119] It should be noted that since the read operation is in the destination clock domain, the rising edge of the destination clock domain dst_clk is marked, that is, Figure 8 At t7, t9, t11 and t12, Figure 8 At times t8 and t10, it can be seen that the Gray code read pointer is synchronized at two levels in the source clock domain.

[0120] At time t8, the read pointer rd_ptr_g_sync1 after primary synchronization synchronizes the value of the Gray code read pointer rd_ptr_g at the previous moment, and is updated to 001 in the next cycle. The read pointer rd_ptr_g_sync2 after secondary synchronization is still 000 (secondary synchronization is not completed).

[0121] At time t9, there is no write operation in the write clock domain, and the signal states remain unchanged. In the read clock domain, the binary read pointer rd_ptr_n increments to 010 in the next cycle, and the second data set data1 is read. The Gray code read pointer rd_ptr_g changes to 011.

[0122] At time t10, the read pointer rd_ptr_g_sync1 is synchronously updated to 011. After the secondary synchronization, the read pointer rd_ptr_g_sync2 completes the secondary synchronization and is updated to the previous cycle value of the Gray code read pointer rd_ptr_g_sync1, 001. At this point, rd_ptr_g_sync2 and wr_ptr_g no longer meet the full condition, and the full flag fifo_full is pulled low.

[0123] At time t11, there is no write operation in the write clock domain, and the signal states remain unchanged. In the read clock domain, the binary read pointer rd_ptr_n increments to 011 in the next cycle, and the Gray code read pointer rd_ptr_g changes to 010, and the third data data2 is read.

[0124] At time t12, there is no write operation in the write clock domain, and all signal states remain unchanged. In the read clock domain, the binary read pointer rd_ptr_n increments to 100 in the next cycle, and the Gray code read pointer rd_ptr_g transitions to 110, indicating that the fourth data entry is read. At this point, the empty condition is met: the synchronized write pointer wr_ptr_g_sync2 is equal to the current read pointer rd_ptr_g, indicating that the data array module is empty. Consequently, the empty flag fifo_empty is set high. This completes all data transfers.

[0125] The present application also provides a microprocessor architecture comprising a processor core, a memory, and a FIFO buffer of any of the above; the memory is communicatively connected to the processor core; and the processor core and the memory are each connected to the FIFO buffer. The specific definition of the FIFO buffer can be found in the definition of the FIFO buffer above and will not be repeated here.

[0126] A chip is also provided in an embodiment of the present application, which includes the above-mentioned microprocessor architecture. For the specific definition of the microprocessor architecture, please refer to the definition of the microprocessor architecture above, which will not be repeated here.

[0127] Although the embodiments of the present application have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations shall fall within the scope defined by the appended claims.

[0128] The FIFO buffer and the method for switching the operating mode of the FIFO buffer described in the above embodiments can be implemented by a computer chip or entity, or by a product having a certain function. A typical implementation device is a computer. Specifically, the computer can be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smartphone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0129] For the convenience of description, the above devices are described as being divided into various units according to their functions. Of course, when implementing this application, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0130] Those skilled in the art will appreciate that the embodiments of the present application may be provided as a FIFO buffer and a method for switching the working mode of a FIFO buffer. Therefore, the present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware.

[0131] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0132] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0133] Each embodiment in this specification is described in a progressive manner. Similar parts between the embodiments can be referred to in detail. Each embodiment focuses on the differences from other embodiments. Since it is basically similar to the method embodiment, the description is relatively simple. For relevant parts, refer to the partial description of the method embodiment.

[0134] The foregoing is merely an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included within the scope of the claims of the present application.

[0135] Although the embodiments of the present application have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations shall fall within the scope defined by the appended claims.

Claims

1. A FIFO buffer, characterized in that: Serving as a connecting component between a source clock domain and a destination clock domain during cross-clock domain data transmission, the FIFO buffer comprises a frequency decoding module, a mode selection logic module and a data array module connected in sequence; The frequency decoding module is configured to output an operating mode selection parameter based on a frequency phase relationship between the source clock domain and the destination clock domain; wherein the operating mode selection parameter is used to indicate a target operating mode of the FIFO buffer; The mode selection logic module is configured to control the FIFO buffer to switch to the target working mode to operate the data array module in the target working mode, and the target working mode is a synchronous working mode or an asynchronous working mode.

2. The FIFO buffer according to claim 1, wherein: The mode selection logic module is further configured to control the FIFO buffer to switch to a synchronous working mode when the working mode selection parameter indicates that the frequency-phase relationship is a same-frequency and same-phase relationship, so as to operate the data array module in the synchronous working mode.

3. The FIFO buffer according to claim 1, wherein: The mode selection logic module is further configured to control the FIFO buffer to switch to an asynchronous working mode when the working mode selection parameter indicates that the frequency-phase relationship is not a same-frequency and same-phase relationship, so as to operate the data array module in the asynchronous working mode.

4. The FIFO buffer according to claim 1, wherein: The mode selection logic module is further configured to use a natural binary-coded read / write pointer if the FIFO buffer switches to the synchronous operating mode, and directly generate a first empty / full flag based on the natural binary-coded read / write pointer value to indicate the storage status of the data array module.

5. The FIFO buffer according to claim 1, wherein: The mode selection logic module is further configured to, if the FIFO buffer switches to the asynchronous operating mode, use the Gray-coded read and write pointers, perform two-level synchronization on the Gray-coded read and write pointers across clock domains, and generate a second empty and full flag based on the read and write pointer values after the two-level synchronization to indicate the storage status of the data array module.

6. The FIFO buffer according to claim 1, wherein: The mode selection logic module includes a selection circuit and a configuration register; The configuration register is connected to the frequency decoding module and is configured to receive and store the operating mode selection parameter; The selection circuit is connected to the configuration register and the data array module respectively, and is configured to control the FIFO buffer to switch to the target working mode based on the working mode selection parameter, so as to operate the data array module in the target working mode.

7. The FIFO buffer according to any one of claims 1 to 6, characterized in that: The frequency decoding module is connected to the frequency cutting control module; The frequency cutting control module is configured to send a frequency cutting command operation code to the frequency decoding module; the frequency cutting command operation code carries the source clock domain frequency and the destination clock domain frequency; The frequency decoding module is further configured to perform analysis based on the source clock domain frequency and the destination clock domain frequency to obtain a frequency phase relationship between the source clock domain and the destination clock domain.

8. The FIFO buffer according to claim 7, wherein: The frequency cutting control module is connected to the frequency cutting execution module; the frequency cutting command operation code also carries the command type; The frequency decoding module is further configured to obtain a frequency phase relationship between the source clock domain and the destination clock domain based on a comparison of the encoded value of the source clock domain frequency and the encoded value of the destination clock domain frequency when the command type indicates that the frequency cutting execution module completes the frequency cutting action.

9. The FIFO buffer according to claim 7, wherein: The frequency cutting control module is further configured to, if a frequency cutting request issued by the frequency cutting control module passes arbitration, send a clear control signal to the FIFO buffer to suspend writing data into the data array module, so that the data array module is gradually cleared; wherein, when the data array module is cleared, the frequency cutting control module issues the frequency cutting command operation code.

10. A method for switching the working mode of a FIFO buffer, characterized in that: The FIFO buffer is used as a connection component between the source clock domain and the destination clock domain during cross-clock domain data transmission. The FIFO buffer includes a frequency decoding module, a mode selection logic module and a data array module connected in sequence; The method further comprises: Outputting an operating mode selection parameter based on a frequency phase relationship between the source clock domain and the destination clock domain through the frequency decoding module; wherein the operating mode selection parameter is used to indicate a target operating mode of the FIFO buffer; The mode selection logic module controls the FIFO buffer to switch to the target working mode, so as to operate the data array module in the target working mode. The target working mode is a synchronous working mode or an asynchronous working mode.

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