Multi-device timing control method

Abstract

The invention discloses a multi-device timing control method, and the method carries out the timing control of each to-be-executed instruction, and executes each to-be-executed instruction based on an execution time sequence, guarantees the instruction sending precision to reach a sub-millisecond level, and meets the high-real-time task demands. Besides, dynamic instruction adjustment is realized through an address jump function, so that the method adapts to variable task scenes, and the flexibility of multi-device timing control is improved; in addition, the block random access memory and the nonvolatile memory support multiple groups of large-scale instruction sets, so that the rewriting overhead is reduced, the hardware upgrading cost can be reduced, functions can be expanded through software configuration, and the system reusability is improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a multi-device timing control method. Background Art

[0002] Multi-device timing control technology is commonly used in multi-device collaboration scenarios to meet the needs of multi-device collaborative tasks. Existing technologies typically implement multi-device timing control using a microcontroller combined with external memory. Parameters are input via a serial port or wireless communication, stored, and then read and executed by the microcontroller in a predetermined sequence. Commands are often transmitted using software timers and sent to the target device via general-purpose input / output ports or other interfaces.

[0003] However, the above-mentioned multi-device timing control method has the problem of poor flexibility. Summary of the Invention

[0004] The present application aims to at least solve the technical problems existing in the prior art. To this end, in a first aspect, the present application proposes a multi-device timing control method, the method comprising:

[0005] After power-on, the custom parameters are loaded into the block random access memory through the field programmable gate array; wherein the custom parameters are stored in the non-volatile memory of the field programmable gate array;

[0006] Reading a set of instruction sets in a block random access memory based on a sending instruction through a field programmable gate array; wherein the set of instruction sets includes a plurality of instructions to be executed;

[0007] For each instruction to be executed, determining the execution timing corresponding to the instruction to be executed based on the sending time field in the custom parameter through the field programmable gate array;

[0008] Based on each execution timing, the instructions to be executed are executed based on the custom parameters through the field programmable gate array until a preset maximum number of reads is reached or a preset termination condition is met.

[0009] In one possible implementation, the method further includes:

[0010] Obtain custom parameters edited using the ground test software; the ground test software supports eight independent custom parameter groups, each corresponding to an instruction set or a task to be executed. An instruction set can contain up to 256 instructions to be executed.

[0011] Inject custom parameters into the FPGA via the serial port.

[0012] In one possible implementation, injecting custom parameters into a field programmable gate array via a serial port includes:

[0013] The ground test software packages the custom parameters into a 40-byte instruction. The 40-byte instruction includes a 2-byte frame header, a 1-byte chip select, a 1-byte target address, a 2-byte send time, 27-byte custom data, a 1-byte instruction jump address, a 1-byte counter, a 2-byte checksum, and a 1-byte frame trailer.

[0014] The 40-byte instruction is sent to the field programmable gate array through the serial port by the ground test software.

[0015] In one possible implementation, the method further includes:

[0016] Writing custom data in custom parameters into internal block random access memory through field programmable gate array;

[0017] After all the customized data are sent, the ground test software sends a save instruction to the field programmable gate array;

[0018] The field programmable gate array saves the custom data into the non-volatile memory based on the save instruction.

[0019] In one possible implementation, executing instructions to be executed based on custom parameters using a field programmable gate array includes:

[0020] The corresponding target device is specified based on the target address in the custom parameter through the field programmable gate array, and the to-be-executed instruction is sent to the target device, so that the target device executes the received to-be-executed instruction.

[0021] In one possible implementation, the method further includes:

[0022] Based on the instruction jump address in the custom parameter, the field programmable gate array jumps to the specified address corresponding to the instruction jump address and sends the custom data in the custom parameter.

[0023] In one possible implementation, writing the custom data in the custom parameters into an internal block random access memory through a field programmable gate array includes:

[0024] Check the checksum and generate a check result;

[0025] When the check result is successful, the custom data in the custom parameters are written into the internal block random access memory through the field programmable gate array.

[0026] In a second aspect, the present application provides a multi-device timing control apparatus, the apparatus comprising:

[0027] A loading module, configured to load the custom parameters into the block random access memory through the field programmable gate array after power-on; wherein the custom parameters are stored in the non-volatile memory of the field programmable gate array;

[0028] A reading module, configured to read a set of instruction sets in a block random access memory based on a sent instruction through a field programmable gate array; wherein the set of instruction sets includes a plurality of instructions to be executed;

[0029] A determination module, configured to determine, for each instruction to be executed, an execution timing corresponding to the instruction to be executed based on a sending time field in the custom parameter through a field programmable gate array;

[0030] The execution module is used to execute the instructions to be executed based on the custom parameters through the field programmable gate array based on each execution timing until a preset maximum number of reads is reached or a preset termination condition is met.

[0031] In a possible implementation manner, the multi-device timing control apparatus is further configured to:

[0032] Obtain custom parameters edited using the ground test software; the ground test software supports eight independent custom parameter groups, each corresponding to an instruction set or a task to be executed. An instruction set can contain up to 256 instructions to be executed.

[0033] Inject custom parameters into the FPGA via the serial port.

[0034] In a possible implementation manner, the multi-device timing control apparatus is further configured to:

[0035] The ground test software packages the custom parameters into a 40-byte instruction. The 40-byte instruction includes a 2-byte frame header, a 1-byte chip select, a 1-byte target address, a 2-byte send time, 27-byte custom data, a 1-byte instruction jump address, a 1-byte counter, a 2-byte checksum, and a 1-byte frame trailer.

[0036] The 40-byte instruction is sent to the field programmable gate array through the serial port by the ground test software.

[0037] In a possible implementation manner, the multi-device timing control apparatus is further configured to:

[0038] Writing custom data in custom parameters into internal block random access memory through field programmable gate array;

[0039] After all the customized data are sent, the ground test software sends a save instruction to the field programmable gate array;

[0040] The field programmable gate array saves the custom data into the non-volatile memory based on the save instruction.

[0041] In a possible implementation, the execution module is specifically configured to:

[0042] The corresponding target device is specified based on the target address in the custom parameter through the field programmable gate array, and the to-be-executed instruction is sent to the target device, so that the target device executes the received to-be-executed instruction.

[0043] In a possible implementation manner, the multi-device timing control apparatus is further configured to:

[0044] Based on the instruction jump address in the custom parameter, the field programmable gate array jumps to the specified address corresponding to the instruction jump address and sends the custom data in the custom parameter.

[0045] In a possible implementation manner, the multi-device timing control apparatus is further configured to:

[0046] Check the checksum and generate a check result;

[0047] When the check result is successful, the custom data in the custom parameters are written into the internal block random access memory through the field programmable gate array.

[0048] The third aspect of the present application proposes an electronic device, which includes a processor and a memory, wherein the memory stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by the processor to implement the multi-device timing control method as described in the first aspect.

[0049] In the fourth aspect of the present application, a computer-readable storage medium is proposed, in which at least one instruction, at least one program, a code set or an instruction set is stored. The at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by a processor to implement the multi-device timing control method as described in the first aspect.

[0050] The embodiments of the present application have the following beneficial effects:

[0051] An embodiment of the present application provides a multi-device timing control method, which includes: after power-on, loading custom parameters into a block random access memory through a field programmable gate array; wherein the custom parameters are stored in a non-volatile memory of the field programmable gate array; reading a group of instruction sets in the block random access memory based on a sent instruction through the field programmable gate array; wherein a group of instruction sets includes multiple instructions to be executed; for each instruction to be executed, determining the execution timing corresponding to the instruction to be executed based on a sending time field in the custom parameters through the field programmable gate array; based on each execution timing, executing the instruction to be executed based on the custom parameters through the field programmable gate array until a preset maximum number of reads is reached or a preset termination condition is met. This solution ensures sub-millisecond instruction sending accuracy by controlling the timing of each instruction to be executed and executing the instructions to be executed based on the execution sequence, meeting the requirements of high real-time tasks. In addition, dynamic instruction adjustment is achieved through the address jump function to adapt to changing task scenarios and improve the flexibility of multi-device timing control. In addition, block random access memory and non-volatile memory support multiple large-scale instruction sets, reducing rewrite overhead and hardware upgrade costs. Functions can be expanded through software configuration to improve system reusability. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 A block diagram of a computer device provided in an embodiment of the present application;

[0053] Figure 2 A flowchart of a multi-device timing control method provided in an embodiment of the present application;

[0054] Figure 3 A flowchart of steps for storing custom parameters provided in an embodiment of the present application;

[0055] Figure 4 A flowchart of the steps of injecting a field programmable gate array into a field programmable gate array according to an embodiment of the present application;

[0056] Figure 5 A flowchart of the steps of saving to a non-volatile memory provided in an embodiment of the present application;

[0057] Figure 6 A flowchart of the steps of writing to an internal block random access memory provided by an embodiment of the present application;

[0058] Figure 7 A schematic diagram of the architecture of a multi-device timing control system provided in an embodiment of the present application;

[0059] Figure 8 A schematic diagram of BRAM address division provided in an embodiment of the present application;

[0060] Figure 9 A schematic diagram of FLASH address division provided in an embodiment of the present application;

[0061] Figure 10 This is a structural block diagram of a multi-device timing control device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0062] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0063] In existing technology, multi-device timing control is typically implemented using a microcontroller combined with external memory. Parameters are input via a serial port or wireless communication, stored, and then read and executed by the MCU in a predetermined order. Instructions are often transmitted via software timers and sent to the target device via a general-purpose input / output (GPIO) or other interface. Typical systems support a limited number of task groups (e.g., 1-2) and instructions (e.g., dozens), with a relatively small storage capacity (typically a few KB to tens of KB).

[0064] In existing solutions, the instruction sequence and sending order are fixed, making it difficult to adjust dynamically (such as inserting or jumping to specific instructions), and unable to adapt to task changes. In addition, the reliance on software timers results in the accuracy of instruction sending being limited by the MCU clock and task scheduling overhead, which cannot meet high real-time requirements (such as sub-millisecond control). In addition, the parameter storage capacity is small, making it difficult to support large-scale instruction sets, and the memory needs to be frequently rewritten when switching between multiple groups of tasks, which is inefficient. In addition, the number of device ports and task groups supported is limited, making it difficult to expand to multi-device collaboration scenarios (such as more than 10 devices or multi-tasking mode).

[0065] Based on this, the present application proposes a multi-device timing control method. This scheme ensures that the instruction sending accuracy reaches sub-millisecond level by performing timing control on each instruction to be executed and executing the instruction to be executed based on the execution sequence, thereby meeting the requirements of high real-time tasks; in addition, dynamic instruction adjustment is achieved through the address jump function to adapt to changing task scenarios and improve the flexibility of multi-device timing control; in addition, block random access memory and non-volatile memory support multiple groups of large-scale instruction sets, reducing rewriting overhead and hardware upgrade costs. Functions can be expanded through software configuration to improve system reusability.

[0066] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "multiple" means two or more. In addition, the use of "based on" or "according to" means openness and inclusiveness, because the process, steps, calculations or other actions "based on" or "according to" one or more of the conditions or values may be based on additional conditions or values beyond the stated in practice.

[0067] The multi-device timing control method provided in the present application can be applied to computer devices (electronic devices), which can be servers or terminals. The server can be a single server or a server cluster composed of multiple servers. The embodiments of the present application do not specifically limit this. The terminal can be, but is not limited to, various personal computers, laptops, smart phones, tablet computers and portable wearable devices.

[0068] Take the computer device as an example, Figure 1 A block diagram of a server is shown, such as Figure 1 As shown, a server may include a processor and memory connected via a system bus. The server's processor is configured to provide computing and control capabilities. The server's memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operating system and computer program stored in the non-volatile storage medium. When executed by the processor, the computer program implements a multi-device timing control method.

[0069] Those skilled in the art will understand that Figure 1 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the server to which the solution of the present application is applied. Optionally, the server may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0070] It should be noted that the execution subject of the embodiments of the present application can be a computer device or a multi-device timing control device. The following method embodiments will be described using a computer device as the execution subject.

[0071] Figure 2 This is a flowchart of a multi-device timing control method provided by an embodiment of the present application. Figure 2 As shown, the method includes the following steps:

[0072] Step 202: After power-on, the user-defined parameters are loaded into the block random access memory through the field programmable gate array.

[0073] Among them, the custom parameters are stored in the non-volatile memory of the field programmable gate array. The custom parameters can have many variations in actual use to adapt to actual scenarios. For example, some instruction parameters are very long, exceeding 27 bytes, or 8 groups of custom instruction sets are not enough, which can be expanded to 16 groups or 64 groups.

[0074] Therefore, during use, you can first determine the number of instruction sets that require flexible configuration in the actual use scenario. For example, this number can be 8, 16, 32, etc., and then determine the maximum number of instructions to be executed that the instruction set can accommodate. If the maximum number of instructions to be executed that the instruction set can accommodate is 128, and the size of a custom parameter is 32, then 16*128*32=65536 (bytes). Here, 65536 is the size of a data block in the external memory. Using the effective memory capacity after triple modular redundancy / 65536, you can know how many instruction sets can be stored.

[0075] In some optional embodiments, such as Figure 3 As shown, Figure 3 A flowchart of steps for storing custom parameters provided in an embodiment of the present application includes:

[0076] Step 302: Obtain the custom parameters edited by the ground test software.

[0077] Among them, the ground test software supports 8 independent custom parameter groups. One custom parameter group corresponds to an instruction set or a task to be executed. An instruction set includes up to 256 instructions to be executed. Each instruction to be executed can include a timestamp, target port and custom data, etc.

[0078] Step 304: Inject the custom parameters into the field programmable gate array through the serial port.

[0079] After obtaining the custom parameters, the custom parameters can be injected into the field programmable gate array (FPGA) through the serial port. Figure 4 As shown, Figure 4 A flowchart of steps for injecting into a field programmable gate array provided in an embodiment of the present application includes:

[0080] Step 402: Pack the custom parameters into 40-byte instructions through ground test software.

[0081] Step 404: Send the 40-byte instruction to the field programmable gate array through the serial port via the ground test software.

[0082] The 40-byte instruction includes a 2-byte frame header, a 1-byte chip select, a 1-byte target address, a 2-byte send time, 27 bytes of custom data, a 1-byte instruction jump address, a 1-byte counter, a 2-byte checksum, and a 1-byte frame trailer.

[0083] The above-mentioned custom parameter injection process is implemented using ground test software. The custom parameters are injected into the internal block random access memory (BRAM) through the serial port and saved in the non-volatile memory FLASH. It supports repeated reading of parameters, timed transmission and data insertion functions. Its core functions include: supporting the timed transmission of instructions and parameters, and reading a maximum of 7680 bytes of custom parameters; providing 8 groups of independent parameter group configurations, adapting to multi-tasking mode, and each group supports 256 parameters to be saved. The address jump insertion data function is implemented to adjust the parameter sending order. The length of each custom parameter sent is fixed at 40 bytes, the custom data area is 27 bytes, and the output interval is controlled by internal pulses in units of 0.1 seconds.

[0084] The instruction frame format includes fields such as a frame header (0xEE, 0xCC), chip select (supporting 8 BRAM caches), target address, transmit time (0.1 seconds, 0-65535), 27 bytes of custom data, jump address, and checksum. The transmit time can be flexibly set based on actual scenarios; the 0.1 second value is for illustrative purposes only. Eight 8KB RAMs (total 64KB) are designed, independently accessed via chip select signals BRAM[0:7] and collectively stored when saved to FLASH. The FLASH uses 128Mbit serial flash memory (HWD25Q128AAS), with a triple-module redundant design and an effective capacity of 4MB. It can store 64 sets of 64KB data and theoretically supports 512 sets of parameters. Upon power-up, the system performs a self-test and loads custom parameters. The read mode starts at address 0 and ends when the jump address is 0, the transmit time is 65535, or 256 reads are completed, ensuring flexible and efficient task execution.

[0085] The instruction format is described in the following table:

[0086]

[0087]

[0088] The contents stored in the BRAM corresponding to the chip select and target address are shown in the following table:

[0089]

[0090]

[0091] In some optional embodiments, such as Figure 5 As shown, Figure 5 A flowchart of the steps of saving to a non-volatile memory provided in an embodiment of the present application includes:

[0092] Step 502: Write the custom data in the custom parameters into the internal block random access memory through the field programmable gate array.

[0093] Step 504: After all the customized data are sent, the ground test software sends a save instruction to the field programmable gate array.

[0094] Step 506: The field programmable gate array saves the custom data into the non-volatile memory based on the save instruction.

[0095] Among them, the user edits the custom parameters through the ground test software or serial port assistant, with a maximum of 256 instructions per group. The ground test software can package the custom parameters into 40-byte instructions, and then send the instructions to the field programmable gate array through the serial port. The field programmable gate array writes the received custom data into the internal BRAM. After all the custom data is sent, the ground test software sends a save instruction to the field programmable gate array, and the field programmable gate array finally saves the custom data from the BRAM to the FLASH for long-term storage. Optionally, the model HWD25Q128AAS, 16MB FLASH can be used. Optionally, the FLASH can adopt a triple-module redundant design. The specific design method can refer to the existing technology and will not be repeated here to ensure storage reliability.

[0096] In some optional embodiments, such as Figure 6 As shown, Figure 6 A flowchart of the steps of writing to an internal block random access memory provided in an embodiment of the present application includes:

[0097] Step 602: Check the checksum and generate a check result.

[0098] Step 604: If the check result is successful, the custom data in the custom parameters are written into the internal block random access memory through the field programmable gate array.

[0099] The checksum is checked to verify data integrity. After obtaining the check result, if the check result is successful, the custom data in the custom parameters is written to the internal block random access memory through the field programmable gate array. If the check result is a check failure, the write is rejected.

[0100] Step 204: Read a set of instruction sets in the block random access memory based on the sent instruction through the field programmable gate array.

[0101] An instruction set contains multiple instructions to be executed. After the system is powered on, the FPGA automatically loads the custom data from the Flash memory into the BRAM. Sending instructions causes the FPGA to read an instruction set from groups 0 to 7 in the BRAM. The eight BRAM caches correspond to different tasks or instruction sets.

[0102] Step 206: For each instruction to be executed, determine the execution timing corresponding to the instruction to be executed based on the sending time field in the custom parameter through the field programmable gate array.

[0103] Among them, for each instruction to be executed, the execution timing is controlled by the field programmable gate array based on the sending time field in the custom parameters. Specifically, if the sending time field is 0, it is executed immediately; if the sending time field is 65535, the task is terminated; if the sending time field is other values, it is executed relative to 0.1 seconds * the sending time of the previous instruction.

[0104] Step 208 : Based on each execution sequence, execute the to-be-executed instruction based on the custom parameters through the field programmable gate array until a preset maximum number of reads is reached or a preset termination condition is satisfied.

[0105] After the execution sequence of each instruction to be executed is obtained, the instruction to be executed can be executed based on the custom parameters through the field programmable gate array.

[0106] In some optional embodiments, a field programmable gate array can be used to specify a corresponding target device based on the target address in the custom parameter, and a to-be-executed instruction can be sent to the target device so that the target device executes the received to-be-executed instruction. Among them, the target port (0-9) specifies the corresponding target device, so that the to-be-executed instruction can be sent to the corresponding target device according to the corresponding target port number. This application supports 10 target ports and 8 groups of tasks, adapts to multi-device collaboration, and can promote the development of multi-device collaboration technology in aerospace, industry and other fields, and improve the reliability of task execution.

[0107] In some optional embodiments, a field programmable gate array (FPGA) can be used to jump to a specified address corresponding to the instruction jump address in a custom parameter and send the custom data in the custom parameter. Depending on the instruction jump address (1-255), the program jumps to the specified address and sends the custom data at that address; if the address is 0, the task is terminated. This address jump function enables dynamic instruction adjustment, adapting to changing task scenarios and improving the flexibility of multi-device timing control.

[0108] In some optional embodiments, custom data is used to define instruction content, such as controlling camera exposure, sensor triggering, or servo platform rotation, and ultimately terminates execution when a preset maximum number of reads is reached or a preset termination condition is met. Optionally, the preset maximum number of reads can be 256, and the preset termination condition can be customized based on experience.

[0109] For example, the user needs to configure three instructions to be executed in BRAM group 0 to implement the following functions:

[0110] 1. Immediately send a rotation command to port 0x01 (PTZ) (corresponding data A0 01 00 5A).

[0111] 2. After 0.5 seconds, send a photo taking command to port 0x02 (camera) (corresponding to data B1 02).

[0112] 3. After 1 second, send a collection command to port 0x03 (sensor) (corresponding data C3 04FF).

[0113] 4. Automatically terminate after execution is completed.

[0114] The specific implementation process is as follows: First, you need to edit the custom parameters obtained through the ground test software, as shown in the following table:

[0115]

[0116] Detailed data description, taking instruction 1 as an example:

[0117]

[0118] Next, the 40-byte instruction EE CC 00 00 00 000104...D9, which packages the custom parameters, is obtained. The checksum is then checked. If the check succeeds, an ACK character (0x55) and an updated counter (0x01) are returned. If the check fails, a NAK (0xFF) is returned.

[0119] After the check succeeds, the content can be written to the BRAM group 0 address 0x00, that is, 0000:00 00 0104A0 01 005A [filled to 31 bytes] 01 00, where the transmission time is 0, the port is 0x01, the data length is 4, and the jump address is 0x01. Finally, it is stored in FLASH, that is, Sector0:00 00 01 04... (the complete 64KB BRAM group 0 data).

[0120] Then, the execution process can be:

[0121] 1. Start instruction 0x00 (execute immediately):

[0122] Output to port 0x01: A0 01 00 5A (PTZ rotation)

[0123] Jump to address 0x01, counter +1

[0124] 2. Execute instruction 0x01 after 0.5 seconds:

[0125] Output to port 0x02: B1 02 (camera photo)

[0126] Jump to address 0x02, counter +1

[0127] 3. Execute instruction 0x02 after 1 second:

[0128] Output to port 0x03: C3 04FF (sensor acquisition)

[0129] Jump address 0x00 (termination condition), counter +1

[0130] 4. The termination condition is met and the task is completed

[0131] Finally, the output data is shown in the following table:

[0132]

[0133] In some optional embodiments, the present application also provides a configurable multi-device timing control system based on FPGA, which is designed for multi-device collaborative scenarios that require high-precision timing control, such as optoelectronic loads. The system achieves precise scheduling and execution of multi-device instructions through flexible parameter configuration, hardware-level timing control, efficient storage management and scalability optimization. The system architecture is divided into a ground configuration layer (ground test software), a control layer (FPGA), a storage layer (FLASH) and an execution layer (target device), supporting multi-tasking mode switching, dynamic parameter loading and instruction timing control, such as Figure 7 As shown, Figure 7 A schematic diagram of the architecture of a multi-device timing control system provided in an embodiment of the present application.

[0134] The system consists of ground test software, serial port, FPGA, FLASH, and custom device, also known as target device. The ground software edits parameters and injects them into the FPGA through the serial port. The FPGA writes the parameters into the internal BRAM and saves them to the FLASH. After power-on, the parameters are automatically loaded from the FLASH into the internal BRAM and wait for execution. The FPGA is the core controller, responsible for instruction parsing, timing transmission, and data management. The internal BRAM of the FPGA provides 8 groups of 8KB cache, totaling 64KB, with 256 instructions per group, such as Figure 8 As shown, Figure 8 A BRAM address division diagram provided in an embodiment of the present application. The FLASH model is HWD25Q128AAS, 128Mbit, with an effective capacity of 4MB after triple-module redundancy design, to achieve long-term storage, such as Figure 9 As shown, Figure 9 A schematic diagram of FLASH address division provided in an embodiment of the present application. Custom devices correspond to target ports 0-9.

[0135] The present application provides a multi-device timing control method, which includes: after power-on, loading custom parameters into a block random access memory through a field programmable gate array; wherein the custom parameters are stored in a non-volatile memory of the field programmable gate array; reading a group of instruction sets in the block random access memory based on a sent instruction through the field programmable gate array; wherein the group of instruction sets includes multiple instructions to be executed; for each instruction to be executed, determining the execution timing corresponding to the instruction to be executed based on a sending time field in the custom parameters through the field programmable gate array; based on each execution timing, executing the instruction to be executed based on the custom parameters through the field programmable gate array until a preset maximum number of reads is reached or a preset termination condition is met. This solution ensures sub-millisecond instruction sending accuracy by controlling the timing of each instruction to be executed and executing the instructions to be executed based on the execution sequence, meeting the requirements of high real-time tasks. In addition, dynamic instruction adjustment is achieved through the address jump function to adapt to changing task scenarios and improve the flexibility of multi-device timing control. In addition, block random access memory and non-volatile memory support multiple large-scale instruction sets, reducing rewrite overhead and hardware upgrade costs. Functions can be expanded through software configuration to improve system reusability.

[0136] It should be understood that, although the various steps in the flowcharts involved in the various embodiments described above are displayed in sequence according to the instructions of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the flowcharts involved in the various embodiments described above can include multiple steps or multiple stages, and these steps or stages are not necessarily executed and completed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0137] Figure 10 This is a structural block diagram of a multi-device timing control device provided in an embodiment of the present application.

[0138] like Figure 10 As shown, the multi-device timing control apparatus 1000 includes:

[0139] The loading module 1002 is used to load the custom parameters into the block random access memory through the field programmable gate array after power is turned on; wherein the custom parameters are stored in the non-volatile memory of the field programmable gate array.

[0140] The reading module 1004 is configured to read a set of instruction sets in the block random access memory based on a sent instruction through a field programmable gate array; wherein the set of instruction sets includes a plurality of instructions to be executed.

[0141] The determination module 1006 is configured to determine, for each instruction to be executed, an execution sequence corresponding to the instruction to be executed based on the sending time field in the custom parameter through a field programmable gate array.

[0142] The execution module 1008 is configured to execute the to-be-executed instructions based on the custom parameters through the field programmable gate array based on each execution sequence until a preset maximum number of reads is reached or a preset termination condition is satisfied.

[0143] Regarding the apparatus in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method and will not be elaborated on here. Each module in the above multi-device timing control apparatus can be implemented in whole or in part through software, hardware, or a combination thereof. Each of the above modules can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software so that the processor can call and execute the operations of each of the above modules.

[0144] In one embodiment of the present application, a computer device is provided. The computer device includes a memory and a processor. The memory stores a computer program. When the processor executes the computer program, the following steps are implemented:

[0145] After power-on, the custom parameters are loaded into the block random access memory through the field programmable gate array; wherein the custom parameters are stored in the non-volatile memory of the field programmable gate array;

[0146] Reading a set of instruction sets in a block random access memory based on a sending instruction through a field programmable gate array; wherein the set of instruction sets includes a plurality of instructions to be executed;

[0147] For each instruction to be executed, determining the execution timing corresponding to the instruction to be executed based on the sending time field in the custom parameter through the field programmable gate array;

[0148] Based on each execution timing, the instructions to be executed are executed based on the custom parameters through the field programmable gate array until a preset maximum number of reads is reached or a preset termination condition is met.

[0149] In one embodiment of the present application, when the processor executes the computer program, the processor further implements the following steps:

[0150] Obtain custom parameters edited using the ground test software; the ground test software supports eight independent custom parameter groups, each corresponding to an instruction set or a task to be executed. An instruction set can contain up to 256 instructions to be executed.

[0151] Inject custom parameters into the FPGA via the serial port.

[0152] In one embodiment of the present application, when the processor executes the computer program, the processor further implements the following steps:

[0153] The ground test software packages the custom parameters into a 40-byte instruction. The 40-byte instruction includes a 2-byte frame header, a 1-byte chip select, a 1-byte target address, a 2-byte send time, 27-byte custom data, a 1-byte instruction jump address, a 1-byte counter, a 2-byte checksum, and a 1-byte frame trailer.

[0154] The 40-byte instruction is sent to the field programmable gate array through the serial port by the ground test software.

[0155] In one embodiment of the present application, when the processor executes the computer program, the processor further implements the following steps:

[0156] Writing custom data in custom parameters into internal block random access memory through field programmable gate array;

[0157] After all the customized data are sent, the ground test software sends a save instruction to the field programmable gate array;

[0158] The field programmable gate array saves the custom data into the non-volatile memory based on the save instruction.

[0159] In one embodiment of the present application, when the processor executes the computer program, the processor further implements the following steps:

[0160] The corresponding target device is specified based on the target address in the custom parameter through the field programmable gate array, and the to-be-executed instruction is sent to the target device, so that the target device executes the received to-be-executed instruction.

[0161] In one embodiment of the present application, when the processor executes the computer program, the processor further implements the following steps:

[0162] Based on the instruction jump address in the custom parameter, the field programmable gate array jumps to the specified address corresponding to the instruction jump address and sends the custom data in the custom parameter.

[0163] In one embodiment of the present application, when the processor executes the computer program, the processor further implements the following steps:

[0164] Check the checksum and generate a check result;

[0165] When the check result is successful, the custom data in the custom parameters are written into the internal block random access memory through the field programmable gate array.

[0166] The computer device provided in the embodiment of the present application has similar implementation principles and technical effects to those of the above-mentioned method embodiment, and will not be described in detail here.

[0167] In one embodiment of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented:

[0168] After power-on, the custom parameters are loaded into the block random access memory through the field programmable gate array; wherein the custom parameters are stored in the non-volatile memory of the field programmable gate array;

[0169] Reading a set of instruction sets in a block random access memory based on a sending instruction through a field programmable gate array; wherein the set of instruction sets includes a plurality of instructions to be executed;

[0170] For each instruction to be executed, determining the execution timing corresponding to the instruction to be executed based on the sending time field in the custom parameter through the field programmable gate array;

[0171] Based on each execution timing, the instructions to be executed are executed based on the custom parameters through the field programmable gate array until a preset maximum number of reads is reached or a preset termination condition is met.

[0172] In one embodiment of the present application, when the computer program is executed by a processor, the following steps are further implemented:

[0173] Obtain custom parameters edited using the ground test software; the ground test software supports eight independent custom parameter groups, each corresponding to an instruction set or a task to be executed. An instruction set can contain up to 256 instructions to be executed.

[0174] Inject custom parameters into the FPGA through the serial port.

[0175] In one embodiment of the present application, when the computer program is executed by a processor, the following steps are further implemented:

[0176] The ground test software packages the custom parameters into a 40-byte instruction. The 40-byte instruction includes a 2-byte frame header, a 1-byte chip select, a 1-byte target address, a 2-byte send time, 27-byte custom data, a 1-byte instruction jump address, a 1-byte counter, a 2-byte checksum, and a 1-byte frame trailer.

[0177] The 40-byte instruction is sent to the field programmable gate array through the serial port by the ground test software.

[0178] In one embodiment of the present application, when the computer program is executed by a processor, the following steps are further implemented:

[0179] Writing custom data in custom parameters into internal block random access memory through field programmable gate array;

[0180] After all the customized data are sent, the ground test software sends a save instruction to the field programmable gate array;

[0181] The field programmable gate array saves the custom data into the non-volatile memory based on the save instruction.

[0182] In one embodiment of the present application, when the computer program is executed by a processor, the following steps are further implemented:

[0183] The corresponding target device is specified based on the target address in the custom parameter through the field programmable gate array, and the to-be-executed instruction is sent to the target device, so that the target device executes the received to-be-executed instruction.

[0184] In one embodiment of the present application, when the computer program is executed by a processor, the following steps are further implemented:

[0185] Based on the instruction jump address in the custom parameter, the field programmable gate array jumps to the specified address corresponding to the instruction jump address and sends the custom data in the custom parameter.

[0186] In one embodiment of the present application, when the computer program is executed by a processor, the following steps are further implemented:

[0187] Check the checksum and generate a check result;

[0188] When the check result is successful, the custom data in the custom parameters are written into the internal block random access memory through the field programmable gate array.

[0189] The computer-readable storage medium provided in this embodiment has similar implementation principles and technical effects to those of the above-mentioned method embodiment, and will not be described in detail here.

[0190] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through a computer program, which can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0191] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the following claims.

[0192] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes can be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A multi-device timing control method, characterized in that: The method comprises: After power-on, the custom parameters are loaded into the block random access memory through the field programmable gate array; wherein the custom parameters are stored in the non-volatile memory of the field programmable gate array; Reading a set of instruction sets in the block random access memory based on a sending instruction through the field programmable gate array; wherein the set of instruction sets includes a plurality of instructions to be executed; For each of the instructions to be executed, determining, by the field programmable gate array, an execution timing corresponding to the instruction to be executed based on a sending time field in the custom parameter; Based on each of the execution timings, the instructions to be executed are executed by the field programmable gate array based on the custom parameters until a preset maximum number of reads is reached or a preset termination condition is met.

2. The method according to claim 1, characterized in that The method further comprises: Obtaining the custom parameters edited by ground test software; wherein the ground test software supports eight independent custom parameter groups, each of the custom parameter groups corresponds to an instruction set or a task to be executed, and the instruction set includes a maximum of 256 instructions to be executed; The custom parameters are injected into the field programmable gate array through a serial port.

3. The method according to claim 2, characterized in that The step of injecting the custom parameters into the field programmable gate array through the serial port includes: The custom parameters are packaged into a 40-byte instruction through the ground test software; wherein the 40-byte instruction includes a 2-byte frame header, a 1-byte chip select, a 1-byte target address, a 2-byte send time, 27 bytes of custom data, a 1-byte instruction jump address, a 1-byte counter, a 2-byte checksum, and a 1-byte frame trailer; The ground test software sends the 40-byte instruction to the field programmable gate array through the serial port.

4. The method according to claim 3, characterized in that The method further comprises: Writing the custom data in the custom parameters into the internal block random access memory through the field programmable gate array; After all the custom data are sent, the ground test software sends a save instruction to the field programmable gate array; The field programmable gate array saves the custom data in the non-volatile memory based on the save instruction.

5. The method according to any one of claims 1 to 4, characterized in that The executing the instruction based on the custom parameter by the field programmable gate array includes: The field programmable gate array specifies a corresponding target device based on the target address in the custom parameter, and sends the instruction to be executed to the target device, so that the target device executes the received instruction to be executed.

6. The method according to claim 5, characterized in that The method further comprises: Based on the instruction jump address in the custom parameter, the field programmable gate array jumps to a designated address corresponding to the instruction jump address and sends the custom data in the custom parameter.

7. The method according to claim 4, characterized in that Writing the custom data in the custom parameters into the internal block random access memory through the field programmable gate array includes: Checking the checksum and generating a check result; When the check result is successful, the custom data in the custom parameters is written into the internal block random access memory through the field programmable gate array.

8. A multi-device timing control device, characterized in that: The device comprises: A loading module, configured to load the custom parameters into the block random access memory through the field programmable gate array after power-on; wherein the custom parameters are stored in the non-volatile memory of the field programmable gate array; A reading module, configured to read a set of instruction sets in the block random access memory based on a sending instruction through the field programmable gate array; wherein the set of instruction sets includes a plurality of instructions to be executed; a determination module, configured to determine, for each of the instructions to be executed, an execution timing corresponding to the instruction to be executed based on a sending time field in the custom parameter through the field programmable gate array; An execution module is used to execute the to-be-executed instructions based on the custom parameters through the field programmable gate array based on each of the execution timings until a preset maximum number of reads is reached or a preset termination condition is met.

9. An electronic device, characterized in that: The electronic device includes a processor and a memory, wherein the memory stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by the processor to implement the multi-device timing control method as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that The storage medium stores at least one instruction, at least one program, code set or instruction set, and the at least one instruction, the at least one program, the code set or instruction set is loaded and executed by the processor to implement the multi-device timing control method as described in any one of claims 1-7.

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