A multi-device timing control method

Abstract

The application discloses a multi-device timing control method, which performs timing control on each to-be-executed instruction, and executes each to-be-executed instruction based on an execution time sequence, so that the instruction sending precision reaches a sub-millisecond level, and the high real-time task requirement is met. In addition, the address jump function is used for realizing dynamic instruction adjustment, adapting to various task scenes, and improving the flexibility of multi-device timing control. In addition, the block random access memory and the nonvolatile memory support a plurality of large-scale instruction sets, reduce rewriting overhead, and can reduce hardware upgrade cost, extend functions through software configuration, and improve system reusability.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a multi-device timing control method. BACKGROUND

[0002] The multi-device timing control technology is usually applied in the multi-device cooperative scene, and can meet the demand of multi-device cooperative task. In the prior art, the multi-device timing control is usually realized by combining a microcontroller with an external memory. Parameters are input through a serial port or wireless communication, and are stored and read by the microcontroller in a predetermined order and executed. The instructions are sent to the target device mainly depending on the software timer and through the general-purpose input / output port or other interfaces.

[0003] However, the above multi-device timing control method has the problem of poor flexibility. SUMMARY

[0004] The present application aims to at least solve the technical problems in the prior art. To this end, the first aspect of the present application provides a multi-device timing control method, which comprises:

[0005] After power-on, the self-defined parameters are loaded into the block random access memory through the field programmable gate array; wherein the self-defined parameters are stored in the non-volatile memory of the field programmable gate array;

[0006] A set of instruction sets in the block random access memory are read by the field programmable gate array based on the sending instructions; wherein the set of instruction sets includes a plurality of to-be-executed instructions;

[0007] For each to-be-executed instruction, the execution time sequence corresponding to the to-be-executed instruction is determined by the field programmable gate array based on the sending time field in the self-defined parameters;

[0008] Based on the execution time sequence, the to-be-executed instructions are executed by the field programmable gate array based on the self-defined parameters until the preset maximum reading number is reached or the preset termination condition is met.

[0009] In one possible implementation, the method further comprises:

[0010] The self-defined parameters obtained by the ground test software are obtained; wherein the ground test software supports 8 independent self-defined parameter groups, and one self-defined parameter group corresponds to one instruction set or one to-be-executed task, and each instruction set includes at most 256 to-be-executed instructions;

[0011] The self-defined parameters are injected into the field programmable gate array through the serial port.

[0012] In one possible implementation, the self-defined parameters are injected into the field programmable gate array through the serial port, comprising:

[0013] The custom parameters are packaged as 40-byte instructions by the ground test software; wherein the 40-byte instructions include a 2-byte frame header, a 1-byte chip select, a 1-byte target address, a 2-byte sending time, a 27-byte custom data, a 1-byte instruction jump address, a 1-byte counter, a 2-byte checksum, and a 1-byte frame tail;

[0014] The 40-byte instructions are sent to the FPGA by the ground test software through a serial port.

[0015] In a possible implementation, the method further includes:

[0016] The custom data in the custom parameters are written into the internal block random access memory by the FPGA.

[0017] After the custom data are completely sent, the ground test software sends a save instruction to the FPGA.

[0018] The FPGA saves the custom data into the non-volatile memory based on the save instruction.

[0019] In a possible implementation, the FPGA executes the to-be-executed instruction based on the custom parameters, including:

[0020] The FPGA specifies a corresponding target device based on the target address in the custom parameters, and sends the to-be-executed instruction to the target device, so that the target device executes the received to-be-executed instruction.

[0021] In a possible implementation, the method further includes:

[0022] The FPGA jumps to a specified address corresponding to the instruction jump address and sends the custom data in the custom parameters based on the instruction jump address in the custom parameters.

[0023] In a possible implementation, the FPGA writes the custom data in the custom parameters into the internal block random access memory, including:

[0024] The checksum is checked to generate a check result.

[0025] In a case where the check result is a check success, the FPGA writes the custom data in the custom parameters into the internal block random access memory.

[0026] The second aspect of the present application proposes a multi-device timing control device, which includes:

[0027] The loading module is configured to load the custom parameters into the block random access memory through the field programmable gate array after power-on, wherein the custom parameters are stored in the non-volatile memory of the field programmable gate array.

[0028] The reading module is configured to read a set of instruction sets in the block random access memory based on the sending instruction through the field programmable gate array, wherein the set of instruction sets comprises a plurality of to-be-executed instructions.

[0029] The determining module is configured to determine, for each to-be-executed instruction, an execution timing corresponding to the to-be-executed instruction based on a sending time field in the custom parameters through the field programmable gate array.

[0030] The execution module is configured to execute the to-be-executed instructions based on the custom parameters through the field programmable gate array based on the execution timings until a preset maximum reading number is reached or a preset termination condition is met.

[0031] In a possible implementation, the multi-device timing control apparatus is further configured to:

[0032] The custom parameters edited by the ground test software are obtained, wherein the ground test software supports 8 independent custom parameter groups, one custom parameter group corresponds to one set of instructions or one to-be-executed task, and one set of instructions comprises at most 256 to-be-executed instructions.

[0033] The custom parameters are injected into the field programmable gate array through a serial port.

[0034] In a possible implementation, the multi-device timing control apparatus is further configured to:

[0035] The custom parameters are packaged into 40-byte instructions through the ground test software, wherein the 40-byte instructions comprise a 2-byte frame header, a 1-byte chip selection, a 1-byte target address, a 2-byte sending time, a 27-byte custom data, a 1-byte instruction jump address, a 1-byte counter, a 2-byte checksum, and a 1-byte frame tail.

[0036] The 40-byte instructions are sent to the field programmable gate array through the serial port through the ground test software.

[0037] In a possible implementation, the multi-device timing control apparatus is further configured to:

[0038] The custom data in the custom parameters are written into the internal block random access memory through the field programmable gate array.

[0039] After the custom data are completely sent, the ground test software sends a saving instruction to the field programmable gate array.

[0040] The field programmable gate array saves the custom data into the non-volatile memory based on the saved instruction.

[0041] In a possible implementation, the execution module is specifically configured to:

[0042] The field programmable gate array specifies the target device corresponding to the target address in the custom parameter, and sends the to-be-executed instruction to the target device, so that the target device executes the received to-be-executed instruction.

[0043] In a possible implementation, the multi-device timing control apparatus is further configured to:

[0044] The field programmable gate array jumps to the specified address corresponding to the instruction jump address in the custom parameter based on the instruction jump address in the custom parameter, and sends the custom data in the custom parameter.

[0045] In a possible implementation, the multi-device timing control apparatus is further configured to:

[0046] The checksum is checked to generate a check result.

[0047] In a case where the check result is a check success, the field programmable gate array writes the custom data in the custom parameter into the internal block random access memory.

[0048] The third aspect of the present application provides an electronic device, the electronic device includes a processor and a memory, the memory stores at least one instruction, at least one program, a code set or an instruction set, the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by the processor to realize the multi-device timing control method as described in the first aspect.

[0049] The fourth aspect of the present application provides a computer readable storage medium, the storage medium stores at least one instruction, at least one program, a code set or an instruction set, the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by the processor to realize the multi-device timing control method as described in the first aspect.

[0050] The embodiments of the present application have the following beneficial effects:

[0051] The multi-device timing control method provided by the embodiment of the application comprises: after power-on, loading a self-defined parameter to a block random access memory through a field programmable gate array; wherein the self-defined parameter is stored in a nonvolatile memory of the field programmable gate array; reading a set of instruction sets in the block random access memory based on a sending instruction through the field programmable gate array; wherein the set of instruction sets comprises a plurality of to-be-executed instructions; for each to-be-executed instruction, determining an execution timing corresponding to the to-be-executed instruction based on a sending time field in the self-defined parameter through the field programmable gate array; and executing the to-be-executed instruction based on the self-defined parameter through the field programmable gate array based on each execution timing until a preset maximum reading number is reached or a preset termination condition is met. The scheme ensures that the instruction sending precision reaches sub-millisecond level by timing control on each to-be-executed instruction and executing the to-be-executed instruction based on the execution timing, and meets the high real-time task demand. In addition, dynamic instruction adjustment is realized through the address jump function, the multi-device timing control flexibility is improved, and the system reusability is improved. BRIEF DESCRIPTION OF DRAWINGS

[0052] Figure 1 A block diagram of a computer device provided by the embodiment of the application;

[0053] Figure 2 A step flowchart of a multi-device timing control method provided by the embodiment of the application;

[0054] Figure 3 A step flowchart of storing a self-defined parameter provided by the embodiment of the application;

[0055] Figure 4 A step flowchart of injecting a field programmable gate array provided by the embodiment of the application;

[0056] Figure 5 A step flowchart of saving to a nonvolatile memory provided by the embodiment of the application;

[0057] Figure 6 A step flowchart of writing to an internal block random access memory provided by the embodiment of the application;

[0058] Figure 7 An architecture schematic diagram of a multi-device timing control system provided by the embodiment of the application;

[0059] Figure 8 A BRAM address division schematic diagram provided by the embodiment of the application;

[0060] Figure 9 A FLASH address division schematic diagram provided for an embodiment of the present application;

[0061] Figure 10 A structure block diagram of a multi-device timing control device provided for an embodiment of the present application. DETAILED DESCRIPTION

[0062] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0063] In the prior art, multi-device timing control is usually realized by combining a microcontroller with an external memory. Parameters are input through a serial port or wireless communication, and are stored and then read and executed by the MCU in a predetermined order. Instruction sending is mostly dependent on a software timer, and is sent to the target device through a general-purpose input / output (GPIO) or other interfaces. A typical system supports a limited number of task groups (such as 1-2 groups) and instruction numbers (such as dozens), and has a small storage capacity (usually several KB to several tens of KB).

[0064] In the prior art, the instruction sequence and sending order are fixed, and it is difficult to dynamically adjust (such as inserting or jumping to a specific instruction), which cannot adapt to task changes. In addition, the dependence on the software timer results in that the instruction sending accuracy is limited by the MCU clock and the task scheduling overhead, which cannot meet the high real-time demand (such as sub-millisecond control). Moreover, the small parameter storage capacity makes it difficult to support large-scale instruction sets, and the memory needs to be frequently rewritten during multi-group task switching, which is inefficient. In addition, the number of supported device ports and task groups is limited, and it is difficult to expand to multi-device collaborative scenarios (such as more than 10 devices or multi-task mode).

[0065] Based on this, the present application proposes a multi-device timing control method. The present application controls each to-be-executed instruction, and executes the to-be-executed instruction based on the execution timing sequence, so as to ensure that the instruction sending accuracy reaches the sub-millisecond level, and meet the high real-time task demand. In addition, the address jump function is used to realize dynamic instruction adjustment, which adapts to variable task scenarios and improves the flexibility of multi-device timing control. In addition, the block random access memory and the non-volatile memory support a large-scale instruction set in multiple groups, reduce the rewriting overhead, and can reduce the hardware upgrade cost. The function can be expanded through software configuration, and the system reusability is improved.

[0066] The terms "first", "second", "third", etc. are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise stated, the meaning of "a plurality of" is two or more. In addition, the use of "based on" or "according to" means open and inclusive, because the process, step, calculation or other action based on one or more stated conditions or values can be based on additional conditions or values beyond those stated in practice.

[0067] The multi-device timing control method provided by the present application can be applied to a computer device (electronic device). The computer device can be a server or a terminal. The server can be a single server or a server cluster composed of multiple servers. The embodiments of the present application do not make specific limitations on this. The terminal can be, but is not limited to, various personal computers, notebook computers, smart phones, tablet computers and portable wearable devices.

[0068] Taking the computer device as a server for example, Figure 1 a block diagram of a server is shown, as Figure 1 As shown, the server can include a processor and a memory connected by a system bus. The processor of the server is used to provide computing and control capabilities. The memory of the server includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The computer program is executed by the processor to implement a multi-device timing control method.

[0069] Those skilled in the art can understand, Figure 1 The structure shown in the figure is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the server to which the scheme of the present application is applied. Alternatively, the server can include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0070] It should be noted that the execution subject of the embodiments of the present application can be a computer device or a multi-device timing control apparatus. The following method embodiments are described with the computer device as the execution subject.

[0071] Figure 2 A step flowchart of a multi-device timing control method provided by the embodiments of the present application is shown in Figure 2 As shown, the method includes the following steps:

[0072] Step 202: After power-on, load the custom parameters into the block random access memory via a field-programmable gate array.

[0073] The custom parameters are stored in the non-volatile memory of the field-programmable gate array. In actual use, these custom parameters can have many variations to adapt to the actual scenario. For example, some instruction parameters are very long, exceeding 27 bytes, or 8 custom instruction sets are not enough, and can be expanded to 16 or 64 sets, etc.

[0074] Therefore, during use, the number of instruction sets that need to be flexibly configured in the actual use scenario can be determined first. For example, this number can be 8, 16, 32, etc. Then, the maximum number of instructions to be executed that the instruction set can hold can be determined. If the maximum number of instructions to be executed that the instruction set can hold is 128, and the size of a custom parameter is 32, then 16 * 128 * 32 = 65536 (bytes). Here, 65536 is the size of a data block in external memory. Dividing the effective memory capacity after triple modular redundancy by 65536 will tell you how many instruction sets can be stored.

[0075] In some alternative embodiments, such as Figure 3 As shown, Figure 3 A flowchart illustrating steps for storing custom parameters provided in this application embodiment includes:

[0076] Step 302: Obtain the custom parameters edited using the ground testing software.

[0077] The ground testing software supports eight independent custom parameter groups. Each custom parameter group corresponds to a set of instructions or a task to be executed. A set of instructions can include up to 256 instructions to be executed. Each instruction to be executed can include a timestamp, target port, and custom data.

[0078] Step 304: Inject custom parameters into the field programmable gate array via serial port.

[0079] After obtaining the custom parameters, they can be injected into the Field-Programmable Gate Array (FPGA) via serial port. In some optional embodiments, such as... Figure 4 As shown, Figure 4 A flowchart illustrating the steps of injecting a field-programmable gate array (FPGA) according to an embodiment of this application includes:

[0080] Step 402: Package the custom parameters into a 40-byte instruction using ground testing software.

[0081] Step 404, sending a 40-byte instruction to the field programmable gate array through a serial port by the ground test software.

[0082] The 40-byte instruction includes a 2-byte frame header, a 1-byte chip selection, a 1-byte target address, a 2-byte sending time, a 27-byte custom data, a 1-byte instruction jump address, a 1-byte counter, a 2-byte checksum and a 1-byte frame tail.

[0083] The above-mentioned custom parameter injection process is realized by ground test software, and the custom parameters are injected into the internal block random access memory (BRAM) through a serial port and saved to the non-volatile memory FLASH, supporting repeated reading, timed sending and data insertion functions of parameters. Its core functions include: supporting timed sending of instructions and parameters, maximum reading of 7680 bytes of custom parameters; providing 8 independent parameter group configurations, adapting to multi-task mode, each group supporting 256 parameter storage. The insertion data function of address jump is realized to adjust the parameter sending sequence. The length of each custom parameter is fixed at 40 bytes, the custom data area is 27 bytes, and the output interval is 0.1 seconds controlled by internal pulses.

[0084] The instruction frame format includes frame header (0xEE, 0xCC), chip selection (supports 8 groups of BRAM cache), target address, sending time (0.1 seconds, 0-65535), 27-byte custom data, jump address and checksum fields. The above-mentioned sending time can be flexibly set according to the actual scene, and 0.1 seconds is only an example. And design 8 8KB RAM (total 64KB), use independently through chip selection signal BRAM[0:7], save to FLASH uniformly. The FLASH selects 128Mbit serial flash (HWD25Q128AAS), with three modular redundancy design effective capacity of 4MB, can save 64 groups of 64KB data, theoretical support 512 groups of parameters. After power-on, the system self-checks and loads custom parameters, and the reading mode starts from address 0, ends when encountering jump address 0, sending time 65535 or reading 256 times, ensuring flexible and efficient task execution.

[0085] The instruction format is described in the following table:

[0086]

[0087]

[0088] The contents stored in the BRAM corresponding to the chip selection and the target address are shown in the following table:

[0089]

[0090]

[0091] In some optional embodiments, as shown in Figure 5 , Figure 5 A step flow chart provided by the embodiment of the application for saving to the non-volatile memory comprises:

[0092] Step 502, write the custom data in the custom parameters into the internal block random access memory through the field programmable gate array.

[0093] Step 504, after the custom data is completely sent, the ground test software sends a save instruction to the field programmable gate array.

[0094] Step 506, the field programmable gate array saves the custom data into the non-volatile memory based on the save instruction.

[0095] Wherein, the user edits the custom parameters through the ground test software or the serial port assistant, and each group has at most 256 instructions. The ground test software can package the custom parameters into 40-byte instructions, and then send the instructions to the field programmable gate array through the serial port. The field programmable gate array writes the received custom data into the internal BRAM. After the custom data is completely sent, the ground test software sends a save instruction to the field programmable gate array. The field programmable gate array finally saves the custom data from the BRAM to the FLASH, realizing long-term storage. Optionally, the model HWD25Q128AAS, 16MB FLASH can be used. Optionally, the FLASH can adopt a triple modular redundancy design. The specific design method can refer to the prior art, and will not be described here to ensure storage reliability.

[0096] In some optional embodiments, as shown in Figure 6 , Figure 6 A step flow chart provided by the embodiment of the application for writing into the internal block random access memory comprises:

[0097] Step 602, check the checksum to generate a check result.

[0098] Step 604, in the case that the check result is a check success, write the custom data in the custom parameters into the internal block random access memory through the field programmable gate array.

[0099] Wherein, checking the checksum can verify the data integrity. After obtaining the check result, in the case that the check result is a check success, write the custom data in the custom parameters into the internal block random access memory through the field programmable gate array. If the check result is a check failure, refuse to write.

[0100] Step 204, reading a set of instruction set in the block random access memory based on the sending instruction by the field programmable gate array.

[0101] The set of instruction set includes a plurality of to-be-executed instructions. After the system is powered on, the FPGA automatically loads the custom data from the FLASH to the BRAM. The sending instruction can make the FPGA read a set of instruction set from the 0th to the 7th set of instructions in the BRAM. The 8th set of BRAM cache corresponds to different tasks or instruction sets.

[0102] Step 206, for each to-be-executed instruction, determining the execution timing corresponding to the to-be-executed instruction based on the sending time field in the custom parameter by the field programmable gate array.

[0103] For each to-be-executed instruction, the execution timing is controlled based on the sending time field in the custom parameter by the field programmable gate array. Specifically, if the sending time field is 0, the execution is immediate; if the sending time field is 65535, the task is terminated; and if the sending time field is other values, the execution is relative to the 0.1 second* sending time of the previous instruction.

[0104] Step 208, executing the to-be-executed instruction based on the custom parameter by the field programmable gate array based on the execution timing until a preset maximum reading number is reached or a preset termination condition is met.

[0105] After obtaining the execution timing of each to-be-executed instruction, the to-be-executed instruction can be executed based on the custom parameter by the field programmable gate array.

[0106] In some optional embodiments, the corresponding target device can be specified based on the target address in the custom parameter by the field programmable gate array, and the to-be-executed instruction can be sent to the target device, so that the target device executes the received to-be-executed instruction. The target port (0-9) specifies the corresponding target device, so that the to-be-executed instruction can be sent to the corresponding target device according to the corresponding target port number. The present application supports 10 target ports and 8 tasks, adapts to multi-device collaboration, can promote the development of multi-device collaboration technology in the fields of aerospace and industry, and improves the reliability of task execution.

[0107] In some optional embodiments, the field programmable gate array can also jump to a specified address corresponding to the instruction jump address based on the instruction jump address in the custom parameter and send the custom data in the custom parameter. According to the instruction jump address (1-255), the custom data of the specified address is sent. If it is 0, the task is terminated. Through the address jump function, dynamic instruction adjustment is realized, which adapts to variable task scenarios and improves the flexibility of multi-device timing control.

[0108] In some optional embodiments, the instruction content is defined by custom data, such as controlling camera exposure, sensor triggering, or servo platform rotation, etc., and finally stops execution when the preset maximum reading number is reached or the preset termination condition is met. Optionally, the preset maximum reading number can be 256, and the preset termination condition can be set according to experience.

[0109] For example, the user needs to configure 3 instructions of BRAM group 0 to be executed to achieve the following functions:

[0110] 1. Immediately send a rotation instruction to port 0x01 (gimbal) (corresponding to data A0 01 00 5A).

[0111] 2. After 0.5 seconds, send a photographing instruction to port 0x02 (camera) (corresponding to data B1 02).

[0112] 3. After 1 second, send a collection instruction to port 0x03 (sensor) (corresponding to data C3 04FF).

[0113] 4. Automatically terminate after execution is completed.

[0114] The specific implementation process is that first, the custom parameters obtained by the ground test software editing are needed, as shown in the following table:

[0115]

[0116] Detailed data explanation, take instruction 1 as an example:

[0117]

[0118] Then, the 40-byte instruction EE CC 00 00 00 000104...D9 after packing the custom parameters can be obtained. Check the checksum, and in the case of successful check, return the acknowledge character (ACK) (0x55) and the updated counter (0x01), and in the case of failed check, return the negative acknowledgement (NAK) (0xFF).

[0119] After successful check, the content at BRAM group 0 address 0x00 can be written, that is, 0000:00 00 0104A0 01 005A[fill to 31 bytes]01 00, wherein the sending time is 0, the port is 0x01, the data length is 4, and the jump address is 0x01. Finally, it is stored by FLASH, that is, Sector0:00 00 01 04...(complete 64KB BRAM group 0 data).

[0120] Then, the execution process can be:

[0121] 1. Start instruction 0x00 (execute immediately):

[0122] Output to port 0x01: A0 01 00 5A (pan-tilt rotation)

[0123] Jump to address 0x01, counter + 1

[0124] 2. Execute instruction 0x01 after 0.5 seconds:

[0125] Output to port 0x02: B1 02 (camera shooting)

[0126] Jump to address 0x02, counter + 1

[0127] 3. Execute instruction 0x02 after 1 second:

[0128] Output to port 0x03: C3 04 FF (sensor acquisition)

[0129] Jump to address 0x00 (termination condition), counter + 1

[0130] 4. Termination condition is met, task is completed

[0131] Finally, the output data is as shown in the following table:

[0132]

[0133] In some optional embodiments, the present application also provides a configurable multi-device timing control system based on FPGA, which is designed for multi-device collaborative scenarios such as photoelectric payload that require high-precision timing control. The system realizes precise scheduling and execution of multi-device instructions through flexible parameter configuration, hardware-level timing control, efficient storage management, and scalability optimization. The system architecture is divided into a ground configuration layer (ground test software), a control layer (FPGA), a storage layer (FLASH), and an execution layer (target device), supporting multi-task mode switching, dynamic parameter loading, and instruction timing control, such as Figure 7 as shown, Figure 7 is a schematic diagram of a multi-device timing control system according to an embodiment of the present application.

[0134] The system is composed of ground test software, a serial port, an FPGA, a FLASH, and a custom device, i.e., a target device. The ground software edits parameters, which are injected into the FPGA through the serial port. The FPGA writes the parameters into an internal BRAM and saves them to the FLASH. After power-on, the FPGA automatically loads the parameters from the FLASH to the internal BRAM and waits for execution. The FPGA is a core controller, responsible for instruction analysis, timing sending, and data management. The internal BRAM of the FPGA provides 8 groups of 8KB cache, a total of 64KB, and each group has 256 instructions. Figure 8 As shown in Figure 8 FIG. 1 is a BRAM address partitioning diagram provided by an embodiment of the application. The FLASH model is HWD25Q128AAS, 128Mbit, with a three-module redundancy design, an effective capacity of 4MB, and long-term storage. Figure 9 As shown in Figure 9 FIG. 2 is a FLASH address partitioning diagram provided by an embodiment of the application. The custom device corresponds to target ports Port 0-9.

[0135] The application provides a multi-device timing control method, which includes: after power-on, loading custom parameters to a block random access memory through a field programmable gate array; wherein the custom parameters are stored in a non-volatile memory of the field programmable gate array; reading a set of instruction groups in the block random access memory based on a sending instruction through the field programmable gate array; wherein the set of instruction groups includes a plurality of to-be-executed instructions; for each to-be-executed instruction, determining an execution timing corresponding to the to-be-executed instruction based on a sending time field in the custom parameters through the field programmable gate array; and executing the to-be-executed instructions based on the custom parameters through the field programmable gate array based on the execution timings until a preset maximum reading number is reached or a preset termination condition is met. The scheme controls the timing of each to-be-executed instruction and executes the to-be-executed instruction based on the execution timing, ensuring that the instruction sending precision reaches sub-millisecond level and meeting the demand of high real-time tasks. In addition, the address jump function is used to realize dynamic instruction adjustment, adapt to variable task scenarios, and improve the flexibility of multi-device timing control. In addition, the block random access memory and the non-volatile memory support a plurality of large-scale instruction groups, reduce rewriting overhead, and can reduce hardware upgrade cost. The function can be expanded through software configuration, improving system reusability.

[0136] It should be understood that although each step in the flowchart involved in the above-described embodiments is shown in sequence according to the direction of the arrow, these steps are not necessarily executed in the order indicated by the arrow. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other orders. Moreover, at least some of the steps in the flowchart involved in the above-described embodiments can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least part of other steps or steps or stages in other steps.

[0137] Figure 10 A structural block diagram of a multi-device timing control device provided by the embodiments of the present application.

[0138] As shown in the above-described embodiments, the multi-device timing control device 1000 includes: Figure 10

[0139] The loading module 1002 is configured to load the custom parameters to the block random access memory through the field programmable gate array after power-on, wherein the custom parameters are stored in the non-volatile memory of the field programmable gate array.

[0140] The reading module 1004 is configured to read a set of instruction sets in the block random access memory based on the sending instruction through the field programmable gate array, wherein the set of instruction sets includes a plurality of to-be-executed instructions.

[0141] The determining module 1006 is configured to determine, for each to-be-executed instruction, an execution timing corresponding to the to-be-executed instruction based on the sending time field in the custom parameters through the field programmable gate array.

[0142] The execution module 1008 is configured to execute the to-be-executed instructions based on the custom parameters through the field programmable gate array based on each execution timing until a preset maximum reading number is reached or a preset termination condition is met.

[0143] Regarding the device in the above-described embodiments, the specific manner in which each module performs an operation has been described in detail in the embodiments related to the method, and will not be described in detail here. Each module in the above-described multi-device timing control device can be realized by software, hardware, and combinations thereof, in whole or in part. Each module described above can be embedded in or independent of the processor in the computer device in hardware form, or can be stored in the memory in the computer device in software form, so as to be called and executed by the processor to perform the operations of each module described above.

[0144] ​In an embodiment of the present application, a computer device is provided, comprising a memory and a processor, the memory storing a computer program, and the processor implementing the following steps when executing the computer program:

[0145] loading the custom parameters into the block random access memory through the field programmable gate array after power-on; wherein the custom parameters are stored in the non-volatile memory of the field programmable gate array;

[0146] reading a set of instruction sets in the block random access memory based on the sending instruction through the field programmable gate array; wherein the set of instruction sets comprises a plurality of to-be-executed instructions;

[0147] for each to-be-executed instruction, determining the execution timing corresponding to the to-be-executed instruction based on the sending time field in the custom parameters through the field programmable gate array;

[0148] based on the execution timing, executing the to-be-executed instructions based on the custom parameters through the field programmable gate array until a preset maximum reading number is reached or a preset termination condition is met.

[0149] In an embodiment of the present application, the processor further implements the following steps when executing the computer program:

[0150] obtaining the custom parameters edited by the ground test software; wherein the ground test software supports 8 independent custom parameter groups, and one custom parameter group corresponds to one set of instructions or one to-be-executed task, and the set of instructions comprises at most 256 to-be-executed instructions;

[0151] injecting the custom parameters into the field programmable gate array through the serial port.

[0152] In an embodiment of the present application, the processor further implements the following steps when executing the computer program:

[0153] packing the custom parameters into 40-byte instructions through the ground test software; wherein the 40-byte instructions comprise a 2-byte frame header, a 1-byte chip selection, a 1-byte target address, a 2-byte sending time, a 27-byte custom data, a 1-byte instruction jump address, a 1-byte counter, a 2-byte checksum and a 1-byte frame tail;

[0154] sending the 40-byte instructions to the field programmable gate array through the serial port through the ground test software.

[0155] In an embodiment of the present application, the processor further implements the following steps when executing the computer program:

[0156] writing the custom data in the custom parameters into the internal block random access memory through the field programmable gate array;

[0157] After the custom data is completely sent, the ground test software sends a save instruction to the FPGA;

[0158] The FPGA saves the custom data into the non-volatile memory based on the save instruction.

[0159] In an embodiment of the present application, when the processor executes the computer program, the following steps are also implemented:

[0160] The FPGA specifies the target device based on the target address in the custom parameter, and sends the to-be-executed instruction to the target device, so that the target device executes the received to-be-executed instruction.

[0161] In an embodiment of the present application, when the processor executes the computer program, the following steps are also implemented:

[0162] The FPGA jumps to the specified address corresponding to the instruction jump address in the custom parameter based on the instruction jump address in the custom parameter, and sends the custom data in the custom parameter.

[0163] In an embodiment of the present application, when the processor executes the computer program, the following steps are also implemented:

[0164] The checksum is checked to generate a check result;

[0165] In the case that the check result is a check success, the FPGA writes the custom data in the custom parameter into the internal block RAM.

[0166] The computer device provided by the embodiment of the present application has similar implementation principles and technical effects to the above method embodiments, and thus will not be described here.

[0167] In an embodiment of the present application, a computer readable storage medium is provided, which stores a computer program, and when the computer program is executed by a processor, the following steps are implemented:

[0168] After power-on, the FPGA loads the custom parameter into the block RAM; wherein the custom parameter is stored in the non-volatile memory of the FPGA;

[0169] The FPGA reads a set of instruction sets in the block RAM based on the sending instruction; wherein the set of instruction sets includes a plurality of to-be-executed instructions;

[0170] For each to-be-executed instruction, the FPGA determines the execution timing corresponding to the to-be-executed instruction based on the sending time field in the custom parameter;

[0171] Based on each execution timing, the field programmable gate array executes the to-be-executed instruction based on the customized parameter until a preset maximum reading number is reached or a preset termination condition is met.

[0172] In one embodiment of the present application, the computer program, when executed by the processor, further implements the following steps:

[0173] Obtaining the customized parameter edited by the ground test software; wherein the ground test software supports 8 independent customized parameter groups, one customized parameter group corresponds to one instruction set or one to-be-executed task, and one instruction set includes at most 256 to-be-executed instructions;

[0174] Injecting the customized parameter into the field programmable gate array through the serial port.

[0175] In one embodiment of the present application, the computer program, when executed by the processor, further implements the following steps:

[0176] Packing the customized parameter into a 40-byte instruction through the ground test software; wherein the 40-byte instruction includes a 2-byte frame header, a 1-byte chip selection, a 1-byte target address, a 2-byte sending time, a 27-byte customized data, a 1-byte instruction jump address, a 1-byte counter, a 2-byte checksum and a 1-byte frame tail;

[0177] Sending the 40-byte instruction to the field programmable gate array through the serial port by the ground test software.

[0178] In one embodiment of the present application, the computer program, when executed by the processor, further implements the following steps:

[0179] Writing the customized data in the customized parameter into the internal block random access memory by the field programmable gate array;

[0180] After the customized data is completely sent, the ground test software sends a save instruction to the field programmable gate array;

[0181] The field programmable gate array saves the customized data into the non-volatile memory based on the save instruction.

[0182] In one embodiment of the present application, the computer program, when executed by the processor, further implements the following steps:

[0183] Specifying the corresponding target device based on the target address in the customized parameter by the field programmable gate array, and sending the to-be-executed instruction to the target device, so that the target device executes the received to-be-executed instruction.

[0184] In one embodiment of the present application, the computer program, when executed by the processor, further implements the following steps:

[0185] The field programmable gate array jumps to the specified address corresponding to the instruction jump address and sends the custom data in the custom parameter based on the instruction jump address in the custom parameter.

[0186] In one embodiment of the present application, the computer program, when executed by the processor, further implements the following steps:

[0187] The checksum is checked to generate a check result.

[0188] In the case where the check result is a check success, the custom data in the custom parameter is written into the internal block random access memory by the field programmable gate array.

[0189] The computer readable storage medium provided in the embodiment has similar implementation principles and technical effects to the above method embodiments, and will not be described here.

[0190] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program instructing related hardware, and the computer program can be stored in a non-volatile computer readable storage medium. When the computer program is executed, it can include the processes of the above-mentioned embodiments. Any reference to memory, storage, database or other medium used in the embodiments provided by the present application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0191] Other embodiments of the present disclosure will be apparent to those skilled in the art with the consideration of the specification and practice of the disclosed application. The present application is intended to cover any variations, uses or adaptive changes of the present disclosure following the general principles of the present disclosure and including common knowledge or conventional technical means in the art which are not disclosed by the present disclosure. The specification and examples are only regarded as exemplary, and the true scope and spirit of the present disclosure are indicated by the following claims.

[0192] It is to be understood that the present disclosure is not limited to the precise construction that has been described above and shown in the accompanying drawings, and that various modifications and changes can be made by those skilled in the art without departing from the scope of the present disclosure. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A multi-device timing control method, characterized by, The method comprises: After power-on, obtaining self-defined parameters edited by ground test software; wherein the ground test software supports 8 groups of independent self-defined parameter groups, one group of the self-defined parameter groups corresponds to one group of instruction sets or one to-be-executed task, and the one group of instruction sets includes at most 256 to-be-executed instructions; injecting the self-defined parameters into a field programmable gate array (FPGA) through a serial port; loading the self-defined parameters into a block random access memory (BRAM) through the FPGA; wherein the self-defined parameters are stored in a non-volatile memory of the FPGA; Reading, by the FPGA, one group of instruction sets in the BRAM based on a sending instruction; wherein the one group of instruction sets includes a plurality of to-be-executed instructions; For each of the to-be-executed instructions, determining, by the FPGA, an execution timing corresponding to the to-be-executed instruction based on a sending time field in the self-defined parameters; Based on each of the execution timings, executing, by the FPGA, the to-be-executed instructions based on the self-defined parameters until a preset maximum reading number is reached or a preset termination condition is met.

2. The method of claim 1, wherein, The injecting of the self-defined parameters into the FPGA through the serial port comprises: Packing, by the ground test software, the self-defined parameters into a 40-byte instruction; wherein the 40-byte instruction includes a 2-byte frame header, a 1-byte chip selection, a 1-byte target address, a 2-byte sending time, a 27-byte self-defined data, a 1-byte instruction jump address, a 1-byte counter, a 2-byte checksum, and a 1-byte frame tail; The sending of the 40-byte instruction to the FPGA through the serial port by the ground test software.

3. The method of claim 2, wherein, The method further comprises: Writing, by the FPGA, the self-defined data in the self-defined parameters into the internal BRAM; After the sending of the self-defined data is completed, sending, by the ground test software, a saving instruction to the FPGA; Saving, by the FPGA, the self-defined data into the non-volatile memory based on the saving instruction.

4. The method according to any one of claims 1 to 3, characterized in that, The executing of the instruction by the FPGA based on the self-defined parameters comprises: Specifying, by the FPGA, a corresponding target device based on the target address in the self-defined parameters, and sending the to-be-executed instruction to the target device, so that the target device executes the received to-be-executed instruction.

5. The method of claim 4, wherein, The method further comprises: Jumping, by the FPGA, to a specified address corresponding to the instruction jump address in the self-defined parameters based on the instruction jump address, and sending the self-defined data in the self-defined parameters.

6. The method of claim 3, wherein, The writing of the self-defined data in the self-defined parameters into the internal BRAM by the FPGA comprises: Checking the checksum to generate a checking result; In a case that the checking result is a successful check, the custom data in the custom parameters is written into the internal block random access memory by the field programmable gate array.

7. A multi-device timing control apparatus, characterized by comprising: The device comprises: A loading module is configured to, after power-on, acquire custom parameters edited by ground test software; the ground test software supports 8 groups of independent custom parameter groups, one group of the custom parameter groups corresponds to one group of instruction sets or one to-be-executed task, and the one group of instruction sets includes at most 256 to-be-executed instructions; the custom parameters are injected into a field programmable gate array (FPGA) through a serial port; the custom parameters are loaded into a block random access memory (BRAM) by the FPGA; and the custom parameters are stored in a nonvolatile memory of the FPGA. A reading module is configured to read one group of instruction sets in the BRAM based on a sending instruction by the FPGA; the one group of instruction sets includes a plurality of to-be-executed instructions. A determining module is configured to, for each of the to-be-executed instructions, determine an execution timing sequence corresponding to the to-be-executed instruction based on a sending time field in the custom parameters by the FPGA. An executing module is configured to execute the to-be-executed instructions based on the custom parameters by the FPGA based on each of the execution timing sequences until a preset maximum reading number is reached or a preset termination condition is met.

8. An electronic device, comprising: The electronic device comprises a processor and a memory, and the memory stores at least one instruction, at least one program, a code set or an instruction set, the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by the processor to implement the multi-device timing control method of any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The storage medium stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by the processor to implement the multi-device timing control method of any one of claims 1-6.

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