Data processing method, system and device and readable storage medium

Abstract

The invention discloses a data processing method, system and device and a readable storage medium, and relates to the technical field of storage. According to the method, the private memories in the chip are arranged for the nodes in the multi-core processor system, and the addresses of the private memories are included in the address space of the whole system, so that the memory access request can directly request to access the private memories, and the access processing efficiency is accelerated. Besides, for a target address, which is not in the private memory address range of the node, but in the private memory address ranges of other nodes, the request can be forwarded, so that indirect access to the private memory is realized. Thus, under the condition that the private memory is fully utilized, access can be completed in the chip, the access duration can be greatly shortened, and the access efficiency is effectively improved.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a data processing method, system, device and readable storage medium. Background Art

[0002] In a multi-core processor system, including homogeneous and heterogeneous processor cores or a chip processor system built by a Master (master / management) node, it is usually necessary to access external DDR memory through a NIC (Network Interface Controller), NoC (Network on Chip), or MESH (Mesh Network) network.

[0003] This access method faces routing network congestion, QoS (Quality of Service) issues, and latency due to cache coherence maintenance, which impacts execution efficiency. Existing technologies are particularly unable to meet the demands of applications requiring extremely high performance and efficiency, such as high-performance computing (HPC), real-time data processing, and artificial intelligence (AI) inference.

[0004] Therefore, those skilled in the art currently need to solve the problem of how to improve the access efficiency of a multi-core processor system. Summary of the Invention

[0005] The present application provides a data processing method, system, device and readable storage medium, which can effectively improve the access efficiency of a multi-core processor system.

[0006] A data processing method, comprising:

[0007] A first node in a multi-core processor system receives a memory access request and determines a target address corresponding to the memory access request; wherein the node in the multi-core processor system has private memory, and the private memory is incorporated into the address space of the entire system through a global address mapping;

[0008] If the target address falls within the private memory address range of the first node, the target address is accessed directly;

[0009] If the target address falls within the private memory address range of the second node, forwarding the memory access request to the second node so as to access the target address through the second node;

[0010] If the target address falls within the external memory address range, the target address is accessed by utilizing the external memory channel.

[0011] Preferably, directly accessing the target address includes:

[0012] The target address is directly accessed by utilizing a high-speed interface connected to its own private memory; wherein the high-speed interface is an address data access interface of a static random access memory.

[0013] Preferably, if the memory access request is sent by the second node, after directly accessing the target address, the method further includes:

[0014] The read target data is sent to the second node.

[0015] Preferably, forwarding the memory access request to the second node includes:

[0016] establishing a communication connection with the second node;

[0017] A memory access request is sent to the second node using the communication connection.

[0018] Preferably, before the first node in the multi-core processor system receives the memory access request, the process includes:

[0019] Perform global address mapping on private memory so that the address of private memory is included in the address space of the entire system;

[0020] Configure the address priority of the private memory. The address priority of the private memory is higher than that of the external memory.

[0021] Preferably, it also includes:

[0022] Monitor access to resources in private memory and determine hot and cold classification of resources;

[0023] Migrate cold resources to external memory;

[0024] Migrate non-local hot resources to the target node with the highest number of indirect accesses.

[0025] Preferably, directly accessing the target address includes:

[0026] Determining whether the memory access request is forwarded to the first node by another node;

[0027] If not, access the target address directly;

[0028] If yes, determine whether the private memory of the first node is busy;

[0029] When the private memory of the first node is in a busy state, access to the target address is prohibited;

[0030] When the private memory of the first node is in an idle state, the target address is directly accessed.

[0031] A multi-core processor system, wherein nodes in the multi-core processor system have private memories, and the private memories are incorporated into the address space of the entire system through global address mapping;

[0032] The first node in the multi-core processor system includes:

[0033] A request receiving module, configured to receive a memory access request and determine a target address corresponding to the memory access request;

[0034] a direct address access module, configured to directly access the target address if the target address falls within the private memory address range of the first node;

[0035] an indirect address access module for forwarding the memory access request to the second node if the target address falls within the private memory address range of the second node, so as to access the target address through the second node;

[0036] The external memory access module is used to access the target address by connecting to the external memory channel if the target address falls within the external memory address range.

[0037] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned data processing methods when executing the computer program.

[0038] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned data processing methods are implemented.

[0039] The present application also provides a computer program product, comprising a computer program, which implements the steps of any of the above-mentioned data processing methods when executed by a processor.

[0040] In the present application, since the nodes in the multi-core processor system have private memory, and the private memory is incorporated into the address space of the entire system through global address mapping; after the first node in the multi-core processor system receives a memory access request and determines the target address corresponding to the memory access request, it can be determined which address range the target address falls into. In the case where the target address falls within the private memory address range of the first node, the target address can be accessed directly. In the case where the target address falls within the private memory address range of the second node, considering that the efficiency of data access within the chip is much higher than the access efficiency of off-chip memory, the memory access request can be forwarded to the second node so that the target address can be accessed through the second node. In the case where the target address falls within the external memory address range, the target address is accessed by connecting to the external memory channel.

[0041] That is to say, in this application, by setting up private memory within the chip for the nodes in the multi-core processor system, and incorporating the addresses of these private memories into the address space of the entire system, memory access requests can directly request access to the private memory, thereby accelerating access processing efficiency. In addition, for targets whose address range is not the private memory address range of this node, but the private memory address range of other nodes, the request will also be forwarded, thereby achieving indirect access to the private memory. In this way, while making full use of the private memory, access can be completed within the chip, which can greatly reduce the access time and effectively improve the technical effect of access efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0043] Figure 1 A flowchart of an implementation of a data processing method provided in an embodiment of the present application;

[0044] Figure 2 An address diagram provided in an embodiment of the present application;

[0045] Figure 3 A schematic diagram of a system structure provided in an embodiment of the present application;

[0046] Figure 4 A schematic diagram of the structure of a multi-core processor system provided in an embodiment of the present application;

[0047] Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0048] Figure 6 A schematic diagram of the specific structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0050] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0051] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0052] The data processing method provided in the embodiment of the present application can be applied to nodes in a multi-core processor system. The multi-core processing system has multiple nodes, each of which has private memory, and the private memory is incorporated into the address space of the entire system through global address mapping. In this way, the private memory can be used globally, rather than being available only to the node to which it belongs. In addition, external DDR memory still exists as a storage medium in the multi-core processor system. These DDR memories can be mounted under the bus and accessed through an internal network (such as NoC or MESH).

[0053] In a multi-core processor system, the hardware architecture related to external memory: External DDR memory is connected to the processor system's main control module (such as the master node) via a high-speed bus. To support concurrent access by multi-core processors, DDR memory is typically divided into multiple partitions, and access requests are managed through a complex arbitration mechanism.

[0054] In multi-core processor systems, the network structure related to external memory: In multi-core processor systems, communication between processor cores and between processor cores and external DDR memory relies on a network on chip (NoC) or mesh network (MESH). These networks use packet switching technology to route data packets from source nodes to destination nodes.

[0055] In multi-core processor systems, cache coherence protocols such as MESI (Modified, Exclusive, Shared, Invalid) and MOESI (Modified, Owned, Exclusive, Shared, Invalid) are commonly used to ensure data consistency across processor cores. These protocols synchronize the cache status of each processor core through broadcast or point-to-point messaging.

[0056] In a multi-core processor system, the process of accessing external memory is as follows: When a processor core needs to access external DDR memory, it first checks its local cache for a hit. If it misses, it sends an access request over the internal network. After routing and arbitration, it finally accesses the DDR memory and returns the data.

[0057] An embodiment of the present application provides a data processing method, which is described in detail below in conjunction with the execution flow of the data processing method.

[0058] Please refer to Figure 1 , Figure 1 This is a flowchart of an implementation of a data processing method provided in an embodiment of the present application. The method can be executed in a first node in a multi-core processor system. The method includes:

[0059] S101: Receive a memory access request and determine a target address corresponding to the memory access request.

[0060] Among them, the nodes in the multi-core processor system have private memory, and the private memory is incorporated into the address space of the entire system through global address mapping.

[0061] The first node may be any node in the multi-core processor system, that is, any core.

[0062] This memory access request can be sent by an application such as a deep learning inference application or a real-time video processing application, or it can be forwarded from another node. The resource requested by the memory access request can be stored in private memory on the chip or in external memory.

[0063] After receiving a memory access request, the first node first determines the target address of the scheme requested by the memory access request. The memory access request can directly carry the target address, and the target address can be determined by parsing the memory access request. The memory access request can also carry an identifier corresponding to the data requested for access, and the target address can be determined based on the identifier.

[0064] It should be noted that since the nodes in the multi-core processor system have private memory, and the private memory is included in the address space of the entire system through global address mapping, the address of the private memory can be globally accessed.

[0065] In a specific embodiment of the present application, before a first node in a multi-core processor system receives a memory access request, the process includes:

[0066] Perform global address mapping on private memory so that the address of private memory is included in the address space of the entire system;

[0067] Configure the address priority of the private memory. The address priority of the private memory is higher than that of the external memory.

[0068] For ease of description, the above steps are combined and explained below.

[0069] High-speed SRAM can be used as private memory, which is directly mounted on the node processor core or Master (RN) node. Compared with traditional DDR, the characteristics of private memory include high speed, moderate capacity and address mapping function.

[0070] Among them, high speed: using internal high-speed SRAM technology, its access speed is much faster than traditional DDR memory.

[0071] Moderate capacity: The memory capacity is usually several MB, which is sufficient to store key intermediate data, model parameters, or temporary calculation results.

[0072] Address mapping function: Although this memory is constructed using SRAM, it is allocated in the system global address space and can be identified and accessed by other nodes in the system.

[0073] In this way, extremely low-latency and high-bandwidth storage access capabilities can be provided to directly connected nodes (such as Master (RN) nodes), while supporting global shared access. However, the access latency to external nodes will be higher, thereby encouraging applications to access critical data on high-performance nodes and reducing access competition across the entire system.

[0074] For details, please refer to Figure 2 , Figure 2 An address diagram provided for an embodiment of the present application; private memory is incorporated into the address space of the entire system through global address mapping, and can be configured with a higher access priority.

[0075] System structure such as Figure 3 , Figure 3 A system structure diagram provided for an embodiment of the present application. When the Master (RN) node accesses memory, the system first detects whether the access request falls within the address range of the private memory (SRAM). If it hits, it directly uses the high-speed interface for access.

[0076] After the target address is determined, it is possible to know which memory address range the target address falls into. In this embodiment, the memory address range is divided into three categories: the private memory address range of the node, the private memory address range of other nodes, and the external memory address range.

[0077] According to the corresponding address range that the target address falls into, the corresponding access operation is performed.

[0078] In a specific embodiment of the present application, when determining whether the target address falls within a range, it is detected whether the target address is within the private memory address range of the first node;

[0079] If yes, go directly to step S102;

[0080] If not, check whether the target address is in the private memory address range of other nodes in the multi-core processor system. If so, determine the corresponding other node as the second node and execute step S103; if not, check whether the target address is in the external memory. If so, execute step S104. If the target address is not detected, output an error.

[0081] The target address is the address of the target resource requested to be accessed by the memory access request.

[0082] That is, in this embodiment, the target resource is searched first in the private memory of the first node, then in the private memories of other nodes, and finally in the external memory. This maximizes the private memory hit rate and improves access speed.

[0083] S102: If the target address falls within the private memory address range of the first node, directly access the target address.

[0084] When it is determined that the target address falls within the private memory address range of the first node, that is, within the private memory address range of the current node, the target address can be directly accessed, thereby quickly completing the access operation of the memory access request.

[0085] In a specific implementation of the present application, directly accessing the target address includes:

[0086] Determining whether the memory access request is forwarded to the first node by another node;

[0087] If not, access the target address directly;

[0088] If yes, determine whether the private memory of the first node is busy;

[0089] When the private memory of the first node is in a busy state, access to the target address is prohibited;

[0090] When the private memory of the first node is in an idle state, the target address is directly accessed.

[0091] For ease of description, the above steps are combined and explained below.

[0092] By determining the source of memory access requests and recording access frequency, other nodes can be prevented from frequently accessing private memory, thereby ensuring priority access to high-performance nodes and avoiding resource abuse.

[0093] Specifically, in order to avoid other nodes occupying the private memory of its own node, resulting in reduced access efficiency, when it is determined that the target address of the memory access request is within the private memory address range of the local node, it is possible to first determine whether the memory access request is forwarded by other nodes. If not, the target address can be directly accessed; if so, it is necessary to further determine whether the private memory of the first node is in a busy state.

[0094] For example 1, a buffer queue can be established to store memory access requests whose target addresses are within the private memory address range of the local node. If the number of memory access requests brought out by the buffer queue exceeds a specified threshold, it can be determined that the private memory of the local node is in a busy state; otherwise, it is in an idle state.

[0095] In Example 2, the number of times other nodes access their own private memory can be counted. When the counted number is greater than a specified threshold, it can be determined that the private memory of the first node is in a busy state, and other nodes are prohibited from accessing the target address. When the counted number is less than or equal to the specified threshold, it can be determined that the private memory of the first node is in an idle state, and other nodes are allowed to access the target address.

[0096] If the local node's private memory is busy, access to the target address can be prohibited; if the local node's private memory is idle, the target address can be directly accessed. In this way, the access needs of the local node can be met first, and then the indirect access needs of other nodes can be met.

[0097] In a specific implementation of the present application, directly accessing the target address includes:

[0098] The target address is directly accessed by utilizing a high-speed interface connected to its own private memory; wherein the high-speed interface is an address data access interface of a static random access memory.

[0099] In this embodiment, in order to accelerate access to private memory, a standard SRAM (Static Random Access Memory) address data access interface can be used. This interface design has the characteristics of low latency and high transmission rate, and can be seamlessly connected with the high-performance processor core.

[0100] In one specific embodiment of the present application, if the memory access request is sent by the second node, then after directly accessing the target address, the method further includes: sending the read target data to the second node. That is, since the memory access request is forwarded by the second node, after accessing the target address, the read target data needs to be sent to the second node, thereby completing the second node's indirect access to the private memory.

[0101] S103: If the target address falls within the private memory address range of the second node, forward the memory access request to the second node so as to access the target address through the second node.

[0102] The second node may be any node with a private memory in the multi-core processor system except the first node.

[0103] If the target address falls within the private memory address range of the second node, and considering that on-chip memory access is faster than off-chip memory access, the target address can be accessed through the second node by forwarding the memory access request to the second node.

[0104] After receiving the memory access request, the second node can process it in a manner similar to the specific access processing operation of the first node when the target address falls within the private memory address range of its own node, which will not be described in detail here.

[0105] In a specific implementation of the present application, forwarding the memory access request to the second node includes:

[0106] establishing a communication connection with the second node;

[0107] A memory access request is sent to the second node using the communication connection.

[0108] For ease of description, the above steps are combined and explained below.

[0109] In this embodiment, to forward the memory access request to the second node, a communication connection may be established with the second node first, and then the memory access request may be sent to the second node based on the communication connection.

[0110] For example, although private memory belongs to the global address space, when other nodes want to access this memory, they can first establish a connection with the Master (RN) node directly mounting the memory via the bus, and then forward the access request through a specific control interface on that node. Due to bus scheduling and additional interface latency involved in this forwarding, other nodes' access speed to this private memory will be significantly slower than directly connected nodes. However, compared to accessing external memory, since it is processed only on-chip, the access speed is significantly higher. In other words, the access speed of indirect access to private memory is between direct access to private memory and access to external memory.

[0111] S104: If the target address falls within the external memory address range, access the target address by using the external memory channel.

[0112] If the target address falls within the address range of the external memory, the target address can be accessed by connecting to the external memory channel. For example, a memory access request is sent from the internal network, and after routing and arbitration, the DDR memory is accessed and the data is returned.

[0113] In a specific embodiment of the present application, it also includes:

[0114] Monitor access to resources in private memory and determine hot and cold classification of resources;

[0115] Migrate cold resources to external memory;

[0116] Migrate non-local hot resources to the target node with the highest number of indirect accesses.

[0117] For ease of description, the above steps are combined and explained below.

[0118] In this embodiment, the access to the resources in the private memory can be monitored, and the hot and cold classification of the resources can be determined based on the monitoring situation. Cold resources can be directly migrated to the external memory, and non-local hot resources can be migrated to the target node with the most access times.

[0119] Specifically, the number of resource accesses and access nodes can be counted. For resources whose total number of accesses is lower than a specified threshold, they can be directly determined as cold resources; for resources whose total number of accesses is higher than a specified threshold, if the number of accesses to the local node is higher than the number of accesses to other nodes, they can be determined as hot resources; if the number of accesses to the local node is lower than the number of accesses to other nodes, they can be determined as non-local hot resources.

[0120] In this way, the hot resources corresponding to the mounted node can be retained in private memory as much as possible, thereby speeding up access.

[0121] In the present application, since the nodes in the multi-core processor system have private memory, and the private memory is incorporated into the address space of the entire system through global address mapping; after the first node in the multi-core processor system receives a memory access request and determines the target address corresponding to the memory access request, it can be determined which address range the target address falls into. In the case where the target address falls within the private memory address range of the first node, the target address can be accessed directly. In the case where the target address falls within the private memory address range of the second node, considering that the efficiency of data access within the chip is much higher than the access efficiency of off-chip memory, the memory access request can be forwarded to the second node so that the target address can be accessed through the second node. In the case where the target address falls within the external memory address range, the target address is accessed by connecting to the external memory channel.

[0122] That is to say, in this application, by setting up private memory within the chip for the nodes in the multi-core processor system, and incorporating the addresses of these private memories into the address space of the entire system, memory access requests can directly request access to the private memory, thereby accelerating access processing efficiency. In addition, for targets whose address range is not the private memory address range of this node, but the private memory address range of other nodes, the request will also be forwarded, thereby achieving indirect access to the private memory. In this way, while making full use of the private memory, access can be completed within the chip, which can greatly reduce the access time and effectively improve the technical effect of access efficiency.

[0123] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0124] In order to facilitate those skilled in the art to better understand and implement the data processing method provided in the embodiments of the present application, the data processing method is described in detail below with reference to a specific practical scenario as an example.

[0125] For high-performance computing application scenarios, high-speed SRAM can be designed as private memory. This memory is directly mounted on the node processor core or Master (RN) node, and has high speed, moderate capacity and address mapping functions.

[0126] In this way, it is possible to provide extremely low-latency and high-bandwidth storage access capabilities for nodes directly connected to the private memory (such as Master (RN) nodes), while supporting global shared access. By encouraging applications to access critical data on high-performance nodes, it reduces access contention across the entire system.

[0127] That is to say, in this multi-core processor system, there are two types of access to private memory: direct connection and indirect access. Direct connection: private SRAM memory is directly connected to the Master (RN) node or node processor core through a dedicated high-speed interface. This direct connection makes data access latency very low and bandwidth very high, which can meet application scenarios with extremely high real-time requirements, such as deep learning inference and real-time video processing. Indirect access: Although private memory belongs to the global address space, when other nodes want to access this memory, they must first establish a connection with the Master (RN) node that directly mounts the memory through the bus, and then forward the access request through the specific control interface on the node. Because this forwarding involves bus scheduling and additional interface delays, the access speed of other nodes to this private memory will be significantly slower than that of directly connected nodes.

[0128] In terms of interface selection, a standard SRAM address data access interface can be used. This interface design has the characteristics of low latency and high transmission rate, and can be seamlessly connected with high-performance processor cores.

[0129] As for the internal structure, the private memory is composed of high-frequency, high-speed SRAM chips, usually with a capacity of several MB, taking into account the needs of high-speed access and sufficient storage space.

[0130] This system achieves global address space integration: private SRAM is mapped into the global address space and has higher address priority than external DDR memory. This means that when a Master (RN) node in the system initiates a memory access, it first checks whether the requested address falls within private memory, thereby obtaining the fastest response. This allows for access path optimization: if a direct hit is found in private memory, data access is handled directly by the high-speed interface; if a miss is found, the access request is automatically redirected to external DDR memory and transmitted over the internal network. Although this process has a higher latency, it ensures system data integrity and unified management.

[0131] Furthermore, access control and resource management (ACSM) can be implemented, for example, by setting up an access control module. To prevent other nodes from frequently occupying and accessing this high-speed private memory, thereby impacting the performance of directly connected nodes, a dedicated access control module has been designed. This module determines whether access is permitted based on the source of the access request (i.e., whether it is from a directly connected Master (RN) node or another indirect access node), and records and limits access frequency when necessary. Optimizing resource allocation: By monitoring and counting access requests, the system can dynamically optimize resource allocation strategies, ensuring that private memory primarily serves local high-performance needs rather than being occupied by a large number of external requests.

[0132] By directly mounting private memory on the Master (RN) node or node processor core, utilizing standard high-speed interfaces and global address mapping, it meets the needs of local high-performance data access while also supporting global shared access (albeit with higher latency for external access). Furthermore, the access control module effectively prevents frequent access from external nodes, thus achieving a balance between system performance and resource sharing. This solution is particularly suitable for applications requiring extremely high memory access speeds, such as deep learning inference, real-time video processing, and scientific computing.

[0133] In high-performance computing, in high-performance computing scenarios such as deep learning reasoning, real-time video processing, and scientific computing, Master (RN) nodes often need to quickly access large amounts of intermediate data and model parameters. The data processing method implemented in this application can store key data and intermediate calculation results in a low-latency, high-bandwidth SRAM; enabling the Master (RN) node to access data at an extremely fast speed, significantly improving the overall performance of the system. In addition, the system load can be balanced and optimized. As a local cache, the directly connected private memory is used as a local cache, which not only speeds up data access, but also reduces dependence on external DDR memory, reducing the delay and energy consumption caused by global data transmission. Sharing and control balance: Although the global address mapping allows other nodes to access this memory, the access control module can effectively prevent frequent access by external nodes, thereby ensuring the high-performance operation of the local node.

[0134] In other words, the data processing method provided in the embodiments of the present application has the following technical features in practical applications:

[0135] High-speed SRAM as private memory: High-speed SRAM replaces traditional DDR memory to store intermediate data and key computational results. This SRAM not only offers lower latency but also significantly outperforms traditional memory systems in speed, meeting the demands of high-performance computing applications.

[0136] Global address mapping of private memory: Although the private SRAM memory is directly connected to the Master node or node processor core, it is included in the system's global address map, allowing other nodes to access it through the bus, optimizing memory access efficiency and bandwidth.

[0137] High-priority memory access control: A memory access control mechanism has been introduced that prioritizes access to external DDR memory. When a Master (RN) node accesses memory, it first checks whether the private memory is a hit. If so, the access is made directly. Otherwise, external DDR memory is accessed through the internal network. This priority management improves the efficiency of local data access and reduces access latency.

[0138] The access control and resource management module, by determining the source of access requests and recording access frequency, can prevent other nodes from frequently accessing private memory, thereby ensuring priority access for high-performance nodes and preventing resource abuse. Global shared access is supported but frequent access is restricted. While private memory is designed to be shared system-wide, this application, through a properly designed access control module, limits frequent access by external nodes to private memory, avoiding degradation of system performance while maintaining the efficiency of local access.

[0139] The combination of high-speed SRAM and global address mapping optimizes the memory access path, providing extremely low-latency direct memory access through a high-speed interface, while also supporting global shared access from other nodes. This design balance of local efficiency and global sharing effectively improves the overall performance of the system and is particularly suitable for application requirements in high-performance computing scenarios.

[0140] These technical features solve the problems of excessive memory access latency and resource conflicts in existing technologies and have important technical value and application prospects.

[0141] It should be noted that in addition to the field of high-performance computing, the data processing method provided by this application can also be applied to many other technical fields. The following are possible extended applications and variations of this technical solution:

[0142] Application Scenarios for Fixed-Line (Wired) Networks: In fixed-line networks, the proprietary SRAM memory design of this invention can be used for fast data storage and access within data centers, server clusters, and high-performance computing (HPC) nodes, reducing memory bandwidth bottlenecks and improving overall computing performance. In fixed-line environments, data access paths are typically short and connected via high-speed fiber or Ethernet, resulting in low memory access latency. This approach is well-suited for high-bandwidth and high-capacity requirements. The proprietary SRAM can be used directly as an accelerator, ensuring rapid response times for various computing tasks.

[0143] Applications Migrating to Mobile (Wireless) Networks: In mobile networks, network nodes communicate wirelessly, and the computing devices involved (such as smartphones and IoT devices) are typically subject to power and bandwidth constraints. Despite this, the design of high-speed private memory can still improve device computing performance, especially in compute-intensive applications such as deep learning inference and real-time video processing. Compared to fixed networks, nodes in mobile networks have more complex network topologies and wireless bandwidth constraints. Therefore, when using private SRAM, it is necessary to optimize the communication interface and network transmission protocol to ensure fast data transmission within limited bandwidth. Mobile devices typically have limited storage and computing resources. Private memory can be designed to offload computing loads by combining local cache with cloud storage, allowing local processing of some compute-intensive tasks and improving response speed. Devices in mobile networks need to adapt to higher bandwidth latency and power consumption constraints. Therefore, in mobile applications, the capacity and power consumption of private SRAM may need to be adjusted to optimize access speed and maintain low energy consumption. For example, low-power, high-efficiency LPDDR memory can be used to replace traditional SRAM while maintaining the efficient access capabilities of private memory. On mobile devices, private SRAM can be combined with the device's local NAND Flash or UFS storage to form a tiered storage system. Data that requires fast access can be stored directly in SRAM, while less frequently accessed data can be stored in slower flash memory.

[0144] Application scenarios in the field of high-performance computing (HPC): In the field of high-performance computing, private SRAM memory is used to optimize fast data transmission and cache access between nodes. It is particularly suitable for tasks such as deep learning and scientific computing, and can significantly improve processing speed and memory bandwidth.

[0145] Applications migrating to embedded systems (IoT): Embedded systems (such as industrial automation, in-vehicle computing, and smart homes) often face space, power, computing, and storage constraints. In these systems, traditional large-capacity memories (such as DDR) may not be suitable due to power and space issues. The core advantages of private SRAM design lie in its low latency and high bandwidth, which can meet the needs for fast access and efficient data processing. In embedded systems, private SRAM can not only be directly mounted on a single core or processor, but can also be used as a data cache to accelerate task execution, especially in real-time operating systems. Combined with low-power memory and optimized network protocols, SRAM can be seamlessly integrated with the overall architecture of the embedded system, providing fast data response.

[0146] Data center application scenarios: In data centers, private SRAM designs can improve computing performance by combining cache and storage systems. This is especially true when processing complex cloud computing tasks and big data analysis, which can increase computing speed and data transmission efficiency.

[0147] Applications migrating to edge computing: Edge computing primarily refers to pushing computing and data processing to the edge of the network (closer to the data source). In edge computing, devices need to process large amounts of data from sensors and IoT devices and respond in real time. Private SRAM can effectively accelerate local computing tasks, reducing data transmission latency and bandwidth requirements. This is particularly useful for real-time data processing applications such as video analysis, AI inference, and intelligent surveillance, which require low latency and high real-time performance. By combining fast private memory with an edge computing architecture, data can be processed quickly close to the data source, avoiding the latency issues associated with large-scale data transmission.

[0148] It can be seen that the data processing method provided by this application is not only widely used in the field of high-performance computing, but can also be migrated to multiple other fields, including fixed-line to mobile networks, embedded systems, edge computing, etc. The changes and adaptations in each field mainly involve the optimization of memory access, the adjustment of storage hierarchy, and compatibility with existing technical architectures. By adjusting the capacity, power consumption management, and network protocol of private SRAM, this application can meet the requirements of efficient, low-latency, and high-bandwidth memory access in different fields.

[0149] The embodiments of the present application further provide a multi-core processor system, which can be cross-referenced with the above method embodiments.

[0150] The multi-core processor system Figure 4 As shown, the node RN in the multi-core processor system has a private memory Sram, and the private memory is included in the address space of the entire system through global address mapping;

[0151] The first node RN0 in the multi-core processor system includes:

[0152] The request receiving module 101 is used to receive a memory access request and determine a target address corresponding to the memory access request;

[0153] a direct address access module 102 for directly accessing the target address if the target address falls within the private memory address range of the first node;

[0154] an indirect address access module 103 for forwarding the memory access request to the second node if the target address falls within the private memory address range of the second node, so as to access the target address through the second node;

[0155] The external memory access module 104 is configured to access the target address by connecting to the external memory channel if the target address falls within the external memory address range.

[0156] In the present application, since the nodes in the multi-core processor system have private memory, and the private memory is incorporated into the address space of the entire system through global address mapping; after the first node in the multi-core processor system receives a memory access request and determines the target address corresponding to the memory access request, it can be determined which address range the target address falls into. In the case where the target address falls within the private memory address range of the first node, the target address can be accessed directly. In the case where the target address falls within the private memory address range of the second node, considering that the efficiency of data access within the chip is much higher than the access efficiency of off-chip memory, the memory access request can be forwarded to the second node so that the target address can be accessed through the second node. In the case where the target address falls within the external memory address range, the target address is accessed by connecting to the external memory channel.

[0157] That is to say, in this application, by setting up private memory within the chip for the nodes in the multi-core processor system, and incorporating the addresses of these private memories into the address space of the entire system, memory access requests can directly request access to the private memory, thereby accelerating access processing efficiency. In addition, for targets whose address range is not the private memory address range of this node, but the private memory address range of other nodes, the request will also be forwarded, thereby achieving indirect access to the private memory. In this way, while making full use of the private memory, access can be completed within the chip, which can greatly reduce the access time and effectively improve the technical effect of access efficiency.

[0158] In a specific embodiment of the present application, the direct address access module is specifically used to directly access the target address using a high-speed interface connected to its own private memory; wherein the high-speed interface is an address data access interface of a static random access memory.

[0159] In a specific embodiment of the present application, it also includes:

[0160] The data transfer module is used for directly accessing the target address and then sending the read target data to the second node if the memory access request is sent by the second node.

[0161] In a specific embodiment of the present application, the indirect address access module is specifically configured to establish a communication connection with the second node;

[0162] A memory access request is sent to the second node using the communication connection.

[0163] In a specific embodiment of the present application, the address mapping module is configured to perform global address mapping on the private memory before the first node in the multi-core processor system receives a memory access request, so that the address of the private memory is included in the address space of the entire system;

[0164] Configure the address priority of the private memory. The address priority of the private memory is higher than that of the external memory.

[0165] In a specific embodiment of the present application, it also includes:

[0166] Resource management module, used to monitor access to resources in private memory and determine the hot and cold classification of resources;

[0167] Migrate cold resources to external memory;

[0168] Migrate non-local hot resources to the target node with the highest number of indirect accesses.

[0169] In a specific embodiment of the present application, the direct address access module is specifically configured to determine whether the memory access request is forwarded to the first node by another node;

[0170] If not, access the target address directly;

[0171] If yes, determine whether the private memory of the first node is busy;

[0172] When the private memory of the first node is in a busy state, access to the target address is prohibited;

[0173] When the private memory of the first node is in an idle state, the target address is directly accessed.

[0174] For the description of the features in the embodiment corresponding to the multi-core processor system, please refer to the relevant description of the embodiment corresponding to the data processing method, and no further details will be given here.

[0175] Corresponding to the above method embodiment, an embodiment of the present application further provides an electronic device. The electronic device described below and the data processing method described above can refer to each other.

[0176] See also Figure 5 As shown, the electronic device includes:

[0177] Memory 332, for storing computer programs;

[0178] The processor 322 is configured to implement the steps of the data processing method of the above method embodiment when executing a computer program.

[0179] For details, please refer to Figure 6 , Figure 6This is a schematic diagram of the specific structure of an electronic device provided in this embodiment. This electronic device may vary significantly due to different configurations or performance. It may include one or more central processing units (CPUs) (for example, one or more processors) and memory 332. The memory 332 stores one or more computer programs 342 or data 344. The memory 332 may be temporary storage or permanent storage. The program stored in the memory 332 may include one or more modules (not shown), each of which may include a series of instruction operations in the data processing device. Furthermore, the processor 322 may be configured to communicate with the memory 332 to execute the series of instruction operations in the memory 332 on the electronic device 301.

[0180] The electronic device 301 may further include one or more power supplies 326 , one or more wired or wireless network interfaces 350 , one or more input / output interfaces 358 , and / or one or more operating systems 341 .

[0181] The steps in the data processing method described above can be implemented by the structure of an electronic device.

[0182] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above-mentioned data processing method embodiments when run.

[0183] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0184] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above data processing method embodiments are implemented.

[0185] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above-mentioned data processing method embodiments are implemented.

[0186] Those skilled in the art may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0187] The above is a detailed introduction to a data processing method, system, device and readable storage medium provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the present application.

Claims

1. A data processing method, characterized in that: include: A first node in a multi-core processor system receives a memory access request and determines a target address corresponding to the memory access request; wherein the node in the multi-core processor system has a private memory, and the private memory is incorporated into the address space of the entire system through a global address mapping; If the target address falls within the private memory address range of the first node, directly accessing the target address; If the target address falls within the private memory address range of the second node, forwarding the memory access request to the second node so as to access the target address through the second node; If the target address falls within the external memory address range, the target address is accessed by utilizing the external memory channel.

2. The data processing method according to claim 1, wherein: Directly access the target address, including: The target address is directly accessed by utilizing a high-speed interface connected to its own private memory; wherein the high-speed interface is an address data access interface of a static random access memory.

3. The data processing method according to claim 1, wherein: If the memory access request is sent by the second node, after directly accessing the target address, the method further includes: The read target data is sent to the second node.

4. The data processing method according to claim 1, wherein: Forwarding the memory access request to the second node includes: establishing a communication connection with the second node; The memory access request is sent to the second node using the communication connection.

5. The data processing method according to claim 1, wherein: Before a first node in a multi-core processor system receives a memory access request, the process includes: Performing global address mapping on the private memory so that the address of the private memory is included in the address space of the entire system; Configure the address priority of the private memory; wherein the address priority of the private memory is higher than the address priority of the external memory.

6. The data processing method according to claim 1, wherein: Also includes: Monitor access to resources in the private memory and determine whether the resources are hot or cold; Migrating cold resources to the external memory; Migrate non-local hot resources to the target node with the highest number of indirect accesses.

7. The data processing method according to any one of claims 1 to 6, characterized in that: Directly access the target address, including: Determining whether the memory access request is forwarded to the first node by another node; If not, directly access the target address; If yes, determining whether the private memory of the first node is in a busy state; When the private memory of the first node is in a busy state, prohibiting access to the target address; When the private memory of the first node is in an idle state, the target address is directly accessed.

8. A multi-core processor system, characterized in that: The nodes in the multi-core processor system have private memories, and the private memories are incorporated into the address space of the entire system through global address mapping; The first node in the multi-core processor system includes: A request receiving module, configured to receive a memory access request and determine a target address corresponding to the memory access request; a direct address access module, configured to directly access the target address if the target address falls within the private memory address range of the first node; an indirect address access module, configured to forward the memory access request to the second node if the target address falls within the private memory address range of the second node, so as to access the target address through the second node; The external memory access module is configured to access the target address by connecting to an external memory channel if the target address falls within the external memory address range.

9. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the data processing method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the data processing method according to any one of claims 1 to 7.

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