A data transmission method, apparatus, device and medium

Abstract

The application discloses a data transmission method and device, equipment and medium, and relates to the technical field of computers. By adopting a redundant architecture of multiple direct memory access channels, combining a channel transmission mode based on a trigger condition and a target screening strategy, a suitable target direct memory access channel is selected from multiple direct memory access channels to execute a data transmission task. When an error occurs in a direct memory access channel, the system can automatically switch to other direct memory access channels to continue executing the data transmission task, avoiding the overall interruption of a non-transparent bridge link caused by the failure of a single direct memory access channel. Meanwhile, for direct memory access failure, a hierarchical repair strategy based on a fault level is adopted to accurately repair the fault channel without the need to reinitialize the entire non-transparent bridge link and all devices, greatly shortening the fault processing time, effectively improving the fault recovery efficiency, and guaranteeing the continuity of cross-storage node data transmission.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a data transmission method, apparatus, device, and medium. Background Art

[0002] With the development of data centers, cloud computing, and high-performance computing (HPC), the demand for multi-server collaboration has increased significantly. To address this, Non-Transparent Bridge (NTB) technology has emerged. It enables direct memory access (DMA) between multiple hosts over the Peripheral Component Interconnect Express (PCI Express) bus, while also providing hardware-level address space isolation to prevent hardware failures on a single node from spreading to other nodes.

[0003] See also Figure 1 As shown in the figure, the traditional solution relies on the "NTB+DMA" architecture to achieve cross-node data interaction. Simply put, the business layer initiates data transmission requirements, relies on NTB to connect system resources, and DMA performs data movement. During the process, the data verification module verifies the integrity, and the error detection module monitors abnormalities. If there is a problem, the error handling module intervenes. Its defects are mainly reflected in the following three aspects: (1) Slow fault recovery: If a link failure occurs in the traditional solution, the link needs to be reinitialized. The initialization includes the initialization of devices such as NTB and DMA, as well as link negotiation. The entire process is in seconds, so the fault recovery speed is slow; (2) Business interruption: Once an error occurs in the DMA controller, the NTB link will be interrupted, and data cannot be transmitted. Because the system cannot perceive the data flow, it is easy to cause the entire storage business to be interrupted. Summary of the Invention

[0004] This application provides a data transmission method, apparatus, device, and medium that avoids the entire non-transparent bridge link interruption caused by a single direct memory access channel failure. At the same time, it can accurately repair the faulty channel, significantly shortening the fault handling time. The specific solution is as follows:

[0005] This application provides a data transmission method, including:

[0006] Initialize non-transparent bridge link;

[0007] Get the data transmission request and determine whether the trigger conditions of the channel transmission mode are currently met;

[0008] If the trigger condition of the channel transmission mode is currently met, a target direct memory access channel is selected from multiple preset direct memory access channels based on the target screening strategy, and the cross-storage node data transmission task for the data transmission request is executed through the target direct memory access channel;

[0009] A repair strategy is determined based on a fault level corresponding to a direct memory access fault detected during a data transmission process, and repair of the direct memory access fault is implemented based on the repair strategy.

[0010] The present application also provides a data transmission device, comprising:

[0011] Initialization module, used to initialize the non-transparent bridge link;

[0012] The mode trigger module is used to obtain data transmission requests and determine whether the trigger conditions of the channel transmission mode are currently met;

[0013] a channel screening module configured to, if a trigger condition of the channel transmission mode is currently met, screen out a target direct memory access channel from a plurality of preset direct memory access channels based on a target screening policy, and execute a cross-storage node data transmission task for the data transmission request through the target direct memory access channel;

[0014] The fault repair module is used to determine a repair strategy based on a fault level corresponding to a direct memory access fault detected during data transmission, and to repair the direct memory access fault based on the repair strategy.

[0015] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned data transmission methods when executing the computer program.

[0016] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned data transmission methods are implemented.

[0017] Beneficial effects: This application adopts a redundant architecture of multiple direct memory access channels, combined with a channel transmission mode based on trigger conditions and a target screening strategy, to select a suitable target direct memory access channel from multiple direct memory access channels to perform data transmission tasks. This allows the system to automatically switch to other direct memory access channels to continue data transmission tasks when an error occurs in a certain direct memory access channel, avoiding the overall interruption of the non-transparent bridge link caused by a single direct memory access channel failure, and solving the problem in traditional solutions that "once an error occurs in the direct memory access channel controller, the non-transparent bridge link will be interrupted." For direct memory access failures, this application adopts a hierarchical repair strategy based on fault levels, which can accurately repair the faulty channel without reinitializing the entire non-transparent bridge link and all devices, significantly shortening the fault processing time, solving the problem of "slow link failure recovery" in traditional solutions, improving fault recovery efficiency, and ensuring the continuity of data transmission across storage nodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0019] Figure 1 This is a schematic diagram of the traditional data transmission architecture;

[0020] Figure 2 A flow chart of a data transmission method provided in an embodiment of the present application;

[0021] Figure 3 A schematic diagram of a data transmission architecture provided in an embodiment of the present application;

[0022] Figure 4 A structural diagram of a data transmission device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0023] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0024] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0025] Traditional solutions rely on the "NTB+DMA" architecture to achieve cross-node data interaction. Simply put, the business layer initiates data transmission requirements, relies on NTB to connect system resources, and DMA performs data transfer. During the process, the data verification module verifies the integrity, and the error detection module monitors abnormalities. If there is a problem, the error handling module intervenes. Its defects are mainly reflected in the following three aspects: (1) Slow fault recovery: In traditional solutions, if a link failure occurs, the link needs to be reinitialized. The initialization includes the initialization of devices such as NTB and DMA, as well as link negotiation. The entire process is in seconds, so the fault recovery speed is slow; (2) Business interruption: Once an error occurs in the DMA controller, the NTB link will be interrupted, and data cannot be transmitted. Because the system cannot perceive the data flow, it is easy to cause the entire storage business to be interrupted.

[0026] To this end, the present application provides a data transmission solution that avoids the entire non-transparent bridge link interruption caused by a single direct memory access channel failure. At the same time, it can accurately repair the faulty channel, significantly shortening the fault handling time. To enable those skilled in the art to better understand the present application solution, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0027] In conjunction with the specific application environment architecture or specific hardware architecture on which the execution of the data transmission method depends, the specific application environment architecture or specific hardware architecture is described here: This solution is mainly used in multi-host collaborative storage systems (such as dual-controller storage systems), where nodes are connected via a PCIe (Peripheral Component Interconnect Express) bus. The hardware architecture uses the NTB module, DMA status detection module, DMA channel management module, DMA fault management module, and data transmission module as core functional carriers, and integrates the CPU and memory modules to implement a complete data transmission link. The NTB module uses the NTB chip at the hardware level to establish physical links and isolate memory between nodes. The DMA channel management module relies on multiple independent channels integrated in the multi-channel DMA controller to support parallel transmission, adapting to the low-latency, high-reliability cross-node communication requirements in scenarios such as data centers and cloud computing.

[0028] The embodiment of the present application provides a data transmission method. In conjunction with the execution process of the data transmission method, see Figure 2 and Figure 3 As shown, the method is described in detail, and the method includes:

[0029] Step S11: Initialize the non-transparent bridge link.

[0030] First, the key technical terms involved in this solution are explained: ① PCIe is a high-speed serial computer expansion bus standard used to connect computer motherboards with various peripheral devices, providing a high-speed, standardized channel for data transmission; ② NTB (Non-Transparent Bridge) is a hardware technology for interconnecting multiple host systems. It supports direct communication between different computing nodes (such as servers and storage devices) through the PCIe bus while achieving memory isolation; ③ CPU (Central Processing Unit) is the core of the computer, responsible for instruction execution, data processing and hardware control; ④ DMA (Direct Memory Access) is an efficient data transmission technology that allows hardware devices to directly access system memory without the CPU being involved in each transmission. This technology can significantly improve system efficiency.

[0031] Secondly, the core architecture of this solution is described: the core architecture of this solution includes the NTB module, DMA status detection module, DMA channel management module, DMA fault management module and data transmission module. These modules work together to implement multi-channel redundant transmission and fault classification processing. Among them, the NTB module, as the basis for cross-node communication, is responsible for link establishment and transmission management; the DMA status detection module monitors the channel status by periodically sending test data packets (such as empty DMA descriptors), and identifies idle, busy, transmission errors, channel timeouts and other states in real time; the DMA channel management module autonomously selects the optimal transmission channel based on the channel status, giving priority to scheduling idle or lightly tasked channels; the DMA fault management module executes repair strategies for different levels of faults, including channel-level soft reset and device-level initialization; the data transmission module is responsible for the execution of transmission tasks and descriptor backup, relying on the descriptor pool to achieve retransmission after a fault. Each module interacts through data streams and status signals, thus forming a closed-loop transmission and fault handling mechanism.

[0032] Furthermore, during the system startup phase, the initialization of NTB and DMA needs to be completed, specifically including: (1) NTB device and link initialization: led by the NTB module, the address and size configuration of the address translation window, link enablement and rate negotiation are completed, and at the same time, the data link is established through the device information verification between the two controllers to build the basic framework for cross-node communication; (2) DMA device and channel initialization: synchronously complete the DMA resource application and channel parameter configuration, including DMA descriptor address setting, descriptor writing and submission, channel opening and closing mechanism deployment, etc.; in this process, the DMA status detection thread is synchronously created to provide support for real-time monitoring of the channel status, ensuring that channel anomalies can be identified and responded to in a timely manner during subsequent transmission.

[0033] Step S12: Obtain a data transmission request, and determine whether a trigger condition for the channel transmission mode is currently met.

[0034] In this embodiment, the channel status of each direct memory access channel is obtained; the channel status includes idle state, busy state, error state and timeout state. The error state indicates that a channel-level transmission abnormality has occurred, and the timeout state indicates that the channel has not responded to the detection data packet sent by the preset detection thread within the preset time. Based on the channel status, it is determined whether the trigger condition of the channel transmission mode is currently met. The following is an expanded analysis:

[0035] In this embodiment, after receiving a data transmission request across storage nodes, the system needs to complete the judgment of the channel transmission mode triggering conditions through the collaboration of the DMA status detection module and the DMA channel management module. The specific process is as follows: First, the DMA status detection module obtains the status of each direct memory access channel in real time through a preset detection thread (created when the system starts). The channel status is divided into four categories: idle state (no transmission task), busy state (transmission task is being executed), error state (channel-level transmission anomaly occurs, such as descriptor queue overflow), and timeout state (failure to respond to the test data packet sent by the detection thread within the preset time, such as an empty DMA descriptor). Among them, the error state and the timeout state are marked by the detection thread based on the periodic heartbeat detection results, which directly reflect the abnormal situation of the channel. Subsequently, the DMA channel management module determines whether the triggering conditions of the channel transmission mode are currently met based on the above channel status.

[0036] Step S13: If the triggering condition of the channel transmission mode is currently met, based on the target screening strategy, a target direct memory access channel is screened out from multiple preset direct memory access channels, and the cross-storage node data transmission task for the data transmission request is executed through the target direct memory access channel.

[0037] In this embodiment, if there is currently at least one direct memory access channel with an idle or busy channel state, it is determined that the trigger condition of the channel transmission mode is currently met; if there are multiple direct memory access channels with an idle channel state, the direct memory access channel with the least number of target records is used as the target direct memory access channel; wherein the target record records that the channel has an error state or a timeout state in the historical transmission; if there is only one direct memory access channel with an idle channel state, the direct memory access channel is directly determined as the target direct memory access channel; if there is no direct memory access channel with an idle channel state, the task count of all direct memory access channels with a busy channel state is obtained; the direct memory access channel with the least number of tasks is used as the target direct memory access channel; the channel state of the target direct memory access channel is updated from idle to busy, or the task count of the target direct memory access channel is increased by one. The following examples are explained:

[0038] Exemplarily, if there are multiple idle DMA channels, the channel with the least number of target records is selected as the target direct memory access channel (the target record is used to record the error state or timeout state that occurred in the historical transmission of the channel). For example, the system presets 5 DMA channels, channels 1, 2, and 3 are idle, and the target record times of the three are 2, 0, and 1 respectively. At this time, channel 2 with the least number of target records is selected as the target direct memory access channel; if there is only one idle DMA channel, such as only channel 4 is idle, it is directly determined as the target direct memory access channel If there is no idle DMA channel, the channel with the smallest number of tasks is selected from all busy channels as the target direct memory access channel. For example, if both channel 5 and channel 6 are busy, the current number of tasks of channel 5 is 3, and the current number of tasks of channel 6 is 1, then channel 6 is selected. After the target direct memory access channel is selected, if the channel was originally in the idle state, its state is updated to the busy state. If it was originally in the busy state, its task number is increased by one. Through this dynamic screening mechanism, channels with lower loads can be scheduled first, and efficient and continuous data transmission across storage nodes can be guaranteed.

[0039] In this embodiment, if the triggering conditions of the channel transmission mode are not currently met, the central processing unit mode is triggered, and the data transmission task across storage nodes for the data transmission request is executed by the central processing unit. Specifically, if the status of all direct memory access channels is an error state or a timeout state, the system automatically triggers the CPU mode, and the CPU executes the data transmission task across storage nodes for the data transmission request. For example, among the five direct memory access channels preset by the system, channel 1 is marked as an error state due to a transmission error, and channels 2, 3, 4, and 5 are marked as a timeout state because they do not respond to the test data packet sent by the detection thread within the preset time. At this time, there is no direct memory access channel in an idle or busy state, that is, it is determined that the triggering conditions of the channel transmission mode are not met. The system then switches to the CPU mode, and the CPU completes the data transmission by reading the source node memory data and forwarding it to the target node memory via a non-transparent bridge link. This ensures that when all direct memory access channels fail, the data transmission task across storage nodes can still continue to be executed to avoid business interruption due to channel failure.

[0040] Step S14: determining a repair strategy based on the fault level corresponding to the direct memory access fault detected during the data transmission process, and implementing repair for the direct memory access fault based on the repair strategy.

[0041] If a direct memory access fault is detected during data transmission, and the channel status of the direct memory access channel where the direct memory access fault occurs is a timeout state or an error state, the direct memory access fault is determined to be a channel-level fault; a channel soft reset is performed on the direct memory access channel where the channel-level fault occurs, and it is determined whether the direct memory access fault still exists; if the direct memory access fault still exists, the direct memory access fault is determined to be a device-level fault, and the corresponding direct memory access channel is marked as unavailable; if the number of channels in the available state is less than a preset threshold, the direct memory access device is reset; wherein the direct memory access device integrates and manages multiple direct memory access channels.

[0042] For example, if a DMA fault is detected during data transmission and the faulty DMA channel is in a timeout or error state, it is considered a channel-level fault. A soft reset is first performed on the channel (e.g., resetting the channel descriptor queue and clearing the error flag). The DMA status detection module then resends test packets to verify that the fault has been resolved. For example, if channel 3 is marked as timed out due to temporary link jitter during transmission, the system performs a soft reset, and the test packets sent by the detection thread are responded to, the channel status returns to idle, and the fault is resolved. If the fault persists after the soft reset (e.g., no response after three consecutive tests), the fault is upgraded to a device-level fault, and the channel is marked as unavailable. The number of available channels in the system (idle or busy) is counted. If the number of available channels falls below a preset threshold (e.g., the preset threshold is 2, and only one channel is currently available), a reset is performed on the DMA device that integrates and manages all channels (e.g., restarting the device firmware and reinitializing the device registers) to restore more available channels. This hierarchical repair strategy not only enables precise repair of single-channel faults, but also ensures system continuity through device-level reset when channel resources are insufficient, avoiding the long interruptions caused by full-link restarts in traditional solutions.

[0043] Furthermore, in the process of implementing the repair for the direct memory access fault based on the repair strategy, the task descriptor corresponding to the data transmission task is determined, and the task descriptor is stored in the descriptor cache pool, so that after the repair is completed, the data transmission task is retransmitted based on the task descriptor in the descriptor cache pool. Specifically, in the process of implementing the repair for the direct memory access fault based on the repair strategy, the system will synchronously determine the task descriptor corresponding to the current data transmission task (including key transmission parameters such as the transmission source address, target address, data length, and verification information), and store the task descriptor in real time in a preset descriptor cache pool (the cache pool is a pre-allocated static memory area, independent of the dynamic memory space of each DMA channel, to ensure that data is not lost in the event of a fault). For example, if channel 2 experiences a sudden timeout while transferring a 10MB cross-node data block, the system identifies it as a channel-level fault and performs a soft reset. The system also stores the transfer task's descriptors (e.g., source address 0x10000, destination address 0x20000, length 0x00A00000, etc.) in the descriptor buffer pool. If channel 2 returns to normal after the soft reset, the DMA channel management module reads the descriptors from the buffer pool and reinitiates the data transfer. If the fault escalates to a device-level fault, marking channel 2 unavailable, the system will initialize another available channel (such as channel 1) and then call the descriptor information in the buffer pool to resume the transfer through the new target channel. This ensures that even during fault repair, the key parameters of the data transfer task are fully preserved, thus ensuring the integrity of the data transfer.

[0044] It can be seen that DMA data transmission relies on the descriptor pool to provide task parameters. The DMA status detection module continuously monitors the channel status and feeds back to the DMA channel management module. When the channel management module determines that the "channel is unavailable", it triggers a mode switch (such as CPU mode fallback). If an error is detected during transmission, it will further distinguish between "data error" and "channel error". In the case of data error, if the number of retransmissions is less than the threshold, the transmission will be re-initiated. If it exceeds the threshold, it will be returned to the NTB link for reprocessing. In the case of channel error, the "serious error flag" is first marked. If no serious error is triggered, the channel repair is performed. After the repair, if the number of channels is still less than the threshold, it is necessary to reset the link in conjunction with the NTB module. If the serious error flag is triggered, the device is directly reset. After the reset, the NTB and DMA link are reinitialized to ensure that the system returns to a usable state.

[0045] Based on the above embodiment, in a feasible implementation manner, in order to reduce the performance loss caused by CPU intervention, the embodiment of the present application may further include the following steps:

[0046] Perform repair operations on each direct memory access channel;

[0047] Continuously detect the channel status of each direct memory access channel;

[0048] If it is detected that the channel state of at least one direct memory access channel is restored to an idle state or a busy state, the data transmission task across storage nodes for the data transmission request executed by the central processor is stopped, and the mode is switched to the channel transmission mode.

[0049] When the system is in CPU mode, it does not interrupt fault handling of DMA channels. Instead, it synchronously performs repair operations (such as soft reset of channels, register check, and link renegotiation) on all DMA channels in error or timeout states. At the same time, the DMA status detection module continuously monitors the status changes of each channel in real time by periodically sending test packets. For example, the system switches to CPU mode because all five DMA channels are in timeout state. While the CPU is processing a transfer task, the repair operation performs a soft reset on channel 1. Three consecutive test packets sent by the detection thread are responded to, and channel 1 returns to idle state. At this point, the system determines that an available DMA channel exists and immediately stops the CPU's transfer process, switching the unfinished transfer task to channel 1 for continued execution, and re-enters channel transfer mode. This allows the system to quickly return to efficient channel transfer mode when the DMA channel becomes available again, ensuring the continuity and efficiency of data transmission across storage nodes.

[0050] In addition, the DMA fault management module in this solution also features error reporting: When a DMA channel or device fails, fault information (such as the faulty channel number, fault type, and occurrence time) is reported in real time to the system management interface or logging system. Once the fault is repaired, the fault record is automatically cleared and the recovery status is reported, allowing administrators to monitor system health in real time. If a DMA device fails to recover after multiple resets, the system triggers an alarm (such as an audible and visual alarm, or an email notification), prompting the administrator to manually intervene, thus preventing system risks caused by unresolved faults.

[0051] To further improve transmission efficiency and resource utilization, the system in this embodiment implements a dynamic threshold self-adjustment mechanism. This mechanism collects multi-dimensional data, such as historical DMA channel fault repair time, transmission load fluctuations, and CPU intervention frequency, in real time. Using machine learning models, it dynamically adjusts the fault retransmission threshold and the channel availability threshold. For example, when traffic peaks and transmission pressure increases, the channel retransmission threshold is automatically lowered, prioritizing quick channel switching to ensure smooth transmission. During periods of low traffic, the threshold is appropriately raised to fully utilize the channel retry and repair capabilities.

[0052] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0053] The embodiment of the present application also provides a data transmission device, see Figure 4 Shown, including:

[0054] Initialization module 11, used to initialize the non-transparent bridge link;

[0055] The mode trigger module 12 is used to obtain a data transmission request and determine whether the trigger condition of the channel transmission mode is currently met;

[0056] a channel screening module 13 configured to, if a trigger condition of the channel transmission mode is currently met, screen a target direct memory access channel from a plurality of preset direct memory access channels based on a target screening policy, and execute a cross-storage node data transmission task for the data transmission request through the target direct memory access channel;

[0057] The fault repair module 14 is configured to determine a repair strategy based on a fault level corresponding to a direct memory access fault detected during data transmission, and repair the direct memory access fault based on the repair strategy.

[0058] In a feasible implementation manner, the data transmission device further includes:

[0059] A status acquisition module is used to obtain the channel status of each direct memory access channel; the channel status includes idle state, busy state, error state and timeout state. The error state indicates that a channel-level transmission anomaly has occurred, and the timeout state indicates that the channel has not responded to the detection data packet sent by the preset detection thread within the preset time;

[0060] The trigger judgment module is used to judge whether the trigger condition of the channel transmission mode is currently met based on the channel status.

[0061] In a feasible implementation, the channel screening module 13 is specifically configured to:

[0062] If there is currently at least one direct memory access channel whose channel status is idle or busy, it is determined that the trigger condition of the channel transmission mode is currently met;

[0063] If there are multiple direct memory access channels whose channel status is idle, the direct memory access channel with the least number of target records is used as the target direct memory access channel; wherein the target record records that the channel has an error state or a timeout state in the historical transmission;

[0064] If there is only one direct memory access channel whose channel status is idle, the direct memory access channel is directly determined as the target direct memory access channel;

[0065] If there is no direct memory access channel whose channel status is idle, the number of tasks of all direct memory access channels whose channel status is busy is obtained;

[0066] The direct memory access channel with the smallest number of tasks is used as the target direct memory access channel;

[0067] The channel state of the target direct memory access channel is updated from the idle state to the busy state, or the number of tasks of the target direct memory access channel is increased by one.

[0068] In a feasible implementation manner, the data transmission device further includes:

[0069] The first mode switching module is configured to trigger the central processing unit mode if the triggering condition of the channel transmission mode is not currently satisfied, and execute the data transmission task across storage nodes for the data transmission request through the central processing unit.

[0070] In a feasible implementation manner, the data transmission device further includes:

[0071] A repair module, configured to perform a repair operation on each direct memory access channel;

[0072] A detection module, used for continuously detecting the channel status of each direct memory access channel;

[0073] The second mode switching module is used to stop executing the cross-storage node data transmission task for the data transmission request through the central processing unit and switch to the channel transmission mode if it is detected that the channel state of at least one direct memory access channel has returned to the idle state or the busy state.

[0074] In a feasible implementation manner, the fault recovery module 14 is specifically configured to:

[0075] If a direct memory access fault is detected during data transmission, and the channel state of the direct memory access channel where the direct memory access fault occurs is a timeout state or an error state, then the direct memory access fault is determined to be a channel-level fault;

[0076] Perform a soft reset on the direct memory access channel that has a channel-level fault, and determine whether the direct memory access fault still exists.

[0077] If the direct memory access fault still exists, the direct memory access fault is determined to be a device-level fault, and the corresponding direct memory access channel is marked as unavailable;

[0078] If the number of channels in the available state is less than a preset threshold, the direct memory access device is reset; wherein the direct memory access device integrates and manages multiple direct memory access channels.

[0079] In a feasible implementation manner, the data transmission device further includes:

[0080] A descriptor determination module, used to determine the task descriptor corresponding to the data transmission task;

[0081] The descriptor storage module is used to store the task descriptor in the descriptor cache pool so that after the repair is completed, the data transmission task can be retransmitted based on the task descriptor in the descriptor cache pool.

[0082] An embodiment of the present application further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any of the above-mentioned data transmission method embodiments.

[0083] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any of the above-mentioned data transmission method embodiments when running.

[0084] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0085] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any of the above-mentioned data transmission method embodiments are implemented.

[0086] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above-mentioned data transmission method embodiments are implemented.

[0087] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0088] The above is a detailed introduction to a data transmission method, apparatus, device and medium provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A data transmission method, characterized in that: include: Initialize non-transparent bridge link; Get the data transmission request and determine whether the trigger conditions of the channel transmission mode are currently met; If the trigger condition of the channel transmission mode is currently met, a target direct memory access channel is screened out from a plurality of preset direct memory access channels based on a target screening strategy, and a cross-storage node data transmission task for the data transmission request is executed through the target direct memory access channel; Determining a repair strategy based on a fault level corresponding to a direct memory access fault detected during data transmission, and implementing repair for the direct memory access fault based on the repair strategy; If the triggering condition of the channel transmission mode is currently met, a target direct memory access channel is screened out from a plurality of preset direct memory access channels based on a target screening strategy, including: If there is currently at least one direct memory access channel whose channel status is idle or busy, determining that the triggering condition of the channel transmission mode is currently met; If there are multiple direct memory access channels whose channel status is the idle state, the direct memory access channel with the least number of target records is used as the target direct memory access channel; wherein the target record records that the channel has an error state or a timeout state in historical transmission; If there is only one direct memory access channel whose channel status is the idle state, directly determining the direct memory access channel as the target direct memory access channel; If there is no direct memory access channel whose channel status is the idle state, obtaining the number of tasks of all direct memory access channels whose channel status is the busy state; Using the direct memory access channel with the smallest number of tasks as the target direct memory access channel; The channel state of the target direct memory access channel is updated from the idle state to the busy state, or the number of tasks of the target direct memory access channel is increased by one.

2. The data transmission method according to claim 1, wherein: The determining whether the triggering condition of the channel transmission mode is currently met includes: Obtaining the channel status of each of the direct memory access channels; the channel status includes an idle state, a busy state, an error state, and a timeout state, wherein the error state indicates that a channel-level transmission anomaly occurs, and the timeout state indicates that the channel fails to respond to a detection data packet sent by a preset detection thread within a preset time; Based on the channel status, it is determined whether a triggering condition for the channel transmission mode is currently satisfied.

3. The data transmission method according to claim 2, wherein: After determining whether the triggering condition of the channel transmission mode is currently met, the method further includes: If the triggering condition of the channel transmission mode is not currently met, the central processing unit mode is triggered, and the data transmission task across storage nodes for the data transmission request is executed by the central processing unit.

4. The data transmission method according to claim 3, wherein: The process of executing the cross-storage node data transmission task for the data transmission request by the central processor further includes: performing a repair operation on each of the direct memory access channels; Continuously detecting the channel status of each of the direct memory access channels; If it is detected that the channel state of at least one of the direct memory access channels has returned to the idle state or the busy state, the data transmission task across storage nodes for the data transmission request executed by the central processing unit is stopped, and the mode is switched to the channel transmission mode.

5. The data transmission method according to any one of claims 2 to 4, characterized in that: The determining of a repair strategy based on a fault level corresponding to a direct memory access fault detected during data transmission, and implementing repair for the direct memory access fault based on the repair strategy, includes: If a direct memory access fault is detected during the data transmission process, and the channel state of the direct memory access channel where the direct memory access fault occurs is the timeout state or the error state, then it is determined that the direct memory access fault is a channel-level fault; performing a channel soft reset process on the direct memory access channel where the channel-level fault occurs, and determining whether the direct memory access fault still exists; If the direct memory access fault still exists, determining the direct memory access fault as a device-level fault and marking the corresponding direct memory access channel as unavailable; If the number of channels in the available state is less than a preset threshold, the direct memory access device is reset; wherein the direct memory access device integrates and manages a plurality of the direct memory access channels.

6. The data transmission method according to claim 5, characterized in that: In the process of repairing the direct memory access fault based on the repair strategy, the method further includes: Determining a task descriptor corresponding to the data transmission task; The task descriptor is stored in a descriptor buffer pool, so that after the repair is completed, the data transmission task is retransmitted based on the task descriptor in the descriptor buffer pool.

7. A data transmission device, characterized in that: include: Initialization module, used to initialize the non-transparent bridge link; The mode trigger module is used to obtain data transmission requests and determine whether the trigger conditions of the channel transmission mode are currently met; a channel screening module configured to, if a trigger condition of the channel transmission mode is currently satisfied, screen a target direct memory access channel from a plurality of preset direct memory access channels based on a target screening policy, and execute a cross-storage node data transmission task for the data transmission request through the target direct memory access channel; a fault repair module, configured to determine a repair strategy based on a fault level corresponding to a direct memory access fault detected during data transmission, and implement repair for the direct memory access fault based on the repair strategy; Channel screening module, specifically used for: If there is currently at least one direct memory access channel whose channel status is idle or busy, it is determined that the trigger condition of the channel transmission mode is currently met; If there are multiple direct memory access channels whose channel status is idle, the direct memory access channel with the least number of target records is used as the target direct memory access channel; wherein the target record records that the channel has an error state or a timeout state in the historical transmission; If there is only one direct memory access channel whose channel status is idle, the direct memory access channel is directly determined as the target direct memory access channel; If there is no direct memory access channel whose channel status is idle, the number of tasks of all direct memory access channels whose channel status is busy is obtained; The direct memory access channel with the smallest number of tasks is used as the target direct memory access channel; The channel state of the target direct memory access channel is updated from the idle state to the busy state, or the number of tasks of the target direct memory access channel is increased by one.

8. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the data transmission method according to any one of claims 1 to 6 when executing the computer program.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the data transmission method according to any one of claims 1 to 6 are implemented.

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