Signal identification circuit for I2C interface circuit and I2C interface circuit

Abstract

The invention discloses a signal identification circuit for an I2C (Inter-Integrated Circuit) interface circuit and the I2C interface circuit. The signal identification circuit comprises a logic judgment module used for comparing a serial clock signal and a serial data signal with a first reference signal to generate a corresponding logic output signal; and the state control module is used for comparing the serial clock signal, the serial data signal and the logic output signal with a second reference signal so as to provide an enabling control signal for the logic judgment module and control the logic judgment module to be in a working state or an idle state. According to the signal identification circuit, on the premise of supporting multiple voltage signals, the static power consumption can be reduced, the occupied area is reduced, and the signal response speed is increased.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and more particularly to a signal recognition circuit for an I2C interface circuit and an I2C interface circuit. Background Art

[0002] I2C (Inter-Integrated Circuit, also known as I 2 The IIC (Inter-IC) bus system is a bidirectional, two-wire bus used for efficient communication and control between master and slave integrated circuit (IC) devices (or nodes) coupled via the bus. The master is the device that initiates data transfers on the bus and generates the clock signals to enable the transfers.

[0003] The two-wire I2C bus has a serial data (SDA) line and a serial clock (SCL) line. Both the SDA and SCL lines are bidirectional and are connected to a power supply voltage, such as VDD, through a current source or pull-up resistor. In the design of I2C bus interface circuits, signal recognition circuits are required to identify the voltages on the SDA and SCL lines. A low voltage on these lines is typically considered a logic 0, while a high voltage on these lines is considered a logic 1.

[0004] In existing technologies, the I2C bus circuit's power supply voltage VDD allows operating voltages in the following ranges: 0-5V, 0-3.3V, 0-1.8V, and 0-1.2V. Therefore, the signal recognition circuit must support logic level determination in multiple voltage domains. Its design involves several key performance considerations, such as recognition accuracy, recognition speed, quiescent current consumption, and chip area. Currently, mainstream input voltage recognition solutions include low-voltage domain inverters and comparators.

[0005] The low-voltage domain inverter solution builds an independent low-voltage domain within the chip (e.g., by adding a source follower and voltage regulator) and uses an inverter to directly perform logic recognition of the voltage on the SDA / SCL lines. This solution avoids the inverter's shoot-through leakage problem when the I2C bus circuit's power supply operating voltage range is low (e.g., 0-1.2V). The inverter also features fast switching speed, no static current consumption, and a simple structure. While its recognition voltage accuracy can vary significantly due to supply voltage, temperature, and process factors, it still meets the requirements of the I2C interface. However, this solution requires additional voltage domain circuitry, significantly increasing the chip area.

[0006] The comparator solution uses the chip's internal supply voltage to build a comparator, comparing the voltage on the SDA / SCL lines directly with a reference signal. This solution is simple and requires no additional voltage domains. Recognition speed can be optimized by adjusting the comparator bias current. However, the increased bias current required to achieve high-speed recognition results in continuous current consumption even in idle mode, increasing circuit power consumption.

[0007] Therefore, there is an urgent need for a signal recognition circuit for I2C interface circuits that can reduce static power consumption, reduce area occupancy, and improve signal response speed while supporting multi-voltage signals to meet the development needs of high-performance, low-power integrated circuits. Summary of the Invention

[0008] In view of the above problems, the object of the present invention is to provide a signal recognition circuit and an I2C interface circuit for an I2C interface circuit, which can reduce static power consumption, reduce area occupation, and improve signal response speed while supporting multi-voltage signals.

[0009] To achieve the above objectives, the technical solution of the present invention provides a signal recognition circuit for an I2C interface circuit, comprising:

[0010] a logic judgment module, configured to compare the serial clock signal and the serial data signal with a first reference signal to generate a corresponding logic output signal;

[0011] The state control module is used to compare the serial clock signal, the serial data signal and the logic output signal with a second reference signal to provide an enable control signal to the logic judgment module to control the logic judgment module to be in a working state or an idle state.

[0012] Preferably, the state control module is used to control the logic judgment module to be in an idle state when the serial clock signal, the serial data signal and the logic output signal are all greater than the second reference signal, and to control the logic judgment module to be in an active state when any one of the serial clock signal, the serial data signal and the logic output signal is less than the second reference signal.

[0013] Preferably, the voltage value of the second reference signal is greater than the voltage value of the first reference signal.

[0014] Preferably, the logic judgment module includes:

[0015] a first comparator, configured to compare the serial clock signal with the first reference signal to generate a first logic output signal; and

[0016] The second comparator is configured to compare the serial data signal with the first reference signal to generate a second logic output signal.

[0017] Preferably, the first comparator comprises:

[0018] a first input pair consisting of a first transistor and a second transistor, wherein a control terminal of the first transistor is connected to the serial clock signal, and a control terminal of the second transistor is connected to the first reference signal;

[0019] a first load unit formed by a third transistor and a fourth transistor, wherein first terminals of the third transistor and the fourth transistor are connected to an on-chip power supply voltage, control terminals of the third transistor and the fourth transistor and a second terminal of the third transistor are connected to the first terminal of the first transistor, and the second terminal of the fourth transistor is connected to the first terminal of the second transistor;

[0020] a fifth transistor, wherein a first terminal of the fifth transistor is connected to the second terminals of the first transistor and the second transistor, and a control terminal of the fifth transistor is connected to the enable control signal;

[0021] a first current source, wherein a first terminal of the first current source is connected to the second terminal of the fifth transistor, and a second terminal of the first current source is connected to ground;

[0022] a sixth transistor, the sixth transistor being arranged in parallel with the third transistor, and a control terminal of the sixth transistor being connected to the enable control signal;

[0023] a seventh transistor, the seventh transistor being arranged in parallel with the fourth transistor, and a control terminal of the seventh transistor being connected to the enable control signal; and

[0024] A first Schmitt trigger, wherein the input terminal of the first Schmitt trigger is connected to the second terminal of the fourth transistor, and the output terminal of the first Schmitt trigger is used to output the first logic output signal.

[0025] Preferably, the second comparator comprises:

[0026] a second input pair transistor consisting of an eighth transistor and a ninth transistor, wherein a control terminal of the eighth transistor is connected to the serial data signal, and a control terminal of the ninth transistor is connected to the first reference signal;

[0027] a second load unit consisting of a tenth transistor and an eleventh transistor, wherein first terminals of the tenth transistor and the eleventh transistor are connected to an on-chip power supply voltage, control terminals of the tenth transistor and the eleventh transistor and a second terminal of the tenth transistor are connected to the first terminal of the eighth transistor, and the second terminal of the eleventh transistor is connected to the first terminal of the ninth transistor;

[0028] a twelfth transistor, a first terminal of the twelfth transistor being connected to the second terminals of the eighth transistor and the ninth transistor, and a control terminal of the twelfth transistor being connected to the enable control signal;

[0029] a second current source, wherein a first terminal of the second current source is connected to the second terminal of the twelfth transistor, and a second terminal of the second current source is connected to ground;

[0030] a thirteenth transistor, the thirteenth transistor being arranged in parallel with the tenth transistor, and a control terminal of the thirteenth transistor being connected to the enable control signal;

[0031] a fourteenth transistor, the fourteenth transistor being arranged in parallel with the eleventh transistor, and a control terminal of the fourteenth transistor being connected to the enable control signal; and

[0032] A second Schmitt trigger, wherein the input terminal of the second Schmitt trigger is connected to the second terminal of the eleventh transistor, and the output terminal of the second Schmitt trigger is used to output the second logic output signal.

[0033] Preferably, the state control module includes:

[0034] a third current source, wherein a first end of the third current source is connected to an on-chip power supply voltage;

[0035] a third input pair transistor consisting of fifteen to nineteen transistors, wherein the first terminals of the fifteen to nineteen transistors are connected to the second terminal of the third current source, the control terminal of the fifteenth transistor is connected to the second reference signal, the control terminal of the sixteenth transistor is connected to the serial clock signal, the control terminal of the seventeenth transistor is connected to the serial data signal, the control terminal of the eighteenth transistor is connected to the first logic output signal, and the control terminal of the nineteenth transistor is connected to the second logic output signal;

[0036] a third load unit consisting of a 20th transistor and a 21st transistor, wherein a first end of the 20th transistor and the control ends of the 20th transistor and the 21st transistor are connected to the second end of the 15th transistor, a first end of the 21st transistor is connected to the second ends of the 16th to 19th transistors, and the second ends of the 20th transistor and the 21st transistor are connected to ground;

[0037] a fourth current source, a first end of the fourth current source being connected to the on-chip power supply voltage;

[0038] a twenty-second transistor, wherein a first terminal of the twenty-second transistor is connected to the second terminal of the fourth current source, a control terminal of the twenty-second transistor is connected to the second terminals of the sixteenth to nineteenth transistors, and a second terminal of the twenty-second transistor is connected to ground; and

[0039] An inverter, wherein an input end of the inverter is connected to the second end of the fourth current source, and an output end of the inverter is used to provide the enable control signal.

[0040] To achieve the above-mentioned purpose, the technical solution of the present invention further provides an I2C interface circuit, including the above-mentioned signal recognition circuit.

[0041] In summary, an embodiment of the present invention provides a signal recognition circuit for an I2C interface, the signal recognition circuit including a logic judgment module and a state control module, the logic judgment module being used to compare a serial clock signal and a serial data signal with a first reference signal, and generating a corresponding logic output signal based on the comparison result, the state control module being used to compare the serial clock signal, the serial data signal, and the output signal of the logic judgment module with a second reference signal, and generating an enable control signal based on the comparison result to control the switching of the logic judgment module between a working state and an idle state. When the logic judgment module is in the working state, the logic judgment speed of the circuit can be increased by a larger bias current, and when the logic judgment module is in the idle state, the static current consumption of the circuit can be reduced. Therefore, the signal recognition circuit of this embodiment can reduce static power consumption, reduce area occupancy, and improve signal response speed while supporting multiple voltage signals, so as to meet the development needs of high-performance, low-power integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0043] Figure 1 A schematic structural diagram of an I2C bus system is shown.

[0044] Figure 2 A schematic circuit diagram of a signal recognition circuit for an I2C interface circuit according to the prior art is shown.

[0045] Figure 3 FIG. 4 is a schematic circuit diagram of another signal recognition circuit for an I2C interface circuit according to the prior art.

[0046] Figure 4 A schematic structural diagram of a signal recognition circuit for an I2C interface circuit according to an embodiment of the present invention is shown.

[0047] Figure 5 Show Figure 4 Schematic circuit diagram of the logic judgment module in .

[0048] Figure 6 Show Figure 4 Schematic circuit diagram of the state control module in.

[0049] Figure 7 FIG. 5 shows a working waveform diagram of the signal recognition circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0050] Reference will now be made in detail to the exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings.Where possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts.

[0051] In the specification, it should be noted that similar reference numerals that have been used to represent similar components in other drawings are used for these elements as much as possible. In the following description, when functions and configurations known to those skilled in the art are not related to the basic configuration of the present disclosure, their detailed description will be omitted. The terms described in the specification should be understood as follows.

[0052] The advantages and features of the present disclosure and their implementation methods will be described through the following embodiments described with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to make the present disclosure comprehensive and complete, so as to fully convey the scope of the present disclosure to those skilled in the art. Furthermore, the present disclosure is limited only by the scope of the claims.

[0053] The shapes, sizes, ratios, angles, and quantities disclosed in the drawings used to describe the embodiments of the present disclosure are merely examples, and the present disclosure is therefore not limited to the details illustrated. Like reference numerals denote like elements throughout. In the following description, when it is determined that a detailed description of related known functions or structures would inevitably obscure the key points of the present disclosure, the detailed description will be omitted.

[0054] In case the terms “including,” “having,” and “comprising” described in this specification are used, another part may be added unless “only to” is used. Terms in the singular form may include plural forms unless otherwise specified.

[0055] It should be understood that although the terms "first," "second," etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another. For example, a first component can be referred to as a second component, and similarly, a second component can be referred to as a first component without departing from the scope of this disclosure.

[0056] The term "at least one" should be understood to include any and all combinations of one or more of the corresponding listed items. For example, "at least one of a first item, a second item, and a third item" means all combinations of two or more of the first item, the second item, and the third item, as well as the first item, the second item, or the third item.

[0057] As will be fully understood by those skilled in the art, the features of the various embodiments of the present disclosure may be combined or combined in part or in whole, and may interoperate and technically drive each other in various ways. The embodiments of the present disclosure may be performed independently of each other, or may be performed together in a mutually dependent relationship.

[0058] In all embodiments of the present invention, since the source and drain of a metal oxide semiconductor (MOS) transistor are symmetrical, and the conduction current between the source and drain of an N-type transistor and a P-type transistor flows in opposite directions, in the embodiments of the present invention, the controlled middle terminal of the MOS transistor is referred to as the control terminal, and the remaining two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. For ease of uniform expression, in this context, the source, drain, and gate of a PMOS transistor are referred to as the first terminal, the second terminal, and the control terminal, respectively, and the drain, source, and gate of an NMOS transistor are referred to as the first terminal, the second terminal, and the control terminal, respectively.

[0059] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0060] Figure 1 FIG. 1 shows a schematic structural diagram of an I2C bus system 100, in which the signal recognition circuit for the I2C interface circuit according to an embodiment of the present invention can be implemented. Figure 1As shown, an I2C bus system 100 has a bidirectional bus 102, which includes a serial data line SDA and a serial clock line SCL for communication and control between a master integrated circuit (IC) device 101 and a slave integrated circuit (IC) device 103. Each of the master device 101 and the slave device 103 can be a system on a chip (SOC) on a standalone IC, or can be a separate module in a general-purpose IC. In the I2C bus system 100, multiple slave IC devices 103 can be coupled for communication and control with the master device 101 via the bus. There can be multiple master devices 101, and the I2C standard provides an arbitration protocol to resolve conflicts between signals from different masters.

[0061] In the I2C bus system 100, the SCL and SDA lines are connected to a supply voltage VDD through current sources or pull-up resistors 104 and 105. The SDA and SCL lines are high in idle mode, and nodes that attempt to transmit a logic 1 by floating the lines high can detect that another node is active at the same time by the fact that the line voltage is pulled low.

[0062] Furthermore, the I2C interface circuits of the master device 101 and the slave device 103 in this embodiment both include a signal recognition circuit, which is used to detect the voltages on the SDA line and the SCL line and generate corresponding logic signals according to the voltage conditions on the lines.

[0063] Figure 2 FIG. 1 shows a schematic circuit diagram of a signal recognition circuit for an I2C interface circuit according to the prior art. Figure 2 As shown, a signal recognition circuit 201 in the prior art includes transistors M1 - M3 , a current source Iref, a source follower 211 composed of capacitors C1 and C2 and a resistor R1 , and inverters 212 and 213 .

[0064] In source follower 211, the gates and drains of transistors M1 and M2 are short-circuited together. A current source Iref, transistors M1, M2, and resistor R1 are connected in series between the on-chip power supply voltage and ground AGND, causing a reference current to flow sequentially through transistors M1, M2, and R1. The gate potential of transistor M3 is determined by the gate-source voltages of transistors M1 and M2 and the voltage drop across resistor R1. The drain of transistor M3 is connected to the on-chip power supply voltage. The source of transistor M3 is used to generate the power supply voltage VDD for the I2C bus circuit. Capacitors C1 and C2 serve as stabilizing capacitors for the gate and source of transistor M2, respectively. Power supply voltage VDD serves as the supply voltage for inverters 212 and 213, which detect the voltage values of serial clock signal SCL and serial data signal SDA, respectively, within the voltage domain of power supply voltage VDD and generate corresponding logic signals SCL_OUT and SDA_OUT.

[0065] exist Figure 2 In the embodiment, the setting voltage of the power supply voltage VDD is determined by the minimum voltage that the I2C communication protocol needs to support. Here, taking VDD=1.2V as an example, since the minimum voltage of the idle potential of the serial clock signal SCL and the serial data signal SDA is VDD*0.9=1.08V, the voltage difference between the power supply voltage VDD and the serial clock signal SCL and the serial data signal SDA is not enough to cause the inverting circuits 212 and 213 to form a through current leakage.

[0066] While the existing signal recognition circuit 201 can avoid the inverter shoot-through leakage problem when the I2C bus circuit's power supply operating voltage range is low (e.g., 0-1.2V), and features fast inverter switching, no static current consumption, and a simple structure, its recognition voltage accuracy can vary significantly due to supply voltage, temperature, and process factors, but it can still meet the requirements of the I2C interface. However, this solution requires additional voltage domain circuitry, significantly increasing chip area.

[0067] Figure 3 FIG. 2 shows a schematic circuit diagram of another signal recognition circuit for an I2C interface circuit according to the prior art. Figure 3 As shown, another existing signal recognition circuit 202 constructs comparators 221 and 222 based on the on-chip power supply voltage inside the chip, and then directly compares the serial clock signal SCL and the serial data signal SDA with the reference signal VREF, and generates corresponding logic signals SCL_OUT and SDA_OUT according to the comparison results.

[0068] Although the existing signal recognition circuit 202 has a simple structure and does not require an additional voltage domain, the recognition speed can be optimized by adjusting the comparator bias current. However, in order to achieve high-speed recognition, the bias current needs to be increased, resulting in continuous current consumption in the idle state, thereby increasing the power consumption of the circuit.

[0069] Figure 4 FIG. 1 shows a schematic structural diagram of a signal recognition circuit for an I2C interface circuit according to an embodiment of the present invention. Figure 4 As shown, the signal identification circuit 300 of this embodiment includes a logic judgment module 310 and a state control module 320. The logic judgment module 310 is configured to compare the serial clock signal SCL and the serial data signal SDA with a first reference signal VREF1 and generate corresponding logic signals SCL_OUT and SDA_OUT based on the comparison results. The state control module 320 is configured to compare the serial clock signal SCL, the serial data signal SDA, and the logic signals SCL_OUT and SDA_OUT with a second reference signal VREF2, and provide an enable control signal EN to the logic judgment module 310 based on the comparison results to control the state of the logic judgment module 310.

[0070] Furthermore, in this embodiment, the voltage value of the second reference signal VREF2 is greater than the voltage value of the first reference signal VREF1.

[0071] Furthermore, the logic judgment module 310 of this embodiment has an operating state and an idle state. The state control module 320 is configured to provide an invalid (e.g., low-level) enable control signal EN to the logic judgment module 310 when the serial clock signal SCL, the serial data signal SDA, and the logic signals SCL_OUT and SDA_OUT are all greater than the second reference signal VREF2, so as to control the logic judgment module 310 to operate in the idle state and reduce the quiescent current of the circuit. The state control module 320 is also configured to provide a valid (e.g., high-level) enable control signal EN to the logic judgment module 310 when any one of the serial clock signal SCL, the serial data signal SDA, and the logic signals SCL_OUT and SDA_OUT is less than the second reference signal VREF2, so as to control the logic judgment module 310 to operate in the operating state. In this case, current consumption is increased to achieve rapid logic judgment.

[0072] Figure 5 Show Figure 4 The schematic circuit diagram of the logic judgment module in . Figure 5As shown, the logic judgment module 310 of this embodiment includes comparators 311 and 312. The comparator 311 is used to compare the serial clock signal SCL with the first reference signal VREF1 and generate a logic output signal SCL_OUT based on the comparison result. The comparator 312 is used to compare the serial data signal SDA with the first reference signal VREF1 and generate a logic output signal SDA_OUT based on the comparison result.

[0073] Furthermore, the comparator 311 includes an input pair of transistors and a load unit adaptively connected to the input pair of transistors, wherein the input pair of transistors is used to receive the serial clock signal SCL and the first reference signal VREF1 to be compared. Figure 5 FIG3 shows an embodiment of a comparator 311. In the figure, an input pair comprises NMOS transistors M1 and M2. Specifically, NMOS transistors M1 and M2 are the two input transistors in the input pair. The second terminal (e.g., source) of NMOS transistor M1 is connected to the second terminal (e.g., source) of NMOS transistor M2. The control terminal (e.g., gate) of NMOS transistor M1 receives the serial clock signal SCL, and the control terminal (e.g., gate) of NMOS transistor M2 receives the first reference signal VREF1. PMOS transistors M3 and M4 form active loads for the input pair M1 and M2. First terminals (e.g., sources) of PMOS transistors M3 and M4 are connected to an on-chip power supply voltage VCC. The control terminals (e.g., gates) of PMOS transistors M3 and M4 and the second terminal (e.g., drain) of PMOS transistor M3 are connected to the first terminal (e.g., drain) of NMOS transistor M1. The second terminal (e.g., drain) of PMOS transistor M4 is connected to the first terminal (e.g., drain) of NMOS transistor M2. An input terminal of the Schmitt trigger SMT1 is connected to an intermediate node between the NMOS transistor M2 and the PMOS transistor M4 , and an output terminal of the Schmitt trigger SMT1 is used to provide the logic output signal SCL_OUT.

[0074] Current source Iref1 is connected to the sources of the input transistors M1 and M2 via NMOS transistor M9, providing tail current for the input transistors M1 and M2. Specifically, the drain of NMOS transistor M9 is connected to the sources of the input transistors M1 and M2, the source of NMOS transistor M9 is connected to current source Iref1, and a second end of current source Iref1 is connected to ground AGND. Furthermore, the gate of NMOS transistor M9 is connected to the enable control signal EN, enabling or disabling the current path from current source Iref1 to the input transistors M1 and M2 in response to the enable control signal EN. For example, the NMOS transistor M9 is configured to be turned off when the enable control signal EN is at a low level, thereby disconnecting the current path from the current source Iref1 to the input pair of transistors M1 and M2, thereby reducing the static current consumption of the circuit in an idle state; the NMOS transistor M9 is configured to be turned on when the enable control signal EN is at a high level, thereby enabling the current source Iref1 to provide a larger bias current to the input pair of transistors M1 and M2, thereby accelerating the flipping speed of the comparator 311, and further improving the circuit's logic recognition speed for the serial clock signal SCL.

[0075] Furthermore, the comparator 311 further includes PMOS transistors M11 and M12 , wherein the PMOS transistors M11 and M12 are connected in parallel between two ends of the transistors M3 and M4 , respectively, and gates of the PMOS transistors M11 and M12 are used to receive the enable control signal EN.

[0076] Furthermore, the comparator 312 includes an input pair of transistors and a load unit adaptively connected to the input pair of transistors, wherein the input pair of transistors is used to receive the serial data signal SDA to be compared and the first reference signal VREF1. Figure 5FIG3 shows an embodiment of a comparator 312. In the figure, an input pair comprises NMOS transistors M5 and M6. Specifically, NMOS transistors M5 and M6 are two input transistors in the input pair. The second terminal (e.g., source) of NMOS transistor M5 is connected to the second terminal (e.g., source) of NMOS transistor M6. The control terminal (e.g., gate) of NMOS transistor M5 receives the serial data signal SDA, and the control terminal (e.g., gate) of NMOS transistor M6 receives the first reference signal VREF1. PMOS transistors M7 and M8 form active loads for the input pair M5 and M6. First terminals (e.g., sources) of PMOS transistors M7 and M8 are connected to an on-chip power supply voltage VCC. The control terminals (e.g., gates) of PMOS transistors M7 and M8 and the second terminal (e.g., drain) of PMOS transistor M7 are connected to the first terminal (e.g., drain) of NMOS transistor M5. The second terminal (e.g., drain) of PMOS transistor M8 is connected to the first terminal (e.g., drain) of NMOS transistor M6. An input terminal of the Schmitt trigger SMT2 is connected to an intermediate node between the NMOS transistor M6 and the PMOS transistor M8 , and an output terminal of the Schmitt trigger SMT2 is used to provide the logic output signal SDA_OUT.

[0077] Current source Iref2 is connected to the sources of the input transistors M5 and M6 via NMOS transistor M10 to provide tail current for the input transistors M5 and M6. Specifically, the drain of NMOS transistor M10 is connected to the sources of the input transistors M5 and M6, the source of NMOS transistor M10 is connected to current source Iref2, and a second end of current source Iref2 is connected to ground AGND. Furthermore, the gate of NMOS transistor M10 is connected to the enable control signal EN to enable or disable the current path from current source Iref2 to the input transistors M5 and M6 based on the enable control signal EN. For example, the NMOS transistor M10 is configured to be turned off when the enable control signal EN is at a low level, thereby disconnecting the current path from the current source Iref2 to the input pair of transistors M5 and M6, thereby reducing the static current consumption of the circuit in an idle state; the NMOS transistor M10 is configured to be turned on when the enable control signal EN is at a high level, thereby enabling the current source Iref2 to provide a larger bias current to the input pair of transistors M5 and M6, thereby accelerating the flipping speed of the comparator 312, and further improving the circuit's logic recognition speed for the serial data signal SDA.

[0078] Furthermore, the comparator 312 further includes PMOS transistors M13 and M14 , wherein the PMOS transistors M13 and M14 are connected in parallel between two ends of the transistors M7 and M8 , respectively, and gates of the PMOS transistors M13 and M14 are configured to receive the enable control signal EN.

[0079] Figure 6 Show Figure 4 The schematic circuit diagram of the state control module in FIG. Figure 6 As shown, the state control module 320 of this embodiment includes an input pair consisting of PMOS transistors M15-M19, a load unit consisting of NMOS transistors M20 and M21, current sources Iref3 and Iref4, an NMOS transistor M22, and an inverter INV. One end of the current source Iref3 is connected to the on-chip power supply voltage VCC, and a second end is connected to the sources of the PMOS transistors M15-M19. The gate of the PMOS transistor M15 is used to receive the second reference signal VREF2, the gate of the PMOS transistor M16 is used to receive the serial clock signal SCL, the gate of the PMOS transistor M17 is used to receive the serial data signal SDA, the gate of the PMOS transistor M18 is used to receive the logic output signal SCL_OUT, and the gate of the PMOS transistor M19 is used to receive the logic output signal SDA_OUT. The gate and drain of NMOS transistor M20 and the gate of NMOS transistor M21 are connected to the drain of PMOS transistor M15. The drain of NMOS transistor M21 is connected to the drains of PMOS transistors M16-M19. The sources of NMOS transistors M20 and M21 are connected to ground AGND. A first terminal of current source Iref4 is connected to on-chip power supply voltage VCC, and a second terminal is connected to the drain of NMOS transistor M22. The gate of NMOS transistor M22 is connected to the drains of PMOS transistors M16-M19, and the source of NMOS transistor M22 is connected to ground AGND. The input of inverter INV is connected to the drain of NMOS transistor M22, and the output of inverter INV is used to output the enable control signal EN.

[0080] Figure 7The following waveform diagram illustrates the operation of the signal recognition circuit according to an embodiment of the present invention. During I2C communication, the SDA and SCL lines are typically pulled up to the off-chip power supply voltage VDD by a current source or resistor in the idle state. During data transmission, they are typically pulled down by an open-drain or open-collector circuit. Due to parasitic capacitance on the bus, the waveforms of the serial clock signal SCL and serial data signal SDA in this embodiment are actually slanted or curved. Even in Ultra Fast-mode, the typical pull-up time (30%*VDD to 70%*VDD) or pull-down time (70%*VDD to 30%*VDD) is approximately 25ns (UM10204 I2C-bus specification and user manual). Assume that the voltage value of the second reference signal VREF2 in this embodiment is the lowest voltage in the I2C idle state, i.e., 0.9*VDD, which is significantly higher than the voltage value of the first reference signal VREF1 (e.g., 0.3*VDD to 0.7*VDD). Therefore, even if the bias current in the state control circuit 320 is relatively small, it can still switch the logic judgment module 310 from the idle state to the working state before the serial clock signal SCL and the serial data signal SDA are pulled down to the first reference signal VREF1. In the working state, since a larger bias current is used in the logic judgment module 310, its flipping speed is relatively fast, thereby ensuring the speed of the circuit logic judgment.

[0081] When the SCL and SDA lines on the I2C bus are both in an idle state, they are pulled high. At this point, the outputs SCL_OUT and SDA_OUT of the logic judgment module 310 are also set high. At this point, the output of the state control module 320 flips, and the enable control signal EN changes from a high level to a low level. The NMOS transistors M9 and M10 in the logic judgment module 310 are turned off, thereby disconnecting the current path from the current sources Iref1 and Iref2 to the input transistors. Current sources Ire1 and Iref2 no longer consume current. At the same time, the PMOS transistors M11-M14 are turned on, pulling the logic output signals SCL_OUT and SDA_OUT up to the power supply voltage VCC. Simultaneously, the NMOS transistor M22 in the state control module 320 is also turned off, so the current source Iref4 no longer consumes current. Therefore, in the idle state, only the current source Iref3 branch of the signal recognition circuit 300 of this embodiment consumes current. Since the second reference signal VREF2 is greater than the first reference signal VREF1, the static current consumed by the signal recognition circuit 300 of this embodiment in the idle state is small, which is beneficial to reducing circuit power consumption.

[0082] Furthermore, an embodiment of the present invention further provides an electronic chip, which includes the I2C interface circuit and the signal recognition circuit according to an embodiment of the present invention. For example, the electronic chip is a power management chip.

[0083] Furthermore, an embodiment of the present invention further provides an electronic device, which includes an electronic chip according to an embodiment of the present invention. For example, the electronic device is a smart terminal device, such as a tablet computer, a smart phone, etc.

[0084] In summary, an embodiment of the present invention provides a signal recognition circuit for an I2C interface, the signal recognition circuit including a logic judgment module and a state control module, the logic judgment module being used to compare a serial clock signal and a serial data signal with a first reference signal, and generating a corresponding logic output signal based on the comparison result, the state control module being used to compare the serial clock signal, the serial data signal, and the output signal of the logic judgment module with a second reference signal, and generating an enable control signal based on the comparison result to control the switching of the logic judgment module between a working state and an idle state. When the logic judgment module is in the working state, the logic judgment speed of the circuit can be increased by a larger bias current, and when the logic judgment module is in the idle state, the static current consumption of the circuit can be reduced. Therefore, the signal recognition circuit of this embodiment can reduce static power consumption, reduce area occupancy, and improve signal response speed while supporting multiple voltage signals, so as to meet the development needs of high-performance, low-power integrated circuits.

[0085] In the above description, the well-known structural elements and steps are not described in detail. However, it should be understood by those skilled in the art that the corresponding structural elements and steps can be implemented by various technical means. In addition, in order to form the same structural elements, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although each embodiment is described separately above, this does not mean that the measures in each embodiment cannot be advantageously used in combination.

[0086] The embodiments of the present invention are described above, but these embodiments do not describe all details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and modify and use it based on the present invention. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention.

Claims

1. A signal recognition circuit for an I2C interface circuit, comprising: a logic judgment module, configured to compare the serial clock signal and the serial data signal with a first reference signal to generate a corresponding logic output signal; The state control module is used to compare the serial clock signal, the serial data signal and the logic output signal with a second reference signal to provide an enable control signal to the logic judgment module to control the logic judgment module to be in a working state or an idle state.

2. The signal recognition circuit according to claim 1, wherein: The state control module is used to control the logic judgment module to be in an idle state when the serial clock signal, the serial data signal and the logic output signal are all greater than the second reference signal, and to control the logic judgment module to be in an active state when any one of the serial clock signal, the serial data signal and the logic output signal is less than the second reference signal.

3. The signal recognition circuit according to claim 1, wherein: A voltage value of the second reference signal is greater than a voltage value of the first reference signal.

4. The signal recognition circuit according to claim 1, wherein: The logic judgment module includes: a first comparator, configured to compare the serial clock signal with the first reference signal to generate a first logic output signal; and The second comparator is configured to compare the serial data signal with the first reference signal to generate a second logic output signal.

5. The signal recognition circuit according to claim 4, wherein: The first comparator comprises: a first input pair consisting of a first transistor and a second transistor, wherein a control terminal of the first transistor is connected to the serial clock signal, and a control terminal of the second transistor is connected to the first reference signal; a first load unit formed by a third transistor and a fourth transistor, wherein first terminals of the third transistor and the fourth transistor are connected to an on-chip power supply voltage, control terminals of the third transistor and the fourth transistor and a second terminal of the third transistor are connected to the first terminal of the first transistor, and the second terminal of the fourth transistor is connected to the first terminal of the second transistor; a fifth transistor, wherein a first terminal of the fifth transistor is connected to the second terminals of the first transistor and the second transistor, and a control terminal of the fifth transistor is connected to the enable control signal; a first current source, wherein a first terminal of the first current source is connected to the second terminal of the fifth transistor, and a second terminal of the first current source is connected to ground; a sixth transistor, the sixth transistor being arranged in parallel with the third transistor, and a control terminal of the sixth transistor being connected to the enable control signal; a seventh transistor, the seventh transistor being arranged in parallel with the fourth transistor, and a control terminal of the seventh transistor being connected to the enable control signal; and A first Schmitt trigger, wherein the input terminal of the first Schmitt trigger is connected to the second terminal of the fourth transistor, and the output terminal of the first Schmitt trigger is used to output the first logic output signal. The signal recognition circuit according to claim 4 , wherein: The second comparator includes: a second input pair transistor consisting of an eighth transistor and a ninth transistor, wherein a control terminal of the eighth transistor is connected to the serial data signal, and a control terminal of the ninth transistor is connected to the first reference signal; a second load unit consisting of a tenth transistor and an eleventh transistor, wherein first terminals of the tenth transistor and the eleventh transistor are connected to an on-chip power supply voltage, control terminals of the tenth transistor and the eleventh transistor and a second terminal of the tenth transistor are connected to the first terminal of the eighth transistor, and the second terminal of the eleventh transistor is connected to the first terminal of the ninth transistor; a twelfth transistor, a first terminal of the twelfth transistor being connected to the second terminals of the eighth transistor and the ninth transistor, and a control terminal of the twelfth transistor being connected to the enable control signal; a second current source, wherein a first terminal of the second current source is connected to the second terminal of the twelfth transistor, and a second terminal of the second current source is connected to ground; a thirteenth transistor, the thirteenth transistor being arranged in parallel with the tenth transistor, and a control terminal of the thirteenth transistor being connected to the enable control signal; a fourteenth transistor, the fourteenth transistor being arranged in parallel with the eleventh transistor, and a control terminal of the fourteenth transistor being connected to the enable control signal; and A second Schmitt trigger, wherein the input terminal of the second Schmitt trigger is connected to the second terminal of the eleventh transistor, and the output terminal of the second Schmitt trigger is used to output the second logic output signal.

7. The signal recognition circuit according to claim 4, wherein: The state control module includes: a third current source, wherein a first end of the third current source is connected to an on-chip power supply voltage; a third input pair transistor consisting of fifteen to nineteen transistors, wherein the first terminals of the fifteen to nineteen transistors are connected to the second terminal of the third current source, the control terminal of the fifteenth transistor is connected to the second reference signal, the control terminal of the sixteenth transistor is connected to the serial clock signal, the control terminal of the seventeenth transistor is connected to the serial data signal, the control terminal of the eighteenth transistor is connected to the first logic output signal, and the control terminal of the nineteenth transistor is connected to the second logic output signal; a third load unit consisting of a 20th transistor and a 21st transistor, wherein a first end of the 20th transistor and the control ends of the 20th transistor and the 21st transistor are connected to the second end of the 15th transistor, a first end of the 21st transistor is connected to the second ends of the 16th to 19th transistors, and the second ends of the 20th transistor and the 21st transistor are connected to ground; a fourth current source, a first end of the fourth current source being connected to the on-chip power supply voltage; a twenty-second transistor, wherein a first terminal of the twenty-second transistor is connected to the second terminal of the fourth current source, a control terminal of the twenty-second transistor is connected to the second terminals of the sixteenth to nineteenth transistors, and a second terminal of the twenty-second transistor is connected to ground; and An inverter, wherein an input end of the inverter is connected to the second end of the fourth current source, and an output end of the inverter is used to provide the enable control signal.

8. An I2C interface circuit, wherein: The invention comprises the signal recognition circuit according to any one of claims 1 to 7.

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