Real-time calibration system for quantum bit waveforms based on pre-calculated pipeline hybrid architecture

Abstract

The present invention discloses a real-time calibration system for quantum bit waveforms based on a pre-calculated pipeline hybrid architecture, which relates to the field of quantum measurement and control technology. The system comprises: a multi-phase envelope distributor for receiving and parsing external pre-defined envelope data and dynamically converting the external envelope data into parallel outputs; a differential module for performing a differential operation on the outputs of the multi-phase envelope distributor to obtain M-channel differential signals; a coefficient generator for latching coefficients transmitted by a host computer and generating filter coefficients required by a filter based on the latched coefficients; a filter for filtering the multi-channel differential signals based on the M-channel differential signals and the filter coefficients generated by the coefficient generator as inputs; and a digital adder for adding the output of the multi-phase envelope distributor to the output of the filter to generate a final calibration waveform. The quantum bit waveform calibration method and system are used to solve the problem of waveform distortion compensation in high-speed, high-fidelity quantum gate operations.

Description

Technical Field

[0001] The present invention relates to the field of quantum measurement and control technology, and in particular to a quantum bit waveform real-time calibration system based on a pre-calculation pipeline hybrid architecture. Background Art

[0002] In superconducting quantum computing systems, precise manipulation of qubits relies on high-speed, high-precision control signals. However, during signal transmission, channel characteristics and device nonlinearities can cause waveform distortion. As a result, the qubit perceives a distorted version of the signal, not the original one. Therefore, calibration is necessary to ensure that the qubit perceives the original signal as closely as possible.

[0003] Currently, in the field of quantum technology, this problem is solved by using the quantum bit itself to measure the distortion at low temperature and calibrate it through deconvolution. Let the ideal signal be , the output signal after the ideal signal is transmitted through the cable ,in represents the convolution operation, Represents the characteristics of the transmission line, The Fourier transform of , is the Fourier transform. The Fourier transform of ,remember The Fourier transform of , then the output signal Fourier transform of . Remember the signal , then the signal The inverse Fourier transform of After being transmitted through the line, it becomes an ideal transmission signal when it reaches the quantum bit. The characteristics of the line are obtained by conducting corresponding experiments on the quantum bit. is the inverse Fourier transform.

[0004] Currently, hardware implementations of this calibration process primarily rely on a host computer, such as a personal computer (PC) or server, to calculate and store the calibration waveform. An arbitrary waveform generator (AWG) then generates control signals to manipulate the qubits as needed. This hardware implementation (e.g., Chinese patents CN112149832A and CN118376970A) offers the advantage of high precision, but suffers from two issues:

[0005] 1) High storage resource consumption: CN112149832A describes direct storage of calibrated waveforms, which is suitable for small-scale applications with short qubit coherence times. However, as qubit lifetimes increase and system scale expands, the storage requirements of this calibration mode increase linearly, making it unsuitable for the real-time calibration requirements of large-scale, long-coherence-time quantum experiments.

[0006] 2) High communication latency, which cannot meet the requirements of low-latency applications;

[0007] CN113760039A addresses the problems of hardware implementation of data storage sent from the host computer and proposes a solution to calibrate the original control signal based on IIR filters. This solution performs real-time calibration on-chip, which can save storage resources and reduce latency. However, in applications of high-speed and high-precision quantum bit control, it will face the following problems: low precision, namely:

[0008] Traditional IIR filters implement filtering operations based on a recursive feedback structure. Their single-cycle operation process requires sequential execution of multiplication and addition operations and feedback, resulting in a long critical path delay, which inherently limits the data rate. With the increase in the clock frequency of quantum measurement and control systems and the increase in DAC sampling rates, the recursive calculation mode of existing IIR filters can no longer meet the data rate requirements. Specifically, the timing dependence of the recursive structure requires each data sample processing cycle to wait for the result of the previous operation, forming a strong coupling constraint between data throughput and clock frequency. Existing technologies use neighboring interpolation (using the same value for multiple sampling points), linear interpolation, or multi-point averaging to solve this problem, but these solutions actually compress the data, and only a part of the data points are valid values, while the rest are approximate. As the system clock frequency and DAC sampling rate continue to increase, this on-chip calibration method will seriously restrict the implementation of high-speed quantum gate operations (such as nanosecond pulse control), especially for pulses with faster rising edges and shorter durations, such as Figure 13 shown.

[0009] Therefore, existing technical solutions cannot meet the application requirements of on-chip high-speed and high-precision real-time calibration. Summary of the Invention

[0010] Based on the technical problems existing in the background technology, the present invention proposes a real-time quantum bit waveform calibration system based on a pre-calculated pipeline hybrid architecture, which is used to solve the waveform distortion compensation problem in high-speed, high-fidelity quantum gate operations and meet the requirements of superconducting quantum computing systems for waveform accuracy, speed and flexibility.

[0011] The present invention proposes a real-time quantum bit waveform calibration system based on a pre-calculated pipeline hybrid architecture, comprising:

[0012] A multi-phase envelope distributor is used to receive and parse external predefined envelope data and dynamically convert the external envelope data into parallel outputs;

[0013] A differential module, configured to perform a differential operation on the output of the polyphase envelope distributor to obtain M differential signals, where M is an integer;

[0014] The coefficient generator is used to latch the coefficients transmitted by the host computer and generate the coefficients required by the filter according to the latched coefficients;

[0015] a filter, which filters the multi-channel differential signals based on the M-channel differential signals and the filter coefficients generated by the coefficient generator as input, and outputs calibrated waveforms in a multi-channel parallel manner;

[0016] A digital adder is used to add the output of the multiphase envelope distributor and the output of the filter to generate a final calibration waveform. The calibration waveform is output by the digital-to-analog converter, acts on the quantum bit after passing through the quantum bit control line, and is used to control the quantum bit.

[0017] Furthermore, the filter adopts an IIR filter, and the filtering process of the multi-path differential signal is as follows:

[0018] Introducing a pre-calculation stage and a pipeline calculation stage into the IIR filter, and providing coefficients for the pre-calculation stage and the pipeline calculation stage through a coefficient generator;

[0019] The pre-calculation stage pre-calculates the M differential signals through M+1 multiplication operations and M addition operations;

[0020] The pipeline calculation stage uses a classic first-order IIR filter to perform calculations based on the results of the pre-calculation stage. The first stage in the pipeline calculation stage uses the delayed differential signal output by the branch corresponding to the differential module and the calculation result of the pre-calculation stage as input signals, and each of the remaining stages uses the delayed differential signal of the branch corresponding to the differential module and the calculation result of the previous stage as input signals.

[0021] Furthermore, in the pipeline calculation stage, the M-1 pipeline stages are split into at least M-1 clock cycles to complete, and each pipeline stage processes at most two multiplications and one addition.

[0022] Furthermore, the pre-calculation stage independently calculates the output signal of the corresponding branch at all times, and each stage in the pipeline completes the calculation within two clock cycles.

[0023] Furthermore, the coefficient generator dynamically calculates and latches the remaining coefficients based on the coefficient data sent by the host computer.

[0024] Furthermore, the complex multipliers used in the coefficient generator and the filter are all divide-and-conquer operation models, specifically:

[0025] Decomposing a complex multiplication into a combination of three real multiplications and five real additions saves one multiplier.

[0026] Furthermore, setting are all real numbers, is an imaginary unit, and is calculated using the divide-and-conquer operation model And output the real part and imaginary part. The specific structure is as follows:

[0027] The real number Input into real adder 1, and add the real number Input to real adder 2;

[0028] The output of adder 1 and the output of adder 2 are used as inputs of real multiplier 1;

[0029] The real number Input to real multiplier 2, the real number Input to real multiplier three;

[0030] The output of the real number multiplier 1 and the inverse of the output of the real number multiplier 2 are used as the input of the real number adder 3;

[0031] The output of the real number multiplier 2 and the inverse of the output of the real number multiplier 3 are used as inputs of the real number adder 4 to output an imaginary part;

[0032] The output of the real adder three and the inverse of the output of the multiplier three are used as inputs of the real adder five to output the real part.

[0033] Furthermore, the calibration waveform is outputted by a digital-to-analog converter and acts on the qubit after passing through the qubit control line, specifically:

[0034] Outputting the calibration waveform to the quantum bit control line through a digital-to-analog converter and a low-noise amplifier;

[0035] The correction waveform is applied to the qubit via the qubit control line.

[0036] Furthermore, the classical first-order IIR filter is as follows:

[0037] ;

[0038] in, represent discrete time indices, Respectively indicate time The output signal value, Indicates time The input signal value, is the weight coefficient of the input path, Represents the weight coefficient of the feedback path.

[0039] Furthermore, the and The calculation formula is as follows:

[0040]

[0041]

[0042] in, and is the line parameter, , is the sampling rate, and T is the sampling period.

[0043] The advantages of the quantum bit waveform real-time calibration system based on a pre-calculation pipeline hybrid architecture provided by the present invention are: proposing a scalable hardware implementation scheme for on-chip real-time calibration of an IIR filter based on the interweaving of pre-calculation and pipeline, and being able to support complex domain calibration schemes, pre-calculating intermediate results through pre-calculation to reduce data correlation, and outputting valid data points through pipeline calculation in multiple channels to improve the output data rate; the IIR filter architecture requires a large number of coefficients for filtering calculations, which will result in high latency when configured on a host computer, while the coefficients are generated on-chip in real time by a coefficient generator without the need for a large amount of storage resources, thereby ensuring low latency and high real-time performance; by constructing a divide-and-conquer operation model for complex multipliers, a complex multiplication is decomposed into an optimized combination of three real multiplications and five real additions, saving hardware overhead and facilitating compatibility with complex calibration schemes; the pipeline structure is easy to expand and will not lengthen the critical path; each sampling point updates its value once, and all sampling points are valid values; the filter coefficients can be dynamically configured to meet the requirements of the superconducting quantum computing system for waveform accuracy, rate, and flexibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 It is a structural schematic diagram of the present invention;

[0045] Figure 2 Schematic diagram of the entire quantum bit control system;

[0046] Figure 3 Schematic diagram of the recursive structure of the classic first-order IIR filter;

[0047] Figure 4 It is a schematic diagram of the fully parallel structure;

[0048] Figure 5 Schematic diagram of incremental block filtering structure;

[0049] Figure 6 Generate coefficient diagrams for coefficient generator in real time;

[0050] Figure 7 Schematic diagram of IIR filter;

[0051] Figure 8 Schematic diagram of the structure of the complex multiplier;

[0052] Figure 9 Schematic diagram showing the comparison of the amplitude of the calibration waveform obtained by using this embodiment and the ideal calibration waveform, wherein the calibration waveform of this solution in the figure is the calibration waveform obtained by using this embodiment;

[0053] Figure 10 Schematic diagram showing the comparison of normalized error between the calibration waveform obtained using this embodiment and the ideal calibration waveform;

[0054] Figure 11 Schematic diagram showing the comparison of the amplitude of the calibration waveform obtained by using the existing interpolation scheme and the ideal calibration waveform, wherein the calibration waveform of the interpolation scheme in the figure is the calibration waveform obtained by the existing interpolation scheme;

[0055] Figure 12 A schematic diagram showing the comparison of normalized errors between the calibration waveform obtained using the existing interpolation scheme and the ideal calibration waveform;

[0056] Figure 13 Schematic diagram comparing the amplitudes of calibration waveforms obtained using an existing linear interpolation scheme, the present embodiment, and an ideal calibration waveform. In the figure, the present scheme is the calibration waveform obtained using the present embodiment, and the linear interpolation scheme is the calibration waveform obtained using an existing linear interpolation scheme.

[0057] Figure 14 This is a schematic diagram comparing the normalized errors of the corrected waveforms obtained using this embodiment and the existing linear interpolation scheme with those of the ideal waveform within the corresponding time. The figure compares four groups of circuits, and each group of circuits compares seven commonly used waveforms. Among them, (a) is a curve diagram of the average value of the normalized error within the time period of 20ns to 40ns after the falling edge, (b) is a curve diagram of the standard deviation within the time period of 20ns to 40ns after the falling edge, (c) is a curve diagram of the average value within the time period of 1μs to 1.11μs after the falling edge, and (d) is a curve diagram of the standard deviation of the normalized error within the time period of 1μs to 1.11μs after the falling edge. The present scheme in (a) to (d) is the present embodiment, and the linear interpolation scheme is the existing interpolation scheme. DETAILED DESCRIPTION

[0058] The technical solutions of the present invention are described in detail below through specific embodiments. Numerous specific details are set forth in the following description to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways than those described herein, and those skilled in the art may make similar modifications without departing from the scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0059] like Figures 1 to 14 As shown, the quantum bit waveform real-time calibration system based on the pre-calculation pipeline hybrid architecture proposed in the present invention includes:

[0060] A multi-phase envelope distributor is used to receive and parse external predefined envelope data and dynamically convert the external envelope data into parallel outputs;

[0061] A differential module, used for performing a differential operation on the output of the multi-phase envelope distributor;

[0062] The coefficient generator is used to latch the coefficients transmitted by the host computer and generate the coefficients required by the filter in this scheme according to the latched coefficients;

[0063] A filter, which filters the multi-channel differential signals based on the multi-channel differential signals output by the differential module and the coefficients generated by the coefficient generator as input;

[0064] A digital adder is used to add the output of the multiphase envelope distributor and the output of the filter to generate a final calibration waveform. The calibration waveform is output by a digital-to-analog converter (DAC), acts on the quantum bit after passing through the quantum bit control line, and is used to control the quantum bit.

[0065] This embodiment aims to achieve high-speed, high-precision, and high-real-time calibration of qubit control waveforms through pre-computation pipeline interleaving. The coefficient generator performs on-chip real-time calculations, eliminating the need for extensive storage resources and ensuring low latency and high real-time performance. Therefore, this embodiment uses the coefficient generator and filter to calibrate the qubit waveform, addressing waveform distortion compensation during high-speed, high-fidelity quantum gate operations and meeting the waveform accuracy, speed, and flexibility requirements of superconducting quantum computing systems.

[0066] Specifically, to address the waveform distortion compensation requirements in superconducting quantum measurement and control systems, a pre-calculated pipelined filter architecture is proposed, along with a calibration circuit that supports complex-domain modeling characteristics. The pre-calculation stage calculates intermediate results in advance, reducing data correlation, while the pipeline stage increases the output data rate. By configuring a coefficient generator, filter coefficients are configured externally and generated on-chip in real time. This approach improves output accuracy and output data rate, with values ​​updated once at each sampling point, ensuring that all sampling points are valid values. The filter coefficients can be dynamically configured, meeting the high-performance requirements of superconducting quantum computing systems.

[0067] In one embodiment, the multi-phase envelope distribution device is mainly used to receive external pre-stored envelope data and output multi-phase data according to a clock frequency to match a subsequent multi-channel parallel filtering structure.

[0068] In one embodiment, the filter is configured with filter coefficients by a coefficient generator to achieve high-speed and high-precision filtering of the multi-channel differential signals output by the differential module.

[0069] Due to its recursive structure, traditional infinite impulse response (IIR) filters have timing constraint issues in hardware implementation. Specifically, the critical path is too long, resulting in a limited clock frequency, which in turn affects the system's data rate and calibration accuracy. To address this issue, this embodiment optimizes the existing IIR filter design, such as Figure 7 As shown in the figure, a high-speed IIR filter based on pre-calculated pipeline interleaving is proposed. The value of its sampling point is updated once in each clock cycle, and all sampling points are valid data points. It can adapt to the performance requirements of high-speed digital-to-analog converters (DACs), thereby significantly improving the data rate and output accuracy of the system.

[0070] Specifically: Figure 3 As shown, the direct first-form representation of the existing classic first-order IIR filter is: ,in, represent discrete time indices, Indicates time The output signal value, Indicates time The input signal value, For the moment The output signal value, is the weight coefficient of the input path, which directly controls the current input signal value Current output signal value The degree of contribution, Mainly affects the overall gain and high-frequency response of the filter; Represents the weight coefficient of the feedback path, which directly controls the output signal value at the previous moment Output signal value at the current moment The contribution of , in the waveform calibration circuit of the quantum bit, , ,in Obtained through quantum bit related experiments, representing the relevant parameters of the circuit, , is the sampling rate, T is the sampling period, and its structure is shown in Figure 2 Its recursive structure makes the current output dependent on past outputs and current inputs. This feedback mechanism makes the critical path excessively long, limiting the system's maximum clock frequency in hardware implementations. The rate of a first-order IIR filter in an FPGA implementation does not exceed 100 MHz, and in a chip implementation, it does not exceed 500 MHz. Existing implementations match the DAC rate by averaging multiple points. However, not all calibration waveforms in this multi-point averaging scheme are valid data points. Errors exist at some points during the real-time calculation of the calibration waveform. As the sampling rate increases, it cannot effectively support the measurement and control requirements of superconducting quantum computing, and short pulses can result in significant errors. A DAC (Digital to Analog Converter) is a device used to convert digital signals into analog signals.

[0071] The filter can be made to output multiple valid calibration waveforms in parallel in the same clock cycle in the slow clock domain. By repeatedly iterating the first-order filtering, we can obtain:

[0072]

[0073] Where M represents the number of pre-calculated levels, is the series index, is the weight coefficient of the input path, Represents the weight coefficient of the feedback path.

[0074] At this moment The output signal value Only with the moment The output signal value The key path can be optimized to increase the speed of a single IIR filter, but it is not enough to support 3G sampling rates. In ASIC implementation, a single IIR filter can operate up to 375M. By splitting the input envelope data through the differential module and calibrating them separately, a complete calibration waveform can be obtained.

[0075]

[0076] in, is the number of pre-calculated levels, which is equal to the number of parallel output paths. The index of the output path.

[0077] Through Figure 4 The method of fully parallelizing iterative calculation shown in FIG1 meets the data rate requirement, but each calculation introduces M additional multiplications and M-1 additions, and requires M paths. The resource overhead will be as follows: Therefore, this embodiment introduces an incremental block filtering structure, such as Figure 5 As shown, The data at the moment is calculated in full parallel, and the subsequent M-1 data are still calculated using a recursive structure, that is:

[0078] ;

[0079] ;

[0080] in, For the path differential signals, is the feedback signal, For the The output signal of the circuit, For the Differential signal of the circuit.

[0081] The overhead is 2M times that of a classic filter, but the recursive structure introduces an M-1 carry chain during calculation. This makes the recursive structure's logic M-1 times more complex than a classic IIR filter, significantly reducing the maximum operating frequency. By inserting registers into the recursive calculation structure, a pipeline structure is formed, reducing the critical path length and increasing the operating frequency.

[0082] In this embodiment, a pre-calculation stage and a pipeline stage based on a classic IIR filter are introduced; the pre-calculation stage includes M+1 multipliers and M adders, and performs pre-calculation based on M differential signals and M+1 coefficients; the hierarchical pipeline uses the classic first-order IIR filter structure to calculate the differential signals of the remaining paths respectively, the first stage uses the corresponding differential input and the pre-calculation result of the pre-calculation stage as input signals, and the remaining stages use the differential input and the calculation result of the previous stage as input signals.

[0083] The pre-calculation stage calculates the signal at all times completely independently , and the pipeline calculation stage can calculate the signal independently of the 3~M stages . You can use the calculation results of the previous level Calculate the current time ,Right now:

[0084] ;

[0085] This does not affect any time The calculation of the remaining stages is similar. At this point, the M-1 carry chain has been broken into an M-1 pipeline structure. The M-1 combinational logic is split into M-1 or more clock cycles to complete. Each pipeline stage only processes two multiplications and one addition at most.

[0086] Assume M=8, and each pipeline stage is implemented using two clock cycles. The structure is detailed in the attached Figure 7 , then the algorithm of the above structure can be specifically expanded as follows:

[0087] .

[0088] This embodiment proposes a pipeline-interleaved IIR filter architecture, and can support calibration circuits with complex domain modeling characteristics. Through the pipeline architecture, intermediate results are calculated in advance, data correlation is reduced, and the output data rate is increased. Due to the IIR filter feedback calculation, the classical structure makes the critical path too long. In the ASIC implementation, it can run up to 375M after timing constraints. In order to match the high-speed DAC, linear interpolation or near-interpolation is required, and there is a large error when calibrating short pulses. The fully parallel architecture consumes a large number of multipliers and occupies more resources. The incremental block structure optimizes resources on the basis of the fully parallel structure, but introduces a carry chain, which makes the critical path too long. This design breaks the carry chain to make it a pipeline structure. Under the premise of ensuring data validity, it shortens the critical path, improves scalability and effective data throughput, and can provide strong support for large-scale, high-speed and high-precision quantum control waveform calibration.

[0089] In one embodiment, Figure 6 As shown, the coefficient generator is used to latch the coefficients transmitted by the host computer and generate the coefficients required by the IIR filter according to the latched coefficients;

[0090] A classic first-order IIR filter only requires and The two filter coefficients can be configured by the host computer, and the implementation of the full parallel IIR filter (taking M=8 as an example) is:

[0091]

[0092] in, is the weight coefficient of the input path, represents the weight coefficient of the feedback path, These are all coefficients configured by the host computer.

[0093] This embodiment requires more coefficients. Taking M=8 as an example, a filter requires nine coefficients, while the classic IIR filter only requires two coefficients. Figure 4If all the coefficients are configured by the host computer, it will take a lot of time, the real-time performance will be poor, and too many coefficients need to be configured. Therefore, this embodiment adopts the host computer configuration Two filter coefficients are calculated on-chip in real time using two complex multipliers.

[0094] In order to support the modeling of the complex characteristics of quantum bits, complex multipliers are used during calibration. Traditional IIR filters do not have this requirement and all use real multipliers. Complex multipliers are used in both the coefficient generator and the IIR filter of this embodiment to optimize the complex multiplication unit to save area and power consumption.

[0095] All complex multipliers used in the coefficient generator and IIR filter of this embodiment are divide-and-conquer operation models, specifically: one complex multiplication is decomposed into a combination of three real multiplications and five real additions, saving one multiplier and thus saving resources required for hardware implementation.

[0096] like Figure 8 The complex multiplier shown in are all real numbers, and their function is to complete the operation And output its real and imaginary parts. Direct calculation requires four multipliers, that is, complex number operation , then 4 real multipliers are required.

[0097] In this embodiment, the real number Input into real adder 1, and add the real number Input to real adder 2; use the output of adder 1 and the output of adder 2 as the input of real multiplier 1; Input to real multiplier 2, the real number Input into real number multiplier three; use the output of real number multiplier one and the opposite number of the output of real number multiplier two as input to real number adder three; use the output of real number multiplier two and the opposite number of the output of real number multiplier three as input to real number adder four to output an imaginary number; use the output of real number adder three and the output of multiplier three as input to real number adder five to output a real number.

[0098] That is, this embodiment arranges complex number operations:

[0099] ;

[0100] Therefore, this embodiment only requires three multipliers. This embodiment constructs a divide-and-conquer operation model for complex multipliers, decomposing one complex multiplication into an optimized combination of three real multiplications and five real additions, thus saving one multiplier.

[0101] In this embodiment, in order to avoid overflow during multiplication and addition operations, the extended bit width and truncation compensation logic are used to reduce the quantization error during the operation and optimize resource utilization. Figure 7 The error analysis results compare the error between the PC pre-stored and on-chip real-time generated calculated code values. The figure shows the normalized error.

[0102] Figure 9 and Figure 11 The ideal calibration waveform is consistent with the Figure 9 and 11 , the rising and falling edges have a clear gap. Figure 9 The rising and falling edges are closer to the ideal calibration waveform. Figure 10 and 12 , normalized error, it can be seen that by adopting this embodiment to perform real-time waveform correction, the final error can be controlled to the order of one ten-thousandth.

[0103] Figure 13 A comparison chart of the effects of this embodiment, the ideal calibration waveform, and the linear interpolation scheme is shown. When the pulse time is short, due to the small number of valid data points, it can be clearly seen that there are large errors at the rising and falling edges when the linear interpolation scheme is used. This scheme adopts a hybrid architecture of pre-calculation and pipeline, and all data points are valid data points. It can achieve high-precision calibration while matching the DAC rate, improving the calibration accuracy of the waveform, and the effect is particularly obvious for short pulses.

[0104] Figure 14 This comparison analyzes the normalized error of different types of control waveforms calibrated with different line parameters, including the mean and standard deviation of the normalized error within the corresponding time after the falling edge. Four lines correspond to four different sets of line parameters, and each line contains seven points, corresponding to waveforms of different lengths and types. It can be seen that compared to the hardware implementation of the linear interpolation solution, this solution can reduce the mean error by at least an order of magnitude for different line parameters within 20ns-40ns after the falling edge. The standard deviation is optimized, and the fluctuations between different lines and different envelopes are relatively small. Most indicators in the 1us-1.1us period after the falling edge are optimized, with no significant degradation.

[0105] Therefore, this embodiment shortens the critical path and optimizes the timing by inserting latches based on the pre-calculation stage. The pipeline stage calculates the remaining output results based on the results of the pre-calculation stage. There is no need to compress the data. One sampling point can be updated in each high-frequency clock cycle, so that all data are valid data, and the equivalent sampling rate and accuracy are greatly improved.

[0106] As an embodiment;

[0107] 1) Multiphase envelope distributor;

[0108] Receives four external parallel inputs, converts the parsed four parallel inputs into eight parallel outputs as needed, and transmits the eight parallel data outputs to the differential module. In addition, the external input can be adjusted as needed.

[0109] 2) Differential module;

[0110] The eight-way parallel data is differentially operated, and the multiple differential signals of the eight-way differential output are transmitted to the IIR filter module.

[0111] 3) Coefficient generator: used for real-time generation of coefficients on chip;

[0112] Based on the coefficient data output by the lookup table, the required filter coefficients are latched; the remaining filter coefficients are generated according to the latched coefficients; in addition, the coefficient generator can adjust the target frequency when calculating the remaining filter coefficients based on the latched coefficients.

[0113] 4) IIR filter;

[0114] The coefficient generator configures the correlation coefficients required by the IIR filter in real time to filter the multi-path differential signals from the differential module.

[0115] 5) Digital adder;

[0116] The output of the multi-phase envelope distributor is added to the multi-channel parallel output signal of the IIR filter to generate the final correction waveform. The correction waveform is output to the quantum bit control line through the analog output module through the high-speed DAC and low-noise amplifier; the correction waveform is applied to the quantum bit through the quantum bit control line.

[0117] This embodiment achieves high-precision waveform generation and synchronous control through multi-path interleaving, combining the advantages of digital and analog circuits, leveraging both the flexibility of digital circuits and the high precision of analog circuits. This embodiment offers high precision, real-time performance, flexibility, synchronicity, and stability, making it suitable for superconducting quantum computing measurement and control systems.

[0118] In this embodiment, a qubit waveform calibration system for a pre-calculated pipelined interleaved IIR filter is also provided, comprising a multiphase envelope distributor, a differential module, a coefficient generator, an IIR filter, and a digital adder;

[0119] A multi-phase envelope distributor is used to receive and parse external predefined envelope data and dynamically convert the external envelope data into parallel outputs;

[0120] A differential module, used for performing a differential operation on the output of the multi-phase envelope distributor;

[0121] The coefficient generator is used to latch the coefficients transmitted by the host computer and generate the remaining coefficients based on the latched coefficients;

[0122] An IIR filter, based on the multi-channel differential signals output by the differential module and the coefficients generated by the coefficient generator as input, filters the multi-channel differential signals;

[0123] A digital adder is used to add the output of the multiphase envelope distributor and the output of the IIR filter to generate a final calibration waveform. The calibration waveform acts on the quantum bit after passing through the quantum bit control line to control the quantum bit.

[0124] In this embodiment, a computer-readable storage medium is further provided. The computer-readable storage medium stores a plurality of classification programs. The plurality of classification programs are used to be called by a processor and execute the waveform calibration method as described above.

[0125] Those skilled in the art will understand that all or part of the steps of implementing the above-mentioned method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above-mentioned method embodiment; and the aforementioned storage medium includes: ROM, RAM, disk or optical disk, etc. Various media that can store program codes.

[0126] The above description is only a preferred specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with the technical field, within the technical scope disclosed by the present invention, who makes equivalent replacements or changes based on the technical solution and inventive concept of the present invention, should be covered by the scope of protection of the present invention.

Claims

1. A real-time qubit waveform calibration system based on a pre-calculated pipeline hybrid architecture, characterized by: include: A multi-phase envelope distributor is used to receive and parse external predefined envelope data and dynamically convert the external envelope data into parallel outputs; A differential module, configured to perform a differential operation on the output of the polyphase envelope distributor to obtain M differential signals, where M is an integer; The coefficient generator is used to latch the coefficients transmitted by the host computer and generate the coefficients required by the filter according to the latched coefficients; a filter, which filters the multi-channel differential signals based on the M-channel differential signals and the filter coefficients generated by the coefficient generator as input, and outputs calibrated waveforms in a multi-channel parallel manner; A digital adder, configured to add the output of the multiphase envelope distributor and the output of the filter to generate a final calibration waveform. The calibration waveform is output by the digital-to-analog converter, passes through the qubit control line, and acts on the qubit to control the qubit. The filtering process of the multi-channel differential signal is as follows: Introducing a pre-calculation stage and a pipeline calculation stage into the filter, and providing coefficients for the pre-calculation stage and the pipeline calculation stage through a coefficient generator; The pre-calculation stage pre-calculates the M differential signals through M+1 multiplication operations and M addition operations; The pipeline calculation stage uses a classic first-order IIR filter to perform calculations based on the results of the pre-calculation stage. The first stage in the pipeline calculation stage uses the delayed differential signal output by the branch corresponding to the differential module and the calculation result of the pre-calculation stage as input signals, and each of the remaining stages uses the delayed differential signal of the branch corresponding to the differential module and the calculation result of the previous stage as input signals.

2. The real-time quantum bit waveform calibration system based on a pre-calculated pipeline hybrid architecture according to claim 1 is characterized in that: In the pipeline calculation stage, the M-1 pipeline stages are split into at least M-1 clock cycles to complete, and each pipeline stage processes at most two multiplications and one addition.

3. The real-time qubit waveform calibration system based on a pre-calculated pipeline hybrid architecture according to claim 2, characterized in that: The pre-calculation stage calculates the output signal of the corresponding branch completely independently, and each stage in the pipeline completes the calculation within two clock cycles.

4. The real-time quantum bit waveform calibration system based on a pre-calculated pipeline hybrid architecture according to claim 1, characterized in that: The coefficient generator is based on the coefficient data sent by the host computer and latched, and uses a complex multiplier to dynamically calculate the remaining coefficients and latch them.

5. The real-time quantum bit waveform calibration system based on a pre-calculated pipeline hybrid architecture according to claim 4 is characterized in that: The complex multipliers used in the coefficient generator and filter are all divide-and-conquer operation models, specifically: Decomposing a complex multiplication into a combination of three real multiplications and five real additions saves one multiplier.

6. The real-time quantum bit waveform calibration system based on a pre-calculated pipeline hybrid architecture according to claim 5, characterized in that: set up are all real numbers, is an imaginary unit, and is calculated using the divide-and-conquer operation model And output the real part and imaginary part. The specific structure is as follows: The real number Input into real adder 1, and add the real number Input to real adder 2; The output of adder 1 and the output of adder 2 are used as inputs of real multiplier 1; The real number Input to real multiplier 2, the real number Input to real multiplier three; The output of the real number multiplier 1 and the inverse of the output of the real number multiplier 2 are used as the input of the real number adder 3; The output of the real number multiplier 2 and the inverse of the output of the real number multiplier 3 are used as inputs of the real number adder 4 to output an imaginary part; The output of the real adder three and the inverse of the output of the multiplier three are used as inputs of the real adder five to output the real part.

7. The real-time qubit waveform calibration system based on a pre-calculated pipeline hybrid architecture according to claim 1, characterized in that: The calibration waveform is outputted by the digital-to-analog converter and acts on the qubit after passing through the qubit control line. Specifically: Outputting the calibration waveform to the quantum bit control line through a digital-to-analog converter and a low-noise amplifier; The correction waveform is applied to the qubit via the qubit control line.

8. The real-time quantum bit waveform calibration system based on a pre-calculated pipeline hybrid architecture according to claim 1, characterized in that: The classic first-order IIR filter is as follows: ； in, represent discrete time indices, Respectively indicate time The output signal value, Indicates time The input signal value, is the weight coefficient of the input path, Represents the weight coefficient of the feedback path.

9. The real-time quantum bit waveform calibration system based on a pre-calculated pipeline hybrid architecture according to claim 8, characterized in that: described and The calculation formula is as follows: in, and is the line parameter, , is the sampling rate, and T is the sampling period.

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