Devices, systems, and methods for latch reset logic

Abstract

The invention relates to an apparatus, system and method for latch reset logic. A memory bank may have a local latch coupled between a local data bus and the memory bank. Some of the local latches may be a shared local latch coupled to a first bank and a second bank. The shared latch may latch data in response to a first clock signal and a second clock signal, and may reset in response to a combined reset signal. The reset logic circuit can receive the clock signal, a first reset signal and a second reset signal. The reset logic circuit may provide the combined reset signal based on the first and second clock signals and the reset signal. The clock signal may be a column valid command, and the reset signal is a waveform (e.g., a falling edge) of a row valid command that acts as part of an access operation on the first memory bank or the second memory bank.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the invention patent application with the application date of February 1, 2021, application number "202110135668.7", and invention name "Device, system and method for latch reset logic". Technical Field

[0003] The present invention relates generally to semiconductor devices, and in particular, to apparatus, systems, and methods for latch reset logic. Background Art

[0004] The present invention generally relates to semiconductor devices, such as semiconductor memory devices. A semiconductor memory device may include a plurality of memory cells for storing information. The stored information may be encoded as binary data, and each memory cell may store a single bit of the information. A memory array may be organized into a plurality of memory banks. During a memory operation, one or more memory banks may be activated, and information may be read from or written to the memory cells of the activated memory bank, for example. To save space, power, etc., certain components of the memory may be shared by multiple memory banks. Summary of the Invention

[0005] In one aspect, the present invention provides an apparatus comprising: a first memory storage body; a second memory storage body; a local latch circuit configured to maintain storage data associated with the first memory storage body or the second memory storage body in response to a first clock signal or a second clock signal at an active level, and configured to reset the storage data in response to a combined reset signal at an active level; and a reset logic circuit configured to receive a first reset signal associated with the first memory storage body, a second reset signal associated with the second memory storage body and provide the combined reset signal based on the first reset signal and the second reset signal, wherein a change of the reset signal from an active level to an inactive level coincides with a change of the first clock signal or the second clock signal from an inactive level to an active level.

[0006] On the other hand, the present invention further provides a device comprising: a first memory storage body, which is configured to be in a first row valid state in response to a first row valid command, and to be in a first column valid state in response to a first column valid command; a second memory storage body, which is configured to be in a second row valid state in response to a second row valid command, and to be in a second column valid state in response to a second column valid command; a reset logic circuit, which is configured to provide a combined reset signal based on each of the first row valid command, the first column valid command, the second row valid command and the second column valid command; and a local latch circuit, which is configured to latch each of the first data of the first memory storage body and the second data of the second memory storage body and to be reset in response to the reset signal.

[0007] On the other hand, the present invention further provides an apparatus comprising: a plurality of local latches, wherein the plurality of local latches include a shared latch coupled to a first memory storage body and a second memory storage body, and wherein the shared latch is configured to latch data in response to a first clock signal or a second clock signal at an active level, and is configured to be reset based on a combined reset signal at an active level; and reset logic configured to store a first row valid signal associated with the first memory storage body in response to the first clock signal, and to store a second row valid signal associated with the second memory storage body in response to the second clock signal, wherein the reset logic is configured to provide the combined reset signal at an active level in response to a falling edge of the first row valid signal or the second row valid signal when the other of the first row valid signal or the second row valid signal is not stored at an active level. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram of a semiconductor device according to an embodiment of the present invention.

[0009] Figure 2 is a block diagram of a memory including shared local latches according to some embodiments of the present invention.

[0010] Figure 3 is a block diagram of a memory with shared local latches according to some embodiments of the present invention.

[0011] Figure 4 is a block diagram of a memory having shared write latches and shared read latches according to some embodiments of the present invention.

[0012] Figure 5 is a block diagram of a memory having shared latches and unshared latches according to some embodiments of the present invention.

[0013] Figure 6 is a schematic diagram of reset logic and local latches according to some embodiments of the present invention.

[0014] Figure 7 is a schematic diagram of reset logic and local latches according to some embodiments of the present invention.

[0015] Figure 8 is a timing diagram of example operation of reset logic and reset latch according to some embodiments of the present invention. DETAILED DESCRIPTION

[0016] The following description of certain embodiments is merely exemplary in nature and is by no means intended to limit the scope of the invention or its application or use. In the following detailed description of the embodiments of the present system and method, reference is made to the accompanying drawings that form a part thereof, and the accompanying drawings are presented by way of illustrative specific embodiments in which the description system and method can be practiced therein. These embodiments are described in sufficient detail to enable those skilled in the art to practice the currently disclosed system and method, and it should be understood that other embodiments may be utilized and that structural and logical changes may be made without departing from the spirit and scope of the present invention. In addition, for the purpose of clarity, when certain features are obvious to those skilled in the art, the detailed description of the features will not be discussed so as not to obscure the description of the embodiments of the present invention. Therefore, the following detailed description should not be understood in a limiting sense, and the scope of the present invention is defined only by the appended claims.

[0017] A memory device may include a memory array having a plurality of memory cells, each of which is positioned at the intersection of a word line (row) and a digit line (column). During an access operation, such as a read or write operation, a row may be activated, and data may be read from or written to the memory cells along the activated row. The memory cells may be organized into banks. When an access operation is performed, it may be directed to a specific bank, one or more rows in the specified bank may be activated, and data may be provided (or received) along the digit lines. The digit lines may be coupled to local latches, which may receive (or provide) data from a global data bus. A clock signal may cause the local latches to latch data from the global bus (or from a memory bank), and a reset signal may cause the local latches to reset when the stored value is no longer needed. The clock signal and reset signal may be specific to one of the banks (e.g., a first reset signal for a first bank, a second reset signal for a second bank, etc.).

[0018] To improve memory performance (e.g., reduce power consumption, reduce space, etc.), local latches can be shared between a pair of memory banks. Therefore, the latches may need to respond to clock signals and reset signals for both memory banks. The two reset signals may be received by reset logic circuitry, which can provide a combined reset signal. If the two reset signals change state rapidly (e.g., if the second signal activates shortly after the first signal deactivates), the reset logic can 'skip' activation of the combined reset signal. For example, if the combined reset signal is stored in the reset logic, rapid changes in inputs can result in metastable states. Even if the two reset signals change state rapidly, it may be desirable to ensure that the combined reset signal is correctly provided.

[0019] The present invention relates to an apparatus, system, and method for latch reset logic. The reset logic may receive a first reset signal and a first clock signal associated with a first memory bank, and a second reset signal and a second clock signal associated with a second memory bank. The reset logic may provide a combination reset signal such that the falling edge of the combination reset signal may coincide with the rising edge of the first or second clock signal. In this manner, a shared latch cannot receive a valid clock signal and a valid reset signal at the same time, which may cause undesirable behavior in a local latch. For example, the reset logic may have a first flip-flop circuit (FF circuit) that latches a first reset signal based on a first clock signal and a second FF circuit that latches a second reset signal based on a second clock signal. The combination reset signal may be provided based on the values stored in the first FF circuit and the second FF circuit.

[0020] Figure 1 1 is a block diagram of a semiconductor device according to an embodiment of the present invention. The semiconductor device 100 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip.

[0021] The semiconductor device 100 includes a memory array 118. The memory array 118 is shown as including a plurality of memory banks. Figure 1 In the embodiment of the present invention, the memory array 118 is shown as including eight memory banks BANK0 to BANK7. More or fewer memory banks may be included in the memory array 118 of other embodiments. Each memory bank includes a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged at the intersections of the plurality of word lines WL and the plurality of bit lines BL. The selection of the word lines WL is performed by the row decoder 108, and the selection of the bit lines BL is performed by the column decoder 110. Figure 1In the embodiment of the present invention, row decoder 108 includes a corresponding row decoder for each memory bank, and column decoder 110 includes a corresponding column decoder for each memory bank. Bit lines BL are coupled to corresponding sense amplifiers (SAMPs). Read data from bit lines BL is amplified by sense amplifiers SAMPs and transferred to read / write amplifiers via complementary local data lines (LIOT / B), transfer gates (TG), and complementary main data lines (MIOT / B) coupled to error correction code (ECC) control circuit 120. Conversely, write data output from ECC control circuit 120 is transferred to sense amplifiers SAMPs via complementary main data lines MIOT / B, transfer gates TG, and complementary local data lines LIOT / B, and written to memory cells MC coupled to bit lines BL.

[0022] To manage the timing of various memory operations, each bank of memory array 118 may be associated with a set of local latches 121. Local latches 121 may store data associated with a memory bank and may couple the stored data to a global data bus, which couples local latches 121 to IO circuits 122 (and to DQ pads). For example, IO circuits 122 may receive data at a DQ pad and provide it along the global data bus to local latches 121, which may then provide the data to the associated bank. Local latches 121 may receive a clock signal that causes them to latch the data along the global data bus. In some embodiments, the clock signal may be associated with a specific operation (e.g., a write signal, a read signal) and may be specific to a particular bank (e.g., a first clock associated with a first bank, a second clock associated with a second bank). Thus, a local latch may respond to a clock signal associated with the bank with which it is associated. Similarly, when the data in local latch 121 is no longer needed, a reset signal can cause the latch to return to a neutral state. Reset signals can also be associated with specific operations and / or memory banks, and certain local latches can respond to specific ones of the reset signals. In some embodiments, the reset signal can be a signal used by the memory for various operations, such as a precharge signal Pre used to turn off a word line.

[0023] The clock and reset signals may represent waveforms of one or more signals used by the memory as part of an access operation. In some embodiments, the reset signal may be part of the waveform of a signal used to activate a row in one of the selected memory banks. For example, the reset signal may be the falling edge (e.g., transition from an active state to an inactive state) of a row activate command such as ACT or RAS. In some embodiments, the clock signal may be a column activate command used to activate a digit line so that data can be read from or written to the digit line. For example, the clock signal may be the read signal RD or the write signal WT. Other signals and other waveforms may be used in other examples.

[0024] Some of the local latches 121 may be shared local latches, which are associated with more than one memory bank. These local latches 121 can be activated to store data associated with any of the memory banks associated with the shared latch. Therefore, the shared local latch can respond to signals associated with any of the memory banks associated with the local latch (e.g., a clock signal and a reset signal). For example, if a particular local latch 121 is shared between a first memory and a second memory bank, the shared local latch can respond to both the first clock signal and the second clock signal. One or more reset logic circuits can receive reset signals associated with the memory banks shared by the shared latches and can provide a combined reset signal to the shared latches. Reset logic and the operation of the reset logic and the combined reset signal are discussed in more detail herein.

[0025] The semiconductor device 100 may employ a plurality of external terminals, including: a command and address (C / A) terminal coupled to a command and address bus to receive command and address and CS signals; a clock terminal for receiving clocks CK and / CK; a data terminal DQ for providing data; and a power supply terminal for receiving power supply potentials VDD, VSS, VDDQ, and VSSQ.

[0026] The clock terminal is supplied with external clocks CK and / CK, which are provided to input circuit 112. The external clocks may be complementary. Input circuit 112 generates an internal clock ICLK based on the CK and / CK clocks. The ICLK clock is provided to command decoder 106 and internal clock generator 114. Internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock can be used for timing operations of various internal circuits. The internal data clock LCLK is provided to input / output circuit 122 to time the operation of circuits included in input / output circuit 122, for example, to a data receiver to time the reception of write data.

[0027] The C / A terminal may be supplied with a memory address. The memory address supplied to the C / A terminal is transferred to the address decoder 104 via the command / address input circuit 102. The address decoder 104 receives the address and supplies the decoded row address XADD to the row decoder 108 and the decoded column address YADD to the column decoder 110. The address decoder 104 may also supply a decoded bank address BADD, which may indicate the bank of the memory array 118 containing the decoded row address XADD and column address YADD. The C / A terminal may be supplied with a command. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing memory, such as a read command for performing a read operation and a write command for performing a write operation, as well as other commands and operations. An access command may be associated with one or more row addresses XADD, column addresses YADD, and bank addresses BADD to indicate the memory cells to be accessed.

[0028] The commands may be provided as internal command signals via the command / address input circuit 102 to the command decoder 106. The command decoder 106 includes circuitry that decodes the internal command signals to generate various internal signals and commands for performing operations. For example, the command decoder 106 may provide row command signals for selecting word lines and column command signals for selecting bit lines.

[0029] Device 100 may receive an access command as a read command. When the read command is received and the bank address, row address, and column address are timely supplied with the read command, read data is read from the memory cells corresponding to the row address and column address in memory array 118. The read command is received by command decoder 106, which provides an internal command causing the read data from memory array 118 to be provided to ECC control circuitry 120. The read command may also cause one or more parity bits associated with the read data to be provided to ECC control circuitry 120 along MIO T / B. ECC control circuitry 120 may use the parity bits to determine whether the read data contains any errors and, if any errors are detected, correct them to generate corrected read data. The corrected read data is stored in local latches 121 associated with the bank indicated by the bank address. Local latches 121 may then provide the corrected read data to IO circuitry 122 along a global data bus. Corrected read data is output from data terminal DQ to the outside of device 100 via input / output circuit 122. In some embodiments, ECC circuit 120 may be omitted, and read data may be provided directly to local latch 121 (eg, without parity bits).

[0030] Device 100 can receive an access command as a write command. When the write command is received and the bank address, row address, and column address are supplied in time with the write command, write data is supplied to ECC control circuit 120 via the DQ terminal. The write data is supplied along the global data bus and stored in the local latch 121 associated with the bank indicated by the bank address. The write data stored in the local latch 121 is written to the memory cell corresponding to the row address and column address in memory array 118. The write command is received by command decoder 106, which provides an internal command, causing the write data to be received by the data receiver in input / output circuit 122. A write clock may also be provided to the external clock terminal to time the receipt of the write data by the data receiver in input / output circuit 122. The write data is supplied to ECC control circuit 120 via the local latch 121. ECC control circuit 120 may generate several parity bits based on the write data, and the write data and parity bits may be provided to memory array 118 for writing into memory cells MC. In some embodiments, ECC control circuit 120 may be omitted, and the data in local latch 121 may be provided to a memory bank.

[0031] Optional ECC control circuitry 120 may be used to ensure the fidelity of data read from a particular group of memory cells to data written to that group of memory cells. Device 100 may include several different ECC control circuits 120, each responsible for a different portion of memory cells MC of memory array 118. For example, there may be one or more ECC control circuits 120 for each bank of memory array 118.

[0032] Each ECC control circuit 120 may receive a certain number of data bits (from either the IO circuit 122 or the memory array 118) and may use a number of parity bits based on the number of data bits to correct potential errors in the data bits. For example, as part of a write operation, the ECC control circuit 120 may receive 128 bits of data from the IO circuit 122 and may generate 8 parity bits based on the 128 data bits. The 128 data bits and 8 parity bits (e.g., a total of 136 bits) may be written to the memory array 118. As part of an example read operation, the ECC control circuit 120 may receive 128 data bits and 8 parity bits from the memory cell array 118. The ECC control circuit 120 may use the 8 parity bits to determine whether there are any errors in the 128 read data bits and, if an error is found, may correct it. For example, the ECC control circuit 120 may be able to locate and correct up to one error in the 128 data bits based on the 8 parity bits. Although various embodiments may be discussed with reference to ECC circuits that find one error in 128 data bits using 8 parity bits, it should be understood that these are for explanation purposes only and other numbers of data bits, error bits, and parity bits may be used in other example embodiments.

[0033] Device 100 may also receive commands causing it to perform one or more refresh operations as part of self-refresh mode. In some embodiments, a self-refresh mode command may be externally issued to memory device 100. In some embodiments, a self-refresh mode command may be periodically generated by a component of the device. In some embodiments, refresh signal AREF may also be activated when an external signal indicates a self-refresh enter command. Refresh signal AREF may be a pulse signal that is activated when command decoder 106 receives a signal indicating entry into self-refresh mode. Refresh signal AREF may be activated once immediately after a command is input and may be periodically activated thereafter with desired internal timing. Refresh signal AREF may be used to control the timing of refresh operations during self-refresh mode, thereby allowing refresh operations to resume automatically. A self-refresh exit command may cause refresh signal AREF to cease automatic activation and return to the idle state. Refresh signal AREF is supplied to refresh control circuit 116. Refresh control circuit 116 supplies a refresh row address RXADD to row decoder 108, which then refreshes one or more word lines WL indicated by the refresh row address RXADD.

[0034] The power supply terminals are supplied with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are supplied to an internal voltage generator circuit 124. The internal voltage generator circuit 124 generates various internal potentials VPP, VOD, VARY, VPERI, and the like based on the power supply terminals VDD and VSS supplied to the power supply terminals. The internal potential VPP is primarily used in the row decoder 108, the internal potentials VOD and VARY are primarily used in the sense amplifiers SAMP included in the memory array 118, and the internal potential VPERI is used in many peripheral circuit blocks.

[0035] The power supply terminals are also supplied with power supply potentials VDDQ and VSSQ. The power supply potentials VDDQ and VSSQ are provided to the input / output circuit 122. In an embodiment of the present invention, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be the same potential as the power supply potentials VDD and VSS supplied to the power supply terminals. In another embodiment of the present invention, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be different potentials from the power supply potentials VDD and VSS supplied to the power supply terminals. The power supply potentials VDDQ and VSSQ supplied to the power supply terminals are used for the input / output circuit 122 so that power supply noise generated by the input / output circuit 122 does not propagate to other circuit blocks.

[0036] Figure 2 is a block diagram of a memory including shared local latches according to some embodiments of the present invention. Memory 200 may be, for example, Figure 1 1 is a diagram of a memory of memory device 100 that highlights the operation of local latches and reset logic. Memory 200 may be a simplified view, and various components of memory 200 may be combined and / or simplified for clarity. For example, C / A circuit 202 may include memory components such as C / A input circuits (e.g., Figure 1 102), a row decoder and a column decoder (eg, Figure 1 108 and 110) and / or a command decoder (e.g., Figure 1 106).

[0037] Memory 200 includes a first memory bank (Bank 0) 210, a second memory bank (Bank 1) 212, a third memory bank (Bank 2) 214, and a fourth memory bank (Bank 3) 216. Each of memory banks 210-216 includes a number of memory cells arranged at the intersection of respective rows and columns. First bank 210 and second bank 212 share a set of local latches 208, and third bank 214 and fourth bank 216 share a set of local latches 209. For clarity, only a single latch is shown in detail in each of the sets of local latches 208 and 209, however, each of the sets of local latches 208 and 209 may include multiple such latches.

[0038] The local latch 208 has a first input / output terminal (labeled D / Q) coupled to the global DQ bus. The global DQ bus is in turn coupled to DQ terminal 201 (and to Figure 2 2 ). The local latch 208 has a second input / output terminal (labeled Q / D) coupled to the memory banks 210 and 212. Two input / output terminals are shown to indicate that data can flow through the latch in different directions based on the operation. For example, if the local latch 208 is used as part of a write operation, the data can be provided along the global DQ bus, the first I / O terminal D / Q can be the input terminal, and the second I / O terminal Q / D can be the output terminal that provides the stored bit to the memory banks 210 / 212. If the local latch 208 is used as part of a read operation, the data can come from one of the memory banks 210 / 212, and the second I / O terminal Q / D can serve as the input, while the first I / O terminal D / Q serves as the output terminal to the global DQ bus.

[0039] C / A circuit 202 can provide various signals to local latches 208 and 209. For example, C / A circuit 202 can provide first, second, third, and fourth reset signals, Rst0 through Rst4, each of which can be associated with a respective one of the four memory banks 210 through 216. Similarly, C / A circuit 202 can provide clock signals, Clk0 through Clk4, each of which can be associated with a respective one of the four memory banks 210 through 216. Clock signals Clk0 through Clk4 can represent any signal that indicates that an access operation is being performed on the associated memory bank 210 through 216. For example, clock signals Clk0 through Clk4 can be column valid commands, such as read signals RD0 through RD4 or write signals WT0 through WT4. Reset and clock signals can be provided by C / A circuit 202 in response to a bank address indicating one of the memory banks 210 through 216 and a received access command. For example, if a read command is received along with a bank address indicating the first bank 210, signals Clk0 and Rst0 may be provided.

[0040] A first clock signal Clk0 and a second clock signal Clk1 are provided to a clock terminal CLK of a first local latch 208. In response to activation of the first clock signal Clk0 or the second clock signal Clk1, the first local latch 208 may latch a value (e.g., from the global DQ bus or the first / second memory bank 210 / 212, depending on whether the local latch is used for a write operation or a read operation). A third clock signal Clk2 and a fourth clock signal Clk3 are provided to a clock terminal CLK of a second local latch 209. The second local latch 209 may latch a value (e.g., from the global DQ bus or the third / fourth memory bank 214 / 216, depending on whether the local latch is used for a write operation or a read operation). When the clock signal coupled to the clock terminal CLK of the local latch 208 is valid (e.g., at a high logic level), the local latch 208 may store the value at its input terminal D.

[0041] The C / A circuit 202 may also provide reset signals Rst0 to Rst3, each of which is associated with a corresponding one of the memory banks 210 to 216. The reset signal may indicate that a particular access operation has ended and that the value in the local latches 208 / 209 is no longer needed. For example, the precharge signal Pre may be used as the reset signal. For example, the falling edge of an access signal such as a row active command (e.g., an activation signal such as ACT or RAS) may be used as the reset signal. The first reset signal Rst0 and the second reset signal Rst1 are received by the first reset logic circuit 204, which provides a first combined reset signal Rst01 based on the two reset signals Rst0 and Rst1. The first reset logic circuit 204 also receives clock signals Clk0 and Clk1 and uses these signals to clock the combined reset signal Rst01. The combined reset signal Rst01 is provided to the reset terminal RST of the local latch 208. When the combination reset signal Rst01 is active (e.g., at a high logic level), the latch 208 can be reset to a neutral state. The reset logic circuit 204 can provide activation of the combination reset signal Rst01 whenever the first reset signal Rst0 or the second reset signal Rst1 is active. The reset logic circuit 204 can provide the combination reset signal Rst01 such that each falling edge of the combination reset signal Rst01 occurs approximately simultaneously with a rising edge of one of the clock signals Clk0 or Clk1. In some embodiments, the falling edge of the combination reset signal Rst01 can coincide with a rising edge of one of the clock signals Clk0 or Clk1. The second reset logic circuit 205 can function in a manner similar to the reset logic circuit 204, except that the reset logic circuit 205 provides a second combination reset signal Rst23 based on the reset signals Rst2 and Rst3 and the clock signals Clk2 and Clk3.

[0042] Figure 3 is a block diagram of a memory with shared local latches according to some embodiments of the present invention. In some embodiments, memory 300 may be included in Figure 2 Memory 200 and / or Figure 1 300 may represent a more detailed view of a pair of memory banks 310 and 312 that share a local latch 308 therebetween. Figure 2 Memory 200 and / or Figure 1 The features and operations described for the memory device 100 will no longer be discussed with respect to Figure 3 repeat.

[0043] The local latches 308 include a number of individual shared latches 330 (labeled here 0 through N), each of which is coupled to a first memory bank 310 and a second memory bank 312. In some embodiments, the number of local latches 330 can be based on the number of bits transmitted along the global data bus. Each of the individual shared latches 330 is commonly coupled to a combined reset signal Rst01, a first clock signal CLk0, and a second clock signal Clk1. In some embodiments, each of the local latches can be coupled to two clock signals, Clk0 and Clk1, via clock logic (not shown). For example, the first and second clock signals can be coupled to the inputs of an OR gate, which can commonly provide the combined clock signal Clk01 to each of the latches 330.

[0044] Figure 4 is a block diagram of a memory with shared write latches and shared read latches according to some embodiments of the present invention. In some embodiments, Figure 4 The memory 400 may be respectively included in Figures 1 to 3 For the sake of brevity, the previous description of Figure 3 Memory 300, Figure 2 Memory 200 and / or Figure 1 The features and operations described for the memory device 100 will no longer be discussed with respect to Figure 4 repeat. Figure 4 Memory 400 shows a set of write latches 432 and a set of read latches 434 in local latches 408.

[0045] The memory 400 has a set of shared write latches 432 used as part of write operations to the first memory bank 410 and the second memory bank 412, and a set of shared read latches 434 used as part of read operations to the first memory bank 410 and the second memory bank 412. The C / A circuit 402 can provide a first write clock WT0 and a second write clock WT1 associated with write operations to the first memory bank 410 and the second memory bank 412, respectively. The C / A circuit 402 can also provide read clocks RD0 and RD1 associated with read operations in the first and second memory banks 410 / 412, respectively.

[0046] Reset logic 404 may include write reset logic 406 that provides a combined write reset signal Rst01_WT based on two reset signals Rst0 and Rst1 and two write clocks WT0 and WT1. Reset logic 404 includes read reset logic 407 that provides a combined read reset signal Rst01_RD based on two reset signals Rst0 and Rst1 and two read clocks RD0 and RD1. Write latch 432 may receive both the combined write reset signal Rst01_WT and the write clocks WT0 and WT1. Read latch 434 may receive both the combined read reset signal Rst01_RD and the read clocks RD01 and RD1.

[0047] The write latch 432 can store data from the global DQ bus in response to activation of either write clock WT0 or WT1. The data stored in the write latch 432 can be provided to the memory bank 410 or the memory bank 412 and written to the memory cells of the activated memory bank. Based on the activation of the first reset signal Rst0 or the second reset signal Rst1, the write reset logic 406 can provide activation of the combined write reset signal Rst01_WT. The falling edge of the write reset signal Rst01_WT can occur approximately simultaneously with the rising edge of one of the write clock signals WT0 or WT1. The activation of the combined write reset signal Rst01_WT can cause the write latch 432 to be reset to a neutral state (e.g., to discard the currently stored data).

[0048] Read latch 434 can store data from memory bank 410 or memory bank 412 in response to activation of one of read clocks RD0 or RD1. The data stored in the read latch can then be read out to DQ terminal 401 along the global DQ bus and provided from memory 400. Based on activation of first reset signal Rst0 or second reset signal Rst1, read reset logic 407 can provide activation of combined read reset signal Rst01_RD. The falling edge of read reset signal Rst01_RD may occur approximately simultaneously with the rising edge of one of read clocks RD0 or RD1. Activation of combined read reset signal Rst01_RD can cause read latch 434 to reset to a neutral state.

[0049] Figure 5 is a block diagram of a memory having shared latches and non-shared latches according to some embodiments of the present invention. In some embodiments, Figure 5 The memory 500 may be respectively included in Figures 1 to 4 For the sake of brevity, the previous description of Figure 4 Memory 400, Figure 3 Memory 300, Figure 2Memory 200 and / or Figure 1 The features and operations described for the memory device 100 will no longer be discussed with respect to Figure 5 repeat. Figure 5 Memory 500 shows a set of local latches 508 including a shared latch 532 shared between two memory banks 510 and 512 and a local latch 534 not shared between the memory banks. In some embodiments, the local latches 508 may represent read latches (e.g., Figure 4 434) or write latches (e.g., Figure 4 432).

[0050] The reset logic 504 includes a shared reset logic 506 and a bank-specific reset logic 507. The shared reset logic 506 can be used with Figure 3 The reset logic 304 of the C / A circuit 502 functions in a generally similar manner. Shared reset logic 506 provides a combined reset signal Rst01 when either reset signal Rst0 or Rst1 is asserted, with timing based in part on clock signals Clk0 and Clk1. Bank-specific reset logic 507 can provide reset signal Rst1, which can have timing affected by clock signal Clk1. In some embodiments, bank-specific reset logic 507 can be omitted, and reset signal Rst1 can be passed directly from C / A circuit 502 to local latch 534. In some embodiments, where a waveform of a row valid signal is used, bank-specific reset logic 507 can receive the row valid signal and can generate reset signal Rst1 based on the row valid signal.

[0051] The shared latch 532 is coupled to the clock signals Clk0 and Clk1 and the combined reset signal Rst01. The unshared latch 534, associated with the second memory bank 512 in this example, is coupled to the clock signal Clk1 and the reset signal Rst1. When clocks Clk0 or Clk1 are active, the shared local latch 532 can store data (e.g., from one of the memory banks 510 / 512 or the global DQ bus) and can be reset based on the combined reset signal Rst01. The unshared latch 534 can store data (e.g., from the second memory bank 512 or the global data bus) in response to the activation of clock Clk1 and can be reset based on the reset signal Rst1.

[0052] In some embodiments, a set of local latches 508 may include various mixes of shared and unshared local latches. Although only a single example shared latch 532 and unshared latch 534 are shown, the local latches 508 may include any number of shared and unshared latches. Similarly, while the unshared latch 534 is coupled to the second memory bank 512, the local latches 508 may include latches coupled to the first memory bank 510, latches coupled to the second memory bank 512, or a mix of latches coupled to each memory bank. For example, the local latches 508 may include a shared read latch instead of separate write latches for the first memory bank 510 and the second memory bank 512 (or a shared write latch instead of a shared read latch).

[0053] Figure 6 is a schematic diagram of reset logic and local latches according to some embodiments of the present invention. In some embodiments, reset logic 602 may be included in Figure 2 Reset logic 204 / 205, Figure 3 304, Figure 4 404 and / or Figure 5 Similarly, in some embodiments, the local latch 608 may be included in Figure 2 Local latch 208 / 209, Figure 3 308, Figure 4 408 and / or Figure 5 508. Specifically, Figure 6 The reset logic 602 may represent write reset logic (e.g., Figure 4 406) and the local latch 608 may be a write local latch (e.g., Figure 4 432). It should be understood that other types of reset logic and shared latches (e.g., read reset logic and latches) can be substantially similar to logic 602 and latches 608. In some embodiments, different types of reset logic and latches can be distinguished by the clock signals to which they are coupled. For example, while reset logic 602 is coupled to write clocks WT_k0 and WT_k1 associated with the first and second memory banks, respectively, read logic can be similar to reset logic 602, but instead coupled to read signals RD_k0 and RD_k1.

[0054] The reset logic 602 includes a first flip-flop (FF) circuit 640 and a second FF circuit 642. The first FF circuit 640 has an input coupled to a first row valid command RAS_k0 and a first write clock WT_k0 (e.g., a column valid command), both of which are associated with operations in the first memory bank. The signal RAS_k0 being at an active level may be associated with an access operation in the first memory bank (e.g., memory bank 0). The signal RAS_k0 falling to an inactive level may indicate that the access operation has ended. Therefore, the falling edge of RAS_k0 may act as a reset signal (e.g., the falling edge of RAS_k0 may be similar to a reset signal). Figures 1 to 5 The second FF circuit 642 can be coupled to a second row valid command RAS_k1 and a second write clock WT_k1 (e.g., a column access signal), both of which are associated with operations in the second memory bank. The falling edge of RAS_k1 can serve as a second reset signal. In some embodiments, the first FF circuit 640 and the second FF circuit 642 can be substantially similar to each other. In some embodiments, the first FF circuit 640 and the second FF circuit 642 can be structurally identical but coupled to different inputs.

[0055] The first FF circuit 640 provides a first inverted reset signal RSTF_k0, and the second FF circuit 642 provides a second inverted reset signal RSTF_k1. When no reset signal is provided, the inverted reset signals RSTF_k0 and RSTF_k1 may be generally valid. A logic gate such as a NOR gate 644 provides a combined reset signal RST_k01 (e.g., similar to Figures 1 to 5 When both inputs of one of the FF circuits 640 and 642 become active, the output signal may become active until the first input becomes inactive. For example, when the first FF circuit 640 receives RAS_k0 and WT_k0 at active levels, the output RSTF_k0 may switch to an active level. As long as RAS_k0 is at an active level, the signal RSTF_k0 may remain at an active level. When the signal RAS_k0 falls to an inactive level, the signal RSTF_k0 may also fall to an inactive level to indicate that a reset signal should be provided to the local latch 608.

[0056] Logic gate 644 may be a NOR gate that provides an overall combined reset signal RST_k01 at an active level (e.g., a high logic level) when both inverted signals RSTF_k0 and RSTF_k1 are inactive (e.g., a low logic level). Thus, when one of clock signals WT_k0 or WT_k1 becomes active, the associated inverted reset signal (RSTF_k0 or RSTF_k1) may become active, which in turn may cause combined signal RST_k01 to become inactive.

[0057] The local latch 608 is shown as including clock logic, which in the example is an OR gate 650. The OR gate 650 receives two clock signals WT_k0 and WT_k1 and provides a combined clock signal WT_k01. The combined clock signal WT_k01 can be active when either the first clock signal WT_k0 or the second clock signal WT_k1 is active. The combined clock signal WT_k01 is provided to a clock terminal CLK of a shared latch 652. A reset terminal RST of the shared latch 652 is coupled to the combined reset signal RST_k01. A data terminal D of the latch 652 is coupled to a first signal A, which can be part of a global data bus. An output terminal Q of the latch 652 is coupled to a signal B, which can be provided to the two memory banks coupled to the shared latch 652.

[0058] Figure 7 is a schematic diagram of reset logic and local latches according to some embodiments of the present invention. In some embodiments, reset logic 702 may be included in Figure 2 Reset logic 204 / 205, Figure 3 304, Figure 4 404, Figure 5 504 and / or Figure 6 Similarly, in some embodiments, the local latch 708 may be included in Figure 2 Local latch 208 / 209, Figure 3 308, Figure 4 408, Figure 5 508 and / or Figure 6 608. The reset logic 702 and the local latch 708 can be Figure 6 The reset logic 602 and Figure 6 For the sake of brevity, the implementation scheme of the local latch 608 has been Figure 6 The details and operations described will no longer be Figure 7 repeat.

[0059] Reset logic 702 includes a first flip-flop circuit (eg, Figure 6 640), which includes a first NAND gate 741, a second NAND gate 743, and an inverter 745. The first NAND gate has a first input terminal coupled to RAS_k0 and a second input terminal coupled to RSTF_k0. The second NAND gate 743 has a first input terminal coupled to the output of the first NAND gate 741 and a second input terminal coupled to WT_k0 through an inverter circuit 745. The output of the second NAND gate 743 is the signal RSTF_k0. The second flip-flop circuit can be substantially similar, having NAND gates 747 and 748 and an inverter 749.

[0060] Latch 752 includes first, second, and third inverters 761 to 763 and a NAND gate 764. Second inverter 762 has an input terminal coupled to input D of latch 752. The second inverter also has a first power terminal coupled to clock terminal CK via first inverter 761 and a second power terminal coupled to clock terminal CK of latch 752. The output of second inverter 762 is provided to a node coupled to the input of third inverter 763, which has an output provided to output terminal Q of latch 752. Output terminal Q is also coupled to one of the inputs of NAND gate 764. The other input terminal of NAND gate 764 may be an inverting input coupled to reset terminal Rst of latch 752. The output of NAND gate 764 is coupled to a node between second inverter 762 and third inverter 763.

[0061] Figure 8 is a timing diagram of an example operation of reset logic and a reset latch according to some embodiments of the present invention. In some embodiments, the timing diagram 800 may represent Figure 2 Reset logic 204 / 205, Figure 3 304, Figure 4 404, Figure 5 504, Figure 6 602 and / or Figure 7 Specifically, the timing diagram may be used Figure 6 and 7 The signal name.

[0062] The different segments of the timing diagram 800 show signals that can be used by the reset logic, as well as input data A and output data B and a combined clock signal WT_k01. Except for data A and B, the signals are represented as idealized binary signals having a low logic level (e.g., an inactive state) and a high logic level (e.g., a valid state).

[0063] At the initial time t0, the second write clock WT_k1 rises to the active level. The signal RAS_k1 may have risen to the active level at a time before the initial time t0 and may remain at the active level at time t0. Since both the signals RAS_k1 and WT_k1 are at the active level, the first flip-flop circuit (e.g., Figure 6640) may switch to provide signal RSTF_k1 at an active level. At an initial time t0, both signals associated with the first memory bank (RAS_k0 and WT_k0) may be inactive, and therefore signal RSTF_k0 may also be inactive. Therefore, at the initial time t0, since RSTF_k0 is inactive but RSTF_k01 is active, the combined reset signal RST_k01 may switch from active to inactive. Since one of the clock signals (WT_k1) is active, the combined clock signal WT_k01 may become active at time t0, which may cause the local latch to latch the value of signal A and provide the latched value as signal B. Since the example of timing diagram 800 is for a write operation, the local latch may receive information A from the global DQ bus and provide it as signal B to the active memory bank (which is the second memory bank at t1).

[0064] At some point after time t0 (but before the first time t1), signal RAS_k1 may fall from an active state to an inactive state. The transition of RAS_k1 from an active state to an inactive state may act as a reset signal (e.g., the activation of Rst1). This may cause signal RSTF_k1 to also fall to an inactive state, which in turn causes combined reset signal RST_k01 to rise to an active level. This may cause the local latch to reset, thereby losing the previously saved value of signal A. Between times t0 and t1, signal RAS_k0 may rise to an active level, but since clock WT_k0 is not activated until time t1, changes in RAS_k0 before time t1 do not affect the value of signal RSTF_k0.

[0065] At time t1, clock signal WT_k0 becomes active. Since signal RAS_k0 is already active, this may cause inverted reset signal RSTF_k0 to become active. Since one of the inverted reset signals is active, the combined reset signal may become inactive. Since one of the clocks is active (WT_k0), the combined clock WT_k01 may become active. As a result, the local latch may latch the new value of signal A and provide the new stored value as signal B. In this case, since clock signal WT_k0 is associated with the first memory bank (e.g., memory bank 0), the local latch may provide the value to the first memory bank.

[0066] At a second time t2, signal RAS_k0 may fall to an inactive level. The falling edge of RAS_k0 may act as activation of a reset signal (e.g., Rst0). The falling edge of RAS_k0 may cause the inverted reset signal RSTF_k0 to fall to an inactive level. Since both inverted reset signals RSTF_k0 and RSTF_k1 are inactive at t2, reset signal RST_k01 may become active. Signal RSTF_k0 becoming active may cause the local latch to reset.

[0067] At a third time, t3, clock signal WT_k1 may become active. Since signal RAS_k1 is active at time t3, signal RSTF_k1 may rise to an active level. The active RSTF_k1 signal may in turn cause combined reset signal RST_k01 to become inactive again. In this way, even though the time between t2 and t3 is relatively short, RST_k01 is properly activated and completes when clock WT_k1 becomes active at t3.

[0068] Of course, it should be understood that any of the examples, embodiments, or processes described herein may be combined with one or more other examples, embodiments, and / or processes, or separated and / or performed in a separate device or device portion according to the present systems, devices, and methods.

[0069] Finally, the above discussion is intended to be merely illustrative of the present system and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Therefore, while the present system has been described in detail with reference to exemplary embodiments, it should be understood that numerous modifications and alternative embodiments may be devised by those skilled in the art without departing from the broader and intended spirit and scope of the present system as subsequently set forth in the claims. Accordingly, the specification and drawings should be viewed in an illustrative manner and are not intended to limit the scope of the appended claims.

Claims

1. A device comprising: a latch circuit configured to store data associated with the first memory bank or the second memory bank and configured to reset the data in response to a combined reset signal; and A reset logic circuit is configured to receive a first clock signal and a first reset signal associated with the first memory storage body and a second clock signal and a second reset signal associated with the second memory storage body, and is configured to provide the combined reset signal based on the first reset signal and the second reset signal, wherein the combined reset signal is invalid when the first clock signal or the second clock signal is valid.

2. The apparatus of claim 1, wherein the first clock signal is associated with access operations in the first memory bank, and the second clock signal is associated with access operations in the second memory bank.

3. The apparatus of claim 1, wherein the first reset signal is a falling edge of a first access signal associated with the first memory bank, and the second reset signal is a falling edge of a second access signal associated with the second memory bank.

4. The apparatus of claim 1 , wherein the reset logic comprises: a first latch configured to receive the first reset signal and the first clock signal and provide a first inverted reset signal; a second latch circuit configured to receive the second reset signal and the second clock signal and provide a second inverted reset signal; and A logic circuit is configured to provide the combined reset signal at an active level when both the first inverted reset signal and the second inverted reset signal are inactive. 5 . The apparatus of claim 1 , wherein the reset logic is configured to set the combined reset signal to an inactive level in response to a rising edge of the first clock signal or the second clock signal.

6. The apparatus of claim 1, wherein the local latch is configured to store the data in response to the first clock signal or the second clock signal.

7. The apparatus of claim 1, wherein the local latch is a write local latch configured to receive data from a global data bus and provide the received data to the first memory bank or the second memory bank.

8. A method comprising: storing stored data in the local latch in response to the first clock signal or the second clock signal at an active level, wherein the stored data is associated with the first memory bank or the second memory bank; resetting the stored data in response to a combined reset signal at an active level; providing the combined reset signal at an active level based on activation of a first reset signal associated with the first memory bank and a second reset signal associated with the second memory bank; and When the first clock signal or the second clock signal rises to the active level, the combined reset signal is deactivated.

9. The method according to claim 8, further comprising: accessing the first memory bank based on a first access signal and the first clock signal, wherein the first reset signal is a falling edge of the first access signal; as well as The second memory bank is accessed based on a second access signal and the second clock signal, wherein the second reset signal is a falling edge of the second access signal.

10. The method of claim 8, further comprising storing write data in the local latch, and writing the stored write data to the first memory bank or the second memory bank.

11. The method of claim 8, further comprising storing read data from the first memory bank or the second memory bank within the local latch and providing the stored read data to a global data bus.

12. The method according to claim 8, further comprising: providing a first inverted reset signal having a level based on the first reset signal and the first clock signal; providing a second inverted reset signal having a level based on the second reset signal and the second clock signal; as well as The combined reset signal at the active level is provided when both the first inverted reset signal and the second inverted reset signal are at an inactive level.

13. The method according to claim 12, further comprising: When the first clock signal rises to an effective level, providing the first inverted reset signal at an effective level; as well as When the second clock signal rises to an active level, the second inverted reset signal at an active level is provided.

14. A device comprising: a first latch circuit configured to receive a first access signal and a first clock signal and provide a first inverted reset signal based on the first access signal and the first clock signal, wherein the first inverted reset signal is at an active level when the first clock signal is active; a second latch circuit configured to receive a second access signal and a second clock signal and to provide a second inverted reset signal based on the second access signal and the second clock signal, wherein the second inverted reset signal is at an active level when the second clock signal is active; and a logic circuit configured to provide a combined reset signal at an active level when both the first inverted reset signal and the second inverted reset signal are at an inactive level; and A local latch is configured to store data and reset the stored data in response to the combined reset signal at the active level.

15. The apparatus of claim 14, wherein the first access signal and the first clock signal are associated with access operations in a first memory bank, and the second access signal and the second clock signal are associated with access operations in a second memory bank.

16. The apparatus of claim 15, wherein the stored data in the local latch is associated with the first memory bank or the second memory bank.

17. The apparatus of claim 14, wherein the first latch circuit and the second latch circuit are flip-flop circuits.

18. The apparatus of claim 14, wherein a falling edge of the first access signal represents a first reset signal, and wherein a falling edge of the second access signal represents a second reset signal.

19. The apparatus of claim 14 , wherein the first latch circuit is further configured to provide the first inverted reset signal at the active level when both the first access signal and the first clock signal are active, and to provide the first inverted reset signal at the inactive level when the first access signal falls to the inactive level; The second latch circuit is further configured to provide the second inverted reset signal at the active level when both the second access signal and the second clock signal are active, and to provide the second inverted reset signal at the inactive level when the second access signal falls to the inactive level.

20. The apparatus of claim 14, wherein the combined reset signal becomes inactive when the first clock signal or the second clock signal becomes active.

Images