Verification method and verification device for randomization effect of flash memory device, and storage medium

Abstract

The application provides a verification method and verification device for randomization effect of a flash memory device, and a storage medium. The method generates a sequence for verifying the randomization effect by splicing or stacking real data subjected to randomization in any direction such as a word line, a bit line and a diagonal line, calculates a first error and / or a second error between a proportion of a number of each type of data state in the sequence and an ideal proportion as a verification value for measuring the randomization effect in the selected direction, and finally determines whether it is qualified or not according to a preset threshold. The application realizes accurate evaluation of the randomization effect of the flash memory through multi-dimensional data sequence construction (word line, bit line and diagonal line direction) and a dynamic threshold adaptation mechanism, the quantitative index can accurately measure the randomization degree, and the objectivity of the result is enhanced. Meanwhile, a state type-proportion mapping model is introduced, which can adaptively meet the verification requirements of different types of storage densities, and is more universal.

Description

Technical Field

[0001] This application relates to the field of storage technology, specifically to a method and apparatus for verifying the randomization effect of flash memory devices, and a storage medium. Background Technology

[0002] Data randomization in flash memory devices is a key means of ensuring data security and device reliability. By disrupting the original data arrangement pattern and distributing it in a disordered yet uniform manner across storage cells, it effectively resists attackers from stealing and tampering with information using data residues, write patterns, and other characteristics, thereby improving data security and protecting user privacy and critical information. Furthermore, it avoids frequent localized erases and writes caused by concentrated data writing to the same area, reducing uneven wear and tear on storage cells, extending device lifespan, and ensuring long-term stable and reliable operation of flash memory devices.

[0003] When data randomization is ineffective, data may exhibit obvious clustering or regular distribution in storage units, leading to security vulnerabilities. Data information may be easily cracked, stolen, or tampered with, seriously threatening user privacy and data security. At the same time, if data is concentrated in specific areas, these areas will be frequently erased and rewritten, accelerating the aging and wear of storage units. This not only significantly shortens the lifespan of the device but may also cause data loss or storage failure due to local damage, resulting in data loss and inconvenience for users.

[0004] Therefore, testing and verifying the randomization effect of flash memory device controllers is essential. Current randomization effect testing methods employ error correction codes to encode randomized data and write it into flash memory, then read and decode this data, indirectly reflecting the randomization effect based on the number of errors generated during the error correction process. This method makes it difficult to directly observe the actual effect of randomization and understand the proportion of memory cell state distribution. Summary of the Invention

[0005] This application provides a method, apparatus, and storage medium for verifying the randomization effect of flash memory devices, which can solve the technical problems that the data randomization effect of existing flash memory devices cannot be directly observed and the proportion of storage cell state distribution cannot be accurately understood.

[0006] In a first aspect, embodiments of this application provide a method for verifying the randomization effect of a flash memory device. The flash memory device includes multiple memory cells arranged in an array. The memory cells are connected horizontally via word lines and vertically via bit lines. Each memory cell has at least two types of data states. The verification method includes:

[0007] Obtain random data after randomization processing by the flash memory controller;

[0008] In any selected direction, the random data is sequentially spliced, stacked, or interleaved in units of storage cells to generate a first sequence; wherein, the selected direction includes word line extension direction, bit line extension direction, and diagonal direction that forms a 45° angle with both word line extension direction and bit line extension direction;

[0009] Using storage cells as units, calculate the first error between the proportion of each type of data state in the first sequence and the ideal proportion, and use it as the first verification value for the first selected direction; wherein, the ideal proportion is determined by the type of the flash memory device and / or the number of data state types in each storage cell;

[0010] When the verification value meets the preset threshold condition, the randomization effect of the flash memory device is deemed qualified.

[0011] In some embodiments, the method for verifying the randomization effect of flash memory devices further includes:

[0012] In the unselected direction, at least one direction is selected to sequentially splice or stack the random data in units of storage cells to generate at least one second sequence;

[0013] Using storage units as the unit, calculate the second error between the proportion of each type of data state in the at least one second sequence and the ideal proportion;

[0014] Construct a total error calculation function with the first error and at least one second error as variables, and use the obtained total error value as a second verification value for at least one second selected direction;

[0015] When the second verification value meets the preset threshold condition, the randomization effect of the flash memory device is determined to be qualified.

[0016] In some embodiments, calculating the first error between the proportion of each type of data state in the first sequence and the ideal proportion, on a storage unit basis, includes:

[0017] Set a first sliding window, slide the first sliding window on the first sequence, and count the number of data states of each type in the first sliding window after each slide;

[0018] Calculate the standard deviation between the number of each type of data state and the ideal proportion within the first sliding window after each sliding action;

[0019] The average of the standard deviations calculated after each slide is used as the first error.

[0020] In some embodiments, calculating the second error between the proportion of each type of data state in the at least one second sequence and the ideal proportion, on a storage unit basis, includes:

[0021] Set a second sliding window, slide the second sliding window on the second sequence, and count the number of data states of each type in the second sliding window after each slide;

[0022] Calculate the standard deviation between the number of each type of data state and the ideal proportion within the second sliding window after each sliding;

[0023] The average of the standard deviations calculated after each slide is used as the second error.

[0024] In some embodiments, when the storage unit has only two types of data states, the first error between calculating the proportion of each type of data state in the first sequence and the ideal proportion, on a storage unit basis, includes:

[0025] Calculate the difference between the proportion of each of the two types of data states in the first sequence and the ideal proportion;

[0026] Set a third sliding window, slide the third sliding window on the first sequence, and count the number of the two types of data states in the third sliding window after each slide;

[0027] Calculate the percentage of times that the number of any type of data state does not fall within the first preset range;

[0028] An error calculation function is constructed with the difference between the proportion of the number of the two types of data states in the first sequence and the ideal proportion, and the proportion of the number of times the number of the data states of any type does not fall within a first preset range as variables, and the calculated error value is used as the first error.

[0029] In some embodiments, calculating the second error between the proportion of each type of data state in the at least one second sequence and the ideal proportion, on a storage unit basis, includes:

[0030] Calculate the difference between the proportion of the two types of data states in the second sequence and the ideal proportion;

[0031] Set a fourth sliding window, slide the fourth sliding window on the second sequence, and count the number of the two types of data states in the fourth sliding window after each slide;

[0032] Calculate the percentage of times that the number of any type of data state does not fall within the second preset range;

[0033] An error calculation function is constructed with the difference between the proportion of the two types of data states in the second sequence and the ideal proportion, and the proportion of the number of times the number of the data states of any type does not fall within the second preset range as variables, and the calculated error value is used as the second error.

[0034] In some embodiments, the first preset range is determined based on the width of the third sliding window; the second preset range is determined based on the width of the fourth sliding window.

[0035] In some embodiments, when the storage cells of the flash memory device are arranged in a three-dimensional array, the sequential splicing, stacking, or interleaving of the random data on a storage cell basis includes:

[0036] The random data corresponding to the storage cells are stacked in the word line direction with priority to the storage layer; the random data corresponding to the storage cells in the same column are stacked in the storage layer direction with priority to the bit line direction; and the random data corresponding to the storage cells are stacked in the word line direction or bit line direction with priority to the control diagonal.

[0037] Secondly, embodiments of this application provide a verification apparatus for the randomization effect of a flash memory device, comprising at least a memory and a processor; the memory is used to store programs or instructions executed by a computer, and the processor is used to execute the computer-executed programs or instructions to implement the verification method for the randomization effect of a flash memory device as described in any embodiment of the first aspect.

[0038] Thirdly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement a method for verifying the randomization effect of a flash memory device as described in any embodiment of the first aspect.

[0039] The present application provides a method and apparatus for verifying the randomization effect of flash memory devices. The method generates a sequence for verifying the randomization effect by splicing or stacking randomized real data in any direction, such as word lines, bit lines, and diagonals. Using storage cells as units, it calculates a first error and / or a second error between the proportion of each type of data state in the sequence and the ideal proportion, using this as a verification value to measure the randomization effect in the selected direction. Finally, it determines whether the result is qualified based on a preset threshold. This application achieves accurate evaluation of flash memory randomization effect through multi-dimensional data sequence construction (word lines, bit lines, and diagonals) and a dynamic threshold adaptation mechanism. The quantitative indicators can accurately measure the degree of randomization, enhancing the objectivity of the results. Simultaneously, it introduces a state type-proportion mapping model, which can adapt to the verification needs of different types of storage densities, making it more universal.

[0040] In addition, this application also provides a computer-readable storage medium, a computer program product, and a chip that have the same beneficial effects as the verification method with randomization effect described above. Attached Figure Description

[0041] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0042] Figure 1 A flowchart illustrating a method for verifying the randomization effect of a flash memory device according to an embodiment of this application;

[0043] Figure 2 A flowchart illustrating a method for verifying the randomization effect of a flash memory device according to another embodiment of this application;

[0044] Figure 3 A flowchart illustrating a method for verifying the randomization effect of a flash memory device according to another embodiment of this application;

[0045] Figure 4 A flowchart illustrating a method for verifying the randomization effect of a flash memory device according to another embodiment of this application;

[0046] Figure 5 This is a schematic diagram of the basic structure of a TLC flash memory device provided in one embodiment of this application;

[0047] Figure 6 This is a schematic diagram illustrating eight states of each storage cell in a TLC flash memory device according to an embodiment of this application.

[0048] Figure 7a This is a schematic diagram of randomized data spliced ​​in the word line extension direction of a TLC flash memory device provided in an embodiment of this application; Figure 7b This is a schematic diagram of randomized data spliced ​​in the bit line extension direction of a TLC flash memory device provided in an embodiment of this application; Figure 7c and Figure 7d This is a schematic diagram illustrating the diagonal splicing of randomized data in two embodiments of the TLC flash memory device provided in this application.

[0049] Figure 8 A flowchart illustrating a method for verifying the randomization effect of a flash memory device according to another embodiment of this application;

[0050] Figure 9 A flowchart illustrating a method for verifying the randomization effect of a flash memory device according to another embodiment of this application;

[0051] Figure 10 A schematic diagram illustrating the use of sliding window statistics in one embodiment of this application;

[0052] Figure 11 This is a schematic diagram of the structure of a device for verifying the randomization effect of a flash memory device according to an embodiment of this application.

[0053] The accompanying drawings have illustrated specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to specific embodiments. Detailed Implementation

[0054] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. Similar elements in different embodiments are referred to by related similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of the present application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to the present application are not shown or described in the specification. This is to avoid obscuring the core parts of the present application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0055] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0056] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class, without limiting the number of objects; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship. Unless otherwise specified, the terms "connection" and "linkage" used in this application include both direct and indirect connections (linkages).

[0057] For flash memory devices, the basic structure is an array of storage cells arranged in rows and columns to form a grid-like storage matrix. In terms of connectivity, horizontally, word lines connect storage cells in the same row for row selection; vertically, bit lines connect storage cells in the same column for column selection. The intersection of word lines and bit lines allows for precise access to specific storage cells. Each storage cell has at least two data states (such as "0" and "1" in binary, or multiple voltage states in multi-level cells). By changing or detecting these data states, information is stored and retrieved, ultimately forming the basic storage architecture of the flash memory device.

[0058] Currently, common flash memory devices can be categorized into five types based on the technical characteristics of their storage cells: SLC, MLC, TLC, QLC, and PLC. The core differences lie in the number of voltage states and storage density of each cell. SLC (Single-Level Cell) stores 1 bit of data using 2 voltage states, offering high speed and durability. MLC (Second-Level Cell) stores 2 bits using 4 voltage states, achieving a balance between performance and cost. TLC (Third-Level Cell) uses 8 voltage states to store 3 bits, becoming the mainstream in the consumer market. QLC (Fourth-Level Cell) stores 4 bits using 16 voltage states, suitable for high-capacity storage. And PLC (Fifth-Level Cell), currently in the experimental stage, uses 32 voltage states to store 5 bits.

[0059] As the number of bits per cell in flash memory devices increases, storage density rises exponentially, raising the requirements for the randomization performance of flash memory device controllers. Higher storage density means that a single storage cell needs to accurately distinguish more states, dramatically increasing the complexity of data distribution. Randomization algorithms must ensure that different data states are evenly distributed in the storage medium to avoid localized wear or increased data recovery risks due to state clustering. Multi-bit cells are significantly more sensitive to noise and interference, requiring randomization to further enhance its resistance to minor errors during write / read operations to prevent data errors caused by state confusion. This poses a greater challenge to the balance, robustness, and lightweight design of randomization algorithms.

[0060] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0061] Figure 1 This is a flowchart illustrating a method for verifying the randomization effect of a flash memory device according to an embodiment of this application. Figure 1As shown, the method for verifying the randomization effect of flash memory devices provided in this embodiment is applied to verifying the effect of randomizing data in flash memory devices. The verification process is based on the characteristics of data storage in flash memory devices. The method for verifying the randomization effect specifically includes the following steps:

[0062] Step S110: Obtain random data after randomization processing by the flash memory controller.

[0063] As the core control component of flash memory devices, the flash memory controller plays a crucial role in randomizing the written data. This randomization enhances the data's resilience against interference and prevents errors caused by specific patterns during storage. To verify the effectiveness of randomization, it is first necessary to obtain the randomized data from the flash memory controller. The acquisition process must ensure the integrity and accuracy of the data.

[0064] In some embodiments, the flash memory controller can be communicated through a specific programming interface or debugging tool to read randomized data from the controller's internal data buffer or related storage area according to predetermined protocols and instructions, and store it in a suitable storage medium for further processing and analysis.

[0065] Step S120: In any selected direction, random data is sequentially spliced, stacked, or interleaved in units of storage cells to generate a first sequence; wherein, the selected direction includes word line extension direction, bit line extension direction, and diagonal direction that forms a 45° angle with both word line extension direction and bit line extension direction.

[0066] Data in flash memory devices is distributed across numerous storage cells, which have physical layout characteristics in different directions such as word lines, bit lines, and diagonals. Directly performing randomization verification on the scattered data in these storage cells is not conducive to verifying the randomization effect due to the data being too fragmented. It is impossible to determine whether the randomization process has truly achieved a uniform random distribution of data in all directions. Therefore, before verification, all the data is concatenated together to form a complete and coherent data sequence, which allows for a unified overall perspective.

[0067] From a resource-saving perspective, when verifying the randomization effect, it is advisable to prioritize evaluating the randomization effect in at least one direction. This allows for a focus on the data characteristics in that direction, avoiding resource dispersion and waste caused by processing data from multiple directions simultaneously, and improving evaluation efficiency. If the verification results in the selected direction meet expectations, it indicates that the randomization algorithm performs well in that direction, reflecting its strong effectiveness and reliability. Conversely, single-direction evaluation can quickly focus on the data characteristics in that direction. If the randomization effect in this direction is poor, the problem can be quickly located, allowing for timely investigation into whether it is caused by algorithm defects, hardware failures, or other factors. This also effectively saves resources and avoids discovering problems only after all verifications have been completed.

[0068] In this embodiment, the selected directions include the word line extension direction, the bit line extension direction, and the diagonal direction forming a 45° angle with both the word line extension direction and the bit line extension direction. Data is sequentially concatenated, stacked, or interleaved according to the selected word line extension direction, bit line extension direction, and diagonal direction to generate a first sequence for analysis. Sequential concatenation connects data from adjacent storage units sequentially, specifically referring to merging data in the word line extension direction; stacking superimposes data from multiple storage units in the bit line extension direction, specifically referring to merging data in the bit line extension direction; interleaving concatenation combines data from different storage units in an alternating manner according to certain rules, specifically referring to merging data in the diagonal direction.

[0069] The aim is to clearly observe the distribution of random data in different directions through this method, accurately calculate the error between the proportion of each type of data state and the ideal proportion, provide a reliable basis for accurately determining whether the randomization effect of the flash memory device is qualified, and ensure the accuracy and effectiveness of the randomization verification results.

[0070] In some embodiments, the storage cells of the flash memory device are arranged in a three-dimensional array. Then, the random data is sequentially spliced, stacked, or interleaved in units of storage cells. This can be achieved by stacking the random data corresponding to the storage cells in the word line direction with priority to the storage layer, stacking the random data corresponding to the storage cells in the same column with priority to the storage layer direction with priority to the bit line direction, or stacking the random data corresponding to the storage cells in the word line direction or bit line direction with priority to the control diagonal.

[0071] Step S130: Calculate the first error between the proportion of each type of data state in the first sequence and the ideal proportion, taking storage cells as the unit, as the first verification value for the first selected direction; wherein, the ideal proportion is determined by the type of flash memory device and / or the number of data state types in each storage cell.

[0072] In flash memory devices, each storage cell can store multiple different types of data states. For example, in multi-level cell (MLC) flash memory, one cell can store 2 bits of data, corresponding to 4 different states; in three-level cell (TLC) flash memory, one cell can store 3 bits of data, corresponding to 8 different states. Ideally, the proportion of each type of data state appearing in the first sequence should be even. This ideal proportion can be determined based on the type of flash memory device and the number of data state types per storage cell. In other words, SLC (Single-order unit) stores 1 bit of data in 2 voltage states, namely 0 and 1. Ideally, the proportion of each type of data state appearing in the first sequence should be 50%. MLC (Second-order unit) stores 2 bits in 4 voltage states. In binary, 2 bits of data can have 2² = 4 different combinations, namely 00, 01, 10 and 11. Ideally, the proportion of each type of data state appearing in the first sequence should be 25%. TLC (Third-order unit) uses 8 voltage states to store 3 bits. 3 bits of data can be represented as 8 different combinations from 000 to 111, which are mapped to the corresponding voltage states, namely 000, 001, 010, 011, 100, 101, 110 and 111.

[0073] In this embodiment, the actual quantity of each type of data state in the first sequence is counted on a storage unit basis, and its proportion is calculated. Then, the actual proportion is compared with the ideal proportion, and the error between the two is calculated. This error is the first verification value for the first selected direction. The first verification value can intuitively reflect the degree of randomization of random data in the first selected direction. The smaller the error, the better the randomization effect.

[0074] Step S140: When the verification value meets the preset threshold condition, the randomization effect of the flash memory device is determined to be qualified.

[0075] After calculating the first verification value in the first selected direction, the verification value is compared with a preset threshold condition. If the first verification value is less than or equal to the preset threshold, it means that the randomization degree of the random data in the first selected direction has met the expected requirements, that is, the randomization effect in that direction is qualified.

[0076] In some embodiments, the calculated verification value can also be used as a basis for the grading, optimization and quality control of flash memory devices. For example, flash memory devices with a verification value of less than 0.1% can be graded as superior products; those with a verification value of 0.1% to 0.5% can be graded as first-class products.

[0077] In summary, the flash memory device randomization effect verification method provided in this embodiment generates a sequence for verifying the randomization effect by splicing or stacking randomized real data in any direction such as word lines, bit lines, and diagonals. Using storage cells as units, the method calculates the first error and / or second error between the proportion of each type of data state in the sequence and the ideal proportion, serving as a verification value to measure the randomization effect in the selected direction. Finally, it determines whether the result is qualified based on a preset threshold. This application achieves accurate evaluation of flash memory randomization effect through multi-dimensional data sequence construction (word lines, bit lines, and diagonals) and a dynamic threshold adaptation mechanism. The quantitative indicators can accurately measure the degree of randomization, enhancing the objectivity of the results. Simultaneously, the introduction of a state type-proportion mapping model can adapt to the verification needs of different types of storage densities, making it more universal.

[0078] Furthermore, even if the verification results of randomization in a single direction meet expectations, there are still certain limitations. Ignoring the impact of data distribution in other directions on the overall randomization cannot fully and accurately reflect the actual effectiveness of randomization in the spatial layout of storage cells. This may still lead to misjudgments of the randomization effect. Even if the verification is successful in one direction, there may still be problems such as uneven data distribution in other directions, which will affect the reliability and stability of data storage in flash memory devices and reduce the overall performance of the device.

[0079] Therefore, if the verification result in a single direction does not meet the preset threshold condition, or even if the verification in a single direction meets the preset threshold condition, but there are higher requirements for the randomization effect of the flash memory device, the randomization effect in other directions can be verified simultaneously or sequentially.

[0080] Figure 2 A flowchart illustrating a method for verifying the randomization effect of a flash memory device according to another embodiment of this application. Figure 2 As shown, the method for verifying the randomization effect of flash memory devices provided in this embodiment, based on any of the above embodiments, further includes the following steps:

[0081] Step S150: In the unselected direction, select at least one direction to sequentially splice or stack random data in storage units to generate at least one second sequence.

[0082] Flash memory devices exhibit multidimensional data storage characteristics, with data distribution in different directions being interconnected and significantly impacting the overall randomization effect. After completing data merging and verification in the initially selected direction (such as the word line extension direction), further verification work needs to be carried out in unselected directions to more comprehensively and deeply evaluate the randomization effect of flash memory devices. Similarly, in unselected directions (such as the bit line extension direction and diagonal directions forming a 45° angle with both the word line extension direction and the bit line extension direction), at least one direction is selected. Using memory cells as the basic unit, random data is recombined in a sequential splicing or stacking manner to generate at least one second sequence. This allows for the acquisition of data distribution information from different dimensions, avoiding verification result bias caused by considering only a single direction.

[0083] Step S160: Calculate the second error between the proportion of each type of data state in at least one second sequence and the ideal proportion, using storage units as the unit.

[0084] Similar to the above, after generating the second sequence, the number and proportion of each type of data state appearing in at least one second sequence are compared. Then, the calculated proportion is compared with the ideal proportion, and a second error is calculated between the two to reflect the deviation between the actual distribution and the ideal distribution of random data in that direction.

[0085] Step S170: Construct a total error calculation function with the first error and at least one second error as variables, and use the calculated total error value as a second verification value for at least one second selected direction.

[0086] To comprehensively consider the randomization effect in different directions, after calculating the first error (the error calculated in the initially selected direction) and the second error for measuring the randomization effect in at least two directions, these errors are used as variables. By reasonably designing the calculation method of the function and / or weighting, the errors in different directions are integrated to calculate a total error value. The total error value can more comprehensively reflect the randomization effect of the flash memory device in multiple directions. It serves as a verification value for measuring the randomization effect in at least two selected directions, providing a more comprehensive and accurate basis for the final randomization effect judgment and reducing the one-sidedness that may arise from considering the error in only one direction.

[0087] Step S180: When the second verification value meets the preset threshold condition, the randomization effect of the flash memory device is determined to be qualified.

[0088] After obtaining the second verification value (total error value), it is further judged according to the preset threshold conditions. When the second verification value meets the preset threshold conditions, it means that the deviation of the random data distribution of the flash memory device from the ideal distribution in multiple directions is within an acceptable range, the randomization effect has reached the expected standard, and therefore the randomization effect of the flash memory device can be judged to be qualified.

[0089] Figure 3 A flowchart illustrating a method for verifying the randomization effect of a flash memory device according to another embodiment of this application. Figure 3 As shown, in any of the above embodiments, step S130, calculating the first error between the proportion of each type of data state in the first sequence and the ideal proportion, using storage units as units, as the first verification value for the first selected direction, specifically includes the following steps:

[0090] Step S310: Set a first sliding window, slide the first sliding window on the first sequence, and count the number of data states of each type in the first sliding window after each slide.

[0091] When calculating the number of data states of each type in the first sequence, a sliding window technique was used to conduct a detailed analysis of the data from a dynamic and local perspective. By sliding the window across the data sequence, different positions can be examined segment by segment, controlling the precision of the statistics. The size of the first sliding window can be determined according to the required accuracy of the randomization effect in practice.

[0092] To count the number of each type of data state within the first sliding window after each slide, the first sliding window is placed at the beginning of the first sequence, at which point the window covers a portion of the data in the first sequence. Then, the window is gradually slid across the first sequence according to a predetermined sliding step size (the step size also needs to be determined based on the actual situation, as it determines the precision of the window movement). After each slide, the window will cover a new data segment on the first sequence, at which point the number of each type of data state within the window is counted. For example, in TLC flash memory, to count the number of data states representing 8 different binary combinations such as 000, 001, and 010 appearing within the window, the data distribution of the first sequence in different local areas can be obtained in this way.

[0093] Compared to simply counting the number of each type of data state in the first sequence, using a sliding window to count the data distribution in the sequence can capture the differences in data distribution in different segments in detail. It can discover local clustering, dispersion and other patterns, and can also observe the trend of data distribution changes with location, providing more comprehensive, detailed and valuable information for accurately evaluating the effects of randomization.

[0094] Step S320: Calculate the standard deviation between the number of each type of data state and the ideal proportion in the first sliding window after each sliding.

[0095] After counting the number of each type of data state within the first sliding window after each slide, the standard deviation between the number of each type of data state within the first sliding window after each slide and the ideal proportion is calculated. This reflects the degree of deviation between the actual distribution of data states within the window and the ideal distribution. If the standard deviation is large, it indicates that the data distribution within the window is relatively dispersed and differs significantly from the ideal distribution; conversely, if the standard deviation is small, it indicates that the data distribution within the window is relatively concentrated and closer to the ideal distribution.

[0096] Step S330: Calculate the average of the standard deviations calculated after each sliding motion, and use it as the first error.

[0097] After obtaining the standard deviation between the number of data states of each type and the ideal proportion within the first sliding window after each slide, in order to more comprehensively and holistically evaluate the overall randomization effect of the first sequence, the average of these standard deviations is calculated as the first error, which can more accurately reflect the randomization effect of the entire first sequence.

[0098] Figure 4 A flowchart illustrating a method for verifying the randomization effect of a flash memory device according to another embodiment of this application. Figure 4 As shown, for any of the above embodiments, step S160, calculating the second error between the proportion of each type of data state in at least one second sequence and the ideal proportion, on a storage unit basis, specifically includes the following steps:

[0099] Step S410: Set a second sliding window, slide the second sliding window on the second sequence, and count the number of data states of each type in the second sliding window after each slide.

[0100] Step S420: Calculate the standard deviation between the number of each type of data state and the ideal proportion in the second sliding window after each sliding.

[0101] Step S430: Calculate the average of the standard deviations calculated after each sliding motion, and use it as the second error.

[0102] Similar to steps S310-S330, which calculate the first error between the proportion of each type of data state in the first sequence and the ideal proportion, steps S410-S430 also use a combination of sliding window statistics and standard deviation calculation to calculate the second error between the proportion of each type of data state in at least one second sequence and the ideal proportion. The specific implementation process is the same as the above process, and will not be repeated here to avoid repetition.

[0103] After calculating the first and second errors in at least two directions to measure the randomization effect using the above method, and then combining a reasonable function calculation method and / or further weight allocation, the errors in different directions are integrated to calculate a total error value, which serves as the basis for the final verification of the randomization effect.

[0104] The verification method described above will be explained in detail below using a TLC (triple-cell) flash memory device as an example.

[0105] Figure 5 This is a schematic diagram of the basic structure of a TLC flash memory device provided in one embodiment of this application. Figure 6 Figure 7 is a schematic diagram illustrating eight states for each storage cell in a TLC flash memory device provided in one embodiment of this application. Figure 8 is a schematic diagram illustrating randomized data spliced ​​in different directions in a TLC flash memory device provided in one embodiment of this application.

[0106] Combination Figure 5 and Figure 6 For TLC flash memory devices, the effect of flash randomization is evaluated by taking the storage cell as the basic unit. Theoretically, after randomization, the ideal proportion of each type of data state x0~0x7 should be 12.5%.

[0107] The randomization effect of this TLC flash memory device was verified using the above method:

[0108] First, the data of the storage units are sequentially concatenated along the word line extension direction (e.g., ...). Figure 7a As shown), the data of the stacked memory cells in the bit line extension direction (such as...) Figure 7b As shown), the data in the storage unit is interwoven and spliced ​​using a diagonal method (such as...). Figure 7c and 7d (As shown in any one of the diagrams), we obtain the first sequence, the second sequence, and the third sequence.

[0109] Secondly, calculate the error between the proportion of each type of data state in the sequence and the ideal proportion in each direction.

[0110] Taking the word line extension direction as an example, a smoothing window N is set. Starting from the first storage unit, the number of {0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7} in the first N storage units is counted, and the standard deviation A0 is calculated. The smoothing window N is then moved one storage unit to the right, that is, the number of {0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7} in the second to the (N+1)th storage units is counted, and the standard deviation A1 is calculated. This process is repeated to calculate A0 to A_Max. The average value A_avg of the standard deviations A0 to A_Max is calculated, which is the first error, and is used as the verification value for the fluctuation description of the word line extension direction randomization.

[0111] Similarly, the verification value B_avg in the bit line extension direction and the verification value C_avg in the diagonal direction can be calculated.

[0112] Finally, a total error function A_avg+B_avg+C_avg is constructed as a comprehensive verification index to verify the degree of balanced error in each state, that is, a comprehensive verification index to verify the randomization effect of the TLC flash memory device. Furthermore, based on the threshold conditions that need to be set for the randomization effect of the TLC flash memory device, the degree of randomization effect of the TLC flash memory device is judged in combination with the comprehensive verification index.

[0113] Figure 8 This is a flowchart illustrating a method for verifying the randomization effect of a flash memory device according to another embodiment of this application. For storage devices with a small number of bits per storage cell, such as SLC (Single-Level Cell), where each cell has data states of 0 and 1, step S130 involves calculating, on a unit of storage cell, a first error between the proportion of each type of data state in the first sequence and the ideal proportion. Figure 8 As shown, the calculation process can also be as follows:

[0114] Step S810: Calculate the difference between the proportion of the two types of data states in the first sequence and the ideal proportion.

[0115] First, count the actual number of these two data states in the first sequence, and then calculate their respective proportions in the sequence. For a sequence with two types of data states, the ideal proportion of each type of data state in the sequence is 50%, which means calculating the difference between the proportion of each type of data state in the first sequence and 50%.

[0116] Step S820: Set a third sliding window, slide the third sliding window on the first sequence, and count the number of data states of the two types in the third sliding window after each slide.

[0117] A third sliding window is set up, and the number of data states of the two types within the third sliding window is counted after each slide. The size and sliding step of the third sliding window need to be reasonably determined based on factors such as the scale of the first sequence, data characteristics, and verification accuracy requirements. Specifically, the third sliding window is placed at the beginning of the first sequence, and the window is gradually slid across the first sequence according to a predetermined sliding step. After each slide, the window will cover a new data segment on the sequence, and the number of data states of the two types within the window is counted.

[0118] Step S830: Calculate the percentage of times when the number of any type of data state does not fall within the first preset range.

[0119] In practice, even with ideal data randomization, it cannot guarantee that the data distribution after each randomization will reach the ideal distribution. That is, for SLC flash memory, as long as the distribution ratio of one data state (0 / 1) is within 50% ± 2%, the randomization effect can be considered satisfactory. Therefore, after counting the number of both types of data states within the third sliding window after each slide, we continue to count the percentage of times the number of either type of data state within the third sliding window after each slide does not fall within the first preset range. The determination of the first preset range needs to comprehensively consider factors such as the performance requirements of the flash memory device, the ideal degree of data randomization, and the actual application scenario.

[0120] It should be noted that since there are only two types of data states, calculating the percentage of times the quantity of one type of data state does not fall within the first preset range can be done by simply calculating the proportion of times the quantity of the other type of data state does not fall within the first preset range. Similarly, calculating the percentage of times the quantity of one type of data state does fall within the first preset range can also be done by simply calculating the proportion of times the quantity of that type of data state falls within the first preset range. Therefore, in step S530, calculating the percentage of times the quantity falls within the range, either method can be arbitrarily selected.

[0121] Step S840: Construct an error calculation function with variables including the difference between the proportion of the number of two types of data states in the first sequence and the ideal proportion, and the proportion of the number of times the number of any type of data state does not fall within the first preset range, and use the calculated error value as the first error.

[0122] Finally, using the difference between the proportion of the two types of data states in the first sequence calculated in step S810 and the ideal proportion, and the proportion of the number of times the number of any type of data state did not fall within the first preset range calculated in step S830 as variables, a reasonable function that can characterize the overall distribution error of the two specific types of data states in the first sequence is constructed as an indicator parameter for measuring the balanced distribution in the selected direction.

[0123] Figure 9 This is a flowchart illustrating a method for verifying the randomization effect of a flash memory device according to another embodiment of this application. Step S160: Calculate, on a unit of storage cell, a second error between the proportion of each type of data state in at least one second sequence and the ideal proportion, such as... Figure 9 As shown, the calculation process can also be:

[0124] Step S910: Calculate the difference between the proportion of the two types of data states in the second sequence and the ideal proportion.

[0125] Step S920: Set a fourth sliding window, slide the fourth sliding window on the second sequence, and count the number of data states of the two types in the fourth sliding window after each slide.

[0126] Step S930: Calculate the percentage of times when the number of any type of data state does not fall within the second preset range.

[0127] Step S940: Construct an error calculation function with the difference between the proportion of the number of two types of data states in the second sequence and the ideal proportion, and the proportion of the number of times the number of any type of data state does not fall within the second preset range as variables, and use the calculated error value as the second error.

[0128] Similar to steps S510-S540, which calculate the first error between the proportion of each type of data state in the first sequence and the ideal proportion, steps S610-S640 also use a combination of sliding window statistics and range calculation to calculate the second error between the proportion of each type of data state in at least one second sequence and the ideal proportion. The specific implementation process is the same as the above process, and will not be repeated here to avoid repetition.

[0129] In some embodiments, the first preset range is determined based on the width of the third sliding window; the second preset range is determined based on the width of the fourth sliding window.

[0130] The verification method described above will be explained in detail below using an SLC (Single Cell) flash memory device as an example.

[0131] First, the data of the storage units are sequentially spliced ​​in the word line extension direction, the data of the storage units are stacked in the bit line extension direction, and the data of the storage units are interleaved in the diagonal method to obtain the first sequence, the second sequence, and the third sequence.

[0132] Then, the error value between the proportion of each type of data state in the sequence and the ideal proportion is calculated in each direction.

[0133] Taking the extension direction of the word line as an example, calculate the difference between the proportion of the two types of data states in the first sequence and the ideal proportion. Assuming that the proportion of 1s in the first sequence is 53% and the proportion of 0s is 47%, then the difference between the proportion of the two types of data states in the first sequence and the ideal proportion is S1 = 3%.

[0134] Figure 10 This is a schematic diagram illustrating a sliding window statistical method according to an embodiment of this application. Further, a sliding window P is defined. Starting from the first bit, the number of 0s and 1s in the first N bits is counted, with the range falling within (P / 2 - Q, P / 2 + Q). If the number of 1s in the first N bits falls within this range, the balance parameter Balance_Count is incremented by 1; otherwise, the unbalance parameter Unbalance_Count is incremented by 1. Similarly, ... Figure 10 As shown, the smoothing window P is shifted one bit to the right, that is, the number of 0s and 1s in the 2nd bit to the (P+1)th bit is counted. If the number of 1s falls within the range of (P / 2 - Q, P / 2 + Q), the balance parameter Balance_Count is increased by 1; otherwise, the unbalance parameter Unbalance_Count is increased by 1. The magnitudes of P and Q represent the required randomization precision; the larger P and Q are, the lower the required precision of the randomization.

[0135] Furthermore, the percentage of Balance_Count and Unbalance_Count can be calculated. The error can be represented by Unbalance_Count / (Balance_Count + Unbalance_Count), which is the percentage of occurrences not falling within the first preset range. For example, if the percentage of Balance_Count is 96%, then the error S2 = 4%.

[0136] Finally, an error calculation function is used as a measure of the error in the direction of word line extension, which is the difference between the proportion of the two types of data states in the first sequence and the ideal proportion, and the proportion of the number of times the number of any type of data state does not fall within the first preset range. For example, it can be S1+S2.

[0137] Similarly, the error S3+S4 in the bit line extension direction and the error S5+S6 in the diagonal direction can be calculated.

[0138] Finally, a total error function S1+S2+S3+S4+S5+S6 is constructed in three directions as a comprehensive verification index to verify the randomization effect of the SLC flash memory device. Furthermore, based on the threshold conditions that need to be set for the randomization effect of the SLC flash memory device, the degree of randomization effect of the SLC flash memory device is judged in combination with the comprehensive verification index.

[0139] Figure 11 This is a schematic diagram of the structure of a device for verifying the randomization effect of a flash memory device according to an embodiment of this application. Figure 11 As shown, the verification device for the randomization effect of the flash memory device described in this embodiment includes at least a memory 1110 and a processor 1120, which can be connected via a bus.

[0140] In this embodiment, the memory 110 is used to store computer execution instructions or commands.

[0141] The memory 1110 may include volatile memory or non-volatile memory, or the memory 910 may include both volatile and non-volatile memory. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct memory bus RAM (DRRAM).

[0142] Memory 1110 includes, but is not limited to, these and any other suitable types of memory.

[0143] In this embodiment, the processor 1120 is used to execute computer programs or instructions to implement various processes of any embodiment of the above-described method for verifying the randomization effect of flash memory devices, and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0144] The processor 1120 may be a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application.

[0145] This application also provides a readable storage medium storing a program or instructions that, when executed by a processor, implement various processes of any embodiment of the above-described verification method for the randomization effect of the flash memory device, and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0146] The processor may be a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application.

[0147] Readable storage media include computer-readable storage media such as computer read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0148] Those skilled in the art will understand that all or part of the functions of the various methods in the above embodiments can be implemented by hardware or by computer programs. When all or part of the functions in the above embodiments are implemented by computer programs, the program can be stored in a computer-readable storage medium, which may include: read-only memory, random access memory, disk, optical disk, hard disk, etc., and the program is executed by a computer to achieve the above functions. For example, the program can be stored in the memory of a device, and when the program in the memory is executed by the processor, all or part of the above functions can be achieved. In addition, when all or part of the functions in the above embodiments are implemented by computer programs, the program can also be stored in a server, another computer, disk, optical disk, flash drive, or external hard drive, etc., and can be downloaded or copied to the memory of a local device, or the system of the local device can be updated. When the program in the memory is executed by the processor, all or part of the functions in the above embodiments can be achieved.

[0149] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art, under the guidance of this application, can make several simple deductions, modifications or substitutions based on the spirit of this application and the scope of protection of the claims without departing from the spirit of this application and the claims. All of these are within the protection scope of this application.

Claims

1. A method for verifying randomization effect of a flash memory device, the flash memory device comprising a plurality of memory cells arranged in an array, the memory cells being connected by word lines in a horizontal direction and by bit lines in a vertical direction, each memory cell having at least two types of data states; the method comprising: obtaining random data processed by a flash controller; sequentially concatenating, stacking or interleaving concatenating the random data in a unit of memory cell in any selected direction to generate a first sequence, wherein the selected direction comprises a word line extension direction, a bit line extension direction and a diagonal direction which forms a 45° angle with both the word line extension direction and the bit line extension direction; calculating a first error between a proportion of a number of each type of data state in the first sequence and an ideal proportion as a first verification value of a first selected direction, wherein the ideal proportion is determined by a type of the flash memory device and / or a number of types of data states of each memory cell; determining that the randomization effect of the flash memory device is qualified when the first verification value meets a preset threshold condition; wherein calculating the first error between the proportion of the number of each type of data state in the first sequence and the ideal proportion in a unit of memory cell comprises: setting a first sliding window, sliding the first sliding window on the first sequence, and counting a number of each type of data state in the first sliding window after each sliding; calculating a standard deviation between the number of each type of data state in the first sliding window after each sliding and the ideal proportion respectively; calculating an average of the standard deviations calculated after each sliding as the first error. characterized in that The method further comprises: selecting at least one direction to sequentially concatenate or stack the random data in a unit of memory cell in a non-selected direction to generate at least one second sequence; calculating a second error between a proportion of a number of each type of data state in the at least one second sequence and an ideal proportion in a unit of memory cell; constructing a total error calculation function with the first error and the at least one second error as variables to obtain a total error value as a second verification value of at least one second selected direction; determining that the randomization effect of the flash memory device is qualified when the second verification value meets a preset threshold condition. The method further comprises: setting a second sliding window, sliding the second sliding window on the second sequence, and counting a number of each type of data state in the second sliding window after each sliding; calculating a standard deviation between the number of each type of data state in the second sliding window after each sliding and the ideal proportion respectively; calculating an average of the standard deviations calculated after each sliding as the second error. In a case where the memory cell has only two types of data states, calculating the first error between the proportion of the number of each type of data state in the first sequence and the ideal proportion in a unit of memory cell comprises: ​ ​ ​ ​ ​ ​ 2. The method of claim 1, wherein the verifying of the randomization effect of the flash memory device is performed by a host device. ​ ​ ​ ​ ​ 3. The method of claim 2, wherein the verifying of the randomization effect of the flash memory device is performed by a host device. ​ ​ ​ ​ 4. The method of claim 2, wherein the verifying of the randomization effect of the flash memory device is performed by a host device. ​ Calculate the difference between the proportion of the number of two types of data states in the first sequence and the ideal proportion; Set a third sliding window, slide the third sliding window on the first sequence, and count the number of two types of data states in the third sliding window after each sliding; Calculate the proportion of the number of any type of data state that does not fall within the first preset range; Construct an error calculation function with the difference between the proportion of the number of two types of data states in the first sequence and the ideal proportion, and the proportion of the number of any type of data state that does not fall within the first preset range as variables, and take the obtained error value as the first error.

5. The method of claim 4, wherein the verifying of the randomization effect of the flash memory device is performed by a host device. The second error between the proportion of the number of each type of data state in the at least one second sequence and the ideal proportion is calculated in units of storage units, including: Calculate the difference between the proportion of the number of two types of data states in the first sequence and the ideal proportion; Set a third sliding window, slide the third sliding window on the first sequence, and count the number of two types of data states in the third sliding window after each sliding; Calculate the proportion of the number of any type of data state that does not fall within the first preset range; Construct an error calculation function with the difference between the proportion of the number of two types of data states in the first sequence and the ideal proportion, and the proportion of the number of any type of data state that does not fall within the first preset range as variables, and take the obtained error value as the first error.

6. The method of claim 5, wherein the verifying of the randomization effect of the flash memory device is performed by a host device. The first preset range is determined according to the width of the third sliding window; the second preset range is determined according to the width of the fourth sliding window.

7. The method of claim 1-6, wherein the method is used to verify the randomization effect of a flash memory device, and the method further comprises: When the storage units of the flash memory device are arranged in a three-dimensional array, the random data is sequentially spliced, stacked or interleaved spliced in units of storage units, including: ​ At least one of the following: stacking the random data corresponding to the storage units in the word line direction first according to the storage layer, stacking the random data corresponding to the storage units in the bit line direction first according to the storage layer, and stacking the random data corresponding to the storage units in the control diagonal line direction first according to the word line direction or the bit line direction.

8. A verification device for the randomization effect of a flash memory device, characterized in that, At least including a memory and a processor; the memory is used to store computer executable programs or instructions, and the processor is used to execute the computer executable programs or instructions to realize the verification method of the randomization effect of the flash memory device as claimed in any one of claims 1 to 7.

9. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer executable instructions, and the computer executable instructions are executed by the processor to realize the verification method of the randomization effect of the flash memory device as claimed in any one of claims 1 to 7.

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