Semiconductor structure and manufacturing method thereof

Abstract

The embodiment of the invention discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes at least one die; the tube core comprises a substrate and a plurality of first bonding pads, the plurality of first bonding pads are located on the first surface of the substrate, and at least two first bonding pads are connected with each other.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] With the continuous development of electronic devices, the demand for high-performance chips with higher power density and compact packaging is growing. This trend poses a major challenge to the thermal management of chips.

[0003] Therefore, how to better dissipate heat from the chip has become a technical problem that needs to be solved urgently. Summary of the Invention

[0004] According to a first aspect of an embodiment of the present disclosure, a semiconductor structure is provided, comprising: at least one tube core; the tube core comprises a substrate and a plurality of first solder pads, the plurality of first solder pads are located on a first surface of the substrate, wherein at least two first solder pads are connected to each other.

[0005] In some embodiments, the multiple first pads include a first signal pad and a multiple first dummy pads, and the first signal pad is spaced apart from each of the first dummy pads; the tube core also includes a device layer and a connection structure; the device layer is located on the second surface of the substrate, wherein the second surface and the first surface are opposite to each other along the thickness direction of the substrate; the connection structure passes through the substrate, wherein the connection structure connects the first signal pad and the device layer respectively; the multiple first dummy pads include a first type of first dummy pads, wherein the first type of first dummy pads are connected to the connection structure.

[0006] In some embodiments, the die further includes a first guard ring located on the first surface; the plurality of first dummy pads further include a second type of first dummy pads, wherein the second type of first dummy pads are connected to the first guard ring.

[0007] In some embodiments, the die further includes a first under bump metallization layer, the first under bump metallization layer being located between the substrate and the first pads, wherein at least two of the first pads are connected to each other through the first under bump metallization layer.

[0008] In some embodiments, the die further includes a plurality of second pads located on the second surface, wherein the device layer is located between the plurality of second pads and the substrate, and at least two second pads are connected to each other.

[0009] In some embodiments, the multiple second pads include second signal pads and multiple second dummy pads, the second signal pads are spaced apart from each second dummy pad, wherein the device layer is connected to the first signal pad through the second signal pad and the connection structure; the multiple second dummy pads include a first type of second dummy pads, wherein the first type of second dummy pads is connected to the connection structure.

[0010] In some embodiments, the die further includes a second guard ring located on the second surface; the plurality of second dummy pads further include a second type of second dummy pads, wherein the second type of second dummy pads are connected to the second guard ring.

[0011] In some embodiments, the die further includes a second under bump metallization layer, the second under bump metallization layer being located between the device layer and the second pads, wherein at least two of the second pads are connected to each other through the second under bump metallization layer.

[0012] In some embodiments, the semiconductor structure includes a plurality of the dies stacked in sequence, wherein, among two adjacent dies, the first signal pad of one die is bonded to the second signal pad of the other die, and the first dummy pad of one die is bonded to the second dummy pad of the other die.

[0013] According to a second aspect of an embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising: forming at least one tube core; the steps of forming the tube core include:

[0014] providing a substrate;

[0015] A plurality of first pads are formed on the first surface of the substrate, wherein at least two first pads are connected to each other.

[0016] In some embodiments, the step of forming the die further comprises:

[0017] forming a device layer on a second surface of the substrate, wherein the second surface and the first surface are opposite to each other along a thickness direction of the substrate;

[0018] forming a connection structure penetrating the substrate, wherein the connection structure is connected to the device layer and the first surface exposes the connection structure;

[0019] The forming of a plurality of first pads on the first surface of the substrate comprises:

[0020] A first signal pad and a plurality of first dummy pads are formed on the first surface, wherein the first signal pad is spaced apart from each of the first dummy pads, wherein the first signal pad is connected to the exposed connection structure, and the plurality of first dummy pads include a first type of first dummy pad connected to the connection structure.

[0021] In some embodiments, the step of forming the die further comprises:

[0022] forming a first guard ring on the first surface;

[0023] The forming of a plurality of first dummy pads on the first surface comprises:

[0024] A second type of first dummy pad connected to the first guard ring is formed on the first surface.

[0025] In some embodiments, the step of forming the die further comprises:

[0026] A first under bump metallization layer is formed between the substrate and the first pads, wherein at least two of the first pads are connected to each other through the first under bump metallization layer.

[0027] In some embodiments, the step of forming the die further comprises:

[0028] A plurality of second pads are formed on the second surface, wherein the device layer is located between the plurality of second pads and the substrate, and at least two second pads are connected to each other.

[0029] In some embodiments, forming a plurality of second pads on the second surface includes:

[0030] A second signal pad and a plurality of second dummy pads are formed on the second surface, and the second signal pad is spaced apart from each of the second dummy pads, wherein the device layer is connected to the first signal pad through the second signal pad and the connection structure, and the plurality of second dummy pads include a first type of second dummy pad connected to the connection structure.

[0031] In some embodiments, the step of forming the die further comprises:

[0032] forming a second guard ring on the second surface;

[0033] The forming of a plurality of second dummy pads on the second surface comprises:

[0034] A second type of second dummy pad connected to the second guard ring is formed on the second surface.

[0035] In some embodiments, the step of forming the die further comprises:

[0036] A second under bump metallization layer is formed between the device layer and the second pads, wherein at least two of the second pads are connected to each other through the second under bump metallization layer.

[0037] In the disclosed embodiments, at least two first solder pads are connected to each other. Firstly, the connected first solder pads can increase the heat dissipation area of the first surface, conducting more heat, thereby improving the horizontal heat dissipation path, accelerating heat dissipation, and avoiding the formation of local hot spots. Secondly, the temperature difference between different areas within the die can be reduced, thereby reducing the impact on the die's timing and reliability. Thirdly, by optimizing the design of the first solder pads, damage to the die due to localized overheating can be avoided, which is conducive to improving the service life. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0039] Figure 1 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0040] Figure 2 is a schematic diagram of a tube die provided by an embodiment of the present disclosure;

[0041] Figure 3 A flowchart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0042] Figure 4A and Figure 4B is a schematic diagram of a manufacturing process of a semiconductor structure shown in an embodiment of the present disclosure;

[0043] Figures 5A to 5G This is a schematic diagram of a process for manufacturing a solder pad shown in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] The technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and examples. Although the accompanying drawings illustrate exemplary implementations of the present disclosure, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0045] The following paragraphs describe the present disclosure in more detail by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present disclosure.

[0046] It will be understood that the meanings of “on,” “over,” and “over” throughout this disclosure should be interpreted in the broadest manner, such that “on” not only means being “on” something with no intervening features or layers (i.e., directly on something), but also includes being “on” something with intervening features or layers.

[0047] In the embodiments of the present disclosure, the terms "first," "second," "third," etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0048] In the embodiments of the present disclosure, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is smaller than the extent of the lower or upper structure. In addition, a layer may be an area of a homogeneous or inhomogeneous continuous structure having a thickness that is smaller than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0049] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0050] As chip integration becomes increasingly complex, the distribution of heat sources within the chip plane becomes extremely uneven. This uneven heat source distribution can lead to the formation of local hotspots in the chip. For example, a local high heat source can even be four times the average heat source, which will seriously affect the performance and reliability of the chip.

[0051] However, current heat dissipation solutions are designed for average heat sources and do not consider hot spots formed by local heat dissipation power concentration, resulting in excessive temperature differences within the chip (for example, greater than 20°C), which in turn leads to chip timing failures and reliability issues.

[0052] Based on one or more of the above technical problems, an embodiment of the present disclosure provides a semiconductor structure.

[0053] Figure 1Schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure. The semiconductor structure includes at least one die, i.e., the semiconductor structure may include one die or multiple dies. In this embodiment, the semiconductor structure includes, but is not limited to, memory, and the die includes, but is not limited to, dynamic random access memory (DRAM).

[0054] As an example, see Figure 1 As shown, the semiconductor structure includes multiple stacked dies, namely die 100a, die 100b, die 100c, and die 100d. The multiple dies can be connected and integrated through three-dimensional stacking technology. For example, through silicon via (TSV) technology can be used to vertically interconnect multiple DRAM dies to form a three-dimensional stacked structure, thereby significantly improving the bandwidth and capacity of the memory.

[0055] In some embodiments, the semiconductor structure further includes a logic die 200, and multiple dies are located on the logic die 200. The logic die 200 is used to manage and control data transmission. Typically, the logic die 200 is located at the bottom of the memory stack (i.e., multiple DRAM dies), responsible for communication and data exchange with the DRAM dies, and is connected to the package substrate through an interposer to achieve efficient data transmission with processors such as a graphics processing unit (GPU) or a central processing unit (CPU). In actual applications, the logic die 200 may include components such as a cache manager, an address decoder, and a command decoder to optimize data processing and cache management.

[0056] Figure 2 This is a schematic diagram of a tube core provided by an embodiment of the present disclosure. Figure 2 The specific structure of the tube core is introduced. Figure 2 The die shown may be Figure 1 An example of any one of die 100a, die 100b, die 100b, and die 100c.

[0057] Reference Figure 2 As shown, the die 100 includes a substrate 102 and a plurality of first pads 104 . The plurality of first pads 104 are located on a first surface 102 a of the substrate 102 , wherein at least two first pads 104 are connected to each other.

[0058] The substrate 102 may be a growth and support substrate during the subsequent deposition of various material layers. In this embodiment, the substrate 102 may be a semiconductor substrate. The material of the substrate 102 includes a semiconductor material, such as a single-element semiconductor material (e.g., silicon (Si) or germanium (Ge)), a III-V compound semiconductor material (e.g., gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP)), a II-VI compound semiconductor material (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe)), an organic semiconductor material, or other semiconductor materials known in the art.

[0059] The substrate 102 may have a first surface 102a and a second surface 102b, wherein the second surface 102b and the first surface 102a are opposite to each other along the thickness direction of the substrate 102. By way of example, the first surface 102a may be one of the front side and the back side of the substrate 102, and the second surface 102b may be the other of the front side and the back side of the substrate 102. In practical applications, the front side and the back side of the substrate 102 may be determined based on the location of the active region. For example, if the active region is located on the front side of the substrate 102, the surface opposite to the front side of the substrate 102 is the back side of the substrate 102. For ease of understanding, the following description will be based on the example of the first surface 102a being the back side of the substrate 102 and the second surface 102b being the front side of the substrate 102.

[0060] The plurality of first pads 104 may be located on the back side of the substrate 102, i.e., the first pads 104 are backside pads. As an example, the first pads 104 may be bumps formed on the back side of the substrate 102. The bumps may be made of a conductive material, such as a single metal (e.g., gold, tin, copper, nickel, indium, or other metals), a metal alloy (e.g., copper-nickel-gold alloy, tin-lead alloy, or other alloys), or other conductive materials known in the art.

[0061] The first pad 104 and the second pad 118 mentioned below can be used to achieve at least one of the functions of electrical connection and signal transmission, heat conduction, reliable packaging, etc. It should be noted that the functions of the pad are not limited to these, and the pad can also have other functions known in the art, which will not be repeated here.

[0062] As an example, pads are used to implement electrical connections in stacked dies. Specifically, by bonding the pads of the stacked dies to each other, effective signal transmission and improved electrical performance can be ensured.

[0063] As an example, the pad is used to achieve heat conduction. Specifically, the pad can form part of the heat dissipation path, helping to transfer heat from the die to the external heat dissipation system, thereby improving heat dissipation efficiency.

[0064] As an example, pads are used to achieve reliable packaging. Specifically, the design and layout of pads help enhance the overall reliability of the package, especially in multi-die stacking. By reallocating pad positions to accommodate different functional requirements, connection density and reliability can be further improved.

[0065] In a semiconductor structure, a region where a local temperature rises due to factors such as current concentration and high power density forms a local hotspot. In the embodiment of the present disclosure, at least two first pads are connected to each other. In this way, on the one hand, the connected first pads can increase the heat dissipation area of the first surface and conduct more heat, thereby improving the horizontal heat dissipation path, accelerating heat dissipation, and avoiding the formation of local hotspots; on the other hand, the temperature difference between different areas inside the die can be reduced (for example, less than 5°C), thereby reducing the impact on the die timing and reliability; on the third hand, by optimizing the design of the first pad, damage to the die due to excessive local temperature can be avoided, which is conducive to improving the service life.

[0066] It should be noted that the term "connected" as used in this embodiment and below refers to the interconnected state between two or more structures, which can include both direct and indirect connections. A direct connection refers to a connection between two physical structures through physical contact, while an indirect connection refers to a connection between two physical structures that is not in direct contact but is connected through one or more intermediate media.

[0067] In some embodiments, the die 100 further includes a first under bump metallurgy layer 116 , which is located between the substrate 102 and the first pads 104 , wherein at least two first pads 104 are connected to each other through the first under bump metallurgy layer 116 .

[0068] The first under bump metallization (UBM) layer 116 may be located on the back side of the substrate 102. That is, the first under bump metallization layer 116 is a backside UBM. The material of the first under bump metallization layer 116 includes a conductive material, for example, at least one of titanium, copper, and nickel.

[0069] As an example, an initial first UBM layer can be formed covering the back side of the substrate 102. The formation process of the initial first UBM layer includes sputtering or chemical vapor deposition. Using the initial first UBM layer as a seed layer, multiple first pads 104 are formed by electroplating. Then, a portion of the initial first UBM layer exposed outside the first pads is removed, and the remaining initial first UBM layer constitutes the first UBM layer 116. In practical applications, the initial first UBM layer exposed outside at least two first pads 104 can be retained to ensure that the at least two first pads 104 are connected to each other through the first UBM layer 116. Of course, in other embodiments, the at least two first pads 104 can also be connected to each other through other conductive structures on the back side of the substrate 102, and the present disclosure has no particular limitations on this.

[0070] In the disclosed embodiments, at least two first pads are connected to each other via a first underbump metallurgy layer. This connection can be achieved simply by adjusting the design and layout of the first underbump metallurgy layer. This makes the process compatible with existing backside UBM and backside bump manufacturing processes without adding additional process steps.

[0071] In some embodiments, reference Figure 2 As shown, the plurality of first pads 104 include a first signal pad 106 and a plurality of first dummy pads 108 , and the first signal pad 106 is spaced apart from each first dummy pad 108 .

[0072] As an example, the at least two first pads 104 connected to each other include: a first signal pad 106 and at least one first dummy pad 108 connected to each other, for example, the first signal pad 106 and the at least one first dummy pad 108 are connected to each other via a first under bump metallization layer 116. In this example, the number of first dummy pads 108 connected to the first signal pad 106 can be one or more, and this disclosure has no particular limitation on this.

[0073] As an example, connecting at least two first pads 104 to each other includes: connecting at least two first dummy pads 108 to each other, for example, the at least two first dummy pads 108 are connected to each other through a first under bump metallization layer 116. In this example, the number of first dummy pads 108 connected to each other can be two or more, and this disclosure has no particular limitation on this.

[0074] In the embodiment of the present disclosure, the first pad 104 can be divided into a first signal pad 106 and a first dummy pad 108 (Dummy pad) according to the different functions of the first pad 104. The first signal pad 106 and the first dummy pad 108 are arranged alternately on the back side of the substrate 102. Among them, the first signal pad 106 is mainly used to realize the functions of electrical connection and signal transmission, and the first dummy pad 108 is mainly used for functions such as heat conduction and reliable packaging. It should be noted that the two first pads 104 used for electrical connection and signal transmission are electrically isolated from each other, that is, the two first signal pads 106 are electrically isolated from each other.

[0075] In some embodiments, the die 100 further includes a device layer 110 and a connection structure 112; the device layer 110 is located on the second surface 102b of the substrate 102; the connection structure 112 passes through the substrate 102, wherein the connection structure 112 connects the first signal pad 106 and the device layer 110 respectively; the plurality of first dummy pads 108 include a first type first dummy pad 108a, wherein the first type first dummy pad 108a is connected to the connection structure 112.

[0076] Device layer 110 may be located on the front surface of substrate 102. At least one of a peripheral circuit and a memory array may be formed in device layer 110. As an example, device layer 110 may include a gate structure and a capacitor. The gate structure and the active region on the front surface of substrate 102 constitute a transistor. The capacitor is connected to the transistor, and the transistors connected thereto constitute a memory cell. Multiple memory cells constitute a memory array. Of course, device layer 110 may also include a dielectric material to physically isolate the multiple memory cells from each other.

[0077] The connection structure 112 may include a first end and a second end disposed opposite each other along the thickness direction of the substrate 102, wherein the first end is connected to the first signal pad 106, and the second end is connected to the device layer 110. As an example, the second end of the connection structure 112 may be connected to the memory array in the device layer 110 via a pad (hereinafter referred to as the second pad 118) formed on the front surface of the substrate 102 and an interconnect structure. The connection structure 112 may be formed using the TSV technology mentioned above, and the material of the connection structure 112 includes a conductive material, for example, at least one of copper, tungsten, and polysilicon.

[0078] At least one first dummy pad 108 among the plurality of first dummy pads 108 may be connected to the connection structure 112. For example, at least one first dummy pad 108 may be connected to the connection structure 112 via a first under-bump metallization layer 116. The first dummy pad 108 connected to the connection structure 112 is a first-type first dummy pad 108a. In this embodiment, the number of first dummy pads 108 connected to the connection structure 112 may be one or more, and this disclosure does not specifically limit this.

[0079] It should be noted that the connection structure 112 is mainly used for vertical interconnection between tube cores, transmitting signals from one tube core to another tube core, so the connection structure 112 is usually connected to the signal pad. In the embodiment of the present disclosure, by setting the first type of first dummy pad connection structure, the vertical heat dissipation path can also be improved, so that heat can be dissipated in both the vertical and horizontal directions, thereby further avoiding the formation of local hot spots. In practical applications, the connection method between the pads and the connection method between the pads and the connection structure can be reasonably set according to factors such as the concentration of current and power density distribution.

[0080] In some embodiments, the die 100 further includes a first guard ring 114 located on the first surface 102 a ; the plurality of first dummy pads 108 further include a second type of first dummy pads 108 b , wherein the second type of first dummy pads 108 b are connected to the first guard ring 114 .

[0081] The first guard ring 114 may be located on the back side of the substrate 102. The guard ring located on the back side of the substrate 102 is generally referred to as a dummy seal ring. As an example, the first guard ring 114 may extend from the first surface 102a into the substrate 102, with the first surface 102a exposing the first guard ring 114. As another example, the first guard ring 114 may be located on the first surface 102a of the substrate 102, with the first guard ring 114 surrounding the plurality of first pads 104. As yet another example, the first guard ring 114 may extend from the first surface 102a through the substrate 102 and contact the second guard ring 124 mentioned below, with the first guard ring 114 and the second guard ring 124 constituting a composite guard ring. The materials of the first guard ring 114 and the second guard ring 124 may both include conductive materials, such as copper, aluminum, or other metal materials.

[0082] At least one first dummy pad 108 among the plurality of first dummy pads 108 may be connected to the first guard ring 114. For example, at least one first dummy pad 108 may be connected to the first guard ring 114 via the first under-bump metallization layer 116. The first dummy pad 108 connected to the first guard ring 114 is a second-type first dummy pad 108b. In this embodiment, the number of first dummy pads 108 connected to the first guard ring 114 may be one or more, and this disclosure does not specifically limit this.

[0083] It should be noted that the first guard ring 114 and the second guard ring 124 mentioned below are primarily used to shield external interference, prevent moisture intrusion, provide support, and balance stress. The guard rings are typically designed to surround the circuitry within the die. In the disclosed embodiment, by providing a second-type first dummy pad connected to the first guard ring, the horizontal heat dissipation path on the back side of the substrate can be further improved, allowing heat to be dissipated more rapidly in the horizontal direction, thereby further preventing the formation of local hot spots.

[0084] In some embodiments, the die 100 further includes a plurality of second pads 118 located on the second surface 102 b , wherein the device layer 110 is located between the plurality of second pads 118 and the substrate 102 , and at least two second pads 118 are connected to each other.

[0085] Multiple second pads 118 can be located on the front side of substrate 102, that is, second pads 118 are front side pads. Second pads 118 can be connected to the memory array in device layer 110 via an interconnect structure formed on the front side of substrate 102, where the interconnect structure is located in an interconnect dielectric layer between second pads 118 and device layer 110. As an example, second pads 118 can be bumps formed on the front side of substrate 102. For the material of the bumps, refer to the relevant description above.

[0086] In the embodiment of the present disclosure, at least two second solder pads are connected to each other, and the connected second solder pads can increase the heat dissipation area of the second surface, so that the heat dissipation area of the front and back sides of the tube core can be increased, reducing the difficulty of chip thermal management, thereby meeting the needs of high-performance chips with higher power density and compact packaging.

[0087] Of course, in other embodiments, only the at least two second solder pads 118 on the front surface of the die 100 may be connected to each other, and the plurality of first solder pads 104 on the back surface of the die 100 may be isolated from each other. In actual applications, the connection method between the plurality of front solder pads and the plurality of back solder pads may be reasonably set according to the heat distribution and heat dissipation requirements of the die 100.

[0088] In some embodiments, the die 100 further includes a second under bump metallurgy layer 126 , which is located between the device layer 110 and the second pads 118 , wherein at least two second pads 118 are connected to each other through the second under bump metallurgy layer 126 .

[0089] The second underbump metallization layer 126 can be located on the front side of the substrate 102. Specifically, the second underbump metallization layer 126 serves as a front-side UBM. The material of the second underbump metallization layer 126 includes a conductive material, such as at least one of titanium, copper, and nickel. The material of the front-side UBM and the back-side UBM can be the same or different, and this disclosure does not specifically limit this.

[0090] As an example, an initial second UBM layer can be formed covering the interconnect dielectric layer on the front side of the substrate 102. The formation process of the initial second UBM layer includes sputtering or chemical vapor deposition. Using the initial second UBM layer as a seed layer, multiple second pads 118 are formed by electroplating. Subsequently, a portion of the initial second UBM layer exposed outside the second pads is removed, and the remaining initial second UBM layer constitutes the second UBM layer 126. In practical applications, the initial second UBM layer 126 exposed outside at least two second pads 118 can be retained to ensure that the at least two second pads 118 are connected via the second UBM layer 126. Of course, in other embodiments, the at least two second pads 118 can also be connected to each other via other conductive structures (e.g., interconnect structures) on the front side of the substrate 102, and this is not particularly limited in the present disclosure.

[0091] In the disclosed embodiments, by providing at least two second pads connected to each other via a second underbump metallurgy layer, the connection between the at least two second pads can be achieved simply by adjusting the design and layout of the second underbump metallurgy layer. This is compatible with existing front-side UBM and front-side bump manufacturing processes without adding additional process steps.

[0092] In some embodiments, the plurality of second pads 118 include a second signal pad 120 and a plurality of second dummy pads 122 , and the second signal pad 120 is spaced apart from each second dummy pad 122 .

[0093] As an example, the at least two second pads 118 connected to each other include: a second signal pad 120 and at least one second dummy pad 122 connected to each other, for example, the second signal pad 120 and the at least one second dummy pad 122 are connected to each other via a second under bump metallization layer 126. In this example, the number of second dummy pads 122 connected to the second signal pad 120 can be one or more, and this disclosure has no particular limitation on this.

[0094] As an example, the at least two second pads 118 are connected to each other, including: at least two second dummy pads 122 are connected to each other, for example, the at least two second dummy pads 122 are connected to each other through the second under bump metallization layer 126. In this example, the number of second dummy pads 122 connected to each other can be two or more, and this disclosure has no particular limitation on this.

[0095] In the disclosed embodiment, the second pads 118 can be divided into second signal pads 120 and second dummy pads 122 according to their different functions. The second signal pads 120 and the second dummy pads 122 are arranged alternately on the front surface of the substrate 102. The second signal pads 120 are primarily used to achieve electrical connection and signal transmission, while the second dummy pads 122 are primarily used for heat conduction and reliable packaging. It should be noted that the two second pads 118 used for electrical connection and signal transmission are electrically isolated from each other, that is, the two second signal pads 120 are electrically isolated from each other.

[0096] In some embodiments, the device layer 110 is connected to the first signal pad 106 through the second signal pad 120 and the connection structure 112 ; the plurality of second dummy pads 122 include a first type second dummy pad 122 a , wherein the first type second dummy pad 122 a is connected to the connection structure 112 .

[0097] At least one second dummy pad 122 among the plurality of second dummy pads 122 can be connected to the connection structure 112. For example, at least one second dummy pad 122 is connected to the connection structure 112 via a second under-bump metallization layer 126. The second dummy pad 122 connected to the connection structure 112 is a first-type second dummy pad 122a. In this embodiment, the number of second dummy pads 122 connected to the connection structure 112 can be one or more, and this disclosure does not specifically limit this.

[0098] In the embodiment of the present disclosure, by providing a first-type second dummy pad connected to the connection structure, the vertical heat dissipation path can be further improved, allowing heat to be quickly dissipated in the vertical direction, thereby further avoiding the formation of local hot spots. It should be noted that the first-type first dummy pad 108a and the first-type second dummy pad 122a can be connected to the same connection structure 112 or different connection structures 112, and this disclosure has no special limitations on this.

[0099] In some embodiments, the die 100 further includes a second guard ring 124 located on the second surface 102 b ; the plurality of second dummy pads 122 further include second-type second dummy pads 122 b , wherein the second-type second dummy pads 122 b are connected to the second guard ring 124 .

[0100] The second guard ring 124 may be located on the front side of the substrate 102. The guard ring located on the front side of the substrate 102 is typically formed by all layers of the die 100 (from the substrate 102 to the top metal layer) and is used to protect the die 100 from damage during the dicing or packaging process. As an example, the second guard ring 124 may be located on the second surface 102b of the substrate 102. The second guard ring 124 surrounds the device layer 110, the interconnect dielectric layer, and the plurality of second pads 118.

[0101] At least one second dummy pad 122 among the plurality of second dummy pads 122 can be connected to the second guard ring 124. For example, at least one second dummy pad 122 is connected to the second guard ring 124 via a second under-bump metallization layer 126. The second dummy pad 122 connected to the second guard ring 124 is a second-type second dummy pad 122b. In this embodiment, the number of second dummy pads 122 connected to the second guard ring 124 can be one or more, and this disclosure has no particular limitation on this.

[0102] In the embodiment of the present disclosure, by providing a second type of second dummy pad connected to the second guard ring, the horizontal heat dissipation path on the front side of the substrate can be further improved, so that heat can be dissipated more quickly in the horizontal direction, thereby further avoiding the formation of local hot spots.

[0103] In some embodiments, among two adjacent dies, the first signal pad of one die is bonded to the second signal pad of the other die, and the first dummy pad of one die is bonded to the second dummy pad of the other die.

[0104] As an example, combined with Figure 1 and Figure 2 As shown, the back side of die 100b can be bonded to the front side of die 100a. Specifically, each first signal pad 106 of die 100b is bonded to the corresponding second signal pad 120 of die 100a, and each first dummy pad 108 of die 100b is bonded to the corresponding second dummy pad 122 of die 100a, thereby obtaining a bonded die 100b and die 100a.

[0105] As an example, combined with Figure 1 and Figure 2 As shown, the front side of die 100b can be bonded to the back side of die 100c. Specifically, each second signal pad 120 of die 100b is bonded to the corresponding first signal pad 106 of die 100c, and each second dummy pad 122 of die 100b is bonded to the corresponding first dummy pad 108 of die 100c, thereby obtaining the bonded die 100b and die 100c.

[0106] It should be noted that the embodiment of the present disclosure has no special restriction on the number of bonded dies, which can be two or more. By bonding and stacking multiple dies, a three-dimensional stacking structure can be formed, thereby significantly improving the bandwidth and capacity of the chip.

[0107] Based on the above semiconductor structure, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure. The manufacturing method can be used to form the semiconductor structure in any of the above embodiments.

[0108] Figure 3 The present disclosure provides a flow chart of a method for manufacturing a semiconductor structure. Figure 3 As shown, the manufacturing method includes step S300: forming at least one tube core; forming the tube core includes the following steps:

[0109] Step S310: providing a substrate;

[0110] Step S320: forming a plurality of first pads on the first surface of the substrate, wherein at least two first pads are connected to each other.

[0111] Figure 4A and Figure 4B This is a schematic diagram of a semiconductor structure manufacturing process shown in an embodiment of the present disclosure. Figure 3 、 Figure 4A and Figure 4B The method for manufacturing the semiconductor structure provided by the embodiment of the present disclosure is exemplarily described.

[0112] In step S310, refer to Figure 4B As shown, a substrate 402 is provided.

[0113] As an example, you can provide Figure 4A The initial substrate 402S shown in FIG. 4 has a first surface 402a and a second surface 402b. After the front surface process of the die is completed, the initial substrate 402S can be thinned from the back surface (ie, the first surface 402a) of the initial substrate 402S to form a substrate as shown in FIG. Figure 4B In the substrate 402 shown, the first surface 402a' of the substrate 402 is the back side of the thinned initial substrate 402S.

[0114] In step S320, refer to Figure 4B As shown, a plurality of first pads 404 are formed on the first surface 402 a ′ of the substrate 402 , wherein at least two first pads 404 are connected to each other.

[0115] As an example, a photolithography and electroplating process may be used to form a thinned back surface of the initial substrate 402S. Figure 4B Multiple first pads 404 are shown. Each first pad 404 has a specific function, for example, for inputting or outputting signals, grounding or connecting to power, balancing stress distribution, and heat dissipation.

[0116] In some embodiments, the step of forming the die further includes forming a device layer 410 on the second surface 402 b of the substrate 402 , wherein the second surface 402 b and the first surface 402 a ′ are opposite to each other along the thickness direction of the substrate 402 .

[0117] As an example, a substrate 402S may be formed on the front side (ie, the second surface 402b) of the initial substrate 402S. Figure 4A The device layer 410 shown in FIG. 4 may include at least one of a peripheral circuit and a memory array. Figure 4A The specific structure of the device layer 410 is omitted.

[0118] In some embodiments, the step of forming the die further includes: forming a connection structure 412 penetrating the substrate 402 , wherein the connection structure 412 connects the device layer 410 , and the first surface 402 a ′ exposes the connection structure 412 .

[0119] As an example, a photolithography and etching process may be used to form Figure 4A The illustrated connection structure 412 has a first end connected to the device layer 410, and a second end extending into the initial substrate 402S. After the front-side processing of the die is completed, the initial substrate 402S is thinned until the second end of the connection structure 412 is exposed, thereby forming the connection structure 412 that penetrates the substrate 402. In other examples, after thinning the initial substrate 402S, the connection structure 412 that penetrates the substrate 402 can also be formed by etching from the back side of the thinned substrate 402.

[0120] In some embodiments, the above step S320 includes: forming a first signal pad 406 and multiple first dummy pads 408 on the first surface 402a, the first signal pad 406 is spaced apart from each first dummy pad 408, wherein the first signal pad 406 is connected to the exposed connection structure 412, and the multiple first dummy pads 408 include a first type of first dummy pad 408a connected to the connection structure 412.

[0121] As an example, a first signal pad 406 and multiple first dummy pads 408 can be formed on the back side of the thinned initial substrate 402S, the first signal pad 406 is connected to the second end of the connection structure 412, and at least one first dummy pad 408 is connected to the connection structure 412. The first dummy pad 408 connected to the connection structure 412 is a first-type first dummy pad 408a, thereby improving the vertical heat dissipation path.

[0122] In some embodiments, the step of forming the die further includes forming a first under bump metallization layer 416 between the substrate 402 and the first pads 404 , wherein at least two first pads 404 are connected to each other through the first under bump metallization layer 416 .

[0123] As an example, an initial first UBM layer can be formed covering the back side of the thinned initial substrate 402S. The formation process of the initial first UBM layer includes sputtering or chemical vapor deposition. Using the initial first UBM layer as a seed layer, multiple first pads 404 are formed by electroplating. Subsequently, portions of the initial first UBM layer exposed outside the first pads 404 are removed, and the remaining initial first UBM layer constitutes the first UBM layer 416. In practical applications, the initial first UBM layer exposed outside at least two first pads 404 can be retained to ensure that the at least two first pads 404 are connected via the first UBM layer 416.

[0124] In some embodiments, the step of forming the die further includes forming a first guard ring 414 on the first surface 402 a ′.

[0125] As an example, a photolithography and etching process may be used to form a Figure 4B The first guard ring 414 is shown extending from the first surface 402a' into the substrate 402. Of course, in other examples, the first guard ring 414 can be formed on the first surface 402a' and surround the plurality of first pads 404.

[0126] In some embodiments, forming the plurality of first dummy pads 408 on the first surface 402 a ′ includes forming a second type of first dummy pads 408 b connected to the first guard ring 414 on the first surface 402 a ′.

[0127] As an example, at least one first dummy pad 408 may be connected to the first guard ring 414 through the first under bump metallization layer 416 . The first dummy pad 408 connected to the first guard ring 414 is a second type first dummy pad 408 b , thereby improving the horizontal heat dissipation path.

[0128] In some embodiments, the step of forming the die further includes forming a plurality of second pads 418 on the second surface 402 b , wherein the device layer 410 is located between the plurality of second pads 418 and the substrate 402 , and at least two second pads 418 are connected to each other.

[0129] As an example, a photolithography and electroplating process may be used to form a surface of the initial substrate 402S. Figure 4A Multiple second pads 418 are shown. Each second pad 418 has a specific function, for example, for inputting or outputting signals, grounding or connecting to power, balancing stress distribution, and heat dissipation.

[0130] In some embodiments, the above-mentioned formation of multiple second pads 418 on the second surface 402b includes: forming a second signal pad 420 and multiple second dummy pads 422 on the second surface 402b, and the second signal pad 420 is spaced apart from each second dummy pad 422, wherein the device layer 410 is connected to the first signal pad 406 through the second signal pad 420 and the connecting structure 412, and the multiple second dummy pads 422 include a first type of second dummy pad 422a connected to the connecting structure 412.

[0131] As an example, a second signal pad 420 and multiple second dummy pads 422 can be formed on the interconnect dielectric layer. The second signal pad 420 can be connected to the storage array in the device layer 410 through the interconnect structure in the interconnect dielectric layer. The second signal pad 420 can also be connected to the first signal pad 406 through the connection structure 412. At least one second dummy pad 422 is connected to the connection structure 412. The second dummy pad 422 connected to the connection structure 412 is a first-type second dummy pad 422a, thereby improving the vertical heat dissipation path.

[0132] In some embodiments, the step of forming the die further includes forming a second under bump metallization layer 426 between the device layer 410 and the second pads 418 , wherein at least two second pads 418 are connected to each other through the second under bump metallization layer 426 .

[0133] As an example, an initial second UBM layer can be formed covering the interconnect dielectric layer. The formation process of the initial second UBM layer includes sputtering or chemical vapor deposition. Using the initial second UBM layer as a seed layer, multiple second pads 418 are formed by electroplating. Subsequently, portions of the initial second UBM layer exposed outside the second pads 418 are removed, and the remaining initial second UBM layer constitutes the second UBM layer 426. In practical applications, the initial second UBM layer exposed outside at least two second pads 418 can be retained to ensure that the at least two second pads 418 are connected via the second UBM layer 426.

[0134] In some embodiments, the step of forming the die further includes forming a second guard ring 424 on the second surface 402 b .

[0135] As an example, a photolithography and etching process may be used to form a pattern such as Figure 4A The second guard ring 424 is shown, and the second guard ring 424 surrounds the device layer 410 , the interconnect dielectric layer, and the plurality of second pads 418 .

[0136] In some embodiments, forming a plurality of second dummy pads 422 on the second surface 402 b includes forming a second type of second dummy pads 422 b connected to the second guard ring 424 on the second surface 402 b .

[0137] As an example, at least one second dummy pad 422 may be connected to the second guard ring 424 via the second under bump metallization layer 426 . The second dummy pad 422 connected to the second guard ring 424 is a second type second dummy pad 422 b , thereby improving the horizontal heat dissipation path.

[0138] Figures 5A to 5G Schematic diagram of a process for manufacturing a pad according to an embodiment of the present disclosure. For ease of understanding, the following description will be given by taking a front pad (ie, a second pad) as an example.

[0139] Reference Figure 5A As shown, an initial second under-bump metallization layer 426S is formed covering the interconnect dielectric layer. For example, a layer of titanium or copper is sputtered on the surface of the interconnect dielectric layer as the initial second under-bump metallization layer 426S. The interconnect dielectric layer has a first opening exposing the interconnect pad. The initial second under-bump metallization layer 426S is deposited in the first opening and contacts the interconnect pad. The device layer is located between the initial substrate 402S and the interconnect dielectric layer. For ease of understanding, Figure 5A The device layer is omitted.

[0140] Reference Figure 5B As shown, a photoresist layer 401S is formed on the initial second under bump metallization layer 426S; the photoresist layer 401S is subjected to the following steps: Figure 5C The exposure process and the development process shown in FIG. 4 can transfer the design pattern to the photoresist layer 401S to form a patterned photoresist layer 401. The patterned photoresist layer 401 has a second opening 403. The second opening 403 exposes the initial second under bump metallization layer 426S located in the first opening. Figure 5D shown.

[0141] Reference Figure 5E As shown, a layer of copper or other metal (eg, nickel) is deposited in the second opening 403 as a seed layer required for subsequent electroplating; based on the seed layer, the second pad 418 is formed by electroplating. Figure 5E The seed layer shown in FIG may include a copper layer and a nickel layer. Figure 5E Only one second pad 418 is shown in the figure, but in actual application, a plurality of second openings 403 may be formed in the photoresist layer, and a plurality of second pads 418 may be formed by electroplating based on the plurality of second openings 403 .

[0142] Still refer to Figure 5EAs shown, after forming the second pad 418, the photoresist layer 401 may be removed to expose the initial second under-bump metallization layer 426S outside the second pad 418, as shown in FIG. Figure 5F shown.

[0143] If the second pad 418 is a second signal pad 420 and the second signal pad 420 needs to be electrically isolated from other second pads 418, the initial second under-bump metallization layer 426S exposed outside the second signal pad 420 is removed by etching to proceed to subsequent steps, such as Figure 5G shown.

[0144] If the second pad 418 is a second dummy pad 422, and the second dummy pad 422 needs to be connected to other structures (for example, the second dummy pad 422 is connected to the second signal pad 420, two second dummy pads 422 are connected, and the second dummy pad 422 is connected to the second guard ring 424), the initial second under-bump metallization layer 426S exposed outside the second dummy pad 422 is retained for subsequent steps, such as Figure 5F It is understood that the retained initial second UBM layer 426S constitutes the second UBM layer 426, and the second dummy pad 422 can be connected to other structures through the second UBM layer 426, for example, Figure 5E The second pad 418 is shown connected to the second guard ring 424 through an outer initial second under bump metallization layer 426S.

[0145] The formation process of the backside pad (ie, the first pad) is similar to the formation process of the frontside pad, and will not be described in detail here.

[0146] Regarding the specific structure of the semiconductor structure, refer to the above embodiments. Since the manufacturing method of this embodiment can be used to form the semiconductor structure of any of the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here.

[0147] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present disclosure, and they should all be covered by the protection scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that include: At least one tube die; the tube die comprises: substrate; A plurality of first pads are located on the first surface of the substrate, wherein at least two first pads are connected to each other.

2. The semiconductor structure according to claim 1, wherein: The plurality of first pads include a first signal pad and a plurality of first dummy pads, wherein the first signal pad is spaced apart from each of the first dummy pads; the die further includes: a device layer, the device layer being located on the second surface of the substrate, wherein the second surface and the first surface are opposite to each other along a thickness direction of the substrate; a connecting structure, the connecting structure penetrating the substrate, wherein the connecting structure is respectively connected to the first signal pad and the device layer; The plurality of first dummy pads include first-type first dummy pads, wherein the first-type first dummy pads are connected to the connection structure.

3. The semiconductor structure according to claim 2, wherein: The tube core also includes: a first guard ring, the first guard ring being located on the first surface; The plurality of first dummy pads further include a second type of first dummy pads, wherein the second type of first dummy pads are connected to the first guard ring.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The tube core also includes: A first under bump metallization layer is located between the substrate and the first pad, wherein at least two of the first pads are connected to each other through the first under bump metallization layer.

5. The semiconductor structure according to claim 2, wherein: The tube core also includes: A plurality of second pads are located on the second surface, wherein the device layer is located between the plurality of second pads and the substrate, and at least two second pads are connected to each other.

6. The semiconductor structure according to claim 5, wherein: The plurality of second pads include second signal pads and a plurality of second dummy pads, the second signal pads are spaced apart from each of the second dummy pads, wherein the device layer is connected to the first signal pads via the second signal pads and the connection structure; The plurality of second dummy pads include first-type second dummy pads, wherein the first-type second dummy pads are connected to the connection structure.

7. The semiconductor structure according to claim 6, wherein: The tube core also includes: a second guard ring located on the second surface; The plurality of second dummy pads further include second-type second dummy pads, wherein the second-type second dummy pads are connected to the second guard ring.

8. The semiconductor structure according to any one of claims 5 to 7, characterized in that: The tube core also includes: A second under bump metallization layer is located between the device layer and the second pad, wherein at least two of the second pads are connected to each other through the second under bump metallization layer.

9. The semiconductor structure according to claim 6, wherein: The semiconductor structure includes a plurality of the tube cores stacked in sequence, wherein, among two adjacent tube cores, the first signal pad of one of the tube cores is bonded to the second signal pad of the other tube core, and the first dummy pad of one of the tube cores is bonded to the second dummy pad of the other tube core.

10. A method for manufacturing a semiconductor structure, characterized in that: include: forming at least one die; The steps of forming the tube core include: providing a substrate; A plurality of first pads are formed on the first surface of the substrate, wherein at least two first pads are connected to each other.

11. The manufacturing method according to claim 10, characterized in that: The step of forming the tube core also includes: forming a device layer on a second surface of the substrate, wherein the second surface and the first surface are opposite to each other along a thickness direction of the substrate; forming a connection structure penetrating the substrate, wherein the connection structure is connected to the device layer and the first surface exposes the connection structure; The forming of a plurality of first pads on the first surface of the substrate comprises: A first signal pad and a plurality of first dummy pads are formed on the first surface, wherein the first signal pad is spaced apart from each of the first dummy pads, wherein the first signal pad is connected to the exposed connection structure, and the plurality of first dummy pads include a first type of first dummy pad connected to the connection structure.

12. The manufacturing method according to claim 11, characterized in that: The step of forming the tube core also includes: forming a first guard ring on the first surface; The forming of a plurality of first dummy pads on the first surface comprises: A second type of first dummy pad connected to the first guard ring is formed on the first surface.

13. The production method according to any one of claims 10 to 12, characterized in that: The step of forming the tube core also includes: A first under bump metallization layer is formed between the substrate and the first pads, wherein at least two of the first pads are connected to each other through the first under bump metallization layer.

14. The manufacturing method according to claim 11, characterized in that: The step of forming the tube core also includes: A plurality of second pads are formed on the second surface, wherein the device layer is located between the plurality of second pads and the substrate, and at least two second pads are connected to each other.

15. The manufacturing method according to claim 14, characterized in that: The forming of a plurality of second pads on the second surface comprises: A second signal pad and a plurality of second dummy pads are formed on the second surface, and the second signal pad is spaced apart from each of the second dummy pads, wherein the device layer is connected to the first signal pad through the second signal pad and the connection structure, and the plurality of second dummy pads include a first type of second dummy pad connected to the connection structure.

16. The manufacturing method according to claim 15, characterized in that: The step of forming the tube core also includes: forming a second guard ring on the second surface; The forming of a plurality of second dummy pads on the second surface comprises: A second type of second dummy pad connected to the second guard ring is formed on the second surface.

17. The production method according to any one of claims 14 to 16, characterized in that: The step of forming the tube core also includes: A second under bump metallization layer is formed between the device layer and the second pads, wherein at least two of the second pads are connected to each other through the second under bump metallization layer.

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