Inductor structure, integrated circuit and chip

Abstract

The present invention provides an inductor structure, integrated circuit, and chip, comprising N layers of rings, N being no less than 2, wound from the same wire and arranged in the same plane when viewed from above. The first layer of rings comprises a single ring, the i-th layer comprises multiple rings arranged in parallel, and the number of rings in the i-th layer is greater than the number of rings in the (i-1)th layer, with N >= i > 1. Furthermore, for each ring, at least one of its adjacent rings has a current direction opposite to that of the other. The present invention can provide a low-interference inductor structure while achieving a high inductance value within a limited space.

Description

Technical Field

[0001] The present invention relates to a technology for reducing interference in a circuit, and in particular to an inductor structure, an integrated circuit and a chip. Background Art

[0002] In the field of chip design, it is often necessary to design an on-chip inductor between point A and point B to improve the quality of the input signal.

[0003] Taking the ADC converter as an example, its processing circuit is mainly concentrated in the back end of the chip, which is used to convert the input analog signal into a multi-bit digital signal output. Figure 7 As shown, input signal 4 is processed by inductor 2 and then fed into the processing circuit. As the processing circuit increases in complexity, its occupied area 3 on chip 1 gradually increases, and its width gradually expands. However, since chip 1 is typically square or rectangular in shape, there is often a significant amount of blank space at the front end. In particular, the horizontal length from point A to point B is short, while the vertical space is relatively large, forming a roughly inverted trapezoidal area that can be used for the design of the on-chip inductor.

[0004] Typically, an inductor can be created by winding a wire into a loop. Using a single loop, the magnetic field generated by the inductor can significantly interfere with the signal lines and surrounding circuits. Furthermore, whether circular or rectangular, the blank area cannot be effectively utilized, resulting in a low inductance value that is difficult to meet practical needs. Using a figure-eight inductor, because the magnetic fields induced by the two coils are in opposite directions, the magnetic field generated by the inductor can be confined to the loop, reducing interference with the signal lines and surrounding circuits. However, this still fails to fully utilize the blank area to increase the inductance value.

[0005] Therefore, how to design an on-chip inductor that minimizes interference to signal lines and surrounding circuits while fully utilizing the blank area at the front end of the chip to obtain a larger inductance value has become an urgent problem to be solved. Summary of the Invention

[0006] One of the purposes of the present invention is to overcome at least some of the deficiencies in the prior art and to provide an inductor structure, an integrated circuit and a chip.

[0007] The technical solutions provided by the present invention are as follows:

[0008] An inductor structure comprising N layers of rings, where N is not less than 2, the N layers of rings being wound from the same wire and being distributed in the same plane when viewed from above.

[0009] The first ring layer has only one ring, the i-th ring layer contains multiple rings distributed in parallel, and the number of rings contained in the i-th ring layer is greater than the number of rings contained in the (i-1)-th ring layer, N>=i>1;

[0010] And for each ring, there is at least one ring among its adjacent rings whose current direction is opposite to that of the ring.

[0011] In some embodiments, the starting and ending points of the wires are located in the first layer of rings.

[0012] In some embodiments, the total area enclosed by the rings in the N-layer rings where the current direction is clockwise is equal to the total area enclosed by the rings in the N-layer rings where the current direction is counterclockwise.

[0013] In some embodiments, N is 3;

[0014] The first layer of rings includes the first ring;

[0015] The second layer of rings includes the second ring and the third ring from left to right;

[0016] The third layer of rings includes the fourth ring, the fifth ring and the sixth ring from left to right.

[0017] In some embodiments, the center points of all the rings form an equilateral triangle or an isosceles triangle.

[0018] In some embodiments, each ring is circular in shape, and each ring encloses an equal area.

[0019] In some embodiments, the first outflow end of the first ring is coupled to the first inflow end of the third ring, the first outflow end of the third ring is coupled to the first inflow end of the sixth ring, the first outflow end of the sixth ring is coupled to the first inflow end of the fifth ring, the first outflow end of the fifth ring is coupled to the first inflow end of the fourth ring, the first outflow end of the fourth ring is coupled to the second inflow end of the fifth ring, the second outflow end of the fifth ring is coupled to the second inflow end of the third ring, the second outflow end of the third ring is coupled to the first inflow end of the second ring, and the first outflow end of the second ring is coupled to the first inflow end of the first ring;

[0020] The wire segment connecting the first inflow end of the first loop and the end of the wire, and the wire segment connecting the first outflow end of the first loop and the starting end of the wire form the first loop.

[0021] The present invention further provides an integrated circuit, comprising a first inductor adopting the inductor structure described in any of the aforementioned embodiments.

[0022] In some embodiments, the invention further includes a second inductor having the same structure as the first inductor;

[0023] The first input signal is processed by the first inductor to obtain a first output signal;

[0024] The second input signal is processed by the second inductor to obtain a second output signal;

[0025] The first input signal and the second input signal constitute a differential input signal; the first output signal and the second output signal constitute a differential output signal.

[0026] The present invention further provides a chip comprising the inductor structure described in any one of the aforementioned embodiments.

[0027] The inductor structure, integrated circuit, and chip provided by the present invention can bring at least the following beneficial effects: by arranging multiple layers of rings, providing one ring in the first layer and gradually increasing the number of rings in subsequent layers, the present invention can fully utilize the blank area at the front end of the chip and improve the inductance value; at the same time, by providing at least one ring with a current direction opposite to that of the adjacent rings of each ring, the external interference of the inductor structure can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The preferred embodiments will be described below in a clear and understandable manner with reference to the accompanying drawings to further illustrate the above-mentioned characteristics, technical features, advantages and implementation methods of an inductor structure, integrated circuit and chip.

[0029] Figure 1 is a structural schematic diagram of an embodiment of an inductor structure of the present invention;

[0030] Figure 2 is a structural schematic diagram of another embodiment of an inductor structure of the present invention;

[0031] Figure 3 is a structural schematic diagram of another embodiment of an inductor structure of the present invention;

[0032] Figure 4 is a schematic structural diagram of an embodiment of an integrated circuit of the present invention;

[0033] Figure 5 is a schematic structural diagram of another embodiment of an integrated circuit of the present invention;

[0034] Figure 6 It is a schematic structural diagram of a chip of the present invention;

[0035] Figure 7 This is a structural diagram of an existing chip. DETAILED DESCRIPTION

[0036] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the specific embodiments of the present invention will be described below with reference to the accompanying drawings. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings and other embodiments can be obtained based on these drawings without inventive work.

[0037] To simplify the drawings, only the parts relevant to the present invention are schematically depicted in each figure. These parts do not represent the actual structure of the product. Furthermore, to simplify the drawings and facilitate understanding, in some figures, only one component with the same structure or function is schematically depicted or labeled. As used herein, "one" not only means "only one" but also "more than one."

[0038] As mentioned in the background, we need an on-chip inductor that interferes with surrounding circuits as little as possible while making full use of the blank area at the front end of the chip, which is approximately an inverted trapezoid, to obtain a larger inductance value.

[0039] To this end, an embodiment of the present invention provides an inductor structure comprising: N layers of rings, where N is not less than 2, wound from the same wire and arranged in the same plane when viewed from above. The first layer of rings comprises a single ring, the i-th layer comprises multiple rings arranged in parallel, and the number of rings in the i-th layer is greater than the number of rings in the (i-1)-th layer, where N>=i>1. Furthermore, for each ring, at least one of its adjacent rings has a current direction opposite to that of the ring itself.

[0040] Those skilled in the art will appreciate that the same conductive line is not necessarily a continuous conductive line, but may be connected by connecting lines due to crossing layers or lines in the layout.

[0041] By providing at least one loop with a current direction opposite to that of each loop in the adjacent loops, the inductor structure itself can achieve the cancellation of positive and negative magnetic fields, thereby maximizing inductor isolation and reducing interference with surrounding circuits.

[0042] By arranging multiple layers of rings, setting one ring in the first layer and gradually increasing the number of rings in subsequent layers, the blank area of ​​the chip, which is approximately an inverted trapezoid, can be fully utilized to increase the area surrounded by all rings, thereby improving the inductance value.

[0043] The inductor structure described in the embodiment of the present invention can not only minimize the generated magnetic field and reduce interference to surrounding circuits, but also fully utilize the available space to obtain a larger inductance value.

[0044] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0045] Figure 1 This is a schematic diagram of an inductor structure according to an embodiment of the present invention. Figure 1, N=3, inductor structure 10 includes three layers of rings. The three layers of rings can be formed by winding a wire. In a top-down view, all the rings are distributed on the same plane. The plane is the plane formed by the x-axis and the y-axis in the figure. The top-down view refers to the state of viewing inductor structure 10 from a direction perpendicular to the plane formed by the x-axis and the y-axis.

[0046] The first layer of rings includes a first ring 11 ; the second layer of rings, from left to right, includes a second ring 12 and a third ring 13 ; the third layer of rings, from left to right, includes a fourth ring 14 , a fifth ring 15 and a sixth ring 16 .

[0047] The first outflow end 111b of the first ring 11 is coupled to the first inflow end 131a of the third ring 13, the first outflow end 131b of the third ring 13 is coupled to the first inflow end 161a of the sixth ring 16, the first outflow end 161b of the sixth ring 16 is coupled to the first inflow end 151a of the fifth ring 15, the first outflow end 151b of the fifth ring 15 is coupled to the first inflow end 141a of the fourth ring 14, the first outflow end 141b of the fourth ring 14 is coupled to the second inflow end 152a of the fifth ring 15, the second outflow end 152b of the fifth ring 15 is coupled to the second inflow end 132a of the third ring 13, the second outflow end 132b of the third ring 13 is coupled to the first inflow end 121a of the second ring 12, and the first outflow end 121b of the second ring 12 is coupled to the first inflow end 111a of the first ring 11.

[0048] The wire segment connecting the first outflow end 111 b of the first loop and the starting end 100 a of the wire, and the wire segment connecting the first inflow end 111 a of the first loop and the ending end 100 b of the wire form the first loop 11 .

[0049] The wire segment connecting the first inflow end 121 a and the first outflow segment 121 b of the second ring forms the second ring 12 .

[0050] The wire segment connecting the first inflow end 131 a and the first outflow segment 131 b of the third ring, and the wire segment connecting the second inflow end 132 a and the second outflow segment 132 b of the third ring form the third ring 13 .

[0051] The wire segment connecting the first inflow end 141 a and the first outflow segment 141 b of the fourth ring forms the fourth ring 14 .

[0052] The wire segment connecting the first inflow end 151 a and the first outflow segment 151 b of the fifth ring, and the wire segment connecting the second inflow end 152 a and the second outflow segment 152 b of the fifth ring form the fifth ring 15 .

[0053] The wire segment connecting the first inflow end 161 a and the first outflow segment 161 b of the sixth ring forms the sixth ring 16 .

[0054] Assuming that the current inflow end of the inductor structure 10 is the starting end 100a of the wire, and the current outflow end is the end 100b of the wire, according to Figure 1 The current directions indicated by the arrows are clockwise when viewed from above. Accordingly, the magnetic fields generated by the first, third, fourth, and sixth rings 11, 13, 14, and 16 are all perpendicular to the plane and extend inward. The currents in the second, third, fourth, and sixth rings 11, 13, 14, and 16 are all in a clockwise direction when viewed from above. The magnetic fields generated by the second, third, fourth, and sixth rings are all perpendicular to the plane and extend outward. The currents in the second, third, fourth, and sixth rings 12 and 15 are all in a counterclockwise direction. Accordingly, the magnetic fields generated by the second and fifth rings are all perpendicular to the plane and extend outward.

[0055] The current directions of the first and second rings are opposite, the current directions of the third and second rings are opposite, the current directions of the fourth and fifth rings are opposite, and the current directions of the fifth and sixth rings are opposite. It can be seen that for any ring, there is at least one adjacent ring with an opposite current direction. This causes the magnetic field of the adjacent ring to cancel out the magnetic field of the current ring, thereby reducing the external magnetic field radiation of the inductor structure 10.

[0056] In one variation, the positions of the current inflow and outflow ends can be reversed. That is, the current can flow into the wire at its end 100b and out of its starting end 100a. In this case, the current flows counterclockwise through the first, third, fourth, and sixth loops 11, 13, 14, and 16, while the current flows clockwise through the second and fifth loops 12 and 15.

[0057] In one or more embodiments, N may be 2, or greater than 3, depending on the space available for inductor fabrication and the area of ​​each loop.

[0058] In one embodiment, the starting end 100a and the ending end 100b of the wire may be located in the same ring among all the rings, or in different rings.

[0059] In one embodiment, the number of rings in the N-layer rings where the current flows in a clockwise direction is equal to the number of rings where the current flows in a counterclockwise direction.

[0060] like Figure 2 In the inductor structure 10 shown, the first layer of rings includes a first ring 21; the second layer of rings, from left to right, includes a second ring 22 and a third ring 23; and the third layer of rings, from left to right, includes a fourth ring 24, a fifth ring 25 and a sixth ring 26.

[0061] The first outflow end 211b of the first ring 21 is coupled to the first inflow end 231a of the third ring 23, the first outflow end 231b of the third ring 23 is coupled to the first inflow end 261a of the sixth ring 26, the first outflow end 261b of the sixth ring 26 is coupled to the first inflow end 251a of the fifth ring 25, the first outflow end 251b of the fifth ring 25 is coupled to the first inflow end 241a of the fourth ring 24, the first outflow end 241b of the fourth ring 24 is coupled to the second inflow end 252a of the fifth ring 25, the second outflow end 252b of the fifth ring 25 is coupled to the second inflow end 232a of the third ring 23, the second outflow end 232b of the third ring 23 is coupled to the first inflow end 221a of the second ring 22, and the first outflow end 221b of the second ring 22 is coupled to the first inflow end 211a of the first ring 21.

[0062] The first loop is formed by connecting the first outflow end of the first loop to the starting end 100a of the wire, and the wire segment connecting the first inflow end of the first loop to the end 100b of the wire. The second loop is formed by connecting the first inflow end of the second loop to the wire segment of the first outflow segment. The third loop is formed by connecting the first inflow end of the third loop to the wire segment of the first outflow segment, and the second inflow end of the third loop to the wire segment of the second outflow segment. The fourth loop is formed by connecting the first inflow end of the fourth loop to the wire segment of the first outflow segment. The fifth loop is formed by connecting the first inflow end of the fifth loop to the wire segment of the first outflow segment, and the second inflow end of the fifth loop to the wire segment of the second outflow segment. The sixth loop is formed by connecting the first inflow end of the sixth loop to the wire segment of the first outflow segment.

[0063] The current directions of the first ring 21 , the third ring 23 , and the fifth ring 25 are all clockwise, and the current directions of the second ring 22 , the fourth ring 24 , and the sixth ring 26 are all counterclockwise.

[0064] In one embodiment, the total area enclosed by the rings in the N-layer rings whose current direction is clockwise is equal to the total area enclosed by the rings in the N-layer rings whose current direction is counterclockwise.

[0065] like Figure 2 In the inductor structure 10 shown, the area enclosed by each loop is equal, and the total area enclosed by the loops with the current direction in the clockwise direction is equal to the total area enclosed by the loops with the current direction in the counterclockwise direction.

[0066] In some embodiments, the areas of the rings may not be exactly equal, as long as the total area enclosed by the rings in the clockwise direction of current flow is equal to the total area enclosed by the rings in the counterclockwise direction of current flow. For example, to accommodate available space, the area of ​​the rings in the first layer may be the smallest, and the areas of subsequent rings may be increased layer by layer. The areas of the rings in the same layer may be equal or unequal.

[0067] In one embodiment, the center points of all the rings form an equilateral triangle or an isosceles triangle.

[0068] In one embodiment, each ring is circular in shape, see Figure 3 The inductor structure shown, its current direction can be referenced but not limited to Figure 1 or Figure 2 .

[0069] The magnetic field distribution of a circular ring is more uniform and symmetrical, with less edge effect and relatively less interference with surrounding components. However, the magnetic field distribution of a rectangular ring is less uniform than that of a circular ring, and the magnetic field at its edges varies more dramatically, especially at right angles, which easily generates strong local magnetic fields.

[0070] Of course, the shape of the ring can also be other shapes, such as pentagon or hexagon, but when other conditions are the same, the circular ring has the least external interference.

[0071] In one embodiment, each ring is circular in shape and has the same area. Figure 3 The inductor structure shown.

[0072] One embodiment of the present invention, as Figure 4 As shown, an integrated circuit includes a first inductor 310 using the inductor structure 10 described in any of the aforementioned embodiments.

[0073] Another embodiment of the present invention, as Figure 5 As shown, an integrated circuit includes a first inductor 310 adopting the inductor structure described in any of the above embodiments, and a second inductor 320 having the same structure as the first inductor 310 .

[0074] The first input signal is processed by the first inductor to obtain a first output signal; the second input signal is processed by the second inductor to obtain a second output signal; the first input signal and the second input signal constitute a differential input signal; the first output signal and the second output signal constitute a differential output signal.

[0075] The starting and ending ends of the wires of the first inductor and the second inductor can be respectively arranged on their respective first-layer loops, the first input signal is connected to the starting end of the wire of the first inductor, and the first output signal is connected to the end of the first inductor, so that the first-layer loop of the first inductor is placed close to the first input signal, and the other layers are far away from the first input signal; the second input signal is connected to the starting end of the wire of the second inductor, and the second output signal is connected to the end of the second inductor, so that the first-layer loop of the second inductor is placed close to the second input signal, and the other layers are far away from the second input signal. This can further reduce the interference of the first inductor and the second inductor on the first input signal and the second input signal.

[0076] One embodiment of the present invention, as Figure 6 As shown, a chip includes the inductor structure 10 described in any of the above embodiments.

[0077] It should be noted that the above embodiments can be freely combined as needed. The above are only preferred embodiments of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of the present invention, and such improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. An inductor structure, characterized in that: include: N layers of rings, N being not less than 2, the N layers of rings being wound by the same wire, and being distributed on the same plane in a top view; The first ring layer has only one ring, the i-th ring layer contains multiple rings distributed in parallel, and the number of rings contained in the i-th ring layer is greater than the number of rings contained in the (i-1)-th ring layer, and N>=i>1; And for each ring, there is at least one ring among its adjacent rings whose current direction is opposite to that of the ring.

2. The inductor structure according to claim 1, characterized in that The starting end and the ending end of the wire are located in the first layer ring.

3. The inductor structure according to claim 1, wherein: The total area surrounded by the rings in the N layers of rings where the current is directed in a clockwise direction is equal to the total area surrounded by the rings in the counterclockwise direction.

4. The inductor structure according to claim 1, wherein: N is 3; The first layer of rings includes a first ring; The second layer of rings includes a second ring and a third ring from left to right; The third layer of rings includes a fourth ring, a fifth ring and a sixth ring from left to right.

5. The inductor structure according to claim 4, characterized in that: The center points of all rings form regular triangles or isosceles triangles.

6. The inductor structure according to claim 4, characterized in that: The shape of each ring is circular, and the area enclosed by each ring is equal.

7. The inductor structure according to claim 4, characterized in that: The first outflow end of the first ring is coupled to the first inflow end of the third ring, the first outflow end of the third ring is coupled to the first inflow end of the sixth ring, the first outflow end of the sixth ring is coupled to the first inflow end of the fifth ring, the first outflow end of the fifth ring is coupled to the first inflow end of the fourth ring, the first outflow end of the fourth ring is coupled to the second inflow end of the fifth ring, the second outflow end of the fifth ring is coupled to the second inflow end of the third ring, the second outflow end of the third ring is coupled to the first inflow end of the second ring, and the first outflow end of the second ring is coupled to the first inflow end of the first ring; The first loop is formed by a wire segment connecting the first inflow end of the first loop and the end of the wire, and a wire segment connecting the first outflow end of the first loop and the starting end of the wire.

8. An integrated circuit, characterized in that: The invention comprises a first inductor adopting the inductor structure according to any one of claims 1 to 7.

9. The integrated circuit according to claim 8, wherein: Also comprising a second inductor having the same structure as the first inductor; The first input signal is processed by the first inductor to obtain a first output signal; The second input signal is processed by the second inductor to obtain a second output signal; The first input signal and the second input signal constitute a differential input signal; the first output signal and the second output signal constitute a differential output signal.

10. A chip, characterized in that: The inductor structure comprises the inductor structure according to any one of claims 1 to 7.

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