MOSFET device

Abstract

The application provides a MOSFET device, comprising: a first part, a second part and a third part, the first part and the third part are adjacent along a first direction, and the second part is located on the third part; a first well region and a second well region, the first well region is located in the first part, and the second well region is located in the second part; a first source region, a second source region, a first channel region and a second channel region, the first source region and the first channel region are located in the first well region, and the second source region and the second channel region are located in the second well region, in the first direction, the first part has a partial region located on a side of the first channel region away from the first source region, and in the second direction, the second part has a partial region located on a side of the second channel region away from the second source region and in contact with the third part; and a gate structure, located on the first part, covering the second source region and the second channel region in the first direction, and covering the first source region and the first channel region in the second direction.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular, relates to a MOSFET device. BACKGROUND

[0002] A Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is a voltage-controlled device, whose core structure includes a source, a gate, a drain, and a substrate. The gate is isolated from the semiconductor material by an oxide layer, forming a capacitor. When a voltage is applied to the gate, an electric field is generated in the semiconductor material, thereby controlling the current from the source to the drain. This control is contactless, making the MOSFET have very low on-resistance and high switching speed.

[0003] MOSFETs mainly include planar gate MOSFETs and trench gate MOSFETs. Currently, planar gate MOSFETs have higher breakdown voltage than trench gate MOSFETs, ensuring stability and reliability in high-voltage environments, but their specific on-resistance is higher, limiting efficiency and current carrying capacity in high power density applications. On the other hand, trench gate MOSFETs have lower specific on-resistance than planar gate MOSFETs, can support higher current density and lower on-resistance, but at the edges and bottom of the trench, due to the unevenness of the electric field distribution, the local area may withstand excessively high electric field strength, thus easily causing premature breakdown.

[0004] Therefore, the MOSFETs in the prior art still have the problem of low device performance. SUMMARY

[0005] The main purpose of the present application is to provide a MOSFET device to solve the problem of the specific on-resistance of the planar gate MOSFET in the prior art tending to bottleneck and reducing difficulty.

[0006] To achieve the above-mentioned purpose, according to one aspect of the present application, a MOSFET device is provided, comprising: a semiconductor substrate, comprising a first portion, a second portion, and a third portion, the first portion and the third portion being adjacent to each other along a first direction, and the second portion being located on the third portion; a well region, comprising a first well region and a second well region, the first well region being located in the first portion, the second well region being located in the second portion, and the conductivity types of the well region and the semiconductor substrate being opposite; an active region, comprising a first source region, a second source region, a first channel region, and a second channel region, the first source region and the first channel region being located in the first well region, the second source region and the second channel region being located in the second well region, the first portion in the first direction having a partial region located on a side of the first channel region away from the first source region, and the second portion in the second direction having a partial region located on a side of the second channel region away from the second source region and in contact with the third portion, the first direction being perpendicular to the second direction; and a gate structure located on the first portion, the gate structure covering the second source region and the second channel region in the first direction, and covering the first source region and the first channel region in the second direction.

[0007] Optionally, the first well region has a partial region in the first direction that is located on a side of the first source region away from the first channel region.

[0008] Optionally, the MOSFET device also includes: a first electric field shielding region, located in the second part, and in a third direction, the first electric field shielding region is adjacent to the second source region, the second channel region and a partial area in the second part, respectively, the third direction is perpendicular to the first direction and the second direction, respectively, and the first electric field shielding region has an opposite conductivity type to the semiconductor substrate.

[0009] Optionally, the MOSFET device also includes: a second electric field shielding region, located in the second part, and in the third direction, the second electric field shielding region is located on a side away from the first electric field shielding region in a partial area of ​​the second source region, the second channel region and the second part; the first electric field shielding region and the second electric field shielding region have the same conductivity type.

[0010] Optionally, the MOSFET device further includes: a third electric field shielding region located in the third portion, and the third electric field shielding region is connected to the first well region in the first direction and is connected to the first electric field shielding region in the second direction.

[0011] Optionally, the MOSFET device further comprises: a third source region located in the first well region, the third source region being in communication with the first source region in the first direction; a fourth source region located in the third field shielding region, the fourth source region being in communication with the third source region in the first direction, and the third portion having a partial region located on a side of the third field shielding region away from the fourth source region in the third direction; and a fifth source region located in the second field shielding region, the fifth source region being in communication with the fourth source region in the second direction, and the second portion having a partial region located on a side of the second field shielding region away from the fifth source region in the third direction.

[0012] Optionally, the MOSFET device further comprises: a source metal located on a surface of the second portion away from the third portion, and the source metal covering the second source region and the partial region of the fifth source region located in the surface.

[0013] Optionally, a doping concentration of the first channel region is less than a doping concentration of the first well region; and / or, a doping concentration of the second channel region is less than a doping concentration of the second well region.

[0014] Optionally, a doping concentration of the first well region is less than a doping concentration of the second well region.

[0015] Optionally, a doping concentration of the second well region is the same as a doping concentration of the partial region of the first portion located on a side of the first channel region away from the first source region in the first direction.

[0016] The technical scheme of the application is applied to a MOSFET device, which comprises a semiconductor substrate, a well region, an active region and a gate structure, and the conductive types of the well region and the semiconductor substrate are opposite. The semiconductor substrate comprises a first part, a second part and a third part, the first part and the third part are adjacent along a first direction, and the second part is located on the third part. The well region comprises a first well region and a second well region, the first well region is located in the first part, and the second well region is located in the second part. The active region comprises a first source region, a second source region, a first channel region and a second channel region, the first source region and the first channel region are located in the first well region, and the second source region and the second channel region are located in the second well region. In the first direction, the first part has a partial region located on a side of the first channel region away from the first source region; in the second direction, the second part has a partial region located on a side of the second channel region away from the second source region and in contact with the third part, and the first direction is perpendicular to the second direction. The gate structure is located on the first part. Further, in the first direction, the gate structure covers the second source region and the second channel region; and in the second direction, the gate structure covers the first source region and the first channel region. It can be understood that the gate structure is shared by the two source regions (the first source region and the second source region) and the channel regions (the first channel region and the second channel region) to simultaneously control the first channel region and the second channel region. On this basis, after a forward voltage is applied to the gate structure, the forward voltage between the gate structure and the first source region can cause the majority carriers in the first well region to be depleted, and the minority carriers are attracted to the first channel region by an electric field, so that a first conductive channel is formed in the first channel region in the case that inversion carriers are formed in the first channel region; and the forward voltage between the gate structure and the second source region can cause the minority carriers in the second well region to be absorbed to the second channel region by an electric field, so that a second conductive channel is formed in the second channel region in the case that inversion carriers are formed in the second channel region. Therefore, compared with a traditional planar gate MOSFET, the application forms a second conductive channel on the sidewall of the gate structure without reducing the cell size, significantly improves the channel density, increases the effective conductive area of the channel, so that more independent channels can be used to conduct current under the same active area, thereby increasing the current path per unit area, reducing the specific on-resistance of the device and improving the performance of the device. In summary, the application solves the bottleneck of the difficulty of continuously reducing the specific on-resistance of the planar gate MOSFET in the prior art. BRIEF DESCRIPTION OF DRAWINGS

[0017] The drawings constituting a part of the specification of the application are used to provide a further understanding of the application, and the schematic embodiments of the application and the description thereof are used to explain the application and do not constitute an improper limitation on the application. In the drawings:

[0018] Figure 1 A three-dimensional structure schematic diagram of a MOSFET device according to an embodiment of the application is shown;

[0019] Figure 2 A three-dimensional structure schematic of the MOSFET device is shown after the gate structure is removed. Figure 1 A three-dimensional structure schematic of the MOSFET device is shown after the gate structure is removed.

[0020] Figure 3 A three-dimensional structure schematic of the MOSFET device is shown after the gate structure is removed. Figure 2 A top view of the MOSFET device is shown.

[0021] Figure 4 A three-dimensional structure schematic of the MOSFET device is shown after the gate structure is removed. Figure 1 A cross-sectional schematic of the MOSFET device along the A1-A2 plane is shown. Figure 3 A cross-sectional schematic of the MOSFET device along the A1-A2 plane is shown.

[0022] Figure 5 A three-dimensional structure schematic of the MOSFET device is shown after the gate structure is removed. Figure 1 A cross-sectional schematic of the MOSFET device along the B1-B2 plane is shown. Figure 3 A cross-sectional schematic of the MOSFET device along the B1-B2 plane is shown.

[0023] Figure 6 A three-dimensional structure schematic of the MOSFET device is shown after the gate structure is removed. Figure 1 A cross-sectional schematic of the MOSFET device along the C1-C2 plane is shown. Figure 3 A cross-sectional schematic of the MOSFET device along the C1-C2 plane is shown.

[0024] Figure 7 A three-dimensional structure schematic of the MOSFET device is shown after the gate structure is removed. Figure 1 A cross-sectional schematic of the MOSFET device along the D1-D2 plane is shown. Figure 3 A cross-sectional schematic of the MOSFET device along the D1-D2 plane is shown.

[0025] Wherein, the above figures include the following reference signs:

[0026] 10, substrate; 20, epitaxial layer; 301, first well region; 302, second well region; 401, first source region; 402, second source region; 501, first channel region; 502, second channel region; 60, gate structure; 601, gate oxide layer; 602, gate; 701, first electric field shielding region; 702, second electric field shielding region; 703, third electric field shielding region; 801, third source region; 802, fourth source region; 803, fifth source region; 901, source metal; 902, drain metal. DETAILED DESCRIPTION

[0027] It should be noted that the following detailed description is merely exemplary and is intended to provide further description of the application. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

[0028] It is to be understood that the terminology used herein is for the purpose of describing specific embodiments only and is not intended to be limiting of example embodiments in accordance with the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0029] It is to be understood that the terms "first", "second", and so on used in the specification and claims and above-described drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the application described herein can be implemented. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0030] It should be understood that when an element (such as a layer, film, region, or substrate) is referred to as being "on" another element, it can be directly on the other element, or intervening elements can also be present. In addition, in the specification and claims, when an element is described as being "connected" to another element, it can be "directly connected" to the other element, or "connected" to the other element through a third element.

[0031] As introduced in the background, the planar gate MOSFET in the prior art has a higher breakdown voltage than the trench gate MOSFET, which ensures stability and reliability in a high-voltage environment, but has a higher specific on-resistance, which limits the efficiency and current carrying capacity in high power density applications. On the other hand, the trench gate MOSFET has a lower specific on-resistance than the planar gate MOSFET, which can support higher current density and lower on-resistance, but at the edge and bottom of the trench, due to the unevenness of the electric field distribution, the local area may bear a too high electric field strength, thus easily causing premature breakdown. Therefore, the MOSFET still has the problem of low device performance. In order to solve the problem of high specific on-resistance of the planar gate MOSFET in the prior art, the embodiments of the present application provide a MOSFET.

[0032] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.

[0033] As Figure 1 and Figure 2As shown, the present application provides a MOSFET device, comprising: a semiconductor substrate, comprising a first part, a second part and a third part, the first part and the third part are adjacent along a first direction A, and the second part is located on the third part; a well region, comprising a first well region 301 and a second well region 302, the first well region 301 is located in the first part, and the second well region 302 is located in the second part, and the well region and the semiconductor substrate are opposite in conductivity type; an active region, comprising a first source region 401, a second source region 402, a first channel region 501 and a second channel region 502, the first source region 401 and the first channel region 501 are located in the first well region 301, and the second source region 402 and the second channel region 502 are located in the second well region 302, in the first direction A, the first part has a partial region located on a side of the first channel region 501 away from the first source region 401, and in the second direction B, the second part has a partial region located on a side of the second channel region 502 away from the second source region 402 and in contact with the third part, and the first direction A is perpendicular to the second direction B; a gate structure 60, located on the first part, in the first direction A, the gate structure 60 covers the second source region 402 and the second channel region 502, and in the second direction B, the gate structure 60 covers the first source region 401 and the first channel region 501.

[0034] It can be understood that, in the case of corresponding the above-mentioned first part, second part and third part in a three-dimensional coordinate system (XYZ), the first part can be located in the fifth quadrant of the three-dimensional coordinate system (XYZ), the third part can be located in the eighth quadrant of the three-dimensional coordinate system (XYZ), and the second part can be located in the fourth quadrant of the three-dimensional coordinate system (XYZ).

[0035] In some optional embodiments, as Figure 1 As shown, the semiconductor substrate comprises a substrate 10 and an epitaxial layer 20 arranged in layers, the substrate 10 comprises a part located in the first part of the semiconductor substrate and a part located in the third part of the semiconductor substrate, and the epitaxial layer 20 comprises a part located in the first part of the semiconductor substrate, a part located in the second part of the semiconductor substrate, and a part located in the third part of the semiconductor substrate. The substrate 10 has a supporting effect, and its material can include but is not limited to silicon carbide, diamond and the like, and further, in order to make the MOSFET device have low on-resistance and low contact resistance, the doping concentration of the substrate 10 can be heavily doped. In addition, the thickness and doping concentration of the epitaxial layer 20 can be determined according to the design requirements of the device, which is not limited in the present application.

[0036] Optionally, the doping ions in the first well region 301, the second well region 302, the first channel region 501 and the second channel region 502 independently include but are not limited to aluminum (Al) and boron (B) and the like.

[0037] Optionally, as Figure 1 ,Figure 2 and Figure 3 As shown, the doping ions in the first source region 401 and the second source region 402 independently include but are not limited to nitrogen (N) and phosphorus (P).

[0038] Alternatively, as Figure 1 and Figure 4 、 Figure 5 、 Figure 6 and Figure 7 As shown, the gate structure 60 may include a gate oxide layer 601 and a gate 602, wherein the gate oxide layer 601 is located between the gate 602 and the semiconductor substrate. Furthermore, the material of the gate oxide layer 601 may include, but is not limited to, silicon oxide (SiO2), hafnium oxide (HfO2), aluminum oxide (Al2O3), and aluminum nitride (AlN), and the thickness of the gate oxide layer 601 may include, but is not limited to, 10 to 1000 nm; the material of the gate 602 may include, but is not limited to, doped polysilicon and silicon carbide, and the dopants therein may include, but are not limited to, phosphorus (P), nitrogen (N), and boron (B). Furthermore, the doping concentration of the dopant in the gate 602 may be 1E18-1E20 cm -3 .

[0039] Alternatively, as Figure 2 As shown, the first portion of the semiconductor substrate has a first surface, a first direction A is parallel to the first surface, and a second direction B is perpendicular to the first surface; the second portion of the semiconductor substrate has a second surface and a third surface opposite to each other, the first direction A is perpendicular to the second surface and the third surface, the second direction B is parallel to the second surface and the third surface, and the first surface and the second surface are adjacent to each other. When the first well region 301 is located in the first portion of the semiconductor substrate and the second well region 302 is located in the second portion of the semiconductor substrate, the first well region 301 extends from the first surface into the first portion of the semiconductor substrate, and the first source region 401 and the first channel region 501 extend from different surface areas of the first surface into the first well region 301; furthermore, the second well region 302 extends from the second surface into the second portion of the semiconductor substrate, and the second source region 402 and the second channel region 502 extend from different surface areas of the second surface into the second well region 302.

[0040] Specifically, combined Figure 2 and Figure 3 As shown, the first source region 401 and the first channel region 501 are adjacently arranged in the first direction A, and the second source region 402 and the second channel region 502 are adjacently arranged in the second direction B.

[0041] Alternatively, as Figure 1 、 Figure 2 and Figure 5As shown in FIG. 1, the first channel region 501 is arranged adjacent to the partial region in the first portion of the semiconductor base in the first direction A, and the second channel region 502 is arranged adjacent to the partial region in contact with the third portion in the second portion of the semiconductor base in the second direction B, so that, in the case that the conductive channel is formed in the first channel region and the second channel region, the carriers can pass from the first source region 401 through the first channel region 501 into the partial region in the first portion of the semiconductor base and can pass from the second source region 402 through the second channel region 502 into the partial region in contact with the third portion in the second portion of the semiconductor base, so as to make the MOSFET in the on state.

[0042] Optionally, the second portion of the semiconductor base comprises two first sub-portions and a second sub-portion adjacent to each other, and the first sub-portion is located between the second sub-portion and the third portion of the semiconductor base in the second direction B. On this basis, as shown in FIG. 2, in the case that the second well region 302 is located in the second portion of the semiconductor base, the second well region 302 can extend from the surface in the second sub-portion located in the second surface to the surface in the second sub-portion located in the third surface; the surface in the second sub-portion located in the second surface can comprise a first sub-region and a second sub-region adjacent to each other, and the second sub-region is located between the first sub-region and the surface in the first sub-portion located in the second surface in the second direction B, and in the case that the second source region 402 and the second channel region 502 are located in the second well region 302, the second source region 402 can extend from the first sub-region into the second sub-portion, and the second channel region 502 can extend from the second sub-region into the second sub-portion. Figure 1 Figure 2 and Figure 5 As shown in FIG. 2, in the case that the second well region 302 is located in the second portion of the semiconductor base, the second well region 302 can extend from the surface in the second sub-portion located in the second surface to the surface in the second sub-portion located in the third surface; the surface in the second sub-portion located in the second surface can comprise a first sub-region and a second sub-region adjacent to each other, and the second sub-region is located between the first sub-region and the surface in the first sub-portion located in the second surface in the second direction B, and in the case that the second source region 402 and the second channel region 502 are located in the second well region 302, the second source region 402 can extend from the first sub-region into the second sub-portion, and the second channel region 502 can extend from the second sub-region into the second sub-portion.

[0043] Specifically, the conductive types of the first portion of the semiconductor base, the second portion of the semiconductor base and the third portion of the semiconductor base can be the same; the conductive types of the first well region 301 and the second well region 302 can be the same; the conductive types of the first source region 401 and the second source region 402 can be the same; and the conductive types of the first channel region 501 and the second channel region 502 can be the same.

[0044] Specifically, the first portion of the semiconductor base can have different conductive types with the first well region 301 and the second well region 302 respectively, the second portion of the semiconductor base can have different conductive types with the first well region 301 and the second well region 302 respectively, and the third portion of the semiconductor base can have different conductive types with the first well region 301 and the second well region 302 respectively.

[0045] Specifically, the first source region 401 can have the same conductive types with the first portion of the semiconductor base, the second portion of the semiconductor base and the third portion of the semiconductor base respectively.

[0046] ​Specifically, the first channel region 501 can have the same conductivity type as the first well region 301 and the second well region 302, respectively.

[0047] In summary, it can be understood that the gate structure 60 in the above-mentioned embodiments is shared by two source regions (the first source region 401 and the second source region 402) and channel regions (the first channel region 501 and the second channel region 502) to simultaneously control the first channel region 501 and the second channel region 502. On this basis, after a forward voltage is applied to the gate structure 60, the forward voltage between the gate structure 60 and the first source region 401 can cause the majority carriers in the first well region 301 to be depleted, and the minority carriers to be attracted to the first channel region 501 by an electric field, thereby forming a first conductive channel in the first channel region 501 in the case that the first channel region 501 forms inversion carriers; the forward voltage between the gate structure 60 and the second source region 402 can cause the minority carriers in the second well region 302 to be absorbed into the second channel region 502 by an electric field, thereby forming a second conductive channel in the second channel region 502 in the case that the second channel region 502 forms inversion carriers. Therefore, compared with the conventional planar gate MOSFET, the present application forms a second conductive channel on the sidewall of the gate structure 60 without reducing the cell size, significantly improves the channel density, increases the effective conductive area of the channel, so that more independent channels can be used to conduct current under the same active area, thereby increasing the current path per unit area, reducing the specific on-resistance of the device, and improving the performance of the device. In summary, through the present application, the bottleneck that the specific on-resistance of the planar gate MOSFET in the prior art is difficult to be further reduced is solved.

[0048] In some optional embodiments, as shown in Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 and Figure 6 , the first well region 301 has a partial region on the side of the first source region 401 away from the first channel region 501 in the first direction A. Further, ion implantation can be performed in the partial region of the first well region 301 on the side of the first source region 401 away from the first channel region 501 in the first direction A, so that the doping concentration of the partial region is consistent with the doping concentration of the second well region 302 and is connected to the second well region 302. It can be understood that the partial region of the first well region 301 on the side of the first source region 401 away from the first channel region 501 in the first direction A can be used as an electric field shielding region to prevent the gate corner electric field from concentrating.

[0049] In the above embodiments, the third portion of the semiconductor body in the first direction A can include a partial region located on a side of the first source region 401 away from the first channel region 501. By reserving the partial region in the first direction A of the first well region 301 on a side of the first source region 401 away from the first channel region 501, the partial region in the first well region 301 can isolate the first source region 401 and the third portion of the semiconductor body, thereby effectively preventing the first source region 401 and the third portion of the semiconductor body from forming a conductive path, and further improving the problem of high leakage current affecting the blocking capability and overall performance of the MOSFET device due to the direct contact between the first source region 401 and the third portion of the semiconductor body when the MOSFET device is off.

[0050] It should be noted that, as shown in Figure 5 , the partial region in the first direction A of the first well region 301 on a side of the first source region 401 away from the first channel region 501 also adjoins the partial region in the second direction B of the second portion of the semiconductor body that contacts the third portion of the semiconductor body, which makes the partial region in the first direction A of the first well region 301 on a side of the first source region 401 away from the first channel region 501 isolate the partial region in the second direction B of the second portion of the semiconductor body that contacts the third portion of the semiconductor body from the first source region 401, thereby effectively preventing the first source region 401 and the second portion of the semiconductor body from forming a conductive path, and further improving the problem of high leakage current affecting the blocking capability and overall performance of the MOSFET device due to the direct contact between the first source region 401 and the second portion of the semiconductor body when the MOSFET device is off.

[0051] In some optional embodiments, as shown in Figure 1 , Figure 2 , Figure 3 and Figure 4 , the MOSFET device further comprises: a first electric field shielding region 701 located in the second portion of the semiconductor body, and the first electric field shielding region 701 adjoins the second source region 402, the second channel region 502 and the partial region in the second portion of the semiconductor body in a third direction C, the third direction C is perpendicular to the first direction A and the second direction B respectively, and the first electric field shielding region 701 is opposite in conductivity type to the semiconductor body.

[0052] Specifically, the conductivity type of the first electric field shielding region 701 is opposite to the conductivity type of the first portion of the semiconductor body, the second portion of the semiconductor body and the third portion of the semiconductor body respectively.

[0053] Optionally, the above-mentioned third direction C is also parallel to the above-mentioned first surface, second surface and third surface respectively.

[0054] In the above embodiments, the first electric field shielding region 701 and the partial region in the second portion adjacent to the first electric field shielding region 701 can form a PN junction, so that when the MOSFET device is off, a depletion region is formed between the first electric field shielding region 701 and the partial region in the second portion, which forces the electric field lines to bypass the depletion region, so that the gate corner electric field can be diverted to the edge of the depletion region, effectively preventing the concentration of the gate corner electric field, thereby making the device have a higher breakdown voltage, and improving the stability and reliability of the device in a high voltage environment.

[0055] Optionally, as shown in Figure 2 and Figure 3 , the first electric field shielding region 701 is in communication with the second well region 302 in the first direction A, and the conductivity type of the first electric field shielding region 701 is the same as that of the second well region 302. Further, the doping concentration of the first electric field shielding region 701 can be the same as that of the second well region 302. In this embodiment, the side surface of the first electric field shielding region 701 away from the second portion of the semiconductor substrate and the side surface of the first electric field shielding region 701 away from the second channel region 502 can both be the surface of the device, so it can be understood that after the first electric field shielding region 701 and the second well region 302 are in communication, the first electric field shielding region 701 and the second well region 302 can both absorb and redistribute the electric field, reduce the surface electric field strength of the device, and guide the surface electric field strength to the middle of the device (the partial region in the second portion of the semiconductor substrate located away from the second source region 402 on the side of the second channel region 502 and in contact with the third portion of the semiconductor substrate), thereby further improving the breakdown voltage of the device and enhancing the voltage withstanding capability of the device.

[0056] Optionally, as shown in Figure 1 , Figure 2 and Figure 3 , the first electric field shielding region 701 is also in communication with the partial region in the first well region 301 located away from the first source region 401 on the side of the first channel region 501. In this embodiment, the partial region in the first well region 301 located away from the first source region 401 on the side of the first channel region 501 can also be an electric field shielding region, so that after the first electric field shielding region 701 and the partial region in the first well region 301 located away from the first source region 401 on the side of the first channel region 501 are in communication, the surface electric field of the device can also be guided to a deeper part of the device, further improving the concentration of the surface electric field, further improving the breakdown voltage of the device, and enhancing the voltage withstanding capability of the device.

[0057] In some optional embodiments, as shown in Figure 1 , Figure 2 , Figure 3 and Figure 6As shown, the MOSFET device further comprises: a second electric field shielding region 702 located in the second portion and on a side of the second source region 402, a side of the second channel region 502 and a partial region in the second portion of the semiconductor substrate away from the first electric field shielding region 701 in the third direction C; and the first electric field shielding region 701 and the second electric field shielding region 702 have the same conductivity type.

[0058] Specifically, the second electric field shielding region 702 is adjacent to the second source region 402, the second channel region 502 and the partial region in the second portion in the third direction C, respectively.

[0059] In the above embodiment, the adjacent second electric field shielding region 702 and the partial region in the second portion can form a PN junction, so that when the MOSFET device is off, a depletion region is formed between the second electric field shielding region 702 and the partial region in the second portion, which forces the electric field lines to bypass the depletion region, thereby diverting the gate corner electric field to the edge of the depletion region, effectively preventing the concentration of the gate corner electric field, and thus the device has a higher breakdown voltage, improving the stability and reliability of the device in a high-voltage environment.

[0060] Optionally, the second electric field shielding region 702 is in communication with the second well region 302 in the first direction A, and the second electric field shielding region 702 has the same conductivity type as the second well region 302. Further, the doping concentration of the second electric field shielding region 702 can be the same as the doping concentration of the second well region 302. In this embodiment, the side surface of the second well region 302 away from the second electric field shielding region 702 in the second portion of the semiconductor substrate and the side surface of the second electric field shielding region 702 away from the second channel region 502 can be the surface of the device, so that it can be understood that after the second electric field shielding region 702 and the second well region 302 are in communication, the second electric field shielding region 702 and the second well region 302 can both absorb and redistribute the electric field, reducing the surface electric field strength of the device, thereby guiding the surface electric field strength to the middle of the device (a partial region in the second portion of the semiconductor substrate located on a side of the second channel region 502 away from the second source region 402 and in contact with the third portion of the semiconductor substrate), thereby further improving the breakdown voltage of the device and enhancing the voltage-withstanding capability of the device.

[0061] Optionally, as Figure 2 and Figure 3As shown, the part of the first well region 301 on the side of the first source region 401 away from the first channel region 501 is also connected with the first electric field shielding region 701 and the second electric field shielding region 702 respectively. In this embodiment, the part of the first well region 301 on the side of the first source region 401 away from the first channel region 501 can also be an electric field shielding region. After the first electric field shielding region 701 and the part of the first well region 301 on the side of the first source region 401 away from the first channel region 501 are connected, and the second electric field shielding region 702 and the part of the first well region 301 on the side of the first source region 401 away from the first channel region 501 are connected, the surface electric field of the device can also be guided to a deeper part of the device, further improving the concentration of the surface electric field, further improving the breakdown voltage of the device, and enhancing the voltage withstanding capability of the device.

[0062] In some optional embodiments, in combination with Figure 1 、 Figure 2 、 Figure 4 、 Figure 6 and Figure 7 As shown, the MOSFET device further comprises: a third electric field shielding region 703 located in the third part of the semiconductor substrate, and the third electric field shielding region 703 is connected with the first well region 301 in the first direction A and connected with the first electric field shielding region 701 in the second direction B.

[0063] Specifically, the third electric field shielding region 703 and the first electric field shielding region 701 can have the same conductivity type.

[0064] In the above embodiments, the abutting third electric field shielding region 703 and the part of the third part of the semiconductor substrate can form a PN junction, so that when the MOSFET device is off, a depletion region is formed between the third electric field shielding region 703 and the part of the third part of the semiconductor substrate, which forces the electric field lines to bypass the depletion region, thereby shifting the gate corner electric field to the edge of the depletion region, effectively preventing the concentration of the gate corner electric field, and further making the device have a higher breakdown voltage, improving the stability and reliability of the device in a high voltage environment.

[0065] Optionally, to form a conductive channel in the second channel region 502 and to enable the MOSFET device to be in an on state after carriers pass through the portion of the second channel region 502 into the portion of the second portion of the semiconductor body, the third electric field shielding region 703 comprises spaced apart first and second sub-electric field shielding regions in the third direction C, the portion of the third portion in the third direction C is located between the first and second sub-electric field shielding regions, and the portion of the third portion in the third direction C between the first and second sub-electric field shielding regions is in communication with the portion of the second portion in the second direction B. Further, the portion of the first well region 301 in the first direction A distal from the first source region 401 can be in communication with the first and second sub-electric field shielding regions, respectively, and the third electric field shielding region 703 can be in communication with the second electric field shielding region 702 in the second direction B. Further, the first sub-electric field shielding region can be in communication with the first electric field shielding region 701 and the second sub-electric field shielding region can be in communication with the second electric field shielding region 702 in the second direction B.

[0066] Optionally, to form a stable charge distribution when the third electric field shielding region 703 is in communication with the first and second electric field shielding regions 701 and 702, respectively, the third electric field shielding region 703 comprises adjacent third and fourth sub-electric field shielding regions in the second direction B, and the second electric field shielding region 702 is in communication with the third and fourth sub-electric field shielding regions and the first electric field shielding region 701 is in communication with the third and fourth sub-electric field shielding regions. Further, the third sub-electric field shielding region can have the same conductivity type as the fourth sub-electric field shielding region. Further, the third sub-electric field shielding region can have a higher doping concentration than the fourth sub-electric field shielding region. Further, the third sub-electric field shielding region can have the same doping concentration as the second well region 302 and the fourth sub-electric field shielding region can have the same doping concentration as the first well region 301. This can help to maintain a uniform electric field around the second channel region 502 and further improve the breakdown voltage of the device.

[0067] In combination Figures 1 to 7As shown, in the case that the MOSFET device simultaneously comprises the first electric field shielding region 701, the second electric field shielding region 702 and the third electric field shielding region 703, the first well region 301, the second well region 302, the first electric field shielding region 701, the second electric field shielding region 702 and the third electric field shielding region 703 can be connected. Among them, since the second source region 402, the second channel region 502 and part of the second part of the semiconductor substrate are respectively adjacent to the first electric field shielding region 701 and the second electric field shielding region 702 on the opposite sides in the third direction C, the third electric field shielding region 703 is adjacent to part of the third part of the semiconductor substrate, so that when the MOSFET device is off, the depletion region between the first electric field shielding region 701 and part of the second part of the semiconductor substrate, the depletion region between the second electric field shielding region 702 and part of the second part of the semiconductor substrate, and the depletion region between the third electric field shielding region 703 and the third part of the semiconductor substrate can disperse the electric field at different gate angles, that is, the MOSFET device in the embodiment can have a multi-dimensional electric field shielding region, which can more effectively prevent the concentration of gate angle electric field, and further improve the breakdown voltage of the device, so as to further improve the stability and reliability of the device in a high-voltage environment.

[0068] Further, in combination with Figures 1 to 7As shown, a longer channel length helps to disperse the current, reduce local heat and voltage drop, and thus support a higher current density under certain conditions, and a shorter channel length helps to reduce the on-resistance of the device. Therefore, in order to maintain a higher current density while reducing the on-resistance of the device, the channel lengths of the first channel region 501 and the second channel region 502 can be 0.3~0.8μm; the channel width of the first channel region 501 can be the same as the length of the MOSFET cell in the third direction C, and the third direction C is perpendicular to the first direction A and the second direction B respectively. The channel width of the second channel region 502 can be 1~5μm. By setting the channel width of the second channel region 502 to be greater than or equal to 1, the current density of the device can be improved. By Setting the width to less than 5 can increase the area of ​​the first electric field shielding region 701 and the second electric field shielding region 702 in the second portion, thereby helping to prevent electric field concentration at the gate. Since the smaller the distance between the channel region and the electric field shielding region, the better the protection of the gate corner by the electric field shielding region, and the larger the size of the portion of the second portion located on the side of the second source region 402 away from the second channel region 502 in a direction perpendicular to the first surface, the lower the resistance of the device. Therefore, to strike a balance between the on-resistance of the device and the protection of the gate corner by the electric field shielding region, the length of the portion of the second portion of the semiconductor body located on the side of the second channel region 502 away from the second source region 402 and in contact with the third portion of the semiconductor body in the second direction B can be 0.2 to 1 μm in the second direction B. It will be understood that the channel length direction of the first channel region 501 is parallel to the first direction A, and the channel length direction of the second channel region 502 is parallel to the second direction B.

[0069] In some optional embodiments, combined with Figure 2 、 Figure 3 and Figure 7 As shown, the MOSFET device also includes: a third source region 801, located in the first well region 301, and connected to the first source region 401 in the first direction A; a fourth source region 802, located in the third electric field shielding region 703, and connected to the third source region 801 in the first direction A, and having a partial area on the side of the third electric field shielding region 703 away from the fourth source region 802 in the third part of the semiconductor substrate in the third direction C; a fifth source region 803, located in the second electric field shielding region 702, and connected to the fourth source region 802 in the second direction B, and having a partial area on the side of the second electric field shielding region 702 away from the fifth source region 803 in the second part of the semiconductor substrate in the third direction C.

[0070] Specifically, the second part of the semiconductor substrate can have a fourth surface, which is a surface of the second part of the semiconductor substrate away from the third part of the semiconductor substrate. The second electric field shielding region 702 is located in the second part of the semiconductor substrate, and the fifth source region 803 is located in the second electric field shielding region 702, so that the fifth source region 803 is located in the second part of the semiconductor substrate. The second well region 302 is located in the second part of the semiconductor substrate, and the second source region 402 is located in the second well region 302, so that the second source region 402 is located in the second part of the semiconductor substrate. On this basis, the second source region 402 can have a first preset area in the fourth surface, and the fifth source region 803 can have a second preset area in the fourth surface, the first preset area and the second preset area being different.

[0071] Optionally, the third source region 801 and the second part of the semiconductor substrate are both isolated by a part of the first well region 301 located on the side of the first source region 401 away from the first channel region 501, and the third source region 801 and the third part of the semiconductor substrate are both isolated by a part of the first well region 301 located on the side of the first source region 401 away from the first channel region 501. In this embodiment, the part of the first well region 301 can effectively prevent the third source region 801 and the second part of the semiconductor substrate from forming a conductive path, and can effectively prevent the third source region 801 and the third part of the semiconductor substrate from forming a conductive path, thereby improving the problem of high leakage current affecting the blocking ability and overall performance of the device due to the direct contact of the third source region 801 with the second part of the semiconductor substrate and the third part of the semiconductor substrate, respectively, when the MOSFET device is off.

[0072] In some optional embodiments, in combination with Figure 2 , Figure 3 and Figure 7 as shown, since the fifth source region 803 is located in the second electric field shielding region 702, the second sub-electric field shielding region is in communication with the second electric field shielding region 702, and in the case that the third electric field shielding region 703 includes the above-mentioned first sub-electric field shielding region and the second sub-electric field shielding region, the fourth source region 802 can be located in the second sub-electric field shielding region. Thus, in this embodiment, the first source region 401, the third source region 801, the fourth source region 802 and the fifth source region 803 can be sequentially connected, and further, when the fifth source region 803 has the above-mentioned second preset area in the fourth surface, the source connection part of the first source region 401 can be led out.

[0073] Optionally, in combination with Figures 1 to 7As shown, the part region in the third electric field shielding region 703 in the third direction C is located between the fourth source region 802 and the part region in the third part of the semiconductor substrate in contact with the second part of the semiconductor substrate in the second direction B, and the part region in the third electric field shielding region 703 is adjacent to the part region in the second part in the third direction C. Therefore, in this embodiment, the part region in the third electric field shielding region 703 can effectively prevent the fourth source region 802 and the part region in the second part of the semiconductor substrate in contact with the third part from forming a conductive path, and isolation between the part region in the third part and the fourth source region 802 can be achieved, effectively preventing the fourth source region 802 and the third part of the semiconductor substrate from forming a conductive path, and further, when the MOSFET device is off, the problem of high leakage current affecting the blocking capability and overall performance of the device due to the direct contact between the fourth source region 802 and the second part of the semiconductor substrate and the problem of high leakage current affecting the blocking capability and overall performance of the device due to the direct contact between the fourth source region 802 and the third part of the semiconductor substrate can be improved.

[0074] Similarly, in combination with Figures 1 to 7 As shown, since the part region in the third electric field shielding region 702 in the third direction C is located between the fifth source region 803 and the part region in the second part of the semiconductor substrate in the second direction B, which is located on the side of the second channel region 502 away from the second source region 402, isolation between the part region in the second part of the semiconductor substrate in the second direction B, which is located on the side of the second channel region 502 away from the second source region 402, and the fifth source region 803 can be achieved, effectively preventing the fifth source region 803 and the second part from forming a conductive path, and further, when the MOSFET device is off, the problem of high leakage current affecting the blocking capability and overall performance of the device due to the direct contact between the fifth source region 803 and the second part of the semiconductor substrate can be improved.

[0075] Similarly, the doping ions in the third source region 801, the fourth source region 802 and the fifth source region 803 can independently include but are not limited to nitrogen (N) and phosphorus (P) and the like. Optionally, the doping concentration of the doping ions in the first source region 401, the second source region 402, the third source region 801, the fourth source region 802 and the fifth source region 803 includes but is not limited to 1E18-1E21cm -3 .

[0076] In the above embodiments, in combination with Figure 1 , Figure 2 , Figure 3 and Figure 7As shown, since the third source region 801 is in communication with the first source region 401, the fourth source region 802 is in communication with the third source region 801, the fifth source region 803 is in communication with the fourth source region 802, and the fifth source region 803 is in communication with the second source region 402, the first source region 401 and the second source region 402 of the embodiment can have independent preset regions in the fourth surface of the second part of the semiconductor substrate, so that the source connection of the first source region 401 and the second source region 402 of the embodiment can be realized in the fourth surface, and the formation of the source metal 901 of the MOSFET device is facilitated.

[0077] In some optional embodiments, as shown in Figure 1 The MOSFET device further comprises a source metal 901 located on the surface of the second part away from the third part, and the source metal 901 covers the second source region 402 and the fifth source region 803 in the surface.

[0078] Optionally, as shown in Figure 1 The source metal 901 further covers the second well region 302 in the surface of the second part of the semiconductor substrate away from the third part of the semiconductor substrate. It can be understood that the source metal 901 covering the second well region 302 increases the contact area between the metal and the semiconductor, thereby reducing the contact resistance per unit area.

[0079] Optionally, the material of the source metal 901 includes but is not limited to titanium (Ti), aluminum (Al), nickel (Ni), and gold (Au), etc.

[0080] In the above embodiment, since the source metal 901 covers the second source region 402 and the fifth source region 803 in the surface of the second part away from the third part of the semiconductor substrate, respectively, the current can be more uniformly distributed between the first channel region 501 and the second channel region 502, thereby improving the overall current carrying capacity.

[0081] In some optional embodiments, the doping concentration of the first channel region 501 is less than the doping concentration of the first well region 301; and / or, the doping concentration of the second channel region 502 is less than the doping concentration of the second well region 302. Optionally, the doping concentration of the doping ions of the first well region 301 is selected from 1E18-1E20 cm -3 The doping concentration of the doping ions of the second well region 302 is selected from 1E19-1E21 cm -3 The doping concentration of the doping ions of the first channel region 501 and the second channel region 502 is selected from 1E17-1E21 cm -3 .

[0082] In the above embodiments, since the doping concentration of the first and second channel regions 501 and 502 is lower than that of the first and second well regions 301 and 302, the initial concentration of free charge carriers (electrons for N-channel) in the semiconductor region under the gate structure 60 is lower. The lower initial electron concentration results in a larger barrier (i.e. a higher gate voltage) to be overcome before the gate voltage produces a strong enough electric field to form an effective conductive channel. Therefore, the threshold voltage of the device is increased by the above embodiments.

[0083] In some alternative embodiments, the doping concentration of the first well region 301 is lower than that of the second well region 302.

[0084] In the above embodiments, the first well region 301 with lower doping concentration can reduce the carrier storage effect during the switching process of the MOSFET device, thereby speeding up the switching time and improving the frequency response of the device. The second well region 302 with higher doping concentration can ensure the formation of a stable current path in the second channel region 502 in the on-state of the MOSFET device, reducing the impact of gate voltage fluctuations on the MOSFET current output.

[0085] It is explained here that since the doping concentration of the second well region 302 is higher, it means that the semiconductor material in this region has higher conductivity. Further, in the case where the source metal 901 is in direct contact with these above-mentioned second well regions 302, the ohmic resistance from the source to the second channel region 502 can be significantly reduced, further meaning that the voltage drop during conduction is reduced, and the efficiency of the device in the on-state is higher.

[0086] In order to ensure the consistency of the electrical performance of the device in different directions and improve the overall performance of the device, in some alternative embodiments, the doping concentration of the second well region 302 is the same as the doping concentration of the part of the semiconductor body in the first direction A in the part of the region located on the side of the first channel region 501 away from the first source region 401.

[0087] In addition, as shown in Figure 1 , Figure 2 and Figures 4 to 7 , the above-mentioned MOSFET device further comprises a drain metal 902 located on the side of the semiconductor body away from the gate structure 60. Further, the material of the drain metal 902 can include but is not limited to titanium (Ti), aluminum (Al), nickel (Ni) and gold (Au), etc.

[0088] According to an embodiment of the present application, a specific method for forming a MOSFET device is provided, comprising the following steps:

[0089] First, a substrate and an epitaxial layer are provided in a stacked arrangement, and then multiple ion implantations are performed on a side of the epitaxial layer facing away from the substrate to form a second well region, a first electric field shielding region, a second electric field shielding region, a third electric field shielding region, a second source region, a second channel region, a fourth source region, and a fifth source region.

[0090] Second, the epitaxial layer is etched to form a groove in a surface of the side of the epitaxial layer facing away from the substrate, and the remaining substrate and epitaxial layer form a semiconductor base including a first portion, a second portion, and a third portion, with the first and third portions adjoining along a first direction and the second portion being located on the third portion. The second well region is located in the second portion, and the second source region and the second channel region are located in the second well region. In the second direction, the second portion has a partial region on a side of the second channel region facing away from the second source region and in contact with the third portion. The first electric field shielding region is located in the second portion and adjoins the second source region, the second channel region, and the partial region in the second portion in the third direction. The second electric field shielding region is located in the second portion and on a side of the second source region, the second channel region, and the partial region in the second portion facing away from the first electric field shielding region in the third direction. The third electric field shielding region is located in the third portion and is in communication with the first electric field shielding region in the second direction. The fourth source region is located in the third electric field shielding region. The fifth source region is located in the second electric field shielding region and is in communication with the fourth source region in the second direction. In the third direction, the second portion has a partial region on a side of the second electric field shielding region facing away from the fifth source region.

[0091] Third, multiple ion implantations are performed in the first portion to form a first well region, a first source region, a first channel region, and a third source region. The first well region is located in the first portion. The first source region and the first channel region are located in the first well region. In the first direction, the first portion has a partial region on a side of the first channel region facing away from the first source region. In the first direction, the first well region has a partial region on a side of the first source region facing away from the first channel region. The third electric field shielding region is in communication with the first well region in the first direction. The third source region is located in the first well region and is in communication with the first source region in the first direction. The fourth source region is in communication with the third source region in the first direction.

[0092] Fourth, a gate structure is formed in the groove such that the gate structure is located on the first portion and covers the second source region and the second channel region in the first direction and covers the first source region and the first channel region in the second direction. A source metal is formed on a surface of the second portion facing away from the third portion and covers the second source region and the fifth source region on a portion of the surface. A drain metal is formed on a side of the semiconductor base facing away from the gate structure.

[0093] According to another embodiment of the present application, a method of forming a specific MOSFET device is provided, comprising the steps of:

[0094] On the basis of the planar gate MOSFET, a secondary epitaxy is performed on the region of the non-gate structure, and then a plurality of ion implantations are performed on the secondary epitaxy part to form the MOSFET device.

[0095] It can be understood that the planar gate MOSFET can include a first part, a third part, a first well region, a first source region, a first channel region, a third source region and a gate structure in a semiconductor substrate. The first part and the third part are adjacent along a first direction, the first well region is located in the first part, the first source region and the first channel region are located in the first well region, there is a partial region in the first part on the side away from the first source region of the first channel region in the first direction, there is a partial region in the first well region on the side away from the first channel region of the first source region in the first direction, the third source region is located in the first well region, the third source region is communicated with the first source region in the first direction, and the gate structure is located on the first part and covers the first source region and the first channel region in a second direction.

[0096] The region of the non-gate structure is the third part of the MOSFET device, and the second part of the MOSFET device is obtained after the secondary epitaxy of the region of the non-gate structure. The multiple ion implantations on the second part are the multiple ion implantations on the second part to form the MOSFET device. It can be understood that the MOSFET device further comprises a second well region, a second source region, a second channel region, a first electric field shielding region, a second electric field shielding region, a third electric field shielding region, a fourth source region and a fifth source region after the multiple ion implantations on the second part. The second well region is located in the second part, the second source region and the second channel region are located in the second well region, the second part has a partial region located on a side of the second channel region away from the second source region and contacting the third part in the second direction, the first electric field shielding region is located in the second part and abuts the second source region, the second channel region and the partial region in the second part in the third direction, the second electric field shielding region is located in the second part and located on a side of the second source region, the second channel region and the partial region in the second part away from the first electric field shielding region in the third direction, the third electric field shielding region is located in the third part and communicates with the first well region in the first direction and communicates with the first electric field shielding region in the second direction, the fourth source region is located in the third electric field shielding region and communicates with the third source region in the first direction, and the third part has a partial region located on a side of the third electric field shielding region away from the fourth source region in the third direction, the fifth source region is located in the second electric field shielding region and communicates with the fourth source region in the second direction, and the second part has a partial region located on a side of the second electric field shielding region away from the fifth source region in the third direction, and the gate structure covers the second source region and the second channel region in the first direction.

[0097] In addition, the MOSFET device further comprises a source metal and a drain metal, the source metal can be formed on a surface of the second part away from the third part, and the source metal covers the second source region and a part of the fifth source region located in the surface; and the drain metal is formed on a side of the semiconductor substrate away from the gate structure.

[0098] From the above description, it can be seen that the above-mentioned embodiments of the present application achieve the following technical effects:

[0099] The technical scheme of the application is applied to a MOSFET device, which comprises a semiconductor substrate, a well region, an active region and a gate structure, and the conductive types of the well region and the semiconductor substrate are opposite. The semiconductor substrate comprises a first part, a second part and a third part, the first part and the third part are adjacent along a first direction, and the second part is located on the third part. The well region comprises a first well region and a second well region, the first well region is located in the first part, and the second well region is located in the second part. The active region comprises a first source region, a second source region, a first channel region and a second channel region, the first source region and the first channel region are located in the first well region, and the second source region and the second channel region are located in the second well region. In the first direction, the first part has a partial region located on a side of the first channel region away from the first source region; in a second direction, the second part has a partial region located on a side of the second channel region away from the second source region and in contact with the third part, and the first direction is perpendicular to the second direction. The gate structure is located on the first part. Further, in the first direction, the gate structure covers the second source region and the second channel region; and in the second direction, the gate structure covers the first source region and the first channel region. It can be understood that the gate structure is shared by the two source regions (the first source region and the second source region) and the channel regions (the first channel region and the second channel region) in the first direction and the second direction to simultaneously control the first channel region and the second channel region. On this basis, after a forward voltage is applied to the gate structure, the forward voltage between the gate structure and the first source region can cause the majority carriers in the first well region to be depleted, and the minority carriers are attracted to the first channel region by an electric field, so that a first conductive channel is formed in the first channel region in the case that inversion carriers are formed in the first channel region; and the forward voltage between the gate structure and the second source region can cause the minority carriers in the second well region to be absorbed to the second channel region by an electric field, so that a second conductive channel is formed in the second channel region in the case that inversion carriers are formed in the second channel region. Therefore, compared with a conventional planar gate MOSFET, the application forms a second conductive channel on the sidewall of the gate structure without reducing the cell size, significantly improves the channel density, increases the effective conductive area of the channel, so that more independent channels can be used to conduct current under the same active area, thereby increasing the current path per unit area, reducing the specific on-resistance of the device and improving the performance of the device. In summary, the application solves the bottleneck that the specific on-resistance of the planar gate MOSFET in the prior art is difficult to be further reduced.

[0100] The above merely describes the preferred embodiments of the application and is not intended to limit the application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the application shall be included in the protection scope of the application.

Claims

1. A MOSFET device, characterized by, Comprising: a semiconductor base including a first portion, a second portion, and a third portion, the first portion and the third portion being contiguous in a first direction, the second portion being located on the third portion; a well region including a first well region and a second well region, the first well region being located in the first portion, the second well region being located in the second portion, the well region and the semiconductor base being opposite in conductivity type; an active region including a first source region, a second source region, a first channel region, and a second channel region, the first source region and the first channel region being located in the first well region, the second source region and the second channel region being located in the second well region, the first portion having a partial area located on a side of the first channel region away from the first source region in the first direction, the second portion having a partial area located on a side of the second channel region away from the second source region and in contact with the third portion in a second direction, the first direction being perpendicular to the second direction; a gate structure located on the first portion, the gate structure covering the second source region and the second channel region in the first direction, the gate structure covering the first source region and the first channel region in the second direction; a first electric field shielding region located in the second portion, the first electric field shielding region being contiguous with the second source region, the second channel region, and the partial area in the second portion in a third direction, the third direction being perpendicular to the first direction and the second direction, the first electric field shielding region being opposite in conductivity type to the semiconductor base.

2. The MOSFET device of claim 1, wherein, The first well region has a partial area located on a side of the first source region away from the first channel region in the first direction.

3. The MOSFET device of claim 1, wherein, The MOSFET device further comprises: a second electric field shielding region located in the second portion, the second electric field shielding region being located on a side of the second source region, the second channel region, and the partial area in the second portion away from the first electric field shielding region in the third direction; the first electric field shielding region and the second electric field shielding region being the same in conductivity type.

4. The MOSFET device of claim 1, wherein, The MOSFET device further comprises: a third electric field shielding region located in the third portion, the third electric field shielding region being in communication with the first well region in the first direction, the third electric field shielding region being in communication with the first electric field shielding region in the second direction.

5. The MOSFET device of claim 4, wherein, The MOSFET device further comprises: a third source region located in the first well region, the third source region being in communication with the first source region in the first direction; a fourth source region located in the third electric field shielding region, the fourth source region being in communication with the third source region in the first direction, the third portion having a partial area located on a side of the third electric field shielding region away from the fourth source region in the third direction; a fifth source region located in the second electric field shielding region, the fifth source region being in communication with the fourth source region in the second direction, the second portion having a partial area located on a side of the second electric field shielding region away from the fifth source region in the third direction.

6. The MOSFET device of claim 5, wherein, The MOSFET device further comprises: a source metal on a surface of the second portion on a side of the second portion away from the third portion, and the source metal covering the portions of the second source region and the fifth source region in the surface.

7. The MOSFET device of any one of claims 1 to 6, wherein, a doping concentration of the first channel region is less than a doping concentration of the first well region; and / or, a doping concentration of the second channel region is less than a doping concentration of the second well region.

8. The MOSFET device of any one of claims 1-6, wherein, a doping concentration of the first well region is less than a doping concentration of the second well region.

9. The MOSFET device of any one of claims 1-6, wherein, a doping concentration of the second well region is the same as a doping concentration of a portion of the first portion in the first direction on a side of the first channel region away from the first source region.

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