Solar cells and photovoltaic modules

Abstract

This application relates to the photovoltaic field, providing a solar cell and a photovoltaic module. The solar cell includes: a substrate having a front side and a back side opposite each other along a first direction; a first region and a second region alternately arranged along a second direction on the back side; a first dielectric layer located on the first region including a plurality of pores, at least a portion of which penetrate the first dielectric layer along the first direction; a first doped layer located on the side of the first dielectric layer away from the substrate, the first doped layer and the substrate having dopants of the same conductivity type; a second dielectric layer located at least on the second region; the second doped layer located on the side of the second dielectric layer away from the substrate, the second doped layer and the first doped layer having opposite conductivity types, which at least helps to improve the electrical performance of the solar cell and reduce its risk of thermal runaway.

Description

Technical Field

[0001] This application relates to the field of photovoltaics, and in particular to a solar cell and a photovoltaic module. Background Technology

[0002] Solar cells, as a sustainable and clean energy source, are being used more and more widely. A solar cell is a device that uses the photovoltaic principle to generate charge carriers to convert solar energy into electrical energy. Solar cells typically use grid lines to extract charge carriers, thus efficiently utilizing electrical energy. Currently, the mainstream types of solar cells include BC cells (Back Contact cells), TOPCON (Tunnel Oxide Passivated Contact) cells, PERC cells (Passivated emitter and real cell), and heterojunction cells.

[0003] However, in the current passivated contact structure of solar cells containing tunneling layers, the carrier transport mechanism in the tunneling layer is mainly quantum tunneling transport. Therefore, the thickness and uniformity of the tunneling layer are extremely important when it is prepared, which poses a great challenge to the process and equipment. Summary of the Invention

[0004] This application provides a solar cell and a photovoltaic module, which at least helps to improve the electrical performance of the solar cell and reduce the risk of thermal runaway.

[0005] According to some embodiments of this application, one aspect of this application provides a solar cell, comprising: a substrate having a front side and a back side opposite to each other along a first direction, the back side having a first region and a second region alternately arranged along a second direction; a first dielectric layer located on the first region, the first dielectric layer including a plurality of pores, at least a portion of the pores penetrating the first dielectric layer along the first direction; a first doped layer located on the side of the first dielectric layer away from the substrate, the first doped layer and the substrate having dopant elements of the same conductivity type; a second dielectric layer located at least on the second region; and a second doped layer located on the side of the second dielectric layer away from the substrate, the second doped layer and the first doped layer having opposite conductivity types.

[0006] In some embodiments, the transport path of charge carriers along the first direction via the substrate, the first dielectric layer, and the first doped layer is a reference transport path, and the transport resistance corresponding to the reference transport path in at least a portion of the solar cells increases with the increase of the temperature of the solar cell.

[0007] In some embodiments, the second dielectric layer is a tunneling layer, and charge carriers are transported to the second doped layer via the substrate and the second dielectric layer; wherein, the transport path of the charge carriers along the first direction via the substrate, the second dielectric layer and the second doped layer is a control transport path, and the transport resistance corresponding to the control transport path decreases as the temperature of the solar cell increases.

[0008] In some embodiments, the second dielectric layer also includes a plurality of the pores, at least a portion of which penetrate the second dielectric layer along the first direction; wherein, the transport path of the charge carriers along the first direction in the substrate, the first dielectric layer and the first doped layer is one of the reference transport paths, and the transport path of the charge carriers along the first direction in the substrate, the second dielectric layer and the second doped layer is another of the reference transport paths.

[0009] In some embodiments, the first dielectric layer includes a first portion having the pores and a second portion not having the pores, wherein the current density in the first portion is greater than the current density in the second portion.

[0010] In some embodiments, the ratio of the current density in the first part to the current density in the second part is greater than or equal to 10.

[0011] In some embodiments, the transport path of charge carriers along the first direction via the substrate, the first dielectric layer, and the first doped layer is a reference transport path, the reference transport path including a first reference transport path and a second reference transport path, wherein the transport path of charge carriers via the substrate, the first portion, and the first doped layer is the first reference transport path; and / or, the transport path of charge carriers via the substrate, the second portion, and the first doped layer is the second reference transport path.

[0012] In some embodiments, the transmission resistance corresponding to the first reference transmission path increases as the temperature of the solar cell increases; and / or, the transmission resistance corresponding to the second reference transmission path decreases as the temperature of the solar cell increases.

[0013] In some embodiments, the impedance corresponding to the reference transmission path is 0.05 mΩ·cm. 2 ~1.4mΩ·cm 2 .

[0014] In some embodiments, at least a portion of the pores contain the substrate and / or the first doped layer; and / or, at least a portion of the pores have air gaps.

[0015] In some embodiments, the temperature range of the first dielectric layer is -50°C to 150°C.

[0016] In some embodiments, a diffusion layer is further disposed between the substrate and the first dielectric layer, wherein the diffusion layer and the first doped layer have doping elements of the same conductivity type.

[0017] In some embodiments, the pores in the first dielectric layer are formed by heat treatment; wherein the heat treatment is performed at a process temperature of 800°C to 1100°C; and / or the heat treatment lasts for 20 min to 60 min.

[0018] In some embodiments, an isolation zone is provided between the first region and the second region.

[0019] In some embodiments, the materials of the first dielectric layer and the second dielectric layer include one or more of silicon oxide, silicon carbide, silicon nitride, and silicon oxynitride; or, the material of the first dielectric layer includes one or more of silicon oxide, silicon carbide, silicon nitride, and silicon oxynitride, and the material of the second dielectric layer includes one or more of intrinsic amorphous silicon, amorphous silicon oxide, microcrystalline silicon, and nanocrystalline silicon.

[0020] In some embodiments, the doping concentration of the dopant element in the first doped layer is 3 × 10⁻⁶. 20 atom / cm 3 ~7×10 20 atom / cm 3 ; and / or, the sheet resistance of the first doped layer is 13Ω~35Ω; and / or, the size of more than 80% of the grains in the first doped layer is 150nm~300nm.

[0021] In some embodiments, the transmission resistivity of the first dielectric layer is 4 mΩ·cm 2 ~5mΩ·cm 2 .

[0022] In some embodiments, the solar cell further includes: a third dielectric layer located between the first dielectric layer and the first doped layer; and / or, a fourth dielectric layer located between the second dielectric layer and the second doped layer.

[0023] In some embodiments, the first doped layer is an N-type conductivity type region, the second doped layer is a P-type conductivity type region, and the pores are only present in the first dielectric layer. The pores are used to allow electrons in the substrate to pass through the first dielectric layer and be transported to the first doped layer.

[0024] In some embodiments, the second doped layer is an amorphous doped layer or a microcrystalline doped layer, and the second dielectric layer is an intrinsic amorphous silicon layer or a microcrystalline silicon layer.

[0025] In some embodiments, along the first direction, the first doped layer and the second doped layer form an overlapping region in a local area of ​​the first region, and the second doped layer located on the overlapping region is located on the side of the first doped layer away from the substrate.

[0026] In some embodiments, the solar cell further includes: a transparent conductive layer located on the side of the second doped layer away from the substrate, and the transparent conductive layer located in the first region and the transparent conductive layer located in the second region having a gap; a first electrode and a second electrode located on the side of the transparent conductive layer away from the substrate, the first electrode being located on the first region and in contact with the transparent conductive layer, and the second electrode being located on the second region and in contact with the transparent conductive layer.

[0027] In some embodiments, the second doped layer is located on the second region and on a portion of the first region, and the second doped layer is discontinuously distributed in the first region.

[0028] In some embodiments, the first dielectric layer is a silicon oxide layer or a silicon oxynitride layer, and the second dielectric layer is an intrinsic amorphous silicon layer or an intrinsic microcrystalline silicon layer with a thickness of 1 nm to 5 nm.

[0029] In some embodiments, the second dielectric layer is located on the second region and on a portion of the surface of the first doped layer on the side away from the substrate. In some embodiments, charge carriers are transported along the first direction via the substrate, the first dielectric layer, and the first doped layer, wherein the transport efficiency of the charge carriers in at least a portion of the first dielectric layer decreases as the temperature of the first dielectric layer increases.

[0030] In some embodiments, the second dielectric layer is a tunneling layer, and charge carriers are transported to the second doped layer via the substrate and the second dielectric layer; wherein, the transport path of the charge carriers along the first direction via the substrate, the second dielectric layer and the second doped layer is a control transport path, and the transport efficiency of the charge carriers in the second dielectric layer increases with the increase of the temperature of the first dielectric layer.

[0031] In some embodiments, the second dielectric layer also includes a plurality of the pores, at least a portion of which penetrate the second dielectric layer along the first direction; wherein, a majority of the charge carriers are transported along the first direction via the substrate and the first dielectric layer to the first doped layer, and a minority of the charge carriers are transported along the first direction via the substrate and the second dielectric layer to the second doped layer.

[0032] According to some embodiments of this application, another aspect of this application provides a photovoltaic module, including: a battery string, formed by connecting a plurality of solar cells as described in any one of the above claims; an encapsulating film for covering the surface of the battery string; and a cover plate for covering the surface of the encapsulating film facing away from the battery string.

[0033] The technical solution provided in this application has at least the following advantages:

[0034] The first dielectric layer is designed to include multiple pores, with at least a portion of these pores penetrating the first dielectric layer along a first direction. This improves the carrier transport mechanism within the first dielectric layer, specifically making carrier transport primarily occur via the pores. In other words, most carriers will be transported to the first doped layer via the substrate and the porous portions of the first dielectric layer. For example, carriers can directly transport to the first doped layer through the pores, while some carriers will transport to the first doped layer via quantum tunneling through the non-porous portions of the first dielectric layer. Therefore, with carrier transport via pores as the primary mechanism in the first dielectric layer, the transport efficiency of carriers in the first dielectric layer is improved, thereby enhancing the electrical performance of the solar cell. Furthermore, if the temperature rises in a localized area of ​​the solar cell, carriers can transport more quickly via the pores compared to other areas in the first dielectric layer, reducing the risk of thermal runaway in the solar cell. Attached Figure Description

[0035] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this application or in the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a first cross-sectional schematic diagram of a solar cell provided in an embodiment of this application;

[0037] Figure 2 This is a second cross-sectional schematic diagram of a solar cell provided in an embodiment of this application;

[0038] Figure 3 This is a third cross-sectional schematic diagram of a solar cell provided in an embodiment of this application;

[0039] Figure 4 This is a partially enlarged cross-sectional schematic diagram of a solar cell provided in an embodiment of this application;

[0040] Figure 5 This is a top view schematic diagram of the first dielectric layer in a solar cell provided in an embodiment of this application;

[0041] Figure 6 This is another partially enlarged cross-sectional schematic diagram of a solar cell provided in an embodiment of this application;

[0042] Figure 7 This is another partially enlarged cross-sectional schematic diagram of a solar cell provided in an embodiment of this application;

[0043] Figure 8 A comparison diagram of the characteristics of the first dielectric layer in three different solar cells provided in an embodiment of this application;

[0044] Figure 9 This is a fourth cross-sectional schematic diagram of a solar cell provided in an embodiment of this application;

[0045] Figure 10 A fifth cross-sectional schematic diagram of a solar cell provided in an embodiment of this application;

[0046] Figure 11 A sixth cross-sectional schematic diagram of a solar cell provided in an embodiment of this application;

[0047] Figure 12 A seventh cross-sectional schematic diagram of a solar cell provided in an embodiment of this application;

[0048] Figure 13 A partial top view schematic diagram of a test structure cut from a solar cell, provided as an embodiment of this application;

[0049] Figure 14 An eighth cross-sectional schematic diagram of a solar cell provided in an embodiment of this application;

[0050] Figure 15 A ninth cross-sectional schematic diagram of a solar cell provided in an embodiment of this application;

[0051] Figure 16 Line graphs showing the change in transmission resistance as a function of temperature in two different solar cells provided in an embodiment of this application;

[0052] Figure 17 A tenth cross-sectional schematic diagram of a solar cell provided in an embodiment of this application;

[0053] Figure 18 An eleventh cross-sectional schematic diagram of a solar cell provided in an embodiment of this application;

[0054] Figure 19 A schematic cross-sectional view of a substrate in a method for manufacturing a solar cell according to another embodiment of this application;

[0055] Figure 20 An enlarged cross-sectional view of a method for manufacturing a solar cell according to another embodiment of this application, after the initial first dielectric layer and the first semiconductor layer have been formed;

[0056] Figure 21 A partial three-dimensional schematic diagram of a cell string in a photovoltaic module provided in another embodiment of this application;

[0057] Figure 22 This is a partial cross-sectional schematic diagram of a photovoltaic module provided in another embodiment of this application.

[0058] Explanation of reference numerals in the attached figures:

[0059] 100, Substrate; 100a, Front side; 100b, Back side; 110, First region; 120, Second region; 130, Isolation region; 101, First dielectric layer; 111, First part; 121, Second part; 131, Initial first dielectric layer; 102, Pore; 103, First doped layer; 113, First semiconductor layer; 104, Second dielectric layer; 105, Second doped layer; 106, Diffusion layer; 107, Third dielectric layer; 108, Fourth dielectric layer; 109, Electrode; 119, First electrode; 129, Second electrode; 139, First passivation layer; 149, Second passivation layer; 159, Third passivation layer; 169, Transparent conductive layer; 40, Solar cell; 41, Encapsulating film; 42, Cover plate; 43, Conductive strip. Detailed Implementation

[0060] As can be seen from the background technology, the transport mechanism of charge carriers in the dielectric layer needs to be improved.

[0061] Analysis revealed that, based on the premise that the primary transport mechanism of charge carriers in the dielectric layer is quantum tunneling, the thickness of the dielectric layer significantly impacts the transport efficiency. Specifically, excessively thick dielectric layers tend to reduce the tunneling probability of charge carriers, leading to poorer contact performance between the dielectric layer and the substrate; conversely, excessively thin dielectric layers result in incomplete passivation at the interface between the dielectric layer and the substrate, i.e., poor passivation performance. Generally, to achieve optimal passivation contact performance, the thickness variation of the dielectric layer needs to be controlled within 0.2 nm, which presents significant challenges in terms of fabrication processes and equipment.

[0062] Furthermore, based on the premise that the main transport mechanism of charge carriers in the dielectric layer is quantum tunneling, the tunneling probability of charge carriers in the dielectric layer increases with the increase of the temperature of the dielectric layer. In other words, the transport resistance corresponding to charge carrier transport in the dielectric layer decreases with the increase of the temperature of the dielectric layer. When the temperature of the dielectric layer increases, the transport resistance corresponding to charge carrier transport in the dielectric layer decreases, and charge carriers can more easily pass through the dielectric layer to other film layers via quantum tunneling.

[0063] It is understandable that as the temperature of the dielectric layer increases, more charge carriers pass through the dielectric layer per unit time via quantum tunneling, which increases the current in the local area of ​​the solar cell. With the simultaneous increase of temperature and current, the risk of thermal runaway of the solar cell increases.

[0064] This application provides a solar cell and a photovoltaic module. In the solar cell, a first dielectric layer is designed to include multiple pores, with at least a portion of the pores penetrating the first dielectric layer along a first direction. This improves the carrier transport mechanism in the first dielectric layer, specifically making carrier transport in the first dielectric layer primarily achieved through the pores. In other words, most carriers will be transported to the first doped layer via the substrate and the porous portion of the first dielectric layer. For example, carriers can be directly transported to the first doped layer through the pores, while some carriers will be transported to the first doped layer via quantum tunneling through the non-porous portion of the first dielectric layer. Therefore, carrier transport via pores is the primary transport mechanism in the first dielectric layer, which helps improve the carrier transport efficiency in the first dielectric layer, thereby improving the electrical performance of the solar cell. Moreover, if the temperature rises in a local area of ​​the solar cell, carriers can transport faster through the pores than in other areas of the first dielectric layer, reducing the risk of thermal runaway in the solar cell.

[0065] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0066] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0067] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A exists, A and B exist simultaneously, and B exists. In addition, the character " / " in this document generally indicates that the related objects before and after it have an "or" relationship.

[0068] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

[0069] In the description of the embodiments of this application, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0070] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0071] In the accompanying drawings corresponding to the embodiments of this application, the thickness and area of ​​the layers are enlarged for better understanding and ease of description. When describing a component (such as a layer, film, region, or substrate) on or on the surface of another component, the component may be "directly" located on the surface of the other component, or there may be a third component between the two components. Conversely, when describing a component on the surface of another component, or when another component is formed or disposed on the surface of a component, it indicates that there is no third component between the two components. Furthermore, when describing a component as being "generally" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a portion of the edge of the entire surface.

[0072] In the description of the embodiments of this application, when a component "includes" another component, other components are not excluded unless otherwise stated, and other components may be further included. Furthermore, when a component such as a layer, film, region, or plate is referred to as being "on / located" on another component, it can be "directly" on the other component (i.e., located on the surface of the other component with no other components between them), or another component may be present therein. Moreover, when a component such as a layer, film, region, or plate is "directly located" on another component, or when a component such as a layer, film, region, or plate is located on the surface of another component, it indicates that no other components are located therein.

[0073] The terminology used in the description of the various embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the description of the various embodiments and the appended claims, the term "component" is also intended to include the plural form unless the context clearly indicates otherwise. Components include layers, films, regions, or plates, etc.

[0074] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0075] This application provides an embodiment of a solar cell, which will be described in detail below with reference to the accompanying drawings.

[0076] Reference Figures 1 to 5The solar cell includes: a substrate 100 having a front side 100a and a back side 100b opposite each other along a first direction X, and a first region 110 and a second region 120 alternately arranged along a second direction Y on the back side 100b; a first dielectric layer 101 located on the first region 110, the first dielectric layer 101 including a plurality of pores 102, at least a portion of the pores 102 penetrating the first dielectric layer 101 along the first direction X; a first doped layer 103 located on the side of the first dielectric layer 101 away from the substrate 100, the first doped layer 103 and the substrate 100 having dopants of the same conductivity type; a second dielectric layer 104 located at least on the second region 120; and a second doped layer 105 located on the side of the second dielectric layer 104 away from the substrate 100, the second doped layer 105 and the substrate 103 having dopants of different conductivity types, wherein the second doped layer 105 and the first doped layer 103 have opposite conductivity types.

[0077] in, Figure 1 This is a first cross-sectional schematic diagram of a solar cell provided in an embodiment of this application; Figure 2 This is a second cross-sectional schematic diagram of a solar cell provided in an embodiment of this application; Figure 3 This is a third cross-sectional schematic diagram of a solar cell provided in an embodiment of this application; Figure 4 This is a partially enlarged cross-sectional schematic diagram of a solar cell provided in an embodiment of this application; Figure 5 This is a top view schematic diagram of the first dielectric layer in a solar cell provided in an embodiment of this application. It should be noted that... Figure 5 The first part 111 and the second part 121 in the first dielectric layer 101 are divided by dashed frames of different shapes.

[0078] It is worth noting that the first dielectric layer 101 is designed to include multiple pores 102, with at least a portion of the pores 102 penetrating the first dielectric layer 101 along the first direction X. This improves the carrier transport mechanism within the first dielectric layer 101, specifically ensuring that carrier transport within the first dielectric layer 101 primarily relies on the pores 102. In other words, most carriers will be transported to the first doped layer 103 via the substrate 100 and the portion of the first dielectric layer 101 containing pores 102. For example, carriers can be directly transported to the first doped layer 103 through the pores 102. A portion of the carriers will also be transported to the first doped layer 103 via quantum tunneling through the portion of the first dielectric layer 101 without pores 102.

[0079] Therefore, in the first dielectric layer 101, the carrier transport mechanism primarily utilizes the pores, which helps improve the carrier transport efficiency in the first dielectric layer 101, thereby enhancing the electrical performance of the solar cell. Furthermore, if the temperature rises in a localized area of ​​the solar cell, carriers can transport more quickly through the pores 102 compared to other areas in the first dielectric layer 101, thus reducing the risk of thermal runaway in the solar cell.

[0080] In some cases, the carrier transport path along the first direction X via the substrate 100, the first dielectric layer 101, and the first doped layer 103 is considered a reference transport path. The transport resistance corresponding to this reference transport path in at least a portion of the solar cell increases with the temperature of the solar cell. Consequently, the carrier transport efficiency in at least a portion of the first dielectric layer 101 decreases with the temperature of the first dielectric layer 101.

[0081] As described above, the first dielectric layer 101 includes a plurality of pores 102, with at least a portion of the pores 102 penetrating the first dielectric layer 101 along the first direction X. This improves the carrier transport mechanism within the first dielectric layer 101, specifically ensuring that carrier transport within the first dielectric layer 101 is primarily achieved via the pores 102. In other words, most carriers will be transported to the first doped layer 103 via the substrate 100 and the portion of the first dielectric layer 101 containing pores 102. For example, carriers can be directly transported to the first doped layer 103 through the pores 102. A portion of carriers will also be transported to the first doped layer 103 via quantum tunneling through the portion of the first dielectric layer 101 without pores 102. The portion of the first dielectric layer 101 containing pores 102 is the first part 111, which will be described in detail later.

[0082] Furthermore, the transmission resistance corresponding to the reference transmission path in at least a portion of the solar cells increases with the temperature of the solar cells, causing the carrier transmission efficiency in the first dielectric layer 101 to decrease with the increase of the temperature of the first dielectric layer 101. Thus, on the one hand, even if the temperature of the first dielectric layer 101 is low, the transmission resistance corresponding to the reference transmission path is also low, meaning that the carriers in the first dielectric layer 101 also have high transmission efficiency, which helps ensure that the solar cells have high photoelectric conversion efficiency even at lower temperatures. On the other hand, if the temperature of the first dielectric layer 101 increases, the increased transmission resistance corresponding to the reference transmission path, i.e., the characteristic that the carrier transmission efficiency is suppressed at higher temperatures, can reduce the amount of carriers transported through the first dielectric layer 101 to the first... The doped layer 103 reduces the number of charge carriers, thereby decreasing the current in localized areas of the solar cell and mitigating the risk of thermal runaway. Furthermore, if a localized temperature rise in the solar cell leads to an increase in the transport resistance of the reference transport path in that area, resulting in a decrease in the carrier transport efficiency, the carriers in that area will tend to laterally transport to other, cooler regions before being transported to the first doped layer 103 via the first dielectric layer 101. This helps reduce the number of charge carriers concentrated in the localized high-temperature regions of the solar cell. By utilizing the temperature difference and the increased transport resistance of the reference transport path in the high-temperature regions, the current distribution in the solar cell becomes more uniform, further reducing the risk of thermal runaway. Therefore, this approach helps maintain high photoelectric conversion efficiency at lower temperatures while reducing the risk of thermal runaway, thus preventing performance degradation caused by localized overheating.

[0083] Furthermore, since the transport mechanism of charge carriers in the first dielectric layer 101 mainly relies on the pores 102, reducing the dependence of charge carriers on the quantum tunneling effect during transport in the first dielectric layer 101 helps to reduce the thickness requirement of the first dielectric layer 101. In other words, the change in the transmission resistance corresponding to the reference transmission path is less affected by the quantum tunneling effect, meaning that the transport efficiency of charge carriers in the first dielectric layer 101 is less affected by the quantum tunneling effect, reducing the sensitivity to the thickness of the first dielectric layer 101. Even if the thickness of the first dielectric layer 101 is large, the transport resistance corresponding to the reference transmission path can still be small by the charge carriers using the pores 102, resulting in good transport efficiency of charge carriers in the first dielectric layer 101. This helps to increase the thickness fluctuation range of the first dielectric layer 101, i.e., increase the process window when fabricating the first dielectric layer 101. Moreover, most of the portion of the first dielectric layer 101 without pores 102, i.e., the second part 121 which will be described in detail later, can ensure that the first dielectric layer 101 has good passivation performance for the substrate 100.

[0084] It should be noted that in practical applications, the temperature of a solar cell is generally the same as the temperature of the first dielectric layer 101 within the solar cell. Furthermore, the following sections will explain in detail that the carrier transport mechanism in the first dielectric layer 101 primarily relies on the pores 102 for transport, and will also explain in detail that the transport resistance corresponding to the reference transport path in at least a portion of the solar cell increases with the temperature of the solar cell, meaning that the carrier transport efficiency in the first dielectric layer 101 decreases with increasing temperature.

[0085] It is worth noting that, reference Figures 1 to 3 The transport path of charge carriers along the first direction X through the substrate 100, the first dielectric layer 101, and the first doped layer 103 is taken as the reference transport path. Due to the insulating properties of the first dielectric layer 101, the main transport obstacle encountered by charge carriers along this path originates from the first dielectric layer 101. Furthermore, the transport efficiency of charge carriers in the first dielectric layer 101 decreases with increasing temperature. Therefore, with increasing temperature, charge carriers encounter greater resistance in the reference transport path, resulting in a higher transport resistance. Consequently, the transport resistance of the reference transport path increases with increasing temperature of the solar cell. In other words, the carrier transport efficiency in the first dielectric layer 101 decreases as the temperature of the first dielectric layer 101 increases, while the transport resistance corresponding to the reference transport path increases as the temperature of the solar cell increases; conversely, the carrier transport efficiency in the first dielectric layer 101 increases as the temperature of the first dielectric layer 101 decreases, while the transport resistance corresponding to the reference transport path decreases as the temperature of the solar cell decreases.

[0086] It is worth emphasizing that the first region 110 and the second region 120 refer to different regions on the substrate 100. Dividing the substrate 100 into the first region 110 and the second region 120 is for the purpose of forming different semiconductor film layers thereon. For example, a first dielectric layer 101 is formed on the first region 110, and a second dielectric layer 104 is formed at least on the second region 120.

[0087] It should be noted that, Figure 2 and Figure 3 Taking the example where the first dielectric layer 101 is located only in the first region 110 and the second dielectric layer 104 is located only in the second region 120, the following example is used. Figure 1 Taking the example of a first dielectric layer 101 located only in the first region 110, and a second dielectric layer 104 located not only in the second region 120 but also in a portion of the first region 110.

[0088] In addition, in some cases, refer to Figure 1 An isolation zone may not be set up between Zone 110 and Zone 120; in other cases, refer to Figure 2 or Figure 3 An isolation zone 130 can be set up between the first zone 110 and the second zone 120.

[0089] In some embodiments, reference Figures 1 to 5 The temperature range of the first dielectric layer 101 can be -50℃ to 150℃, for example, it can be -45℃, -40℃, -35℃, -30℃, -25℃, -20℃, -15℃, -10℃, -5℃, 0℃, 5℃, 10℃, 15℃, 20℃, 25℃, 30℃, 35℃, 40℃, 45℃, 50℃, 55℃, 60℃, 65℃, 70℃, 75℃, 80℃, 85℃, 90℃, 95℃, 100℃, 105℃, 110℃, 115℃, 120℃, 125℃, 130℃, 135℃, 140℃ or 145℃, etc.

[0090] The relationship between the first dielectric layer 101 and the second dielectric layer 104 will be described in detail below through three embodiments.

[0091] In some embodiments, reference Figure 2 or Figure 3 The second dielectric layer 104 can be a tunneling layer, through which charge carriers are transported to the second doped layer 105 via the substrate 100 and the second dielectric layer 104. The transport path of charge carriers along the first direction X via the substrate 100, the second dielectric layer 104, and the second doped layer 105 is a control transport path, and the transport resistance corresponding to the control transport path decreases as the temperature of the solar cell increases. In other words, the second dielectric layer 104 does not have pores similar to those in the first dielectric layer 101, and the transport of charge carriers in the second dielectric layer 104 relies on the quantum tunneling effect. Studies have shown that when the quantum tunneling effect is the main transport mechanism, the transport resistance corresponding to the control transport path decreases as the temperature of the solar cell increases.

[0092] In some cases, the materials of the first dielectric layer 101 and the second dielectric layer 104 may include one or more of silicon oxide, silicon carbide, silicon nitride, and silicon oxynitride. Based on this, the solar cell can be a TBC cell (TOPConBack Contact).

[0093] It is worth noting that the second dielectric layer 104 does not have pores similar to those in the first dielectric layer 101, which helps to reduce the film layer differences between the various parts of the second dielectric layer 104, thereby improving the passivation effect of the second dielectric layer 104 on the substrate 100, reducing the defect state density at the contact between the substrate 100 and the second dielectric layer 104, and thus improving the open circuit voltage of the solar cell.

[0094] In other embodiments, in conjunction with reference to Figure 2 and Figure 6 ,or Figure 3 and Figure 6 The second dielectric layer 104 may also include a plurality of pores 102, at least a portion of which penetrate the second dielectric layer 104 along the first direction X; wherein, the transport path of charge carriers along the first direction X in the substrate 100, the first dielectric layer 101, and the first doped layer 103 is one type of reference transport path, and the transport path of charge carriers along the first direction X in the substrate 100, the second dielectric layer 104, and the second doped layer 105 is another type of reference transport path. Figure 6 This is another partially enlarged cross-sectional schematic diagram of a solar cell provided in an embodiment of this application.

[0095] In other words, each of the first region 110 and the second region 120 corresponds to a reference transport path. One reference transport path involves the transport of charge carriers along the first direction X through the substrate 100, the first dielectric layer 101, and the first doped layer 103, where a majority of the charge carriers are transported along the first direction X via the substrate 100 and the first dielectric layer 101 to the first doped layer 103. Another reference transport path involves the transport of charge carriers along the first direction X through the substrate 100, the second dielectric layer 104, and the second doped layer 105, where a minority of the charge carriers are transported along the first direction X via the substrate 100 and the second dielectric layer 104 to the second doped layer 105.

[0096] In some cases, the materials of the first dielectric layer 101 and the second dielectric layer 104 can both include one or more of silicon oxide, silicon carbide, silicon nitride, and silicon oxynitride. Based on this, the solar cell can be a TBC cell. In yet other embodiments, refer to... Figure 1The material of the first dielectric layer 101 may include one or more of silicon oxide, silicon carbide, silicon nitride, and silicon oxynitride, and the material of the second dielectric layer 104 may include one or more of intrinsic amorphous silicon, amorphous silicon oxide, microcrystalline silicon, and nanocrystalline silicon. Based on this, the solar cell can be an HTBC cell, which is a heterojunction tunnel oxide passivated contact hybrid passivated back contact photovoltaic cell (abbreviated as HTBC).

[0097] In some examples, the first dielectric layer 101 can be a silicon oxide layer or a silicon oxynitride layer, and the second dielectric layer 104 can be an intrinsic amorphous silicon layer or an intrinsic microcrystalline silicon layer with a thickness of 1 nm to 5 nm. It should be noted that the HTBC battery will be described in detail later, and only the first dielectric layer 101 and the second dielectric layer 104 are described here.

[0098] It should be noted that the carrier transport paths may differ slightly in different types and structures of solar cells. The carrier transport direction and path shown in one embodiment of this application are merely examples of one or more of these, and are not limited thereto. In the various embodiments described above, the dopant element in the substrate 100 can be a first dopant element, and the dopant element with a different conductivity type from the first dopant element can be a second dopant element; one of the first dopant element and the second dopant element is an N-type dopant element, and the other is a P-type dopant element.

[0099] In some examples, the N-type dopant can be at least one of group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As); the P-type semiconductor substrate is doped with a P-type element, which can be at least one of group III elements such as boron (B), aluminum (Al), gallium (Ga), or gallium (In). The positional relationship between the pore 102, the substrate 100, and the first doped layer 103 is described in detail below.

[0100] In some embodiments, reference Figure 7 , Figure 7 This is a partially enlarged cross-sectional view of a solar cell provided in an embodiment of this application, in which at least a portion of the pores 102 contain a substrate 100 and / or a first doped layer 103.

[0101] In some examples, reference Figure 7One pore 102 can accommodate and be completely filled with the substrate 100; another pore 102 can accommodate and be completely filled with the first doped layer 103; yet another pore 102 can be filled by both the substrate 100 and the first doped layer 103. Based on this, the first doped layer 103 in the regions containing these pores 102 can contact the substrate 100. Therefore, compared to the region with the first dielectric layer 101, charge carriers are more likely to accumulate in the region containing the pores 102, which have relatively lower impedance. In other words, the pores 102 provide charge carriers with a new transport path besides quantum tunneling.

[0102] It should be noted that the filling conditions of the substrate 100 and the first doped layer 103 in different pores 102 within the same first dielectric layer 101 can be the same or different.

[0103] In other embodiments, reference is made to... Figure 4 or Figure 7 At least a portion of the pores 102 may also have air gaps. In other words, at least a portion of the pores 102 have spaces that are not filled by the substrate 100 or the first doped layer 103.

[0104] It should be noted that the reference Figure 6 In the case where the second dielectric layer 104 also has pores 102, the positional relationship between the pores 102 and the substrate 100 and the second doped layer 105 is similar to the positional relationship between the pores 102 and the substrate 100 and the first doped layer 103 described above, and will not be repeated here.

[0105] The first dielectric layer 101 will be described in detail below.

[0106] In some embodiments, reference Figure 5 The first dielectric layer 101 includes a first portion 111 with pores 102 and a second portion 121 without pores 102. The current density in the first portion 111 is greater than the current density in the second portion 121. In other words, the first dielectric layer 101 includes a plurality of spaced-apart first portions 111, and the second portion 121 wraps around the outer wall of each first portion 111 extending along a first direction X. The arrangement of the plurality of first portions 111 along a direction perpendicular to the first direction X can be irregular and randomly spaced, that is, the first portions 111 and the second portions 121 alternate and are arranged irregularly.

[0107] It is worth noting that for the pore 102 that penetrates the first dielectric layer 101 along the first direction X and is filled with the substrate 100 and / or the first doped layer 103, the charge carriers can directly travel from the substrate 100 through the pore 102 in the first part 111 through the first dielectric layer 101 to the first doped layer 103 without relying on the quantum tunneling effect. For the pore 102 that does not penetrate the first dielectric layer 101 along the first direction X, the pore 102 is usually filled with the substrate 100 or the first doped layer 103. Moreover, the portion of the first dielectric layer 101 that is directly opposite the pore 102 along the first direction X is thinner than the other portions of the first dielectric layer 101. Therefore, the charge carriers can more easily pass through the thinner portion of the first dielectric layer 101 based on the quantum tunneling effect and eventually travel to the first doped layer 103. Furthermore, due to the thinning of the thickness, the portion of the first dielectric layer 101 located near the pore 102 has a higher electric field strength, which has a stronger driving effect on the tunneling of the charge carriers. Therefore, based on the cooperation of various aspects, compared with the part of the first dielectric layer 101 that does not have pores 102, namely the second part 121, the part of the first part 111 located near the pores 102 has a smaller obstruction effect on the transmission of charge carriers along the first direction X, which can improve the efficiency of charge carriers passing through the first dielectric layer 101, that is, enable more charge carriers to pass through the first dielectric layer 101 per unit time, which is conducive to enabling more charge carriers to gather at the substrate 100 and pass through the first dielectric layer 101 with the help of the pores 102.

[0108] Based on the above, in a solar cell, the reference transport path can be considered to include a first reference transport path and a second reference transport path, wherein the transport path of charge carriers via the substrate 100, the first part 111 and the first doped layer 103 is the first reference transport path, and the transport path of charge carriers via the substrate 100, the second part 121 and the first doped layer 103 is the second reference transport path.

[0109] Since the pore 102 is located in the first part 111 of the first dielectric layer 101, most charge carriers pass directly through the first dielectric layer 101 through the pore 102. In other words, because the pore 102 penetrating the first dielectric layer 101 is filled with the substrate 100 and / or the first doped layer 103, charge carriers do not need to undergo quantum tunneling through the first dielectric layer 101 and can be transported directly between the substrate 100 and the first doped layer 103. Of course, for some pores 102 that do not penetrate the first dielectric layer 101, due to their thinness, charge carriers can still be transported through the quantum tunneling effect. In other words, the first reference transport path primarily transports charge carriers through the aperture 102. However, due to structural differences in the various apertures 102, the first reference transport path includes at least two carrier transport methods. Compared to the quantum tunneling effect, the primary carrier transport method is still through the aperture 102 penetrating the first dielectric layer 101. Therefore, the transport resistance of the first reference transport path increases with the temperature of the solar cell. Conversely, the second part 121 does not have apertures. Although a large number of charge carriers accumulate in the first part 111, some charge carriers still pass through the first dielectric layer 101 through the quantum tunneling effect. That is, the carrier transport method of the second reference transport path is quantum tunneling. Therefore, the transport resistance of the second reference transport path decreases with the temperature of the solar cell. It is worth noting that since most of the charge carriers are concentrated in the first part 111, the aperture transport method has a greater impact on the charge carriers than the quantum tunneling effect.

[0110] In some cases, the ratio of the current density in the first part 111 to the current density in the second part 121 can be greater than or equal to 10.

[0111] It is worth noting that, based on the effect of the pores 102 in the first dielectric layer 101 on improving the efficiency of carriers passing through the first dielectric layer 101, not only will the photogenerated carriers located in the region corresponding to the first part 111 gather at the pores 102, but the photogenerated carriers located in the region corresponding to the second part 121 and close to the first part 111 will also first be transversely transported along the second direction Y to the region corresponding to the first part 111. Finally, with the help of the pores 102, some carriers will still gather in the region corresponding to the second part 121 and pass through the first dielectric layer 101 through the quantum tunneling effect, resulting in a large difference between the current density in the first part 111 and the current density in the second part 121. Generally, the ratio of the two will be greater than or equal to 10.

[0112] In some embodiments, reference Figures 1 to 5 The arrangement density of pores 102 in the first dielectric layer 101 can be 1×10⁻⁶. 6 pcs / cm 2~1×10 8 pcs / cm 2 For example, it can be 2×10 6 pcs / cm 2 3×10 6 pcs / cm 2 4×10 6 pcs / cm 2 5×10 6 pcs / cm 2 6×10 6 pcs / cm 2 7×10 6 pcs / cm 2 8×10 6 pcs / cm 2 9×10 6 pcs / cm 2 1×10 7 pcs / cm 2 2×10 7 pcs / cm 2 3×10 7 pcs / cm 2 4×10 7 pcs / cm 2 5×10 7 pcs / cm 2 6×10 7 pcs / cm 2 7×10 7 pcs / cm 2 8×10 7 pcs / cm 2 Or 9×10 7 pcs / cm 2 wait.

[0113] It is worth noting that, in conjunction with references Figure 8 And Table 1, Figure 8 This is a comparison diagram of the relevant characteristics of the first dielectric layer in three different solar cells provided in an embodiment of this application. If the arrangement density of pores 102 in the first dielectric layer 101 is less than 1×10 6 pcs / cm 2 The relatively small number of pores 102 per unit area in the first dielectric layer 101 generally has a limited effect on improving the transport efficiency of charge carriers within the first dielectric layer 101. For example, due to the sparse arrangement of the pores 102, a significant number of charge carriers still pass through the first dielectric layer 101 via quantum tunneling, which can easily lead to a decrease in the fill factor of the solar cell. If the arrangement density of the pores 102 in the first dielectric layer 101 is greater than 1 × 10⁻⁶, the effect is more pronounced. 8 pcs / cm 2The large number of pores 102 per unit area in the first dielectric layer 101 reduces the passivation effect of the first dielectric layer 101 on the substrate 100. Although the fill factor of the solar cell is improved, the open-circuit voltage of the solar cell is reduced. Therefore, the arrangement density of pores 102 in the first dielectric layer 101 is designed to be 1×10⁻⁶. 6 pcs / cm 2 ~1×10 8 pcs / cm 2 This not only helps to improve the transport efficiency of charge carriers in the first dielectric layer 101 by using pores 102 with appropriate arrangement density, thereby improving the fill factor of the solar cell, but also helps to ensure that the first dielectric layer 101 has a good passivation effect on the substrate 100, thereby reducing the defect state density at the contact between the substrate 100 and the first dielectric layer 101, so as to ensure that the solar cell has a high open-circuit voltage, thereby maintaining the photoelectric conversion efficiency of the solar cell at a high level.

[0114] Table 1: Fill factor for three different types of solar cells

[0115]

[0116] It should be noted that, Figure 8 This is a comparison diagram of the dielectric layer-related characteristics in three different solar cells provided in one embodiment of this application. Figure 8 The three images in the image correspond to the etching pit traces caused by pores in the dielectric layer of three different solar cells. Figure 8 The box plots located below the three images correspond to the impedance values ​​of the reference propagation paths in three different types of solar cells. Specifically, Figure 8 The three images illustrate the etching pits caused by the pores 102 when three different solar cells are etched down to the first dielectric layer 101. These pits can be used to characterize the arrangement density of the pores 102 in the first dielectric layer 101. Figure 8 The three box plots corresponding to the three different types of solar cells can respectively illustrate the impedance value of the reference transport path, and thus characterize the carrier transport efficiency in the first dielectric layer 101. In addition, Table 1 shows the fill factor corresponding to the three different types of solar cells.

[0117] In some cases, the solar cell can be first acid-etched, for example, using hydrofluoric acid to remove other dielectric layers, such as the silicon nitride layer, located on the surface of the first dielectric layer 101; then, the solar cell can be alkaline-etched until the pores 102 in the first dielectric layer 101 are exposed, so that they can be observed under a microscope. Figure 5 or Figure 8 The etching pits shown are caused by the pore 102.

[0118] It should be noted that the reference Figure 6 In the case where the second dielectric layer 104 also has pores 102, the second dielectric layer 104 may include a third part with pores 102 and a fourth part without pores 102. The pores 102 are located in the third part, and the current density in the third part may be greater than the current density in the fourth part. The third part and the first part 111 are the same or corresponding parts, and the second part 121 and the fourth part are the same or corresponding parts; these will not be described further here.

[0119] In some embodiments, reference Figures 1 to 5 The carrier transport path along the first direction X, sequentially passing through the substrate 100, the first dielectric layer 101, and the first doped layer 103, is taken as the reference transport path. The impedance corresponding to the reference transport path can be 0.05 mΩ·cm. 2 ~1.4mΩ·cm 2 Further preferably 0.1 mΩ·cm 2 ~1.3mΩ·cm 2 For example, it can be 0.05 mΩ·cm 2 0.1mΩ·cm 2 0.15mΩ·cm 2 0.2mΩ·cm 2 0.25mΩ·cm 2 0.3mΩ·cm 2 0.35mΩ·cm 2 0.4mΩ·cm 2 0.45mΩ·cm 2 0.5mΩ·cm 2 0.55mΩ·cm 2 0.6mΩ·cm 2 0.65mΩ·cm 2 0.7mΩ·cm 2 0.75mΩ·cm 2 0.8mΩ·cm 2 0.85mΩ·cm 2 0.9mΩ·cm 2 0.95mΩ·cm 2 1mΩ·cm 2 1.05mΩ·cm 2 1.1mΩ·cm 2 1.15mΩ·cm 2 1.2mΩ·cm 2 1.25mΩ·cm 2 1.3mΩ·cm 2 1.35mΩ·cm2 Or 1.4 mΩ·cm 2 wait.

[0120] It is worth noting that the density of the pores 102 in the first dielectric layer 101 also affects the impedance corresponding to the reference transmission path. If the impedance corresponding to the reference transmission path is less than 0.05 mΩ·cm 2 This requires a larger number of pores 102 arranged per unit area in the first dielectric layer 101. Although the fill factor of the solar cell is improved, it will reduce the passivation effect of the first dielectric layer 101 on the substrate 100, thus reducing the open-circuit voltage of the solar cell. If the impedance corresponding to the reference transmission path is greater than 1.4 mΩ·cm 2 Therefore, the number of pores 102 arranged per unit area in the first dielectric layer 101 needs to be relatively small, and the effect of the first dielectric layer 101 on improving the transport efficiency of charge carriers in the first dielectric layer 101 is generally small. Therefore, the impedance corresponding to the design reference transmission path is 0.05 mΩ·cm. 2 ~1.4mΩ·cm 2 This not only helps to improve the carrier transport efficiency in the first dielectric layer 101 by relying on the low impedance corresponding to the reference transport path, thereby improving the fill factor of the solar cell, but also helps to ensure that the first dielectric layer 101 has a good passivation effect on the substrate 100, thereby reducing the defect state density at the contact between the substrate 100 and the first dielectric layer 101, so as to ensure that the solar cell has a high open-circuit voltage, thereby maintaining the photoelectric conversion efficiency of the solar cell at a high level.

[0121] In some cases, compared to a first dielectric layer located in the first region that does not have the aforementioned porosity, an embodiment of this application, by means of a designed first dielectric layer 101, can reduce the reference transmission path corresponding to the first region by at least approximately 0.5 mΩ·cm. 2 ~1mΩ·cm 2 .

[0122] The following section provides a detailed explanation of the carrier transport mechanism in the first dielectric layer 101, which is mainly achieved through the pores 102.

[0123] refer to Figure 8 Comparing the three types of solar cells corresponding to Group 1, Group 2 and Group 3, the greater the arrangement density of pores 102 in the first dielectric layer 101, the smaller the impedance corresponding to the reference transmission path. This means that the carriers are less obstructed when they are transmitted in the reference transmission path, which is more conducive to improving the transmission efficiency of carriers in the first dielectric layer 101. Therefore, it can be indirectly explained that the transmission mechanism of carriers in the first dielectric layer 101 is mainly achieved by means of pores 102.

[0124] It should be noted that when the second dielectric layer 104 also has pores 102, the transport path of charge carriers along the first direction X in the substrate 100, the second dielectric layer 104, and the second doped layer 105 can also be regarded as a type of reference transport path. Based on this, the parts of the reference transport path corresponding to the charge carriers and the second dielectric layer 104 that are the same as or corresponding to the reference transport path corresponding to the charge carriers and the first dielectric layer 101 will not be described again here.

[0125] In some embodiments, reference Figure 9 , Figure 9 This is a fourth cross-sectional view of a solar cell provided in an embodiment of this application. A diffusion layer 106 is further disposed between the substrate 100 and the first dielectric layer 101. The diffusion layer 106 and the first doped layer 103 contain dopant elements of the same conductivity type. It should be noted that... Figure 9 In order to be in Figure 1 A diffusion layer 106 is added to the solar cell shown. In practical applications, in Figure 2 or Figure 3 A diffusion layer can also be added to the solar cell shown.

[0126] It is worth noting that the introduction of doping elements in the diffusion layer 106 can saturate the dangling bonds on the side of the first dielectric layer 101 away from the first doped layer 103 and reduce the transmission resistance of the diffusion layer 106 itself. This helps to reduce the obstruction encountered by the transverse transmission of charge carriers along the second direction Y, making it easier for charge carriers to gather at the pore 102, increasing the current density in the first part 111, and allowing more charge carriers to pass through the first dielectric layer 101 per unit time.

[0127] It should be noted that the morphology of the diffusion layer 106 includes at least the following two cases:

[0128] In some cases, continue to refer to Figure 9 After forming a first dielectric layer 101 with pores 102 on a substrate 100, during the fabrication of the first doped layer 103, a small amount of dopant elements in the first doped layer 103 will pass through the pores 102 (see reference). Figure 4 The diffusion layer diffuses into the substrate 100, causing the portion of the substrate 100 in contact with the first dielectric layer 101 to transform into a diffusion layer 106 doped with doped elements. In other words, the diffusion layer 106 can be regarded as a substrate doped with doped elements.

[0129] In other cases, a doped layer is first formed on the substrate, and then a porous dielectric layer and a doped layer are sequentially formed on the side of the doped layer away from the substrate. In other words, the doped layer is not transformed from a substrate doped with doped elements.

[0130] In some examples, the doping concentration of the dopant element in the diffusion layer 106 can be 1 × 10⁻⁶. 18 atom / cm 3 ~1×10 19 atom / cm 3 For example, it can be 2×10 18 atom / cm 3 3×10 18 atom / cm 3 4×10 18 atom / cm 3 5×10 18 atom / cm 3 6×10 18 atom / cm 3 7×10 18 atom / cm 3 8×10 18 atom / cm 3 Or 9×10 18 atom / cm 3 wait.

[0131] It is worth noting that if the doping concentration of the dopant element in the diffusion layer 106 is less than 1×10 18 atom / cm 3 The effect on reducing the transfer resistance of the diffusion layer 106 itself is limited; if the doping concentration of the dopant element in the diffusion layer 106 is greater than 1×10 19 atom / cm 3 Excessive doping in the diffusion layer 106 will create more defect states within it, increasing the recombination probability of charge carriers. Therefore, the doping concentration in the diffusion layer 106 is designed to be 1 × 10⁻⁶. 18 atom / cm 3 ~1×10 19 atom / cm 3 This is beneficial because the smaller transmission resistance of the diffusion layer 106 itself reduces the obstruction to the transverse transmission of charge carriers along the second direction Y, while avoiding the presence of more defect states inside the diffusion layer 106, so as to prevent the charge carriers from recombinating in the diffusion layer 106 in advance, and to ensure that the charge carriers gather at the pore 102.

[0132] In some embodiments, reference Figures 10 to 12The solar cell further includes: a first electrode 119, which is in contact with the first doped layer 103, and the first electrode 119 is located at least on the side of the first doped layer 103 away from the substrate 100; and a second electrode 129, which is in contact with the second doped layer 105, and the second electrode 129 is located at least on the side of the second doped layer 105 away from the substrate 100. It is worth noting that after charge carriers in the substrate 100 are transported to the first doped layer 103 via the first dielectric layer 101 having pores 102, they are further transported to the first electrode 119 in contact with the first doped layer 103 for collection by the first electrode 119.

[0133] in, Figure 10 A fifth cross-sectional schematic diagram of a solar cell provided in an embodiment of this application; Figure 11 A sixth cross-sectional schematic diagram of a solar cell provided in an embodiment of this application; Figure 12 This is a seventh cross-sectional schematic diagram of a solar cell provided in an embodiment of this application.

[0134] In some cases, in conjunction with references Figure 6 as well as Figures 10 to 12 When the second dielectric layer 104 also includes a plurality of pores 102, the charge carriers in the substrate 100 are transported to the second doped layer 105 via the second dielectric layer 104 with pores 102, and then further transported to the second electrode 129 which is in contact with the second doped layer 105, so as to be collected by the second electrode 129.

[0135] The following details how the carrier transport efficiency in the first dielectric layer 101 decreases with increasing temperature, and that is, how the transport resistance of the reference transport path for carriers in at least a portion of the solar cell increases with increasing temperature. It should be noted that the reference... Figure 6 When the second dielectric layer 104 also includes multiple pores 102, the transport efficiency of charge carriers in the second dielectric layer 104 decreases as the temperature of the second dielectric layer 104 increases. The following explanation will only take the test of the transport efficiency of charge carriers in the first dielectric layer 101 as an example. The method for testing the transport efficiency of charge carriers in the second dielectric layer 104 is similar to the method for testing the transport efficiency of charge carriers in the first dielectric layer 101, and will not be repeated here.

[0136] Reference Figures 10 to 13 , Figure 13This is a partial top view schematic diagram of a test structure cut from a solar cell according to an embodiment of this application. The transmission resistance corresponding to a reference transmission path is measured using the Transmission Line Model (TLM) method. The reference transmission path is the transmission path of charge carriers along the first direction X through the substrate 100, the first dielectric layer 101, and the first doped layer 103. In other words, the reference transmission path is the transmission path corresponding to the transport of charge carriers along the first direction X through the substrate 100 and the first dielectric layer 101 to the first doped layer 103.

[0137] Among them, continue to refer to Figure 13 A typical TLM structure is obtained by cutting from a solar cell. A single TLM structure includes multiple electrodes 109 spaced apart along the second direction Y. The transport resistance can be fitted by measuring the resistance values ​​between different electrodes 109. This transport resistance is the transport resistance corresponding to the aforementioned reference transport path and can characterize the transport resistance of charge carriers moving along the first direction X in the first doped layer, the first dielectric layer, and the substrate 100. It should be noted that... Figure 14 and Figure 15 Electrode 109 can be the first electrode 119 (reference). Figure 12 For example, in practical applications, the electrode can also be a second electrode.

[0138] It should be noted that, Figure 13 The diagram illustrates four examples of testing the resistance values ​​between different electrodes 109. (See reference...) Figure 13 Along the second direction Y, multiple electrodes 109 are sequentially designated as the first electrode, second electrode, third electrode, fourth electrode, and fifth electrode, based on... Figure 13 The two probes shown in scenario 1 measure the resistance between the first and second electrodes, based on... Figure 13 In scenario 2, the two probes measure the resistance between the first and third electrodes, based on... Figure 13 In scenario 3, the two probes measure the resistance between the first and fourth electrodes and based on... Figure 13 In scenario 4, two probes measure the resistance between the first and fifth electrodes. Based on the test methods shown in scenarios 1, 2, 3, and 4, an IV curve can be obtained, and the slope of each curve corresponds to the resistance value between two different first electrodes 119.

[0139] In some cases, the resistance value between two electrodes 109 and the resistance value between other two electrodes 109, for example, Figure 14 The resistance value between the first and second electrodes shown corresponds to case 1, and... Figure 15In the resistance values ​​between the first and third electrodes corresponding to scenario 2, the charge carriers are transported sequentially along the first direction X through the substrate 100 and the first dielectric layer 101 to the first doped layer 103, and further transported to the electrode 109 that is in contact with the first doped layer 103, so as to be collected by the electrode 109. The difference between the resistance values ​​between the two electrodes 109 and the resistance values ​​between the other two electrodes 109 is mainly reflected in the length of the transport path of the charge carriers in the substrate 100 along the second direction Y.

[0140] In other words, reference Figure 14 and Figure 15 The transport path of charge carriers along the first direction X, sequentially passing through the substrate 100 and the first dielectric layer 101 to the first doped layer 103, is taken as the reference transport path. The transport resistance corresponding to the reference transport path can be regarded as the first vertical resistance R1. The transport path of charge carriers along the second direction Y in the substrate 100 from the portion opposite one electrode 109 to the portion opposite another electrode 109 is taken as the first lateral transport path. The transport resistance corresponding to the first lateral transport path is the first lateral resistance R2. Based on Figure 14 and Figure 15 The resistance measured between any two electrodes 109 in the example shown mainly includes a first longitudinal resistance R1 and a first transverse resistance R2. The resistance value between the two electrodes 109 is consistent with the resistance value between the other two electrodes 109, that is, the difference is very small and almost negligible. The first transverse resistance R2 increases linearly with the increase of the distance between the two electrodes 109 in the second direction Y. Therefore, the first longitudinal resistance R1 can be fitted by the change of resistance value between multiple different electrodes 109, for example, the first longitudinal resistance R1 can be fitted based on the change of resistance value measured in cases 1, 2, 3 and 4.

[0141] It is understandable that the difference between the resistance values ​​between the two electrodes 109 and the other two electrodes 109 is very small and can be almost ignored in the first longitudinal resistance R1 corresponding to the reference transmission path. However, the lengths of the first transverse transmission paths are significantly different. Therefore, the first transverse resistance R2 corresponding to the two first transverse transmission paths are significantly different, which leads to the difference between the resistance values ​​between the two electrodes 109 and the other two electrodes 109.

[0142] In one example, a comparison reference Figure 14 and Figure 15The transmission path of charge carriers along the second direction Y in the substrate 100 from the portion directly opposite the first electrode to the portion directly opposite the second electrode is defined as the first sub-lateral transmission path. The transmission path of charge carriers along the second direction Y in the substrate 100 from the portion directly opposite the first electrode to the portion directly opposite the third electrode is defined as the second sub-lateral transmission path. The length of the second sub-lateral transmission path is significantly longer than the length of the first sub-lateral transmission path. There is no significant difference between the reference transmission paths corresponding to the first, second, and third electrodes and the substrate 100. The difference in resistance between the first and second electrodes and between the first and third electrodes is mainly caused by the difference in length between the first and second sub-lateral transmission paths. Based on this, the transmission resistance corresponding to the reference transmission path is a stable value, which can be fitted by measuring the resistance values ​​between different electrodes 109.

[0143] It should be noted that, Figure 14 An eighth cross-sectional schematic diagram of a solar cell provided in an embodiment of this application; Figure 15 This is a ninth cross-sectional schematic diagram of a solar cell provided in one embodiment of this application. Furthermore, Figure 14 and Figure 15 The first longitudinal resistor R1 and the first transverse resistor R2 are roughly indicated by thick dashed boxes, and the positional relationship between the probe and the electrode 109 is indicated by white-filled arrows.

[0144] Further reference Figure 16 , Figure 16 Line graphs showing the transmission resistance as a function of temperature in two different types of solar cells provided in one embodiment of this application, where the temperature of the solar cell is changed... Figure 16 The test temperature is shown, and the transmission resistance corresponding to the reference transmission path in the solar cell at different temperatures is measured using the Transmission Line Model (TLM) method, thereby obtaining... Figure 16 The graph shows the increase in transport resistance of the reference transport path as the temperature of the solar cell rises. It is worth noting that the magnitude of the transport resistance of the reference transport path in the solar cell at different temperatures can reflect the carrier load in the first dielectric layer 101 (reference layer). Figure 1 The transmission efficiency in the reference transmission path is high, and an increase in the transmission resistance reflects a decrease in the transmission efficiency of charge carriers in the first dielectric layer 101. Based on this, Figure 16 The transmission resistance of the reference transmission path shown increases with the temperature of the solar cell, which reflects that the transmission efficiency of charge carriers in the first dielectric layer 101 decreases with the temperature of the first dielectric layer 101.

[0145] It should be noted that, Figure 16 The orange line indicates that battery-1 corresponds to the TBC battery (TOPCon BackContact, referring to cross-passivated back contact battery), and the dark blue line indicates that battery-2 corresponds to the TOPCON battery.

[0146] It is worth noting that, in reality, Figure 14 and Figure 15 The first longitudinal resistance R1 shown includes not only the transmission resistance corresponding to the reference transmission path, but also the contact resistance at the contact point between electrode 109 and the first doped layer 103. Furthermore, similar to the transmission resistance corresponding to the reference transmission path, the contact resistance at the contact point between electrode 109 and the first doped layer 103 is identical in value to the contact resistance between the other two electrodes 109; that is, the difference is very small and almost negligible.

[0147] To further improve the accuracy of the transmission resistance corresponding to the fitted reference transmission path, the contact resistance at the contact point between electrode 109 and the first doped layer 103 can be obtained using the following method. Then, the contact resistance can be subtracted from the first longitudinal resistance R1, which can be considered as the transmission resistance corresponding to the reference transmission path, fitted using the method described above.

[0148] refer to Figure 17 and Figure 18 The transport path of charge carriers along the first direction X from the first doped layer 103 to the electrode 109 is taken as the longitudinal transport path, and the transport resistance corresponding to the longitudinal transport path is the second longitudinal resistance R3; the transport path of charge carriers along the second direction Y in the first doped layer 103 from the portion opposite one electrode 109 to the portion opposite another electrode 109 is taken as the second lateral transport path, and the transport resistance corresponding to the second lateral transport path is the second lateral resistance R4. Based on Figure 17 and Figure 18 The resistance measured between any two electrodes 109 in the example shown mainly includes the second longitudinal resistance R3 and the second lateral resistance R4. The second longitudinal resistance R3 is consistent with the resistance values ​​between two other electrodes 109, meaning the difference is very small and almost negligible. The second lateral resistance R4 increases linearly with the increase of the distance between the two electrodes 109 in the second direction Y. Therefore, the second longitudinal resistance R3 can be fitted by the changes in resistance values ​​between multiple different electrodes 109, for example, based on... Figure 13The changes in the measured resistance values ​​corresponding to scenarios 1, 2, 3, and 4 are used to fit the second longitudinal resistance R3. The second longitudinal resistance R3 can be considered as the contact resistance at the contact point between electrode 109 and the first doped layer 103.

[0149] It should be noted that, Figure 17 A tenth cross-sectional schematic diagram of a solar cell provided in an embodiment of this application; Figure 18 This is an eleventh cross-sectional view of a solar cell provided in an embodiment of this application. Furthermore, Figure 17 and Figure 18 The second longitudinal resistor R3 and the second transverse resistor R4 are roughly indicated by thick dashed boxes, and the positional relationship between the probe and the first electrode 119 is indicated by white-filled arrows.

[0150] In some embodiments, reference Figures 1 to 12 The pores 102 in the first dielectric layer 101 are formed by heat treatment.

[0151] In some cases, the heat treatment process temperature is 800℃~1100℃.

[0152] In some cases, the heat treatment time is 20 to 60 minutes.

[0153] It should be noted that the reference Figure 6 In the case where the second dielectric layer 104 also has pores 102, the pores 102 in the second dielectric layer 104 can also be formed by heat treatment, and the parts that are the same as or corresponding to the first dielectric layer 101 will not be described again.

[0154] It is worth noting that, due to the heat treatment, the first dielectric layer 101 has pores 102, thus diversifying the transport paths of charge carriers within the first dielectric layer 101. This allows charge carriers to transport through the first dielectric layer 101 via both quantum tunneling and the pores 102, thereby improving the transport efficiency of charge carriers in the first dielectric layer 101. Compared to the existing technology that only transports charge carriers via quantum tunneling, the presence of pores 102 causes charge carriers to preferentially accumulate in the pore region, thus lengthening the transport path from the substrate to the electrode in the solar cell and further improving the transport efficiency. The aforementioned electrode can be either the first electrode or the second electrode described above.

[0155] In some examples, the heat treatment process temperature can be 800℃~890℃, for example, it can be 805℃, 815℃, 820℃, 825℃, 830℃, 835℃, 840℃, 845℃, 850℃, 855℃, 860℃, 865℃, 870℃, 875℃, 880℃ or 885℃, etc.

[0156] In other examples, the process temperature used for heat treatment can be 900℃~950℃ or 890℃~930℃, for example, it can be 880℃, 890℃, 895℃, 900℃, 905℃, 910℃, 915℃, 920℃, 925℃, 930℃, 935℃, 940℃ or 945℃, etc.

[0157] It is worth noting that, reference Figure 8 Compared to Figure 8 The arrangement density of pores 102 in the first dielectric layer 101 of the solar cell corresponding to Group 3 shown will be greater if the heat treatment process temperature is greater than 930℃ or 950℃. Therefore, the impedance corresponding to the reference transmission path will be more easily compared to 0.1mΩ·cm. 2 It's even lower, for example, than 0.05 mΩ·cm 2 It is still low, but requires more pores per unit area in the first dielectric layer. Although the fill factor of the solar cell is improved, it will reduce the passivation effect of the first dielectric layer on the substrate and reduce the open circuit voltage of the solar cell.

[0158] Compared to Figure 8 The arrangement density of pores 102 in the first dielectric layer 101 of the solar cell corresponding to Group 1 shown will be even lower if the annealing process temperature is less than 900℃ or 890℃, or the arrangement density of pores in the first dielectric layer of the final solar cell will be smaller. Figure 8 If the arrangement of pores 102 in the solar cell corresponding to Group 1 is sparse, then the impedance corresponding to the reference transmission path is easily 1.4 mΩ·cm. 2 Still higher, for example, equal to Figure 8 The value shown is 1.46 mΩ·cm 2 This will reduce the effect of the first dielectric layer 101 on improving the transmission efficiency of charge carriers in the first dielectric layer 101.

[0159] Therefore, the heat treatment process temperature is designed to be 900℃~950℃ or 890℃~930℃, which is beneficial for controlling the appropriate arrangement density of pores 102 in the first dielectric layer 101, thereby controlling the impedance corresponding to the reference transmission path to be within 0.1mΩ·cm. 2 ~1.3mΩ·cm 2Within a certain range, while relying on the low impedance corresponding to the reference transmission path to improve the transmission efficiency of carriers in the first dielectric layer 101, the first dielectric layer 101 is guaranteed to have a good passivation effect on the substrate 100.

[0160] In some other examples, the heat treatment process temperature can be 950℃~1100℃, for example, it can be 955℃, 960℃, 965℃, 970℃, 975℃, 980℃, 985℃, 990℃, 995℃, 1000℃, 1005℃, 1010℃, 1015℃, 1020℃, 1025℃, 1030℃, 1035℃, 1040℃, 1045℃, 1050℃, 1055℃, 1060℃, 1065℃, 1070℃, 1075℃, 1080℃, 1085℃, 1090℃ or 1095℃, etc.

[0161] In some embodiments, reference Figures 1 to 12 The transfer resistivity of the first dielectric layer 101 is 4 mΩ·cm 2 ~5mΩ·cm 2 It should be noted that the transmission resistivity of the first dielectric layer 101 refers to the transmission resistivity of the transmission path along the thickness direction of the first dielectric layer 101, from one side of the first dielectric layer 101 to the other side.

[0162] In some cases, compared to a first dielectric layer located in the first region that does not have the porosity described above, one embodiment of this application, by means of a designed first dielectric layer 101, can reduce the transmission resistivity of the first dielectric layer 101 by at least about 1 mΩ·cm. 2 ~2mΩ·cm 2 .

[0163] The first doped layer 103 will be described in detail below.

[0164] In some embodiments, reference Figures 1 to 12 The materials of the first dielectric layer 101 and the second dielectric layer 104 can both include one or more of silicon oxide, silicon carbide, silicon nitride, and silicon oxynitride. The materials of the first doped layer 103 and the second doped layer 105 can both include polycrystalline silicon doped with dopant elements. Based on this, the solar cell can be a TBC cell.

[0165] In other embodiments, reference is made to... Figures 1 to 12The material of the first dielectric layer 101 may include one or more of silicon oxide, silicon carbide, silicon nitride, and silicon oxynitride; the material of the first doped layer 103 may include polycrystalline silicon doped with a dopant element; the material of the second dielectric layer 104 may include one or more of amorphous silicon, microcrystalline silicon, and nanocrystalline silicon; and the material of the second doped layer 105 may include amorphous silicon or microcrystalline silicon doped with a dopant element. Based on this, the solar cell can be an HTBC cell.

[0166] In the various types of solar cells described above, the doping concentration of the dopant element in the first doped layer 103 can be 3 × 10⁻⁶. 20 atom / cm 3 ~7×10 20 atom / cm 3 For example, it can be 4×10 20 atom / cm 3 5×10 20 atom / cm 3 Or 6×10 20 atom / cm 3 wait.

[0167] It should be noted that the doping concentration of the dopant element in different regions of the first doped layer 103 can be basically the same, that is, the dopant element is uniformly doped in the first doped layer 103. In practical applications, the doping concentration of the dopant element in the first doped layer can gradually change along the direction from the first dielectric layer to the first doped layer, for example, gradually increasing or gradually decreasing. In addition, the first doped layer can be a single-layer structure or a multi-layer stacked structure.

[0168] In the various types of solar cells mentioned above, the sheet resistance of the first doped layer 103 can be 13Ω to 35Ω, for example, it can be 14Ω, 15Ω, 16Ω, 17Ω, 18Ω, 19Ω, 20Ω, 21Ω, 22Ω, 23Ω, 24Ω, 25Ω, 26Ω, 27Ω, 28Ω, 29Ω, 30Ω, 31Ω, 32Ω, 33Ω or 34Ω, etc.

[0169] In the various types of solar cells described above, the size of more than 80% of the grains within the first doped layer 103 can be between 150 nm and 300 nm, for example, 160 nm, 170 nm, 180 nm, 190 nm, 200 nm, 210 nm, 220 nm, 230 nm, 240 nm, 250 nm, 260 nm, 270 nm, 280 nm, or 290 nm. It is worth noting that the first doped layer 103 may contain grains with sizes outside the 150 nm to 300 nm range, but approximately 80% or more of the grains within the first doped layer 103 have sizes within the 150 nm to 300 nm range.

[0170] In some embodiments, reference Figure 3 or Figure 12 The solar cell may further include a third dielectric layer 107 located between the first dielectric layer 101 and the first doped layer 103. This allows the third dielectric layer 107 to enhance the blocking effect on doped elements in the first doped layer 103, thereby preventing excessive diffusion of doped elements into the first region 110.

[0171] In some cases, the material of the third dielectric layer 107 may include one or more of silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, amorphous silicon, microcrystalline silicon, and nanocrystalline silicon.

[0172] In some embodiments, reference Figure 3 or Figure 12 The solar cell may further include a fourth dielectric layer 108 located between the second dielectric layer 104 and the second doped layer 105. This allows the fourth dielectric layer 108 to enhance the blocking effect on dopants in the second doped layer 105, thus preventing excessive dopant from diffusing into the second region 120.

[0173] In some cases, the material of the fourth dielectric layer 108 may include one or more of silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, amorphous silicon, microcrystalline silicon, and nanocrystalline silicon.

[0174] In some embodiments, reference Figures 1 to 12 Regardless of whether the solar cell is a TBC cell or an HTBC cell, the first doped layer 103 can be an N-type conductivity region, and the second doped layer 105 can be a P-type conductivity region. In other words, the first doped layer 103 is doped with N-type dopant elements, and the second doped layer 105 is doped with P-type dopant elements. Based on this, only the first dielectric layer 101 has pores 102. The pores 102 allow electrons from the substrate 100 to pass through the first dielectric layer 101 and be transported to the first doped layer 103, realizing a transport mechanism where charge carriers are primarily transported via the pores 102.

[0175] In some embodiments, reference Figures 1 to 12 The solar cell is an HTBC cell, the second doped layer 105 can be an amorphous doped layer or a microcrystalline doped layer, and the second dielectric layer 104 can be an intrinsic amorphous silicon layer or a microcrystalline silicon layer.

[0176] In some cases, refer to Figure 1 or Figure 10Along the first direction X, the first doped layer 103 and the second doped layer 105 form an overlapping region in a local area of ​​the first region 110, with the second doped layer 105 located on the side of the first doped layer 103 away from the substrate 100. Therefore, the second doped layer 105 is located on the second region 120 and a portion of the first region 110, and the second doped layer 105 is discontinuously distributed in the first region 110.

[0177] In some cases, refer to Figure 1 or Figure 10 The second dielectric layer 104 is located on the second region 120 and on a portion of the surface of the first doped layer 103 on the side away from the substrate 100.

[0178] In some cases, refer to Figure 10 The solar cell may further include: a transparent conductive layer 169 located on the side of the second doped layer 105 away from the substrate 100, and there is a gap between the transparent conductive layer 169 located in the first region 110 and the transparent conductive layer 169 located in the second region 120.

[0179] Based on this, in the first electrode 119 and the second electrode 129 located on the side of the transparent conductive layer 169 away from the substrate 100, the first electrode 119 is located on the first region 110 and is in contact with the transparent conductive layer 169, and the second electrode 129 is located on the second region 120 and is in contact with the transparent conductive layer 169. In other words, the first electrode 119 may not be in contact with the first doped layer 103, and the second electrode 129 may not be in contact with the second doped layer 105.

[0180] In some embodiments, reference Figures 10 to 12 The solar cell may also include a first passivation layer 139 located on the front side 100a.

[0181] In some cases, refer to Figure 10 or Figure 11 The first passivation layer 139 can be a single film layer structure, for example, the first passivation layer 139 can be a silicon nitride layer.

[0182] In other cases, refer to Figure 12 The first passivation layer 139 can be a stacked structure. For example, the first passivation layer 139 can be a combined film of aluminum oxide layer and silicon nitride layer, with the aluminum oxide layer closer to the front side 100a.

[0183] In some embodiments, reference Figure 11 The solar cell may further include: a second passivation layer 149 located on the side of the first doped layer 103 away from the substrate 100, and on the side of the second doped layer 105 away from the substrate 100; and a third passivation layer 159 located on the isolation region 130.

[0184] In some embodiments, reference Figure 12 The solar cell may further include: a second passivation layer 149 located on the surface formed by the first doped layer 103, the second doped layer 105 and the back surface 100b; and a third passivation layer 159 located on the side of the second passivation layer 149 away from the substrate 100.

[0185] In the two embodiments described above, the second passivation layer 149 can be an aluminum oxide layer, and the third passivation layer 159 can be a silicon nitride layer.

[0186] In summary, the first dielectric layer 101 is designed to include multiple pores 102, with at least a portion of the pores 102 penetrating the first dielectric layer 101 along the first direction X. This improves the carrier transport mechanism within the first dielectric layer 101, specifically ensuring that carrier transport primarily occurs via the pores 102. In other words, most carriers will be transported to the first doped layer 103 via the substrate 100 and the portion of the first dielectric layer 101 containing the pores 102. For example, carriers can directly transport to the first doped layer 103 through the pores 102. A portion of carriers will also be transported to the first doped layer 103 via quantum tunneling through the portion of the first dielectric layer 101 without pores 102. Therefore, with carrier transport via pores as the primary transport mechanism in the first dielectric layer 101, the transport efficiency of carriers in the first dielectric layer 101 is improved, thereby enhancing the electrical performance of the solar cell. Moreover, if the temperature rises in a local area of ​​the solar cell, charge carriers can be transported faster through the pores 102 than in other areas of the first dielectric layer 101, thereby reducing the risk of thermal runaway of the solar cell.

[0187] Another embodiment of this application provides a method for manufacturing a solar cell, used to form the solar cell provided in the foregoing embodiment. The method for manufacturing a solar cell according to another embodiment of this application will be described in detail below with reference to the accompanying drawings. It should be noted that parts that are the same as or corresponding to those in the foregoing embodiment will not be repeated here.

[0188] refer to Figures 19 to 20 ,as well as Figures 1 to 5 The manufacturing method of solar cells includes at least the following steps: (Refer to...) Figure 19 A substrate 100 is provided, the substrate 100 having a front side 100a and a back side 100b opposite each other along a first direction X, the back side 100b having a first region 110 and a second region 120 alternately arranged along a second direction Y; in conjunction with reference Figures 19 to 20 ,as well as Figures 1 to 5A first dielectric layer 101 and a first doped layer 103 are formed on a first region 110; wherein the first dielectric layer 101 includes a plurality of pores 102, at least a portion of which penetrate the first dielectric layer 101 along a first direction X; the first doped layer 103 and the substrate 100 have doping elements of the same conductivity type; charge carriers in the substrate 100 are transported along the first direction X via the first dielectric layer 101 to the first doped layer 103; Reference Figures 1 to 3 A second dielectric layer 104 is formed at least on the second region 120, and a second doped layer 105 is formed on the side of the second dielectric layer 104 away from the second region 120. The second doped layer 105 and the substrate 100 have dopants with different conductivity types.

[0189] in, Figure 19 A schematic cross-sectional view of a substrate in a method for manufacturing a solar cell according to another embodiment of this application; Figure 20 This is an enlarged cross-sectional view of a method for manufacturing a solar cell according to another embodiment of this application, after the initial first dielectric layer and the first semiconductor layer have been formed.

[0190] It is worth noting that in the solar cell formed by the manufacturing method of the solar cell provided in another embodiment of this application, the first dielectric layer 101 includes a plurality of pores 102, and at least a portion of the pores 102 penetrate the first dielectric layer 101 along the first direction X, so that the transport mechanism of charge carriers in the first dielectric layer 101 is mainly achieved by means of pores 102, which is beneficial to increase the thickness fluctuation range of the first dielectric layer 101, that is, to increase the process window when preparing the first dielectric layer 101. At the same time, most of the portions of the first dielectric layer 101 that do not have pores 102 can ensure that the first dielectric layer 101 has good passivation performance for the substrate 100.

[0191] In some cases, the carrier transport path along the first direction X via the substrate 100, the first dielectric layer 101, and the first doped layer 103 is considered a reference transport path. The transport resistance corresponding to this reference transport path in at least a portion of the solar cells increases with the temperature of the solar cell. Consequently, the carrier transport efficiency in the first dielectric layer 101 decreases with increasing temperature of the first dielectric layer 101.

[0192] Based on this, the transmission resistance corresponding to the reference transmission path in at least a portion of the solar cells increases with the increase of the solar cell temperature. That is, the carrier transmission efficiency in the first dielectric layer 101 decreases with the increase of the temperature of the first dielectric layer 101. In this way, on the one hand, it is beneficial to ensure that the solar cell has a high photoelectric conversion efficiency at a lower temperature. On the other hand, if the temperature of the first dielectric layer 101 increases, the transmission resistance corresponding to the reference transmission path increases, that is, the characteristic that the carrier transmission efficiency is suppressed at higher temperatures, which can reduce the current in the local area of ​​the solar cell, thereby helping to reduce the risk of thermal runaway of the solar cell. Furthermore, by taking advantage of the temperature difference and the characteristic that the transmission resistance corresponding to the reference transmission path in the high-temperature region of the solar cell increases, or by taking advantage of the characteristic that the carrier transmission efficiency in the high-temperature region of the solar cell decreases, the uniform distribution of current in the solar cell can be promoted, thereby further reducing the risk of thermal runaway of the solar cell.

[0193] The following is formed Figure 1 The HTBC cell shown is an example to illustrate the manufacturing method of solar cells in detail.

[0194] In some embodiments, the steps of forming the first dielectric layer 101 and the first doped layer 103 include: combining with a reference Figure 19 and Figure 20 An initial first dielectric layer 131 is formed on the back surface 100b, and a first semiconductor layer 113 is formed on the side of the initial first dielectric layer 131 away from the substrate 100. The first semiconductor layer 113 can be amorphous silicon or polycrystalline silicon; refer to the reference. Figure 19 and Figure 20 The first semiconductor layer 113 is subjected to doping treatment (e.g., phosphorus diffusion treatment) and heat treatment, which causes the first semiconductor layer 113 to be doped with doping elements and crystallized, so that the first semiconductor layer 113 is transformed into polycrystalline silicon doped with doping elements, i.e., the first doped film; and in the heat treatment step, pores 102 are formed in the initial first dielectric layer 131, so that the initial first dielectric layer 131 is transformed into a first dielectric film with multiple pores 102.

[0195] It should be noted that in practical applications, a first dielectric film with pores can be formed on the substrate first, and then a first doped film can be formed directly on the first dielectric film.

[0196] Furthermore, the first dielectric film and the first doped film are patterned, for example by laser grooving, to remove the first dielectric film and the first doped film located on the second region 120. The remaining first dielectric film located on the first region 110 is used as the first dielectric layer 101, and the remaining first doped film located on the first region 110 is used as the first doped layer 103.

[0197] In some cases, the heat treatment process temperature is 800℃~1100℃. Preferably, the heat treatment process temperature can be 900℃~950℃ or 890℃~930℃, for example, 895℃, 900℃, 905℃, 910℃, 915℃, 920℃, 925℃, 930℃, 935℃, 940℃ or 945℃, etc.

[0198] It is worth noting that, reference Figure 8 Compared to Figure 8 The arrangement density of pores 102 in the first dielectric film of the solar cell corresponding to Group 3 shown will be even greater if the heat treatment process temperature is greater than 930℃ or 950℃. Therefore, the impedance corresponding to the reference transmission path will be more easily compared to 0.1mΩ·cm. 2 It's even lower, for example, than 0.05 mΩ·cm 2 It is still low, but requires a greater number of pores per unit area in the first dielectric layer. Although the fill factor of the solar cell is improved, it will reduce the passivation effect of the dielectric layer on the substrate and reduce the open-circuit voltage of the solar cell.

[0199] Compared to Figure 8 The arrangement density of pores 102 in the first dielectric layer 101 of the solar cell corresponding to Group 1 shown will be even lower if the heat treatment process temperature is less than 900℃ or 890℃, or the arrangement density of pores in the first dielectric layer of the final solar cell will be smaller, or the same as... Figure 8 If the arrangement of pores 102 in the solar cell corresponding to Group 1 is sparse, then the impedance corresponding to the reference transmission path is easily 1.4 mΩ·cm. 2 Still higher, for example, equal to Figure 8 The value shown is 1.46 mΩ·cm 2 This will reduce the effect of the first dielectric layer 101 on improving the transmission efficiency of charge carriers in the first dielectric layer 101.

[0200] Therefore, the heat treatment process temperature is designed to be 900℃~950℃ or 890℃~930℃, which is beneficial for controlling the appropriate arrangement density of pores 102 in the first dielectric layer 101, thereby controlling the impedance corresponding to the reference transmission path to be within 0.1mΩ·cm. 2 ~1.3mΩ·cm 2 Within a certain range, while relying on the low impedance corresponding to the reference transmission path to improve the transmission efficiency of carriers in the first dielectric layer 101, the first dielectric layer 101 is guaranteed to have a good passivation effect on the substrate 100.

[0201] In some cases, the heat treatment time can be 20 min to 60 min, for example, 21 min, 22 min, 23 min, 24 min, 25 min, 26 min, 27 min, 28 min, 29 min, 30 min, 31 min, 32 min, 33 min, 34 min, 35 min, 36 min, 37 min, 38 min, 39 min, 40 min, 41 min, 42 min, 43 min, 44 min, 45 min, 46 min, 47 min, 48 min, 49 min, 50 min, 51 min, 52 min, 53 min, 54 min, 55 min, 56 min, 57 min, 58 min, or 59 min, etc.

[0202] In some cases, the initial first dielectric layer 131 can be formed using a PECVD (Plasma Enhanced Chemical Vapor Deposition) process. In some examples, the thickness of the initial first dielectric layer 131 along the first direction X can be 1 nm to 3 nm, for example, it can be 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, 1.9 nm, 2 nm, 2.1 nm, 2.2 nm, 2.3 nm, 2.4 nm, 2.5 nm, 2.6 nm, 2.7 nm, 2.8 nm, or 2.9 nm, etc.

[0203] In some cases, a deposition process can be used to form the first semiconductor layer 113.

[0204] In some examples, the deposition process for forming the first semiconductor layer 113 can be PECVD, LPCVD (Low Pressure Chemical Vapor Deposition), or ALD (Atomic Layer Deposition), etc.

[0205] In some examples, the thickness of the first semiconductor layer 113 along the first direction X can be less than or equal to 150 nm. Preferably, the thickness of the first semiconductor layer 113 can be 60 nm to 100 nm, for example, it can be 62 nm, 65 nm, 67 nm, 70 nm, 72 nm, 75 nm, 78 nm, 80 nm, 83 nm, 85 nm, 88 nm, 90 nm, 93 nm, 95 nm, or 98 nm, etc.

[0206] In some embodiments, the step of forming the second dielectric layer 104 and the second doped layer 105 includes: forming a second dielectric film and a second doped film on the surface jointly formed by the first dielectric layer 101, the first doped layer 103, and the back surface 100b; Reference Figure 1 The second dielectric film and the second doped film are patterned, for example by laser grooving, to remove part of the second dielectric film and the second doped film located on the first region 110 to expose part of the surface of the first doped layer 103. The remaining second dielectric film located on the second region 120 and part of the first region 110 is used as the second dielectric layer 104, and the remaining second doped film located on the second region 120 and part of the first region 110 is used as the second doped layer 105.

[0207] It should be noted that the reference Figure 6 In the case where the second dielectric layer 104 also has pores 102, the step of forming the second dielectric film includes: forming an initial second dielectric layer on the surface formed by the first dielectric layer 101, the first doped layer 103 and the back surface 100b, and performing the same heat treatment on the initial second dielectric layer as on the initial first dielectric layer 131 to form a second dielectric film with pores.

[0208] Further reference Figure 1 An initial transparent conductive layer is formed on the surface formed by the second dielectric layer 104, the second doped layer 105, and the exposed first doped layer 103. The initial transparent conductive layer is patterned, for example by laser grooving, to form a transparent conductive layer 169 located on the first region 110 and a transparent conductive layer 169 located on the second region 120, with a gap between the transparent conductive layer 169 located in the first region 110 and the transparent conductive layer 169 located in the second region 120.

[0209] In some embodiments, providing substrate 100 may include the following steps: providing an initial substrate, wherein the initial substrate is doped with a first dopant element. In some examples, the resistivity of the initial substrate may be 0.3 Ω·cm to 7 Ω·cm; and texturing the initial substrate on both sides to form a pyramid textured surface. In some examples, the size of the pyramid may be 0.5 μm to 3 μm.

[0210] The emitter is formed on the front side of the initial substrate. In some examples, the initial substrate is doped with an N-type dopant, and the emitter is a P+ emitter, i.e., a boron-doped emitter. The boron doping concentration in the P+ emitter can be 1 × 10⁻⁶. 18 atom / cm 3 ~1×10 19 atom / cm 3The sheet resistance of the P+ emitter can be 300Ω / sq~500Ω / sq, preferably 350Ω / sq~450Ω / sq.

[0211] The back side of the initial substrate is polished. In some examples, silicon oxide is formed on the back side of the initial substrate in the aforementioned process. The back side silicon oxide is first removed using a single-sided chain device with hydrofluoric acid, and then the back side is alkaline polished to remove edge junctions and back side plating. Finally, a cleaning process is performed.

[0212] In some embodiments, after forming the second doped layer 105, the method for manufacturing a solar cell may further include: forming electrode pastes on the first region 110 and the second region 120 respectively using a screen printing process, and then metallizing the electrode pastes to form a first electrode 119 that is in contact with the first doped layer 103 and a second electrode 129 that is in contact with the second doped layer 105.

[0213] Finally, the manufactured solar cells are tested, sorted, and stored.

[0214] Another embodiment of this application provides a photovoltaic module for converting received light energy into electrical energy. The photovoltaic module provided in another embodiment of this application will be described in detail below with reference to the accompanying drawings. It should be noted that parts that are the same as or corresponding to those in the foregoing embodiments will not be repeated here.

[0215] Reference Figure 21 and Figure 22 ,as well as Figures 1 to 20 The photovoltaic module includes: a battery string, which is formed by connecting multiple solar cells 40 provided in the foregoing embodiments, or by connecting multiple solar cells 40 formed by the manufacturing method of the solar cells provided in the foregoing embodiments; an encapsulating film 41 for covering the surface of the battery string; and a cover plate 42 for covering the surface of the encapsulating film 41 facing away from the battery string.

[0216] in, Figure 21 A partial three-dimensional schematic diagram of a cell string in a photovoltaic module provided in another embodiment of this application; Figure 22 This is a partial cross-sectional schematic diagram of a photovoltaic module provided in another embodiment of this application.

[0217] In some embodiments, the solar cell 40 is electrically connected in the form of a single sheet or multiple segments to form multiple cell strings, and the multiple cell strings are electrically connected in series and / or parallel. The solar cell 40 can be a single cell or a sliced ​​cell, where a sliced ​​cell refers to a cell formed by cutting a complete single cell.

[0218] In some embodiments, in conjunction with reference Figure 21and Figure 22 Multiple solar cells 40 can be electrically connected through conductive strips 43. Figure 21 and Figure 22 The illustration only shows one positional relationship between the solar cells 40, where the sides of the solar cells 40 with grid lines are arranged facing the same side, so that the conductive strip 43 connects the same side of two adjacent solar cells 40 respectively. In other embodiments, the solar cells may also be arranged with the grid lines of adjacent solar cells facing different sides, in which case the conductive strip connects two adjacent solar cells on different sides.

[0219] In some embodiments, the encapsulating film 41 includes a first encapsulating layer and a second encapsulating layer. The first encapsulating layer covers one of the front or back sides of the solar cell 40, and the second encapsulating layer covers the other of the front or back sides of the solar cell 40. Specifically, at least one of the first or second encapsulating layer can be an organic encapsulating film such as polyvinyl butyral (PVB) film, ethylene-vinyl acetate copolymer (EVA) film, polyvinyl octene elastomer (POE) film, or polyethylene terephthalate (PET) film. Alternatively, at least one of the first or second encapsulating layer can also be an EP film, an EPE film, or a PVP film. Here, EP film refers to a co-extruded film composed of stacked EVA film and POE film; EPE film refers to a co-extruded film formed by sequentially stacking EVA film + POE film + EVA film; and PVP film refers to a co-extruded film formed by stacking POE film + EVA film + POE film. Co-extruded films can be prepared by sequentially extruding one or more raw materials onto another pre-made film during the film processing, or by bonding different types of pre-made films together.

[0220] In some cases, the first encapsulation layer and the second encapsulation layer still have a boundary line before lamination. After lamination, the photovoltaic module will no longer have the concept of a first encapsulation layer and a second encapsulation layer. That is, the first encapsulation layer and the second encapsulation layer have formed an integral encapsulation film 41.

[0221] In some embodiments, the cover plate 42 can be a glass cover plate, a plastic cover plate, or other cover plate with light-transmitting function. Specifically, the surface of the cover plate 42 facing the encapsulating film 41 can be an uneven surface or a textured surface containing multiple raised structures, thereby increasing the utilization rate of incident light. The cover plate 42 includes a first cover plate and a second cover plate, the first cover plate being opposite to the first encapsulation layer, and the second cover plate being opposite to the second encapsulation layer.

[0222] Those skilled in the art will understand that the above-described embodiments are specific examples of implementing this application, and in practical applications, various changes can be made in form and detail without departing from the spirit and scope of the embodiments of this application. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of this application; therefore, the scope of protection of the embodiments of this application should be determined by the scope defined in the claims.

Claims

1. A solar cell, characterized in that, include: A substrate having a front and a back facing each other along a first direction, the back having a first region and a second region alternately arranged along a second direction; A first dielectric layer is located on the first region. The first dielectric layer includes a plurality of pores, at least a portion of which penetrate the first dielectric layer along the first direction. The pore density in the first dielectric layer is 1×10⁻⁶. 6 pcs / cm 2 ~1×10 8 pcs / cm 2 ; A first doped layer is located on the side of the first dielectric layer away from the substrate, and the first doped layer and the substrate have doping elements of the same conductivity type. A second dielectric layer is located at least on the second region; The second doped layer is located on the side of the second dielectric layer away from the substrate, and the second doped layer has the opposite conductivity type to the first doped layer.

2. The solar cell according to claim 1, characterized in that, The transport path of charge carriers along the first direction through the substrate, the first dielectric layer and the first doped layer is a reference transport path, and the transport resistance corresponding to the reference transport path in at least a portion of the solar cells increases with the increase of the temperature of the solar cell.

3. The solar cell according to claim 1, characterized in that, The second dielectric layer is a tunneling layer, through which charge carriers are transported to the second doped layer via the substrate and the second dielectric layer; The transport path of the charge carriers along the first direction via the substrate, the second dielectric layer, and the second doped layer is a control transport path, and the transport resistance corresponding to the control transport path decreases as the temperature of the solar cell increases.

4. The solar cell according to claim 1, characterized in that, The second dielectric layer also includes a plurality of the aforementioned pores, at least a portion of which penetrate the second dielectric layer along the first direction; Wherein, the transport path of charge carriers along the first direction in the substrate, the first dielectric layer and the first doped layer is one of the reference transport paths, and the transport path of charge carriers along the first direction in the substrate, the second dielectric layer and the second doped layer is another of the reference transport paths.

5. The solar cell according to claim 1, characterized in that, The first dielectric layer includes a first portion having the pores and a second portion not having the pores, wherein the current density in the first portion is greater than the current density in the second portion.

6. The solar cell according to claim 5, characterized in that, The ratio of the current density in the first part to the current density in the second part is greater than or equal to 10.

7. The solar cell according to claim 5, characterized in that, The transport path of charge carriers along the first direction via the substrate, the first dielectric layer, and the first doped layer is a reference transport path. The reference transport path includes a first reference transport path and a second reference transport path, wherein the transport path of charge carriers via the substrate, the first portion, and the first doped layer is the first reference transport path; and / or, the transport path of charge carriers via the substrate, the second portion, and the first doped layer is the second reference transport path.

8. The solar cell according to claim 7, characterized in that, The transmission resistance corresponding to the first reference transmission path increases as the temperature of the solar cell increases; and / or, the transmission resistance corresponding to the second reference transmission path decreases as the temperature of the solar cell increases.

9. The solar cell according to claim 2 or 4, characterized in that, The impedance corresponding to the reference transmission path is 0.05 mΩ·cm. 2 ~1.4mΩ·cm 2 .

10. The solar cell according to claim 1, characterized in that, At least a portion of the pores contain the substrate and / or the first doped layer; and / or, at least a portion of the pores have air gaps.

11. The solar cell according to claim 1, characterized in that, The temperature range of the first dielectric layer is -50℃ to 150℃.

12. The solar cell according to claim 1, characterized in that, A diffusion layer is further disposed between the substrate and the first dielectric layer, and the diffusion layer and the first doped layer have doping elements of the same conductivity type.

13. The solar cell according to claim 1, characterized in that, The pores in the first dielectric layer are formed by heat treatment; wherein the heat treatment is performed at a process temperature of 800°C to 1100°C; and / or the heat treatment lasts for 20 min to 60 min.

14. The solar cell according to claim 1, characterized in that, An isolation zone is set up between the first area and the second area.

15. The solar cell according to claim 1, characterized in that, The materials of the first dielectric layer and the second dielectric layer include one or more of silicon oxide, silicon carbide, silicon nitride, and silicon oxynitride; or, the material of the first dielectric layer includes one or more of silicon oxide, silicon carbide, silicon nitride, and silicon oxynitride, and the material of the second dielectric layer includes one or more of intrinsic amorphous silicon, amorphous silicon oxide, microcrystalline silicon, and nanocrystalline silicon.

16. The solar cell according to claim 1, characterized in that, The doping concentration of the dopant element in the first doped layer is 3 × 10⁻⁶. 20 atom / cm 3 ~7×10 20 atom / cm 3 ; and / or, the sheet resistance of the first doped layer is 13Ω~35Ω; and / or, the size of more than 80% of the grains in the first doped layer is 150nm~300nm.

17. The solar cell according to claim 1, characterized in that, The transfer resistivity of the first dielectric layer is 4 mΩ·cm 2 ~5mΩ·cm 2 .

18. The solar cell according to claim 1, characterized in that, Also includes: The third dielectric layer is located between the first dielectric layer and the first doped layer; And / or, a fourth dielectric layer, located between the second dielectric layer and the second doped layer.

19. The solar cell according to claim 1, characterized in that, The first doped layer is an N-type conductivity region, the second doped layer is a P-type conductivity region, and the pores are only present in the first dielectric layer. The pores are used to allow electrons in the substrate to pass through the first dielectric layer and be transported to the first doped layer.

20. The solar cell according to claim 1, characterized in that, The second doped layer is an amorphous doped layer or a microcrystalline doped layer, and the second dielectric layer is an intrinsic amorphous silicon layer or a microcrystalline silicon layer.

21. The solar cell according to claim 1, characterized in that, Along the first direction, the first doped layer and the second doped layer form an overlapping region in a local area of ​​the first region, and the second doped layer located on the overlapping region is located on the side of the first doped layer away from the substrate.

22. The solar cell according to claim 1, characterized in that, Also includes: A transparent conductive layer is located on the side of the second doped layer away from the substrate, and there is a gap between the transparent conductive layer located in the first region and the transparent conductive layer located in the second region; A first electrode and a second electrode are located on the side of the transparent conductive layer away from the substrate. The first electrode is located on the first region and is in contact with the transparent conductive layer, and the second electrode is located on the second region and is in contact with the transparent conductive layer.

23. The solar cell according to claim 1, characterized in that, The second doped layer is located on the second region and on a portion of the first region, and the second doped layer is discontinuously distributed in the first region.

24. The solar cell according to claim 1, characterized in that, The first dielectric layer is a silicon oxide layer or a silicon oxynitride layer, and the second dielectric layer is an intrinsic amorphous silicon layer or an intrinsic microcrystalline silicon layer with a thickness of 1 nm to 5 nm.

25. The solar cell according to claim 1, characterized in that, The second dielectric layer is located on the second region and on a portion of the surface of the first doped layer on the side away from the substrate.

26. The solar cell according to claim 1, characterized in that, Charge carriers are transported along the first direction through the substrate, the first dielectric layer, and to the first doped layer. The transport efficiency of the charge carriers in at least a portion of the first dielectric layer decreases as the temperature of the first dielectric layer increases.

27. The solar cell according to claim 1, characterized in that, The second dielectric layer is a tunneling layer, through which charge carriers are transported to the second doped layer via the substrate and the second dielectric layer; The transport path of the charge carriers along the first direction via the substrate, the second dielectric layer, and the second doped layer is the control transport path, and the transport efficiency of the charge carriers in the second dielectric layer increases with the increase of the temperature of the first dielectric layer.

28. The solar cell according to claim 1, characterized in that, The second dielectric layer also includes a plurality of the aforementioned pores, at least a portion of which penetrate the second dielectric layer along the first direction; In this process, the majority of the charge carriers are transported along the first direction through the substrate and the first dielectric layer to the first doped layer, and the minority of the charge carriers are transported along the first direction through the substrate and the second dielectric layer to the second doped layer.

29. A photovoltaic module, characterized in that, include: A battery string, comprising a plurality of solar cells connected together as described in any one of claims 1 to 28; An encapsulating film is used to cover the surface of the battery string; A cover plate is used to cover the surface of the encapsulating film that faces away from the battery string.

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