Memory system for generating parity check code using random generator

Abstract

Aspects of the present disclosure provide a memory system. For example, a memory system may include a memory device configured to store data and one or more parity codes. The memory system may also include a random generator configured to generate a sequence of pseudo-random numbers using a random generator seed in response to the clock signal according to a predetermined rule. The memory system may also include a codec coupled to the memory device and the random generator. The codec may be configured to generate one or more parity check codes from the pseudo-random number and the data. The parity code is to be written to the memory device when the write operation is performed, and is to be used to recover at least one of the data stored in the memory device when the read operation is performed and the at least one of the data is incorrect.

Description

Technical Field

[0001] This application describes embodiments generally related to semiconductor memory devices. Background Art

[0002] As semiconductor devices (such as semiconductor memory devices) become more powerful, a consistent trend is to increase the amount of data to be transferred per period of time. For example, modern semiconductor memory devices may require data to be written to and read from them at high speeds.

[0003] As the critical dimensions of devices in integrated circuits shrink to the limits of conventional memory cell technology, designers have been seeking techniques for stacking multiple planes of memory cells to achieve greater storage capacity and lower cost per bit. Three-dimensional (3D) NAND memory devices are an example of devices that stack multiple planes of memory cells to achieve greater storage capacity and lower cost per bit. 3D NAND memory devices may include a stack of alternating insulating layers and wordline layers above a substrate and trenches. Summary of the Invention

[0004] Aspects of the present disclosure provide a memory system. For example, the memory system may include a memory device configured to store data and one or more parity codes. The memory system may also include a random generator configured to generate a sequence of pseudo-random numbers using a random generator seed in response to a clock signal according to predetermined rules. The memory system may also include a codec coupled to the memory device and the random generator. The codec may be configured to generate one or more parity codes based on the pseudo-random numbers and the data. The parity code may be written to the memory device when a write operation is performed, and may be used to recover at least one of the data stored in the memory device when a read operation is performed and at least one of the data is incorrect.

[0005] In one embodiment, the codec may be configured to generate a parity code by multiplying a pseudo-random number by data and performing a bitwise logical operation of the multiplication of the pseudo-random number and the data. In another embodiment, the codec may be configured to generate a plurality of parity codes, and the random generator may be configured to generate a sequence of pseudo-random numbers using a random generator seed in response to each number of clocks of the clock signal according to a predetermined rule.

[0006] In one embodiment, the random generator seed may be selected based on the data and the pseudo-random number. In another embodiment, the random generator may include a linear feedback shift register (LFSR). For example, the LFSR may be specified by a primitive polynomial. In some embodiments, the LFSR may include a first number of cascaded shift registers, the data may include a second number of pages, the one or more parity check codes may include a third number of parity check codes, and the first number to the power of two may be greater than the second number minus one multiplied by the third number minus one.

[0007] Aspects of the present disclosure also provide a method for controlling a memory system. For example, the method may include: generating a sequence of pseudo-random numbers using a random generator seed in response to a clock signal according to a predetermined rule using a random generator, receiving data to be stored in a memory device, generating one or more parity codes based on the pseudo-random numbers and the data, and writing the parity codes and the data to the memory device when performing a write operation, and recovering at least one of the data stored in the memory device using the one or more parity codes when performing a read operation and at least one of the data stored in the memory device is incorrect.

[0008] Aspects of the present disclosure also provide a memory controller. For example, the memory controller may include a random generator configured to generate a sequence of pseudo-random numbers using a random generator seed in response to a clock signal according to predetermined rules. The memory controller may also include a codec coupled to the random generator. The codec may be configured to generate one or more parity codes based on the pseudo-random numbers and data to be stored in the memory device. The parity code may be written to the memory device when a write operation is performed, and may be used to recover at least one of the data stored in the memory device when a read operation is performed and at least one of the data is incorrect. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The following detailed description may be read in conjunction with the accompanying drawings to better understand aspects of the present disclosure. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0010] Figure 1 is a functional block diagram of an example of a system according to some embodiments of the present disclosure.

[0011] Figure 2A is a schematic diagram of a system's memory controller and memory devices integrated into a memory card.

[0012] Figure 2Bis a schematic diagram of a system in which a memory controller and more than one memory device are integrated into a memory card.

[0013] Figure 3 is a schematic circuit diagram of an example of a memory device according to some embodiments of the present disclosure.

[0014] Figure 4 is a functional block diagram of an example of a memory system according to some embodiments of the present disclosure.

[0015] Figure 5A is a circuit diagram of an example of a 4-bit linear feedback shift register (LFSR) according to some embodiments of the present disclosure.

[0016] Figure 5B The operation of the LFSR is shown.

[0017] Figure 5C Lists the pseudo-random numbers generated by the LFSR.

[0018] Figure 6A and Figure 6B The 64 elements of the gflog and gfilog tables are listed in hexadecimal format.

[0019] Figure 7 The polynomial matrix is shown.

[0020] Figure 8A It is shown that the Vandermonde matrix has geometric series terms in each row.

[0021] Figure 8B The Vandermonde matrix is shown.

[0022] Figures 9A-9D It is shown that n blocks of data are encoded by using a polynomial matrix to generate a parity check code and recover some of the data that is stored and affected and incorrect.

[0023] Figures 10A-10F It is shown that n data blocks are encoded to generate a parity-check code by using a polynomial matrix that can be specified by a random generator according to some embodiments of the present disclosure.

[0024] Figures 11A-11H It is shown that some affected and incorrect data among the data D0-D5 are decoded (or recovered) by using a random generator according to some embodiments of the present disclosure.

[0025] Figure 12 is a functional block diagram of an example of a memory system according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0026] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may repeat figure numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or configurations discussed.

[0027] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc., may be used herein to describe the relationship of one element or feature to another (or multiple) elements or features as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should similarly be interpreted accordingly.

[0028] In modern storage systems, Redundant Array of Independent Disks (RAID) technology is known to be the preferred technology for achieving high performance and high reliability. The most common RAID technology is RAID 5 (block-level striping with single distributed parity), which can tolerate one failed disk. RAID-6 (block-level striping with double distributed parity) can tolerate two failed disks and offers the best balance between storage efficiency and reliability.

[0029] Figure 11 is a functional block diagram of an example of a system 10 according to some embodiments of the present disclosure. In one embodiment, the system 10 may include a memory system 100 and a host device 190. The system 10 may be included in an electronic device, such as a mobile phone, virtual reality (VR), a game console, a wearable electronic device, a computer (such as a desktop computer, a laptop computer, a tablet computer, and a car computer), or any other electronic device. In some embodiments, the host device 190 may be a processor (e.g., a central processing unit (CPU)) or a system on a chip (SoC) (e.g., an application processor (AP)) of the electronic device in which the system 10 is included. The host device 190 may be configured to follow a corresponding protocol (e.g., NVMe, PCIe, etc.). The host device 190 may also be configured to send data to the memory system 100 and receive data from the memory system 100. In one embodiment, the host device 190 may send instructions to the memory system 100 in addition to data.

[0030] refer to Figure 1 According to some embodiments, memory controller 140 is coupled to memory device 110 and host device 190 via host interfaces 130A and 130A′ and memory interfaces 130B and 130B′, respectively, and is configured to control memory device 110. Memory controller 140 may be implemented by a microprocessor, a microcontroller (also known as a microcontroller unit (MCU), which may include one or more processing cores), a central processing unit (CPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a programmable logic device (PLD), a state machine, a gated logic unit, a discrete hardware circuit, or a combination thereof, as well as other suitable hardware, firmware, and / or software configured to perform various functions described in detail below. For example, memory controller 140 may include MCU 141, which includes processing core 142.

[0031] The memory controller 140 can manage data stored in the memory device 110 and communicate with the host device 190. In some embodiments, the memory controller 140 can be designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 140 can be designed to operate in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC), which is used as a data storage device for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays. The memory controller 140 can be configured to control the operations of the memory device 110 (e.g., read operations, erase operations, and program operations).

[0032] The memory controller 140 may communicate with an external device (e.g., the host device 190) according to a specific communication protocol. For example, the memory controller 140 may communicate with the external device through at least one of various interface protocols (e.g., a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer miniature interface (SCSI) protocol, an enhanced minidisk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a FireWire protocol, etc.).

[0033] In some embodiments, the memory controller 140 may receive a write command (also referred to as a program command), a read command, an erase command, etc. from the host device 190, and accordingly perform corresponding operations on the memory device 110. For example, the memory controller 140 may receive a write command with an address (ADDR) and data (DATA) from the host device 190, and then perform a write operation by storing the data at the address in the memory device 110. As another example, the memory controller 140 may receive a read command with an address from the host device 190, and then perform a read operation by accessing the memory device 110 and outputting the data stored at the address in the memory device 110. In various embodiments, the memory controller 140 may receive an erase command with an address from the host device 190, and then perform an erase operation by resetting one or more blocks of memory cells at the address to an unprogrammed state (also referred to as an erased state).

[0034] The memory controller 140 may also be configured to manage various functions regarding data stored or to be stored in the memory device 110, including, but not limited to, bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 140 may also be configured to process error correction code (ECC) regarding data read from or written to the memory device 110. The memory controller 140 may also perform any other suitable functions, such as, for example, formatting the memory device 110.

[0035] In some embodiments, the memory device 110 and the memory controller 140 may be integrated into various types of storage packages (e.g., Universal Flash Storage (UFS) or Embedded Multimedia Card (eMMC)) and included in various types of electronic devices. Figure 2A As shown, the memory controller 140 and one of the memory devices 110 may be integrated into the memory card 200A. The memory card 200A may include a PC card (e.g., Personal Computer Memory Card International Association (PCMCIA)), a Compact Flash (CF) card, a Smart Media (SM) card, a memory stick, a Secure Digital (SD) card (e.g., SD, miniSD, microSD, SD High Capacity (SDHC)), a Universal Flash Storage (UFS), etc. The memory card 200A may also include a processor for coupling the memory card 200A to a host device (e.g., Figure 1 As another example, the memory card connector 210A of the host device 190 shown in FIG. Figure 2B As shown, the memory controller 140 and more than one of the memory devices 110 (e.g., six memory devices 110) may be included in a solid-state drive (SSD) 200B. The SSD 200B may also include a host device (e.g., Figure 1 190 ).

[0036] In some embodiments, memory system 100 may include a memory controller 140 and a memory device 110. Memory device 110 may be any type of memory device disclosed herein, such as a NAND memory device. In one embodiment, memory device 110 may include a memory cell array 160 and peripheral circuitry 120 coupled to memory cell array 160. In some embodiments, memory cell array 160 and peripheral circuitry 120 may be provided on the same die (chip). In other embodiments, memory cell array 160 may be provided on an array die, while peripheral circuitry 120 may be provided on a different die (e.g., a die implemented using complementary metal oxide semiconductor (CMOS) technology and referred to as a CMOS die). The array die and CMOS die may be appropriately bonded and electrically coupled to each other. In some embodiments, a CMOS die may be coupled to multiple array dies. In some embodiments, an array die may be coupled to multiple CMOS dies. In one embodiment, memory device 110 may be an integrated circuit (IC) package that encapsulates one or more array dies and one or more CMOS dies.

[0037] In general, the memory device 110 may include one or more memory cell arrays 160, and each memory cell array in the memory cell array 160 may include multiple memory planes. Each memory plane in the multiple memory planes may include multiple memory blocks, for example, memory blocks blk-1 to blk-n. In some embodiments, simultaneous operations may be performed at different memory planes. In one embodiment, each memory block in memory blocks blk-1 to blk-n is the minimum unit for performing an erase operation. Each memory block in memory blocks blk-1 to blk-n may include multiple pages. In some embodiments, a page is the minimum unit that can be programmed (i.e., written) or read.

[0038] Figure 3 is a memory device 300 (eg, Figure 1 3. The memory device 300 may include a memory cell array 310 (eg, Figure 1 ) and the peripheral circuit 330 (e.g., Figure 1 The memory cell array 310 may include one or more memory planes, and each of the memory planes may include a plurality of memory blocks 315, such as Figure 1. The memory cell array 310 may be a NAND memory cell array in which memory cells 311 are provided in the form of an array of NAND memory strings 312, each NAND memory string 312 extending vertically above a substrate (not shown). In some embodiments, each of the NAND memory strings 312 may include a plurality of memory cells 311 coupled in series and stacked vertically on top of each other above the substrate. Each of the memory cells 311 may maintain a continuous analog value, such as a voltage or charge, depending on the number of electrons trapped in the region of the memory cell 311. Each of the memory cells 311 may be a floating type memory cell including a floating gate transistor or a charge trapping type memory cell including a charge trapping transistor.

[0039] In some embodiments, each of the memory cells 311 may be a single-level cell (SLC) having two possible storage states and thus capable of storing one bit of data. For example, the first storage state "0" may correspond to a first voltage range, and the second storage state "1" may correspond to a second voltage range. In some embodiments, each of the memory cells 311 may be a multi-level cell (MLC) capable of storing at least two bits of data in more than four storage states. For example, an MLC may store two bits per cell (also known as a dual-level cell (DLC)), three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC may be programmed to achieve a range of possible nominal storage values. For example, a DLC may be programmed to achieve one of three possible programming levels from an erased state by writing one of the three possible nominal storage values to the memory cell. A fourth nominal storage value may be used for the erased state. In one embodiment, an MLC can also be programmed to achieve only one programming level from an erased state by writing a possible nominal storage value (e.g., a first nominal storage value) to a memory cell, and a second nominal storage value can be used for an erased state. For example, although a TLC is capable of storing three bits, the TLC can be programmed to achieve only one programming level from an erased state by writing a possible nominal storage value (e.g., a first nominal storage value) to a memory cell, and a second nominal storage value can be used for an erased state.

[0040] Each of the NAND strings 312 can include a source select gate (SSG) 313 at its source terminal and a drain select gate (DSG) 314 at its drain terminal. The SSG 313 and DSG 314 can be configured to activate a selected NAND string 312 (i.e., a column of the memory cell array 310) during read and program operations. In some embodiments, the sources of the NAND strings 312 in the same block 315 can be coupled via the same source line (SL) 316 (e.g., a common SL). In other words, according to some embodiments, all of the NAND strings 312 in the same block 315 have an array common source (ACS). In some embodiments, the DSG 314 of each of the NAND strings 312 can be coupled to a corresponding bit line 321, from which data can be read or written via an output bus (not shown). In some embodiments, each of the NAND memory strings 312 can be configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor having the DSG 314) or a deselect voltage (e.g., 0 V) to the corresponding DSG 314 through one or more DSG lines 317 and / or by applying a select voltage (e.g., higher than the threshold voltage of the transistor having the SSG 313) or a deselect voltage (e.g., 0 V) to the corresponding SSG 313 through one or more SSG lines 318.

[0041] NAND memory strings 312 can be organized into a plurality of blocks 315, where each block 315 can have a common source line (SL) 316 (e.g., coupled to an ACS). In some embodiments, each block in a block 315 is a basic data unit for an erase operation, i.e., all memory cells 311 located in the same block 315 should be erased simultaneously. To erase the memory cells 311 in a selected block 315, the source line (SL) 316 coupled to the selected block 315 and unselected blocks 315 located in the same plane as the selected block 315 can be biased with an erase voltage (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some embodiments, an erase operation can be performed at the half-block level, the quarter-block level, or at any suitable number of blocks or any suitable portion of a block. Memory cells 311 of adjacent NAND memory strings 312 can be coupled via word lines 319, which select which row of memory cells 311 should be affected by read and program operations. In some embodiments, each of the word lines 319 can be coupled to a page 320 of memory cells 311, which is a basic data unit for programming operations. The size of one page 320 in bits can be related to the number of NAND memory strings 312 coupled by the word lines 319 in one block 315. For ease of description, the memory cells 311 in one page 320 can be coupled to the same word line 319, and in this disclosure, the terms "page" and "word line" can be used interchangeably. However, it should be understood that in some embodiments, the memory cells 311 in one page 320 can be coupled to more than one word line 319. Each of the word lines 319 can include a plurality of control gates (or gate electrodes) (not shown) located at each of the memory cells 311 in the corresponding page 320 and a gate line (not shown) that couples the control gates.

[0042] Return Reference Figure 1 . In some embodiments, the memory device 110 may include a peripheral circuit 120, which may be coupled to the memory cell array 160 via a bit line 321, a word line 319, a source line 316, an SSG line 318, and a DSG line 317. The peripheral circuit 120 may include any appropriate analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 160 by applying a voltage signal and / or a current signal to each target (select) memory cell 311 via the bit line 321, the word line 319, the source line 316, the SSG line 318, and the DSG line 317 and sensing the voltage signal and / or the current signal from each target (select) memory cell 311. The peripheral circuit 120 may include various types of peripheral circuits formed using metal oxide semiconductor (MOS) technology. For example, Figure 1 As shown, the peripheral circuit 120 may include an I / O circuit 121, a control logic unit 122, a page buffer / sense amplifier 125, an address decoder / BL-WL driver 124, and a voltage generator 123. The control logic unit 122 may be coupled to each of the peripheral circuits described above and configured to control the operation of each peripheral circuit. It should be understood that in some examples, the peripheral circuit 120 may also include Figure 1 No additional peripheral circuits are shown.

[0043] In some embodiments, the address decoder / BL-WL driver 124 can be coupled to the memory cell array 160. The address decoder / BL-WL driver 124 can include a column decoder and a row decoder. The column decoder can be connected to the memory cell array 160 via a bit line 321 and can select a bit line based on a column address. The column decoder can be configured to be controlled by the control logic unit 122 and select one or more NAND memory strings 312 by applying a bit line voltage generated from the voltage generator 123. The row decoder can be connected to the memory cell array 160 via a word line 319 and can select a word line based on a row address. The row decoder can be configured to be controlled by the control logic unit 122 according to a control signal and select / deselect a memory block 315 of the memory cell array 160 and select / deselect a word line 319 of the memory block 315. The row decoder can also be configured to drive the word line 319 using the word line voltage generated from the voltage generator 123. In some embodiments, the row decoder can also use the SSG voltage and DSG voltage generated from the voltage generator 123 to select / deselect and drive the SSG line 318 and the DSG line 317. In some embodiments, during a write operation, the address decoder / BL-WL driver 124 can provide a word line (WL) signal and a select signal to the memory cell array 160 to select a page to be programmed. During a read operation, the address decoder / BL-WL driver 124 can provide a WL signal and a select signal to select a page for buffering. During an erase operation, the address decoder / BL-WL driver 124 can provide a WL signal and a select signal to select a block to be erased.

[0044] The page buffer / sense amplifier 125 can be coupled to the memory cell array 160 via the bit line 321 and is configured to read data from the memory cell array 160 and program (write) data to the memory cell array 160 according to the control signal from the control logic unit 122. The page buffer / sense amplifier 125 can be configured to buffer data (e.g., one or more pages of data) during a read operation and a write operation. In one embodiment, during a write operation (programming operation), the page buffer / sense amplifier 125 can buffer the data to be programmed and drive the data to the bit line 321 of the memory cell array 160 to write the data into the memory cell array 160. During the write operation, the page buffer / sense amplifier 125 can sense a signal (e.g., a current) from the bit line 321 to verify whether the data has been correctly programmed into the target memory cell 311 coupled to the select word line 319. In another embodiment, during a read operation, page buffer / sense amplifier 125 can sense a low power signal (eg, current) from bit line 321 representing a data bit stored in memory cell 311 and amplify the small voltage swing to a recognizable logic level.

[0045] exist Figure 1 In one embodiment, the I / O circuit 121 is coupled to the control logic unit 122 and acts as a control buffer to buffer and relay control commands (e.g., program commands) received from the memory controller 140 and destined for the control logic unit 122, as well as status information received from the control logic unit 122 and destined for the memory controller 140. In another embodiment, the I / O circuit 121 may also be coupled to the address decoder / BL-WL driver 124 and may act as a data I / O interface and data storage device to buffer and relay data to and from the memory cell array 160.

[0046] In some embodiments, the memory system 100 may include a memory device 110, which may include an I / O circuit. The I / O circuit may be coupled to an external device, such as a host device (e.g., host device 190). The external device may implement the functionality of the memory controller described above. The external device may send commands to the memory device 110 via the I / O circuit. The external device may send data to the memory device 110 and receive data from the memory device 110 via the I / O circuit. The external device may receive signals generated by the memory device 110 in response to commands sent by the external device.

[0047] The voltage generator 123 can be configured to be controlled by the control logic unit 122 and configured to generate voltages of appropriate levels suitable for the operation of the memory device 110. For example, during a read operation, the voltage generator 123 can generate voltages of appropriate levels suitable for the source voltage of the read operation, various word line (WL) voltages, select voltages, etc. In some embodiments, during a read operation, the source voltage can be provided to the source line 316 as an array common source (ACS) voltage. The WL voltage and the select voltage can be provided to the address decoder / BL-WL driver 124, and thus, the address decoder BL-WL driver 124 can output WL signals and select signals (e.g., TSG signals and BSG signals) at appropriate voltage levels during the read operation.

[0048] In another embodiment, during an erase operation, the voltage generator 123 can generate voltages of appropriate levels, such as a source voltage, a WL voltage, a select voltage, a BL voltage, etc., suitable for the erase operation. In some embodiments, during an erase operation, the source voltage can be provided to the source line 316 as an ACS voltage. The WL voltage and the select voltage can be provided to the address decoder / BL-WL driver 124, and thus, the address decoder BL-WL driver 124 can output the WL signal and the BSG and TSG signals at appropriate voltage levels during the erase operation. The BL voltage can be provided to the page buffer / sense amplifier 125, and thus, the page buffer / sense amplifier 125 can drive the bit line (BL) at an appropriate voltage level during the erase operation. In some embodiments, the BL voltage can be applied directly to the bit line without passing through the page buffer / sense amplifier 125.

[0049] Figure 4 is a functional block diagram of an example of a memory system 400 according to some embodiments of the present disclosure. In one embodiment, the memory system 400 may include a memory device 410 (e.g., Figure 1 ) and via memory interfaces 430B and 430B′ (eg, Figure 1 ) are coupled to a memory controller 440 (eg, Figure 1 In one embodiment, the memory controller 440 may communicate with the host via the host interfaces 430A and 430A' (e.g., Figure 1 ) are coupled to a host device 490 (eg, Figure 1 ).

[0050] In one embodiment, the memory controller 440 may include a storage device 441, a control component 442, and a correction (e.g., error correction code (ECC)) component 443. The control component 442 may be implemented as a processor, such as a central processing unit (CPU). The storage device 441 may serve as a working memory of the memory system 400 and store data for driving the memory system 400. For example, when the memory controller 440 controls the operation of the memory device 410 (e.g., read, write, program, and erase operations), the storage device 441 may store data used by the memory controller 440 for the operation. The storage device 441 may be implemented using a volatile memory (e.g., dynamic random access memory (DRAM) or static random access memory (SRAM)). In order to store data for read, write, program, and erase operations, the storage device 441 may include a program memory, a data memory, a write buffer, a read buffer, a mapping buffer, etc.

[0051] The control component 442 may be configured to control, for example, a read operation or a write operation of the memory device 410 in response to a read command or a write command, respectively, from the host device 490 .

[0052] The correction module 443 can be configured to detect and correct errors in data read from the memory device 410 during a read operation by using an error correction code (ECC). The correction module 443 may not correct the error bits when the number of error bits exceeds the ECC correction capability of the memory device 410, and the read operation using the set read threshold voltage fails. When the read operation using the set read threshold voltage fails, the control component 442 can execute an error recovery algorithm. For example, the control component 442 can perform one or more read retry operations on the memory cells storing data in the memory device 410 until it is determined that the decoding associated with the corresponding read retry operation is successful. As another example, when all read retry operations fail, the control component 442 can perform additional recovery operations, which may include an optimal read threshold voltage search, soft decoding using ECC, and redundant array of independent disks (RAID) recovery.

[0053] Correction module 443 may include an encoder and a decoder. In one embodiment, the encoder (or codec) may encode data of a predetermined size written to the same page to generate a parity code. The parity code may be written to the page where the data that forms the programming basis has already been written. In some embodiments, the decoder may use the parity code to decode and recover the data.

[0054] Figure 5Ais a circuit diagram of an example of a 4-bit linear feedback shift register (LFSR) 500 according to some embodiments of the present disclosure. The LFSR 500 includes a plurality of shift registers (e.g., flip-flops (FF) FF0-FF3), and a feedback network consisting of an exclusive OR (XOR) gate (denoted by the symbol ⊕), and the outputs (also referred to as taps) of some of the shift registers FF0-FF3 are fed as inputs to the XOR gate ⊕. The LFSR 500 is specified by its polynomial. For example, a fourth-degree polynomial in which each term exists is represented by the equation x 4 +x 3 +x 2 +x+1. There exists 2 (4-1) = 8 different possible polynomials of this size (i.e., 4), some of which are primitive polynomials. If an LFSR (e.g., LFSR 500) is specified by primitive polynomials, then the LFSR can generate a finite field (e.g., Galois Field (GF(2 4 Finite fields have the important property that arithmetic operations (e.g., addition, subtraction, multiplication, and division) on elements of the field always have results that are also in the finite field.

[0055] like Figure 5A As shown, LFSR 500 is composed of primitive polynomial q(x)=x 4 +x+1 specifies and can generate 2 4 -1=15 pseudo-random numbers (such as Figure 5C As shown in FIG. 5 ). Thus, the LFSR 500 can be implemented as a random generator. In a finite field, addition is defined as the bitwise XOR of the coefficients of the polynomial, and multiplication corresponds to the multiplication of the polynomial of primitive elements (e.g., x). In operation, as Figure 5B As shown, initially, the binary random generator seed (e.g., "1001", as Figure 5C ) can be input to the random generator 500, and a subsequent field element can be enumerated every clock by multiplying the previous field element of the subsequent field element by the primitive element (i.e., x) and taking the result modulo q(x) if it has a degree greater than or equal to 4. For example, x 2 ("0100") can be multiplied by x to get x 3 (“1000”), x 3 ("1000") can be multiplied by x to get x+1 (which is x 4 Modulo q(x) = x 4 +x+1), x 3 +x("1010") can be multiplied by x to get x 2 +x+1(which is x 4 +x 2Modulo q(x) = x 4 +x+1), and so on. In some embodiments, another random generator (e.g., LFSR) can include any number (e.g., n) of shift registers, and can enumerate a subsequent field element every two, three, or any number less than n.

[0056] Because GF(e.g., GF(2 n )) are enumerated by raising primitive elements (e.g., x) to powers, so the i-th element can be represented by x i To express it. Similarly, GF(2 n ) can be represented by x j The multiplication of the i-th element by the j-th element can be achieved by adding their corresponding exponentials, that is, x i ×x j =x i+j , if i+j<2 n -1, which is GF(2 n ), or if i+j≥2 n -1, which is GF(2 n ) in the (i+j-255)th element. Since x i Is GF(2 n ) is the i-th element in , so i = log x x i If GF(2 n ) is enumerated as a list of indices, then the index of the value is the logarithm of the value. i By sorting, we can create a table of logarithms (i.e., gflog) to find the logarithm of any value. Therefore, GF(2 n ) is simply to find the logarithm of the multiplicand, add the logarithms (modulo 2) n -1), and look up the antilogarithm table for addition (i.e., glilog).

[0057] Figure 6A and Figure 6BThe 64 elements of the hexadecimal values of the gflog and gfilog tables are listed to demonstrate examples of multiplication and division of elements in a finite field. The value of x is represented by row and column so that the function result (in hexadecimal) can be found by looking up the cell with row R and column C. In one embodiment, gflog[0x13] is found in the cell with row -1 and column -3 of the gflog table, which gives the value of 0x0e. In another embodiment, gfilog[0x0e] is found by looking up in the gfilog table at row -0 and column -e, which gives the value of 0x13. For example, 2 multiplied by 8 = gfilog[gflog[2] + gflog[8]]) = gfilog[1+3] = gfilog[4] = 0x10. As another example, 0x12 multiplied by 5 = gfilog[gflog[0x12]+gflog[5]]=gfilog[0xe0+0x32]=gfilog[0x13]=0x5e.

[0058] In one embodiment, n (e.g., 2 16 ) data blocks (e.g., D0 to D n-1 (For example, D2 16 -1 )) will be encoded and stored, and at most k data blocks can be corrected (or k parity codes can be generated, such as P0 to P k-1 ), and can choose GF(2 m ) as coefficients of a polynomial matrix (e.g., a Vandermonde matrix) that has full rank, is invertible, and has k rows and n columns (e.g., Figure 7 As shown). n data blocks D0 to D n-1 Each data block in may include data stored in a memory cell or data to be written to a page. n-1 Form a column vector or a matrix with only one column, with n (e.g., 2 16 ) rows. The polynomial matrix has n (e.g., 2 16 ) columns and k rows. Each row represents a number of n (e.g., 2 16 ) polynomial coefficients, the number of polynomial coefficients is equal to the data D0 to D n-1 The number of rows of the polynomial matrix (eg, k), that is, the number of correction coding polynomials, is equal to the number of parity check codes (eg, P0 to P k-1 ) quantity.

[0059] In one embodiment, the polynomial matrix is a linearly independent matrix, and when the data D0-D n-1When at most k data in the are affected and incorrect, the corresponding k parity check codes P0-P k-1 It can be used to recover and correct incorrect data. For example, in the polynomial matrix, 1 and (n-1) consecutive non-zero elements with indices that are multiples of 0 (i.e., the first row) of the Vandermonde matrix (i.e., 1, 1, ..., 1) can be selected and multiplied by the data D0 to D n-1 (ie, for data D0 to D n-1 An XOR operation (similar to a RAID 5 operation) is performed to generate a parity code P0, followed by 1 and (n-1) consecutive non-zero elements of an index that is a multiple of 1 (i.e., the second row) of the Vandermonde matrix (i.e., 1, GF(1), GF(2), ..., GF(n-1)) can be selected and multiplied by the data D0 to D n-1 To generate the parity code P1 (similar to the RAID 6 operation), 1 and (n-1) consecutive non-zero elements of an index that is a multiple of 2 (i.e., the third row) of the Vandermonde matrix (i.e., 1, GF(2×1), GF(2×2), ..., GF(2×(n-1))) may be selected and multiplied by the data D0 to D n-1 To generate the parity check code P2, 1 and (n-1) consecutive non-zero elements of an index that is a multiple of 3 (i.e., the fourth row) of the Vandermonde matrix (i.e., 1, GF(3×1), GF(3×2), ..., GF(3×(n-1))) may be selected and multiplied by the data D0 to D n-1 To generate the parity check code P3, ..., and followed by 1 and (n-1) consecutive non-zero elements of an index that is a multiple of (k-1) (i.e., the kth row) of the Vandermonde matrix (i.e., 1, GF((k-1)×1), GF((k-1)×2), ..., GF((k-1)×(n-1))) can be selected and multiplied by the data D0 to D n-1 To generate the parity check code P3, where (n-1)×(k-1)≤2 m -1.

[0060] In RAID decoding for recovering incorrect data, the corresponding parity check code is multiplied by the inverse matrix of the polynomial matrix to obtain the correct data recovered from the incorrect data. In an alternative embodiment, a reduced polynomial matrix can be formed that includes the rows of the polynomial matrix corresponding to the incorrect data, and the inverse matrix of the reduced polynomial matrix can then be calculated and multiplied by the corresponding parity check code to recover the incorrect data.

[0061] In one embodiment, if a NAND memory having 4 dies is provided, each die has 4 planes, each plane has 128 layers (6 strings), where two adjacent strings are coupled to different word lines (WLs) as a group, each group has 128 (WLs) × 2 (strings) × 4 (planes) × 4 (dies) = 4096 (2 12 ) elements (pages), SLC is a group of 3, TLC is a group of 9, and four errors will be corrected, n = 4096, k = 4, (n-1) × (k-1) = 4095 × 3 < 2 16 -1, and can choose GF(2 16 In another embodiment, the LSFR may include a first number of cascaded shift registers, the data may include a second number of pages, the one or more parity codes may include a third number of parity codes, and the first number to the power of two may be greater than the second number minus one multiplied by the third number minus one.

[0062] In linear algebra, Figure 8A As shown, the Vandermonde matrix has a geometric series of terms in each row. The Vandermonde matrix has full rank and is reversible. A rectangular matrix with m rows selected from the Vandermonde matrix is also reversible. In one embodiment, each row of the Vandermonde matrix is mapped to an index term. For example, the first row of the Vandermonde matrix can correspond to an index of 0, and the second row of the Vandermonde matrix can correspond to an index of 1, the third row of the Vandermonde matrix can correspond to an index of 2, ..., and the kth row of the Vandermonde matrix can correspond to an index of k-1. In one embodiment, the domain elements in the second row of the Vandermonde matrix can be enumerated for every two clocks input to a random generator (e.g., an LFSR comprising n shift registers), the domain elements in the third row of the Vandermonde matrix can be enumerated for every three clocks input to the random generator, ..., and the domain elements in the kth row of the Vandermonde matrix can be enumerated for every k clocks input to the random generator.

[0063] The Vandermonde matrix can also be applied to polynomial matrices that have polynomial coefficients corresponding to the entries of the Vandermonde matrix, for example, Figure 8B As shown, GF(1) corresponds to x 1 , GF(2) corresponds to x 2 , ..., and GF((k-1)(n-1)) corresponds to x (n-1)(k-1)In some embodiments, the encoding matrix can be formed by adding a unit (or identity) matrix (where all diagonal elements are equal to 1 and all other elements are equal to 0) to the polynomial matrix. The identity matrix has the same number of columns as the polynomial matrix. Therefore, the result obtained from multiplying the encoding matrix by the data vector includes not only the parity check code, but also the data D0-D that can be stored as a whole. n-1 , thus avoiding data loss.

[0064] Figures 9A-9D The present invention shows a method of encoding n data blocks (e.g., D0 to D5) by using a polynomial matrix to generate parity check codes (e.g., P0 and P1), and recovering some (e.g., two) data (e.g., D1 and D4) stored and affected and incorrect data. Figures 9A-9D In the example shown, the primitive polynomial x is implemented by the LFSR. 4 A random generator specified by +x+1 (eg, random generator 500) may be used to generate a polynomial matrix.

[0065] like Figure 9A As shown, the first and second rows of the Vandermonde matrix, i.e., (1,1,1,1,1,1) and (1,x 1 ,x 2 ,x 3 ,x 4 ,x 5 ) can be selected and multiplied by the data D0 to D5 to generate parity check codes P0 and P1, which are equal to (D0+D1+D2+D3+D4+D5) and (D0+D1×x+D2×x 2 +D3×x 3 +D4×x 4 +D5×x 5 ).like Figure 9B As shown, a simplified polynomial matrix can be formed to include the first row and the second column and the fifth column of the second row of the polynomial (Vandermonde) matrix, and can be multiplied by the data D1 and D4 to generate (P0+D0+D2+D3+D5) and (P1+D0+D2×x 2 +D3×x 3 +D5×x 5 ).like Figure 9C As shown, the inverse matrix of the simplified polynomial matrix is calculated, and the data D1 and D4 can be equal to the inverse matrix multiplied by (P0+D0+D2+D3+D5) and (P1+D0+D2×x 2 +D3×x 3 +D5×x 5 ). Therefore, if Figure 9D As shown, data D1 is equal to x 4×(P0+D0+D2+D3+D5)+(P1+D0+D2×x 2 +D3×x 3 +D5×x 5 ), and data D4 is equal to x 1 ×(P0+D0+D2+D3+D5)+(P1+D0+D2×x 2 +D3×x 3 +D5×x 5 ). Therefore, the random generator 500 can be used to recover and correct incorrect data D1 and D4. i " indicates the number of clocks that have been input to the random generator 500 since data was input to the random generator 500. For example, "x 4 ” indicates that four clocks have been input to the random generator 500 since data was input to the random generator 500.

[0066] Figures 10A-10F The method of encoding n data blocks to generate parity check codes by using a polynomial matrix that can be specified by a random generator according to some embodiments of the present disclosure is shown. Figure 10A As shown, six data blocks (eg, D0-D5) will be stored in the memory device, for example, Figure 1 . For example, D0 is "10011101", D1 is "10010110", D2 is "10010101", D3 is "11010110", D4 is "11010101", and D5 is "11010101". A parity code is generated before being stored in the memory device 110 so as to be used to recover some data (if affected and incorrect) among the data D0-D5 through the parity code.

[0067] like Figure 10B As shown, the choice is made by the primitive polynomial (for example, q(x) = x 4 +x+1) specifies the polynomial (Vandermonde) matrix. Figure 10B In the exemplary embodiment shown in , two parity check codes (e.g., P0 and P1) are generated, and accordingly, the first row (i.e., [1,1,1,1,1,1]) and the second row (i.e., [1,x 1 ,x 2 ,x 3 ,x 4 ,x 5]) can be selected and multiplied by data D0-D5 to generate parity check codes P0 and P1. In some embodiments, k parity check codes will be generated, and therefore, the first row, the second row, ..., and the (k-1)th row of the Vandermonde matrix can be selected and multiplied by data D0-D5 to generate parity check codes P0, P1, ..., and P k-1 , so that it can be used to pass the parity check code P0-P k-1 Restore k data (if affected and incorrect) among the data D0-D5.

[0068] like Figure 10C As shown, the parity code P0 is generated. For example, the parity code P0 can be generated by bitwise XOR of the data D0-D5 to obtain "01001000". Figure 10D As shown, a random generator 1000, such as a LFSR (e.g., LFSR 500), can be used to implement the primitive polynomial q(x)=x 4 +x+1. Figure 10E A simplified circuit diagram of the random generator 1000 is shown. Figure 10B In the exemplary embodiment shown, a subsequent domain element can be enumerated every clock cycle by using the random generator 1000. For example, Figure 10F As shown, initially, data D0 is multiplied by 1; after one clock, data D1 is multiplied by x (ie, D1x) output from the random generator 1000; after two clocks, data D2 is multiplied by x output from the random generator 1000. 2 (ie, x is shifted right by one bit) (ie, D2x 2 ); After three clocks, the data D3 is multiplied by the x output from the random generator 1000 3 (i.e., x 2 Shift right one bit) (i.e., D3x 3 ); After four clocks, the data D4 is multiplied by x+1 (ie, x) output from the random generator 1000. 4 Module (x 4 +x+1))(i.e., x 3 Shifted right by one bit) (ie, D4(x+1)); after five clocks, the data D5 is multiplied by x output from the random generator 1000. 2 +x (i.e., (x+1) shifted right by one bit) (i.e., D5(x 2 +x)); and can be achieved through D0, D1x, D2x 2 、D3x 3 , D4(x+1) and D5(x 2 + x) to generate the parity code P1 to obtain "01000001".

[0069] In some embodiments, more than two parity codes may be generated to recover and correct more than two incorrect data among the data stored in the memory device 110. For example, k parity codes may be generated to recover k incorrect data among the stored data. k-1 Initially, data D0 is multiplied by 1; after k-1 clocks, data D1 is multiplied by x output from random generator 1000. k-1 (i.e., D1x k-1 ); After 2(k-1) clocks, data D2 is multiplied by x 2(k-1) (modulo q(x))(i.e., D2x 2(k-1) ); After 3(k-1) clocks, data D3 is multiplied by x 3(k-1) (modulo q(x))(i.e., D3x 3(k-1) ); After 4(k-1) clocks, data D4 is multiplied by x 4(k-1) (modulo q(x))(i.e., D4x 4(k-1) ); After 5(k-1) clocks, data D5 is multiplied by x 5(k-1) (modulo q(x))(i.e., D5x 5(k-1) ); and can be achieved through D0, D1x k-1 、D2x 2(k-1) 、D3x 3(k-1) 、D4x 4(k-1) and D5x 5(k-1) The parity code P is generated by bitwise XOR of k-1 .

[0070] Figures 11A-11H FIG. 1 shows how to decode (or recover) some affected and incorrect data in the data D0-D5 by using the random generator 1000 according to some embodiments of the present disclosure. Figure 11A As shown in FIG, data D1 and D4 (indicated by the gray background) are affected and are incorrect. Figure 11B As shown, by reference Figure 9B , D1×x and D4×x 4 (indicated by the gray background) can be used to recover the incorrect data D1 and D4. Figure 11C and Figure 11D As shown, D1+D4 (bitwise XOR of D1 and D4) = "01000011", and D1×x+D4×x 4 (D1×x and D4×x 4 bitwise XOR of ) = "01010011". Figure 11EThe simultaneous equations of data D1 and D4 are shown, which are obtained by multiplying a simplified polynomial matrix including the first row and second column and fifth column of the second row of the polynomial (Vandermonde) matrix by the data matrix (or vector) of data D1 and D4. Figure 11F It is shown that the inverse matrix of the simplified polynomial matrix is obtained by adding D1+D4 and D1×x+D4×x 4 In some embodiments, the data D1 and D4 can be obtained by using a random generator 1000. For example, Figure 11G As shown, four clocks after the random generator seed is input to the random generator 1000, the bit-by-bit XOR of the parity code P0 and the data D0, D2, D3, and D5 may be multiplied by the output of the random generator 1000 (as indicated by Figure 10E ) to generate (D1+D4)×x 4 ; Similarly, parity code P1 and data D0, D2×x 2 (Two clocks after the random generator seed is input to the random generator 1000, the data D2 is multiplied by the output of the random generator 1000), D3×x 3 and D5×x 5 Bitwise XOR of D1×x+D4×x 4 ; and then (D1+D4)×x 4 and D1×x+D4×x 4 D1 is obtained by bitwise XOR. Figure 11H As shown, data D4 can also be obtained by using the random generator 1000 in a similar manner.

[0071] Aspects of the present disclosure provide a memory system, for example, Figure 1 In one embodiment, the memory system may include a memory device (e.g., Figure 1 ), the memory device is configured to store data (e.g., data D0-D5) and one or more parity codes (e.g., parity codes P0 and P1). In another embodiment, the memory system may further include a memory controller, for example, Figure 1 . For example, the memory controller 140 may include a random generator (e.g., random generators 500 and 1000) configured to generate a sequence of pseudo-random numbers using a random generator seed in response to a clock signal according to a predetermined rule. As another example, the memory controller may further include a codec (e.g., included in Figure 4), the codec is coupled to the memory device and the random number generator, and is configured to generate one or more parity check codes based on the pseudo-random number. In one embodiment, the parity check code can be written to the memory device when a write operation is performed, and is used to recover at least one of the data stored in the memory device when a read operation is performed and at least one of the data is incorrect. In another embodiment, the random number generator seed can be selected based on the data and the pseudo-random number. For example, the random number generator seed can be selected from the sum of the data and the pseudo-random number.

[0072] In one embodiment, the codec may be configured to generate a parity code by multiplying a pseudo-random number by data and performing a bitwise logical operation of the multiplication of the pseudo-random number and the data. In another embodiment, the codec may be configured to generate a plurality of parity codes, and the random generator may be configured to generate a sequence of pseudo-random numbers using a random generator seed in response to each number of clocks of the clock signal according to a predetermined rule.

[0073] Figure 12 is a functional block diagram of an example of a memory system 1200 according to some embodiments of the present disclosure. The memory system 120 may include a memory device 1210 (e.g., memory devices 110 and 410), which is configured to store data (e.g., input data) and one or more parity check codes. In one embodiment, the memory device 1210 may be implemented using a volatile memory (e.g., DRAM or SRAM). The memory system 1200 may also include a random generator 1220, which is configured to generate a sequence of pseudo-random numbers using a random generator seed in response to a clock signal CLK according to predetermined rules. In one embodiment, the random generator 1220 may include an LFSR that may be specified by a primitive polynomial. The memory system 1200 may also include a codec 1230 (e.g., included in Figure 4), the codec 1230 is coupled to the memory device 1210 and the random generator 1220 and is configured to generate one or more parity check codes based on the pseudo-random number and data (e.g., input data). In one embodiment, the codec 1230 can be configured to generate multiple parity check codes, and the random generator is configured to generate a sequence of pseudo-random numbers using a random generator seed in response to each number of clocks of the clock signal according to a predetermined rule. For example, the codec 1230 can generate one parity check code (e.g., parity check code P0) among the parity check codes, and the random generator 1220 can be configured to generate a sequence of pseudo-random numbers using a random generator seed in response to each clock of the clock signal CLK. As another example, the codec 1230 can generate two parity check codes (e.g., parity check codes P0 and P1) among the parity check codes, and the random generator 1220 can be configured to generate a sequence of pseudo-random numbers using a random generator seed in response to every two clocks of the clock signal CLK. In one embodiment, the codec 1230 may be configured to generate a parity code by multiplying a pseudo-random number by data and performing a bitwise logical operation of the multiplication of the pseudo-random number and the data. Figure 10C As shown in FIG, the parity code P0 can be generated by bit-by-bit XOR of the input data. As another example, Figure 9A As shown, the parity code P1 can be generated by multiplying the pseudo random number by the input data and performing a bit-by-bit logical operation of the multiplication of the pseudo random number and the data. In some embodiments, the random generator 1220 and the codec 1230 can be included in the memory controller 1290, for example, Figure 4 The memory controller 440 shown in FIG.

[0074] In one embodiment, data and parity codes may be written to the memory device 1210 via the memory interfaces 1230B and 1230B' when a write operation is performed, and used to recover at least one of the data stored in the memory device 1210 when a read operation is performed and at least one of the data is incorrect. In some embodiments, the LSFR included in the random generator 1220 may include a first number of cascaded shift registers, the input data may include a second number of pages, the one or more parity codes may include a third number of parity codes, and the first number to the power of two is greater than the second number minus one multiplied by the third number minus one. For example, if a NAND memory having 4 dies is provided, each die having 4 planes, each plane having 128 layers (6 strings), wherein two adjacent strings are coupled to different word lines (WLs) as a group, each group has 128 (WLs) × 2 (strings) × 4 (planes) × 4 (dies) = 4096 (2 12) elements (pages), SLC is a group of 3, TLC is a group of 9, and four errors will be corrected, n = 4096, k = 4, (n-1) × (k-1) = 4095 × 3 < 2 16 -1, and can choose GF(2 16 ).

[0075] In one embodiment, the memory system 1200 may further include an operator 1240 that uses a pseudo-random number to operate on input data, and a random generator seed may be selected based on the input data and the pseudo-random number. For example, the operator 1240 may include an adder configured to add the input data and the pseudo-random number to generate output data, and the random generator seed may be selected from the output data.

[0076] Aspects of the present disclosure also provide a method for controlling a memory system. For example, the method may include: generating a sequence of pseudo-random numbers using a random generator seed in response to a clock signal according to a predetermined rule using a random generator, receiving data to be stored in a memory device, generating one or more parity codes based on the pseudo-random numbers and the data, and writing the parity codes and the data to the memory device when performing a write operation, and recovering at least one of the data stored in the memory device using the one or more parity codes when performing a read operation and at least one of the data stored in the memory device is incorrect.

[0077] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A memory system comprising: a memory device configured to store data and one or more parity codes; a random generator configured to generate a sequence of pseudo-random numbers using a random generator seed in response to a clock signal according to predetermined rules; as well as A codec is coupled to the memory device and the random generator, the codec being configured to generate the one or more parity codes based on the pseudo-random number and the data, the parity codes to be written to the memory device when a write operation is performed, and to be used to recover the at least one of the data stored in the memory device when a read operation is performed and at least one of the data is incorrect.

2. The memory system according to claim 1, wherein: The codec is configured to generate the parity code by multiplying the pseudo random number by the data and performing a bit-by-bit logical operation of the multiplication of the pseudo random number and the data.

3. The memory system according to claim 1, wherein: The codec is configured to generate a plurality of the parity codes, and the random generator is configured to generate a sequence of the pseudo-random numbers using the random generator seed in response to each number of clocks of the clock signal according to the predetermined rule.

4. The memory system according to claim 1, wherein: The random generator seed is selected based on the data and the pseudo-random number.

5. The memory system according to claim 1, wherein: The random generator includes a linear feedback shift register (LFSR). The memory system according to claim 5 , wherein: The LFSR is specified by a primitive polynomial.

7. The memory system according to claim 6, wherein: The LSFR includes a first number of cascaded shift registers, the data includes a second number of pages, the one or more parity codes include a third number of parity codes, and the first number to the power of two is greater than the second number minus one multiplied by the third number minus one.

8. A method comprising: generating a sequence of pseudorandom numbers by using a random generator in response to a clock signal according to a predetermined rule using a random generator seed; receiving data to be stored in a memory device; generating one or more parity codes based on the pseudo-random number and the data, and writing the parity codes and the data to the memory device when performing a write operation; as well as When a read operation is performed and at least one of the data stored in the memory device is incorrect, the at least one of the data stored in the memory device is recovered using the one or more parity codes.

9. The method according to claim 8, wherein The parity code is generated by multiplying the pseudo random number by the data and performing a bit-by-bit logical operation of the multiplication of the pseudo random number and the data.

10. The method according to claim 8, wherein A plurality of the parity codes are generated, and a sequence of the pseudo-random numbers is generated in response to each number of clocks of the clock signal according to the predetermined rule by using the random generator seed.

11. The method according to claim 8, wherein The random generator seed is selected based on the data and the pseudo-random number.

12. The method according to claim 8, wherein The random generator includes a linear feedback shift register (LFSR).

13. The method according to claim 12, wherein: The LFSR is specified by a primitive polynomial.

14. The method according to claim 13, wherein The LSFR includes a first number of cascaded shift registers, the data includes a second number of pages, the one or more parity codes include a third number of parity codes, and the first number to the power of two is greater than the second number minus one multiplied by the third number minus one.

15. A memory controller comprising: a random generator configured to generate a sequence of pseudo-random numbers using a random generator seed in response to a clock signal according to predetermined rules; as well as A codec is coupled to the random generator, the codec being configured to generate one or more parity codes based on the pseudo-random number and the data to be stored in the memory device, the parity codes to be written to the memory device when a write operation is performed, and to be used to recover at least one of the data stored in the memory device when a read operation is performed and at least one of the data is incorrect.

16. The memory controller according to claim 15, wherein: The codec is configured to generate the parity code by multiplying the pseudo random number by the data and performing a bit-by-bit logical operation of the multiplication of the pseudo random number and the data.

17. The memory controller according to claim 15, wherein: The codec is configured to generate a plurality of the parity codes, and the random generator is configured to generate a sequence of the pseudo-random numbers using the random generator seed in response to each number of clocks of the clock signal according to the predetermined rule.

18. The memory controller according to claim 15, wherein: The random generator seed is selected based on the data and the pseudo-random number.

19. The memory controller according to claim 15, wherein: The random generator includes a linear feedback shift register (LFSR).

20. The memory controller according to claim 19, wherein: The LSFR is specified by a primitive polynomial and includes a first number of cascaded shift registers, the data includes a second number of pages, the one or more parity codes include a third number of parity codes, and the first number raised to the power of two is greater than the second number minus one multiplied by the third number minus one.

Images