Digital memory computing circuit, word line input switching circuit and digital memory computing system

Abstract

This application discloses a digital memory computing circuit, a word line input switching circuit, and a digital memory computing system. The digital memory computing circuit includes a first switching transistor, a second switching transistor, and a latching circuit. The first terminal of the first switching transistor is connected to a bit line, and the second terminal of the first switching transistor is connected to the first terminal of the second switching transistor and the operation output terminal. The control terminal of the second switching transistor is connected to a word line. When both the first and second switching transistors are simultaneously turned on, a second signal input from the bit line is sent to the latching circuit for storage. When either the first or second switching transistor is turned on individually, a multiplication operation is performed based on a third signal, the inverted signal of the third signal, and the output data signal of the latching circuit. This application controls the on / off state of the first and second switching transistors through different signal inputs, combined with the latching circuit for storage and multiplication calculations, thereby reducing the number of switching transistors required in the digital memory computing process and effectively reducing resource consumption.

Description

Technical Field

[0001] This application relates to the field of memory computing technology, and in particular to a digital memory computing circuit, a word line input switching circuit, and a digital memory computing system. Background Technology

[0002] With the rapid development of technology, the amount of data and computation required for offline training and online applications is increasing. The traditional von Neumann computing architecture separates the computing unit and the storage unit. When faced with large-scale computing tasks, insufficient memory and high power consumption greatly limit the hardware's computing efficiency and energy consumption performance.

[0003] In-memory computing is a popular new computing architecture in both academia and industry. Its main idea is to integrate computing and storage units, avoiding the bandwidth and energy consumption caused by data movement. Static Random Access Memory (SRAM) is the mainstream storage medium for in-memory computing research due to its mature technology and stable structure. The technical routes for SRAM-based in-memory computing research are mainly divided into analog in-memory computing and digital in-memory computing. Analog in-memory computing typically involves adding analog computing circuits within the SRAM array to perform multiplication and addition operations, and then converting the results into digital signals via an ADC. Analog in-memory computing has lower computational accuracy; in contrast, digital in-memory computing offers stable performance and high computational accuracy, making it more advantageous in many application scenarios.

[0004] Existing digital in-memory (DIM) systems primarily utilize SRAM with at least six transistors. To enable data multiplication, an auxiliary operational structure connected to the SRAM is also required, typically consisting of multiple transistors. Consequently, existing DIM schemes require a dozen or even dozens of transistors to work in coordination, resulting in a large number of transistors and significant resource consumption in DIM circuits. Summary of the Invention

[0005] The main purpose of this application is to provide a digital memory circuit that aims to solve the technical problem of excessive resource consumption caused by the excessive number of switching transistors required in the digital memory process.

[0006] To achieve the above objectives, this application provides a digital memory circuit; the digital memory circuit includes: a first switching transistor, a second switching transistor, and a latching circuit;

[0007] The first terminal of the first switching transistor is connected to the bit line, and the second terminal of the first switching transistor is connected to the first terminal of the second switching transistor and the operation output terminal; the control terminal of the second switching transistor is connected to the word line, and the second terminal of the second switching transistor is connected to the latch circuit; the word line is used to input a first signal to the control terminal of the second switching transistor, and the bit line is used to input a second signal to the first terminal of the first switching transistor.

[0008] The first switch and the second switch are configured to be turned on when both the third signal input to the control terminal of the first switch and the first signal input from the word line to the control terminal of the second switch are high-level signals, and to send the second signal input from the bit line to the latch circuit for storage.

[0009] The first or second switch is turned on when the second signal input to the bit line is a low-level signal, performs a multiplication operation based on the third signal input to the control terminal of the first switch, the inverse signal of the third signal, and the output data signal of the latch circuit, and outputs the operation result through the operation output terminal;

[0010] The first signal is a word line input signal, the second signal is a bit line input signal, and the third signal is a calculation input signal.

[0011] Optionally, the second switch is further configured to be turned on when the second signal input to the bit line is a low-level signal and the first signal input to the word line is a high-level signal, to receive the output data signal of the latch circuit, and to perform a multiplication operation on the third signal, the inverted signal of the third signal, and the output data signal of the latch circuit.

[0012] Optionally, the second switching transistor is further configured to output a first calculation result through the arithmetic output terminal when the output data signal of the latch circuit is a high-level signal;

[0013] When the output data signal of the latch circuit is a low-level signal, the second calculation result is output through the calculation output terminal; the first calculation result is the opposite of the second calculation result.

[0014] Optionally, the first switch is further configured to be turned on when the second signal input to the bit line is a low-level signal and the third signal is a high-level signal, and to output the second calculation result through the calculation output terminal.

[0015] Optionally, the latching circuit includes: a third switch, a fourth switch, a fifth switch, and a sixth switch;

[0016] The control terminal of the third switch is connected to the second terminal of the fourth switch, the control terminal of the fifth switch, and the first terminal of the sixth switch. The first terminal of the third switch is connected to the power supply, and the second terminal of the third switch is connected to the second terminal of the second switch and the first terminal of the fifth switch.

[0017] The control terminal of the fourth switch is connected to the control terminal of the sixth switch, the second terminal of the second switch, the second terminal of the third switch, and the first terminal of the fifth switch; the first terminal of the fourth switch is connected to the power supply.

[0018] The second terminal of the fifth switch and the second terminal of the sixth switch are grounded.

[0019] In addition, to achieve the above objectives, this application also provides a word line input switching circuit, wherein the word line input switching circuit is connected to the control terminal of the second switching transistor via the word line, the word line input switching circuit is connected to the control terminal of the first switching transistor, and the word line input switching circuit is also connected to a controller;

[0020] The word line input switching circuit is used to receive the working mode instruction output by the controller, and output the third signal to the control terminal of the first switch according to the working mode instruction, and control the word line to output the first signal to the control terminal of the second switch.

[0021] The word line input switching circuit is further configured to, when the received working mode instruction is data write mode, output a high-level signal as a first signal through the word line to the control terminal of the second switching transistor, and output a high-level signal as a third signal to the control terminal of the first switching transistor.

[0022] Optionally, the word line input switching circuit is further configured to, when the received operating mode instruction is a multiplication operation mode, output the first signal through the word line to the control terminal of the second switching transistor, and input the third signal to the control terminal of the first switching transistor, wherein the signal level of the first signal is opposite to the signal level of the third signal.

[0023] Optionally, the word line input switching circuit includes: a selector and an inverter;

[0024] The first input terminal of the selector is used to receive control signals input to the digital memory circuit.

[0025] The second input terminal of the selector is connected to the input terminal of the inverter;

[0026] The control terminal of the selector is connected to the controller and is used to receive the working mode command output by the controller;

[0027] The output of the selector is connected to the control terminal of the second switching transistor via the word line;

[0028] The output terminal of the inverter is connected to the control terminal of the first switching transistor.

[0029] In addition, to achieve the above objectives, this application also provides a digital storage and computing system, including: an addition tree, a storage array, and a word line input switching circuit as described in any of the above claims; the storage array includes at least one row of the digital storage and computing circuit as described in any of the above claims;

[0030] The digital storage circuit is connected to the addition tree through its arithmetic output terminal;

[0031] The number of word line input switching circuits is the same as the number of rows of the digital memory circuit;

[0032] Each of the aforementioned word line input switching circuits is connected to the corresponding digital storage circuit within the same row.

[0033] One or more technical solutions proposed in this application have at least the following technical effects:

[0034] This application discloses a digital memory circuit comprising: a first switching transistor, a second switching transistor, and a latching circuit; a first terminal of the first switching transistor is connected to a bit line, and a second terminal of the first switching transistor is connected to a first terminal of the second switching transistor and an arithmetic output terminal; a control terminal of the second switching transistor is connected to a word line, and a second terminal of the second switching transistor is connected to the latching circuit; the word line is used to input a first signal to the control terminal of the second switching transistor, and the bit line is used to input a second signal to the first terminal of the first switching transistor; the first and second switching transistors are configured to be turned on when both a third signal input to the control terminal of the first switching transistor and the first signal input from the word line to the control terminal of the second switching transistor are high-level signals, thereby sending the second signal input from the bit line to the latching circuit for storage; the first or second switching transistor is configured to be turned on when the second signal input from the bit line is low-level, performing a multiplication operation based on the third signal input to the control terminal of the first switching transistor, the inverse signal of the third signal, and the output data signal of the latching circuit, and outputting the operation result through the arithmetic output terminal; the first signal is a word line input signal, the second signal is a bit line input signal, and the third signal is a computation input signal. In this application, the on / off state of the first and second switching transistors is controlled by inputting different signals, and storage and multiplication calculations are performed in combination with latching circuits, thereby reducing the number of switching transistors required for the digital storage and computation process and effectively reducing the resource consumption of the digital storage and computation process. Attached Figure Description

[0035] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0036] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a schematic diagram of the hardware structure used in a typical digital in-memory computing scheme.

[0038] Figure 2 This is a typical layout for digital in-memory computing circuits;

[0039] Figure 3 This is a typical circuit diagram of a digital in-memory computing circuit.

[0040] Figure 4 This is a schematic diagram of the structure of the first embodiment of the digital memory computing circuit proposed in this application;

[0041] Figure 5 This is a circuit schematic diagram of the digital memory computing circuit in the second embodiment of the digital memory computing circuit proposed in this application;

[0042] Figure 6 This is a timing diagram showing the changes of each signal in the second embodiment of the digital memory computing circuit proposed in this application;

[0043] Figure 7 This is a schematic diagram of the connection relationship of the word line input switching circuit proposed in this application;

[0044] Figure 8 This is a circuit schematic diagram of the digital memory computing circuit proposed in this application.

[0045] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0046] It should be understood that the specific embodiments described herein are merely used to explain the technical solutions of the present application and are not intended to limit the present application.

[0047] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0048] In the field of digital storage computing technology, typical digital storage computing solutions use hardware architectures such as... Figure 1As shown, the core idea of ​​this digital storage and computing scheme is to input the input data bit-by-bit serially into the SRAM array storing the weight data. The value of each bit of weight data is directly derived from the inverted output terminal of the SRAM cell and multiplied by a bit-NOT logic gate with the input data to be calculated via the word line inverted line IN_B. The multiplication result is input to the adder tree circuit next to the SRAM array to perform the addition operation. The word line WL, bit line BL, bit line inverted line BLB, and word line inverted line IN_B are all used for input data.

[0049] This scheme places a multiplier, an auxiliary computing structure, next to the original Weight SRAM cell, which includes six switching transistors. The layout of the digital in-memory computing circuit is as follows: Figure 2 As shown, the multiplier auxiliary operation structure is a NOR gate composed of at least four switching transistors, and its digital memory circuit schematic is as follows. Figure 3 As shown. The implementation of the multiplication function specifically includes: if the SRAM storage value including 6 switching transistors is 1, that is, the output terminal Q is high and the inverting output terminal QB is low, then if the input value is 1, that is, In_B is low, the upper half of the auxiliary operation structure is turned on, and the output terminal Out is high, that is, the output multiplication result is 1. If the SRAM storage value and the input value are not both 1, the upper half of the auxiliary operation structure cannot be turned on, the output terminal Out is low, that is, the output multiplication result is 0. This digital memory circuit includes at least 10 switching transistors, resulting in a large number of switching transistors and a large resource consumption in the memory operation process.

[0050] Therefore, to overcome the above-mentioned defects, this application provides a digital memory circuit including: a first switching transistor, a second switching transistor, and a latching circuit; a first end of the first switching transistor is connected to a bit line, and a second end of the first switching transistor is connected to a first end of the second switching transistor and an operation output terminal; a control terminal of the second switching transistor is connected to a word line, and a second end of the second switching transistor is connected to the latching circuit; the word line is used to input a first signal to the control terminal of the second switching transistor, and the bit line is used to input a second signal to the first end of the first switching transistor; the first and second switching transistors are used to be turned on when both the third signal input to the control terminal of the first switching transistor and the first signal input from the word line to the control terminal of the second switching transistor are high-level signals, and to send the second signal input from the bit line to the latching circuit for storage; the first or second switching transistor is used to be turned on when the second signal input from the bit line is low-level signal, to perform a multiplication operation based on the third signal input to the control terminal of the first switching transistor, the inverse signal of the third signal, and the output data signal of the latching circuit, and to output the operation result through the operation output terminal; the first signal is a word line input signal, the second signal is a bit line input signal, and the third signal is a calculation input signal.

[0051] Because this application controls the on / off state of the first and second switching transistors through the input of different signals, and combines the latch circuit for storage and multiplication calculation, the number of switching transistors required for the digital storage and computing process is reduced, effectively reducing the resource consumption of the digital storage and computing process.

[0052] Based on this, embodiments of this application provide a digital memory computing circuit, referring to... Figure 4 , Figure 4 This is a schematic diagram of the structure of the first embodiment of the digital memory computing circuit proposed in this application.

[0053] In the first embodiment, the digital memory circuit includes: a first switching transistor Q1, a second switching transistor Q2, and a latching circuit 10;

[0054] The first terminal of the first switching transistor Q1 is connected to the bit line BL, and the second terminal of the first switching transistor Q1 is connected to the first terminal of the second switching transistor Q2 and the operational output terminal OUT; the control terminal of the second switching transistor Q2 is connected to the word line WL, and the second terminal of the second switching transistor Q2 is connected to the latch circuit 10; the word line WL is used to input a first signal to the control terminal of the second switching transistor Q2, and the bit line BL is used to input a second signal to the first terminal of the first switching transistor Q1.

[0055] The first switch Q1 and the second switch Q2 are turned on when both the third signal input to the control terminal of the first switch Q1 and the first signal input to the control terminal of the second switch Q2 via the word line WL are high-level signals, and the second signal input via the bit line BL is sent to the latch circuit 10 for storage.

[0056] The first switch Q1 or the second switch Q2 is turned on when the second signal input to the bit line BL is a low-level signal. It performs a multiplication operation based on the third signal input to the control terminal of the first switch Q1, the inverse signal of the third signal, and the output data signal of the latch circuit 10, and outputs the operation result through the operation output terminal.

[0057] The first signal is a word line input signal, the second signal is a bit line input signal, and the third signal is a calculation input signal.

[0058] It should be understood that the first switching transistor Q1 and the second switching transistor Q2 are power transistors with on / off control functions, such as MOSFETs, IGBTs, magnetic switches, etc. The on / off states of the first switching transistor Q1 and the second switching transistor Q2 are not the same in different operating modes. The latch circuit 10 also exhibits different functions in different operating modes. In the data write mode, the latch circuit 10 is used to store the data to be stored; in the multiplication mode, the latch circuit 10 is used to provide a multiplier required for the multiplication operation.

[0059] It should be noted that the control terminal of the first switch Q1 receives different signals or is connected to different signal lines in different operating modes. For example, in storage mode, the control terminal of the first switch Q1 can be connected to the word line inversion line, but the signal input to the word line inversion line will not change with the input signal of the word line WL. Alternatively, the control terminal of the first switch Q1 can be directly connected to the connection line used for control of conduction, so that data writing can be performed when both the first switch Q1 and the second switch Q2 are conducting. As another example, in multiplication mode, the control terminal of the first switch Q1 can be directly connected to the word line inversion line, and the signal input to the word line inversion line is opposite in potential to the signal input to the word line WL.

[0060] It is understandable that when both the first switch Q1 and the second switch Q2 are on, the second signal input to the bit line BL can be directly input to the latch circuit 10 through the first switch Q1 and the second switch Q2. Therefore, in data writing mode, the data writing mode can be entered by inputting the level signals used to turn on the first switch Q1 and the second switch Q2 to the corresponding control terminals of the first switch Q1 and the second switch Q2. When one of the first switch Q1 and the second switch Q2 is on, and the first switch Q1 is on while the second switch Q2 is off, the signal input to the bit line BL is a low-level signal. The latch circuit 10 cannot provide an output data signal through the second switch Q2, and the result of the operation at the output terminal OUT is a low-level second operation result. When the first switch Q1 is off while the second switch Q2 is on, the latch circuit 10 can provide an output data signal through the second switch Q2, and the second signal input to the bit line BL cannot pass through the first switch Q1. In this case, the result of the operation at the output terminal OUT is a high-level second operation result. Therefore, in the multiplication operation mode, it is necessary to control one of the first switch Q1 and the second switch Q2 to be turned on and the other to be turned off.

[0061] Furthermore, considering that some switching transistors have different conduction logics—for example, the conduction logic of NMOS and PMOS transistors in MOSFETs is completely different—the levels of the first and third input signals need to change accordingly when different conduction logic switching transistors are set. When both the first and second switching transistors Q1 and Q2 are NMOS transistors, entering data write mode requires both the first and third signals to be high-level signals. When both the first and second switching transistors Q1 and Q2 are PMOS transistors, entering data write mode requires both the first and third signals to be low-level signals. When the first switching transistor Q1 is an NMOS transistor and the second switching transistor Q2 is a PMOS transistor, entering data write mode requires the first signal to be high-level and the third signal to be low-level. When the first switching transistor Q1 is a PMOS transistor and the second switching transistor Q2 is an NMOS transistor, entering data write mode requires the first signal to be low-level and the third signal to be high-level. When entering the multiplication operation mode, it is necessary to control one of the first switch Q1 and the second switch Q2 to be turned on and the other switch to be turned off. The specific control logic of the first switch Q1 and the second switch Q2 can be adjusted adaptively. For example, if one of the first switch Q1 and the second switch Q2 is an NMOS transistor and the other is a PMOS transistor, the control terminals of the two transistors can receive signals of the same level.

[0062] It should be noted that the first signal is a word line input signal, used to input to the control terminal of the second switch Q2 to control the on / off state of the second switch Q2. The second signal is a bit line input signal, input to the first terminal of the first switch Q1, used to input to the operation output terminal OUT or the latch circuit 10 when the first switch Q1 is turned on. The third signal is a calculation input signal, used to input to the control terminal of the first switch Q1 to control the on / off state of the first switch Q1.

[0063] In specific implementation, in data writing mode, a high-level third signal can be input to the control terminal of the first switch Q1 and a high-level first signal can be input to the control terminal of the second switch Q2. At this time, both the first switch Q1 and the second switch Q2 are in the on state. The second signal input through the bit line BL can be input to the latch circuit 10 for storage through the first switch Q1 and the second switch Q2, thereby realizing data writing. During this process, if the second signal input through the bit line BL is a high-level signal, the data "1" is written, the output terminal Q of the latch circuit 10 becomes "1", and the inverted output terminal QB node of the latch circuit 10 becomes "0"; conversely, if the second signal input through the bit line BL is a low-level signal, the data "0" is written, the output terminal Q of the latch circuit 10 becomes "0", and the inverted output terminal QB node of the latch circuit 10 becomes "1". In the multiplication operation mode, the second signal input to the bit line BL needs to be controlled to be a low-level signal, then one of the first switch Q1 and the second switch Q2 is controlled to be turned on. Finally, the multiplication operation is performed using the third signal, the inverse signal of the third signal, and the output data signal of the latch circuit 10, and the corresponding operation result is output at the operation output terminal OUT.

[0064] In this embodiment, the on / off state of the first and second switching transistors is controlled by inputting different signals, and storage and multiplication calculations are performed in combination with latch circuit, thereby reducing the number of switching transistors required for the digital storage and computation process and effectively reducing the resource consumption of the digital storage and computation process.

[0065] Based on the first embodiment described above, a second embodiment of the digital memory computing circuit of this application is proposed. In the second embodiment, considering that multiplication can be performed when one of the first switch Q1 and the second switch Q2 is turned on and the other is turned off, the operation result presented at the operation output terminal OUT is not the same whether the first switch Q1 is turned on or the second switch Q2 is turned on. In order to avoid the second signal at the bit line BL input terminal affecting the multiplication operation, in this embodiment, it is necessary to control the second signal at the bit line BL input terminal to be a low-level signal.

[0066] When the second switch Q2 is turned on, it conducts when the second signal input to the bit line BL is a low-level signal and the first signal input to the word line WL is a high-level signal. At this time, it receives the output data signal of the latch circuit 10 and performs a multiplication operation on the third signal, the inverted signal of the third signal, and the output data signal of the latch circuit to obtain the corresponding calculation result. The third signal and its inverted signal have opposite signal levels.

[0067] Reference Figure 4 When the second switch Q2 is turned on and the first switch Q1 is turned off, the calculation result output at the operational output terminal OUT is mainly affected by the output data signal of the latch circuit 10. When the output data signal of the latch circuit 10 is a high-level signal, the high-level signal outputs a first calculation result at the operational output terminal OUT through the second switch Q2; this first calculation result is the result of a multiplication operation with a result of "1". Of course, when the output data signal of the latch circuit 10 is a low-level signal, the low-level signal outputs a second calculation result at the operational output terminal OUT through the second switch Q2; this second calculation result is the result of a multiplication operation with a result of "0".

[0068] When the first switch Q1 is turned on, the first switch Q1 is turned on when the second signal input to the bit line is a low level signal and the third signal is a high level signal. At this time, since the second switch Q2 is turned off, the output data signal of the latch circuit 10 cannot reach the operation output terminal OUT. At this time, since the first switch Q1 is turned on, the potential of the operation output terminal OUT is pulled down to a low level by the second signal input to the bit line BL, that is, the second operation result is output at the operation output terminal OUT.

[0069] Referring to the table below, which is the circuit truth table of the digital memory computing circuit of this application in multiplication mode, when the output data signal of latch circuit 10 (i.e., the signal output by output terminal Q of latch circuit 10) is 1, the third signal In input by word line WL is 1, and the inverted signal InB of the third signal In is 0, the first operation result of outputting a high level "1" at the operation output terminal OUT is displayed. When the output data signal of latch circuit 10 (i.e., the signal output by output terminal Q of latch circuit 10) is 1, the third signal In input by word line WL is 0, and the inverted signal InB of the third signal In is 1, the second operation result of outputting a 0 at the operation output terminal OUT is displayed. When the output data signal of latch circuit 10 (i.e., the signal output by output terminal Q of latch circuit 10) is 0, the third signal In input by word line WL is 1, and the inverted signal InB of the third signal In is 0, the second operation result of outputting a 0 at the operation output terminal OUT is displayed. When the output data signal of latch circuit 10, i.e. the signal output by output terminal Q of latch circuit 10, is 0, the third signal In input by word line WL is 0, and the inverse signal InB of the third signal In is 1, the second operation result of 0 is output at the operation output terminal OUT.

[0070]

[0071] In addition, refer to Figure 5 , Figure 5 This is a circuit diagram of the digital memory computing circuit in the second embodiment of the digital memory computing circuit proposed in this application. In this embodiment, the latch circuit 10 includes: a third switch Q3, a fourth switch Q4, a fifth switch Q5, and a sixth switch Q6;

[0072] The control terminal of the third switch Q3 is connected to the second terminal of the fourth switch Q4, the control terminal of the fifth switch Q5, and the first terminal of the sixth switch Q6. The first terminal of the third switch Q3 is connected to the power supply, and the second terminal of the third switch Q3 is connected to the second terminal of the second switch Q2 and the first terminal of the fifth switch Q5.

[0073] The control terminal of the fourth switch Q4 is connected to the control terminal of the sixth switch Q6, the second terminal of the second switch Q2, the second terminal of the third switch Q3, and the first terminal of the fifth switch Q5. The first terminal of the fourth switch Q4 is connected to the power supply.

[0074] The second terminal of the fifth switch Q5 and the second terminal of the sixth switch Q6 are grounded.

[0075] It should be noted that the third switch Q3, the fourth switch Q4, the fifth switch Q5, and the sixth switch Q6 are all power transistors with control terminals. The third switch Q3 and the fourth switch Q4 are switches of the same conduction type, such as PMOS transistors; the fifth switch Q5 and the sixth switch Q6 are switches of the same conduction type, such as NMOS transistors. The third switch Q3 and the fifth switch Q5 form an inverter, and the fourth switch Q4 and the sixth switch Q6 form another inverter.

[0076] In this embodiment, an input-output interconnected latch circuit 10 is formed by connecting the control terminal of the third switch Q3 to the second terminal of the fourth switch Q4, the control terminal of the fifth switch Q5, and the first terminal of the sixth switch Q6, and connecting the control terminal of the fourth switch Q4 to the control terminal of the sixth switch Q6, the second terminal of the three switches Q3, and the first terminal of the fifth switch Q5. The output terminal Q of the latch circuit 10 is connected to the second terminal of the second switch Q2, and a data signal can be output through the output terminal Q in multiplication mode. The inverting output terminal QB of the latch circuit 10 is connected to the control terminals of the third switch Q3 and the fifth switch Q5, thereby controlling the third switch Q3 and the fifth switch Q5 using the signal output from the inverting output terminal QB. The output terminal Q of the latch circuit 10 is connected to the control terminals of the fourth switch Q4 and the sixth switch Q6, thereby controlling the fourth switch Q4 and the sixth switch Q6 using the signal output from the output terminal Q. In input write mode, the storage function of the second signal is realized by controlling the output terminal Q and the inverting output terminal QB.

[0077] It should be understood that the power supply is the voltage input source when the switching transistors are turned on. When both the third switch Q3 and the fifth switch Q5 are turned on, or both the fourth switch Q4 and the sixth switch Q6 are turned on, the power supply will be directly grounded. However, considering that the third switch Q3 and the fifth switch Q5 are inverters, and the fourth switch Q4 and the sixth switch Q6 are also inverters, their control terminals are connected to the same control signal, and their conduction types are not the same, the power supply will not be directly grounded.

[0078] Reference Figure 6 In specific implementation, under data input mode, the input of word line WL and inverted signal InB controls the first switch Q1 and the second switch Q2 to be in the conducting state. At this time, the second signal input by bit line BL can be directly input to the output terminal Q of latch circuit 10 through the first switch Q1 and the second switch Q2, and then stored in latch circuit 10 through the third switch Q3, the fourth switch Q4, the fifth switch Q5 and the sixth switch Q6 inside latch circuit 10.

[0079] In multiplication mode, it is necessary to control the second signal input to bit line BL to be a low-level signal and to control one of the first switch Q1 and the second switch Q2 to be turned on. For example, if the input inverted signal InB is a high-level signal, then the third signal is a low-level signal, controlling the first switch Q1 to be turned on and the second switch Q2 to be turned off. At this time, the multiplication result is the second operation result. Figure 6 In this context, CLK is the clock signal, BL is the second signal input through the bit line, WL is the first signal input through the word line, Q is the output data signal of the latch circuit 10, In is the third signal, InB is the inverse signal of the third signal, and OUT is the operation result signal output by the operation output terminal.

[0080] Furthermore, in this embodiment, for word lines WL, bit lines BL, and word line inversion lines used to input inversion signals InB in the peripheral circuit, when a high-level signal is required, the supply voltage can be set to 0.9V, and the supply voltage of latch circuit 10 can be set to 0.6V, thereby reducing power consumption while ensuring data writing.

[0081] Based on the first and second embodiments of the digital memory circuit described above, this application proposes a first embodiment of the word line input switching circuit.

[0082] Reference Figure 7 , Figure 7 This is a schematic diagram showing the connection relationship of the word line input switching circuit proposed in this application. In this embodiment, the word line input switching circuit 20 is connected to the control terminal of the second switching transistor Q2 through the word line WL, the word line input switching circuit 20 is connected to the control terminal of the first switching transistor Q1, and the word line input switching circuit 20 is also connected to the controller.

[0083] It should be understood that the first signal input to the control terminal of the second switch Q2 is different in different operating modes. In data writing mode, the first signal input to the control terminal of the second switch Q2 is a signal used to control the on / off state of the second switch Q2; while in multiplication mode, the first signal input to the control terminal of the second switch Q2 is the input data used to perform multiplication operations.

[0084] It should be noted that the word line input switching circuit 20 is used to control the switching of the first signal input to the second switch Q2. Upon receiving a working mode command corresponding to different working modes, the word line input switching circuit 20 can output the first signal corresponding to that command to the control terminal of the second switch Q2. The controller is a device used to control the switching of the working modes of the digital memory circuit. This controller can input commands to the word line input switching circuit 20, causing the word line input switching circuit 20 to output the first signal on the word line WL to the control terminal of the second switch Q2.

[0085] In a specific implementation, the controller can output the corresponding working mode instruction to the word line input switching circuit 20 according to the user's settings. When the word line input switching circuit 20 receives the working mode instruction, it inputs the corresponding first signal to the control terminal of the second switch Q2 according to the working mode instruction. At this time, the control terminal of the first switch Q1 can receive the third signal corresponding to the working mode instruction, thereby controlling the digital storage circuit to perform data writing or multiplication operations.

[0086] Specifically include:

[0087] When the controller outputs the working mode instruction corresponding to the data writing mode, the word line input switching circuit 20, upon receiving the working mode instruction, outputs a high-level signal as the first signal through the word line WL to the control terminal of the second switch Q2, and outputs a high-level signal as the third signal to the control terminal of the first switch Q1. At this time, both the first switch Q1 and the second switch Q2 are in the on state, thereby writing data to the second signal input by the bit line BL.

[0088] When the controller outputs a working mode instruction corresponding to the multiplication operation mode, the word line input switching circuit 20, upon receiving the working mode instruction, outputs the first signal used for multiplication calculation input through the word line WL to the control terminal of the second switch Q2, and inputs the calculation input signal used for calculation as the third signal to the control terminal of the first switch Q1. The signal level of the first signal is opposite to the signal level of the third signal.

[0089] Understandably, in multiplication mode, the control terminal of the second switch Q2 is connected to the word line WL, and the control terminal of the first switch Q1 is connected to the word line inverted. Therefore, in multiplication mode, the signal levels of the first and third signals are opposite. If the first signal is high, the third signal is low; if the first signal is low, the third signal is high.

[0090] Reference Figure 8 , Figure 8This is a circuit diagram of the digital memory computing circuit proposed in this application. In this embodiment, the word line input switching circuit includes: a selector S and an inverter P;

[0091] The first input terminal WL_in of the selector S is used to receive control signals input to the digital memory circuit.

[0092] The second input terminal In of the selector S is connected to the input terminal of the inverter P and is used to receive the calculation input signal input to the digital memory circuit for multiplication. The calculation input signal is input to the control terminal of the second switch Q2 in the form of the inverted signal of the third signal through the word line WL.

[0093] The control terminal C of the selector S is connected to the controller and is used to receive the working mode command output by the controller;

[0094] The output terminal of the selector S is connected to the control terminal of the second switch Q2 via the word line WL;

[0095] The output terminal of the inverter P is connected to the control terminal of the first switching transistor Q1.

[0096] It should be understood that the selector S has multiple input terminals, used to select one signal from multiple input signals for output. In this embodiment, the selector S is a 2-to-1 selector. The two input terminals of the selector S are respectively used to input a control signal in the form of a first signal through the word line WL to the control terminal of the second switch Q, and to input a calculation input signal in the form of the first signal (the inverse form of the third signal) to the control terminal of the second switch Q2. The inverter P is used for the multiplication operation mode. The output terminal of the inverter P is connected to the control terminal of the first switch Q1, and the input terminal is connected to the second input terminal of the selector S. That is, in the multiplication operation mode, the output terminal of the selector S outputs the calculation input signal in the form of the inverse of the third signal to the control terminal of the second switch Q2, and the output terminal of the inverter P outputs the calculation input signal in the form of the third signal to the control terminal of the first switch Q1.

[0097] In specific implementation, when data writing is required, the controller can input the corresponding operating mode command for the data writing mode through the control terminal of the selector S. At this time, the control signal at the first input terminal of the selector S is output to the control terminal of the second switch Q2. The second input terminal of the selector S does not input a calculation input signal and is in a low-level state. After passing through the inverter P, it is converted into a high-level third signal and input to the control terminal of the first switch Q1, thereby controlling both the first switch Q1 and the second switch Q2 to conduct, and the digital memory circuit enters the data writing mode. When multiplication is required, the controller can input the corresponding operating mode command for the multiplication operation mode through the control terminal of the selector S. At this time, the output terminal of the selector S outputs the calculation input signal input at the second input terminal and inputs it to the control terminal of the second switch Q2 in the form of a first signal. The calculation input signal input at the second input terminal is inverted by the inverter P and input to the control terminal of the first switch Q1 in the form of a third signal, thereby enabling either the first switch Q1 or the second switch Q2 to conduct, and the digital memory circuit to perform the multiplication operation mode.

[0098] Furthermore, in the multiplication operation mode, since the signal input to the second input terminal of selector S needs to be delayed by selector S in the path to the control terminal of the second switch Q2, and the signal input to the second input terminal needs to be delayed by inverter P in the path to the control terminal of the first switch Q1, the delay times of the two are relatively close. This allows the time when the first signal arrives at the control terminal of the second switch Q2 to be very close to the time when the third signal arrives at the first switch Q1. The phase difference between the first signal and the third signal is very small, thereby improving the glitches in the operation process and reducing circuit power consumption.

[0099] In addition, to achieve the above objectives, this application also provides a digital storage and computing system, including: an addition tree, a storage array, and a word line input switching circuit as described in the above embodiments; the storage array includes at least one row of digital storage and computing circuits as described in the above embodiments; the digital storage and computing circuits are connected to the addition tree through an operation output terminal; the number of word line input switching circuits is the same as the number of rows of the digital storage and computing circuits; each word line input switching circuit is connected to each of the digital storage and computing circuits in the corresponding row.

[0100] It should be noted that memory arrays often include a large number of digital in-memory (DIM) circuits. Each DIM circuit requires switching of the first signal of the word line input. Each DIM circuit has a word line input switching circuit on one side, and each word line input switching circuit requires considerable resources for control. Both the driver devices that drive the word line input switching circuits and the controllers that perform mode control on the word line input switching circuits consume significant resources. Therefore, in a DIM system, a DIM circuit can be connected to a row of DIM circuits in the memory array. By using one DIM circuit to control the signal switching of a row of DIM circuits, the resource consumption of the DIM system can be effectively reduced without affecting mode switching.

[0101] Furthermore, in this application, the digital in-memory computing system can be integrated into a System-on-a-Chip (SoC), such as the WTM2101. In addition to the CPU and accelerator set, the SoC also houses an embedded neural network processor with in-memory computing capabilities, boasting a computing power of 50 Gops and the ability to store 1.8 MB of weighted data. The WTM2101 chip can be widely used in the fields of intelligent voice and smart wearables, providing solutions for speech recognition, speech enhancement, health monitoring, environmental recognition, gesture recognition, motion recognition, visual recognition, and AOA positioning, helping products achieve a superior user experience. Regarding keyword wake-up and 100-word speech recognition, the WTM2101 chip can achieve wake-up with 1-20 words and continuous speech recognition of 40-300 words in a low-power state.

[0102] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0103] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

[0104] The above description is only a part of the embodiments of this application and does not limit the scope of this application. All equivalent structural transformations made under the technical concept of this application and using the content of this application specification and drawings, or direct / indirect applications in other related technical fields, are included within the protection scope of this application.

Claims

1. A digital memory circuit, characterized in that, The digital memory circuit includes: a first switching transistor, a second switching transistor, and a latching circuit; The first terminal of the first switching transistor is connected to the bit line, and the second terminal of the first switching transistor is connected to the first terminal of the second switching transistor and the operation output terminal; the control terminal of the second switching transistor is connected to the word line, and the second terminal of the second switching transistor is connected to the latch circuit; the word line is used to input a first signal to the control terminal of the second switching transistor, and the bit line is used to input a second signal to the first terminal of the first switching transistor. The first switch and the second switch are configured to be turned on when both the third signal input to the control terminal of the first switch and the first signal input from the word line to the control terminal of the second switch are high-level signals, and to send the second signal input from the bit line to the latch circuit for storage. The first or second switch is turned on when the second signal input to the bit line is a low-level signal, performs a multiplication operation based on the third signal input to the control terminal of the first switch, the inverse signal of the third signal, and the output data signal of the latch circuit, and outputs the operation result through the operation output terminal; The first signal is a word line input signal, the second signal is a bit line input signal, and the third signal is a calculation input signal.

2. The digital memory computing circuit as described in claim 1, characterized in that, The second switch is also configured to turn on when the second signal input to the bit line is a low-level signal and the first signal input to the word line is a high-level signal, receive the output data signal of the latch circuit, and perform a multiplication operation on the third signal, the inverted signal of the third signal, and the output data signal of the latch circuit.

3. The digital memory computing circuit as described in claim 2, characterized in that, The second switching transistor is also used to output the first calculation result through the operation output terminal when the output data signal of the latch circuit is a high-level signal; When the output data signal of the latch circuit is a low-level signal, the second calculation result is output through the calculation output terminal; the first calculation result is the opposite of the second calculation result.

4. The digital memory computing circuit as described in claim 1, characterized in that, The first switch is also configured to be turned on when the second signal input to the bit line is a low-level signal and the third signal is a high-level signal, and to output the second calculation result through the calculation output terminal.

5. The digital memory circuit as described in any one of claims 1 to 4, characterized in that, The latching circuit includes: a third switch, a fourth switch, a fifth switch, and a sixth switch; The control terminal of the third switch is connected to the second terminal of the fourth switch, the control terminal of the fifth switch, and the first terminal of the sixth switch. The first terminal of the third switch is connected to the power supply, and the second terminal of the third switch is connected to the second terminal of the second switch and the first terminal of the fifth switch. The control terminal of the fourth switch is connected to the control terminal of the sixth switch, the second terminal of the second switch, the second terminal of the third switch, and the first terminal of the fifth switch; the first terminal of the fourth switch is connected to the power supply. The second terminal of the fifth switch and the second terminal of the sixth switch are grounded.

6. A digital storage and computing system, characterized in that, include: An addition tree, a storage array, and a word line input switching circuit; the storage array includes at least one row of digital storage circuitry as described in any one of claims 1 to 5; The digital storage circuit is connected to the addition tree through its arithmetic output terminal; The number of word line input switching circuits is the same as the number of rows of the digital memory circuit; Each of the aforementioned word line input switching circuits is connected to the corresponding digital storage circuit within the same row.

7. The digital storage system as described in claim 6, characterized in that, The word line input switching circuit is connected to the control terminal of the second switching transistor via the word line, the word line input switching circuit is connected to the control terminal of the first switching transistor, and the word line input switching circuit is also connected to the controller; The word line input switching circuit is used to receive the working mode instruction output by the controller, and output a third signal to the control terminal of the first switching transistor according to the working mode instruction, and control the word line to output a first signal to the control terminal of the second switching transistor.

8. The digital storage system as described in claim 7, characterized in that, The word line input switching circuit is further configured to, when the received working mode instruction is data write mode, output a high-level signal as a first signal through the word line to the control terminal of the second switching transistor, and output a high-level signal as a third signal to the control terminal of the first switching transistor.

9. The digital storage system as described in claim 7, characterized in that, The word line input switching circuit is further configured to output the first signal to the control terminal of the second switch transistor via the word line when the received operating mode instruction is the multiplication operation mode, and to input the third signal to the control terminal of the first switch transistor, wherein the signal level of the first signal is opposite to the signal level of the third signal.

10. The digital storage system according to any one of claims 7 to 9, characterized in that, The word line input switching circuit includes: a selector and an inverter; The first input terminal of the selector is used to receive control signals input to the digital memory circuit. The second input terminal of the selector is connected to the input terminal of the inverter; The control terminal of the selector is connected to the controller and is used to receive the working mode command output by the controller; The output of the selector is connected to the control terminal of the second switching transistor via the word line; The output terminal of the inverter is connected to the control terminal of the first switching transistor.

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