A circuit netlist generation method supporting multi-stage inference of a deep learning model

Abstract

The application discloses a circuit netlist generation method supporting multi-stage inference of a deep learning model, and belongs to the technical field of electronic circuit design and automation, which acquires a circuit diagram image through optical scanning, pre-processes the image, and uses a deep learning model YOLOv5 to identify components and determine their bounding box coordinates and category information.Further, the components are finely identified at ports to determine the positions and directions of the ports.Optical character recognition technology is used to exclude text interference, identify wires, including Hough line detection and jumper processing, and determine the start and end coordinates of the wires.The identification results of the components, ports and wires are matched to construct the topological structure of the circuit diagram, finally generate a circuit netlist, and perform error elimination and JSON format output.The application can realize automatic netlist generation of an analog circuit diagram, convert an analog circuit diagram file into a netlist file with component function annotations, and improve the efficiency and quality of circuit design and simulation.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of electronic circuit design and automation technology, and specifically relates to a circuit netlist generation method supporting multi-stage inference of a deep learning model. BACKGROUND

[0002] With the wide application of electronic products, the design and simulation of analog circuits play a crucial role in the field of electronic engineering. However, the traditional analog circuit design process has many problems, which seriously restrict the efficiency and quality of circuit design.

[0003] On the one hand, manually drawing circuit diagrams and converting them into netlists is inefficient. Engineers need to spend a lot of time and effort to accurately draw each component and its connection relationship, and manual operation is prone to errors, which may lead to inaccurate simulation results of the entire circuit, thereby affecting the reliability and performance of the circuit design.

[0004] On the other hand, some existing auxiliary tools have deficiencies in component recognition accuracy, connection relationship recognition, and circuit function recognition. For example, some tools cannot accurately recognize components with similar shapes or non-standard labels, especially for active components with positive and negative polarities, the error rate is high; for complex cross-line and cross-line structures, it often leads to incorrect connection relationship judgment, affecting the accuracy of the netlist; and most existing tools lack the ability to recognize circuit functions, which cannot provide engineers with more in-depth circuit information, and are not conducive to circuit optimization and innovation.

[0005] In addition, there is often a problem of missing circuit diagram information in early projects and historical documents, which brings great difficulty to the maintenance, upgrading, and innovation of the circuit.

[0006] Therefore, in view of the problems of low efficiency, easy error, insufficient component recognition accuracy, difficult connection relationship recognition, and missing function recognition in the prior art, there is an urgent need for an efficient, highly automated, and high-accuracy analog circuit diagram to netlist solution. SUMMARY

[0007] To solve the above problems, the application provides a circuit netlist generation method supporting multi-stage inference of a deep learning model, which solves the problem of automatic conversion of analog circuit diagrams to netlists. Through machine learning and image processing technology, automatic netlist generation of analog circuit diagrams is realized, which can convert standard format analog circuit diagram files into netlist files with component function annotations, improving the efficiency and quality of circuit design and simulation.

[0008] To achieve the above purpose, the technical solution adopted by the application is:

[0009] The application provides a circuit netlist generation method supporting multi-stage inference of a deep learning model. The method obtains a circuit diagram image through optical scanning, pre-processes the image, and uses a deep learning model YOLOv5 to identify components and determine their bounding box coordinates and category information. Further, the method performs fine port identification on the components to determine the positions and directions of the ports. Meanwhile, the method uses optical character recognition technology to exclude text interference, performs wire identification, including Hough line detection and jumper processing, to determine the start and end coordinates of the wires. The identification results of the components, ports, and wires are matched to construct the topology of the circuit diagram, and finally a circuit netlist is generated, error elimination is performed, and JSON format output is obtained.

[0010] The above technical solution has the following beneficial effects: The automatic analysis of the circuit diagram is realized, and the efficiency and accuracy of the circuit netlist generation are improved. Through multi-stage deep learning model inference, the components, ports, and wires in the circuit diagram can be accurately identified, effectively solving the problem of identifying complex connection relationships in the circuit diagram. Meanwhile, by combining optical character recognition technology and Hough line detection methods, the accuracy and reliability of the identification are further improved. The finally generated JSON format netlist is convenient for subsequent circuit simulation, analysis, and optimization, and has high practicality and scalability. Compared with the prior art, the application can significantly improve the efficiency and quality of circuit netlist generation, and provides strong support for circuit design and analysis.

[0011] As a further improvement of the above scheme, the training process of the deep learning model YOLOv5 includes: collecting component image data in the circuit diagram, labeling the bounding box coordinates and category information of the components, dividing the labeled data set into a training set and a validation set, training the YOLOv5 model using the training set, and testing it on the validation set to obtain the precision and recall rate indicators of the model.

[0012] The above technical solution has the following beneficial effects: Through reasonable data set division and model training optimization, the accuracy and generalization ability of the YOLOv5 model in the component identification task can be improved, ensuring that the model has good performance in actual application. Compared with the prior art, the model training method of the application is more systematic and scientific, and can effectively improve the reliability of circuit netlist generation.

[0013] As a further improvement of the above scheme, the method of fine port identification includes determining the possible positions and directions of the ports according to the category information of the components, performing local feature extraction within the bounding box of the components, using a deep learning model or a traditional image processing algorithm to determine the specific positions and directions of the ports, calculating the center coordinates of the ports, and associating them with the bounding box coordinates of the components to form the correspondence between the ports and the components.

[0014] The technical scheme has the beneficial effects that the port position and direction of the component can be accurately identified, the accuracy and reliability of the port identification are improved, and more accurate data support is provided for subsequent circuit topology construction and net list generation.

[0015] As a further improvement of the above scheme, the optical character recognition technology uses an OCR tool to identify the text in the circuit diagram, including character recognition and position positioning of the text, and removes the identified text information from the image to avoid interference with the wire identification.

[0016] The technical scheme has the beneficial effects that the interference of the text in the circuit diagram with the wire identification is effectively eliminated, the accuracy and reliability of the wire identification are improved, and the correct construction of the circuit topology is ensured.

[0017] As a further improvement of the above scheme, the method of the Hough line detection includes:

[0018] Edge detection is performed on the image from which the text and component boxes are removed to extract edge pixel points in the image;

[0019] The edge pixel points are converted to a Hough space, and the number of votes for different line parameters is counted through an accumulator array;

[0020] The line in the image is determined according to the size of the number of votes, and the start and end point coordinates of the line are obtained;

[0021] The method of the Hough line detection is divided into two stages:

[0022] Stage one: initial line extraction;

[0023] Edge detection is performed on the image;

[0024] A probabilistic Hough transform is used to detect all possible line segments;

[0025] The end point coordinates of each line are obtained;

[0026] The result output by the stage one is a large number of short line segments, which may belong to the same electrical wire but are cut by image noise, symbols and the like;

[0027] Stage two: greedy coupling into a wire;

[0028] A distance threshold is set, for example, no more than δ pixels between the end points;

[0029] The greedy algorithm is used to combine the line segments close to each other and in the same direction into a single wire.

[0030] The final output wire is a combination of multiple original Hough line segments, representing a Net in the circuit.

[0031] The second-stage greedy coupling algorithm is used to handle the realistic problem that electrical wires may be "polyline" or "multi-segment splicing", which belongs to the part of geometric topology reconstruction.

[0032] The above technical solution has the beneficial effects of: through phased processing, efficient and accurate wire recognition is achieved. In the first stage, the probability Hough transform is used to extract short line segments in the image, effectively dealing with the wire breakage problem caused by image noise and symbol interference; the second-stage greedy coupling algorithm innovatively combines short line segments into complete wires, accurately solving the polyline or splicing problem of electrical wires, ensuring the integrity of wire recognition. This method significantly improves the accuracy of wire recognition, provides reliable basis for circuit topology structure construction, reduces false connections, enhances the accuracy and reliability of netlist generation, reduces manual correction cost, and promotes the efficiency of circuit design and simulation.

[0033] As a further improvement of the above scheme, the jumper processing method includes designing a specific convolution kernel to detect different types of node connections, or using a trained deep learning model to distinguish node types, determining the connection mode of the node according to the detection result, and processing the wire accordingly.

[0034] The above technical solution has the beneficial effects of: effectively solving the recognition problem of jumpers in the circuit diagram, improving the accuracy of wire connection relationship determination, and ensuring the correctness of the circuit topology structure. Compared with the prior art, the jumper processing method of the present application combines the advantages of convolution kernel detection and deep learning model, and can better adapt to the recognition needs of different types of nodes.

[0035] As a further improvement of the above scheme, the matching method includes determining the connection relationship between the port and the component according to the bounding box coordinates of the component and the position information of the port, determining the connection relationship between the wire and the port according to the start and end coordinates of the wire, and constructing the topology structure of the circuit diagram, including nodes, edges and connection relationships.

[0036] The above technical solution has the beneficial effects of: realizing accurate matching between components, ports and wires, improving the efficiency and accuracy of circuit topology structure construction, and providing reliable data support for subsequent netlist generation. Compared with the prior art, the matching method of the present application can better adapt to the complex connection relationship in the circuit diagram, and ensure the correctness of the circuit topology structure.

[0037] As a further improvement of the above scheme, the method of generating a circuit netlist includes integrating the type of components, port connection information and wire connection information to form a netlist data structure, assigning a unique identifier to each component and wire, verifying and optimizing the netlist data.

[0038] The technical scheme produces the beneficial effects that the generated circuit netlist structure is clear and complete, and can accurately reflect the connection relationship and electrical characteristics in the circuit diagram, providing a reliable data foundation for subsequent circuit simulation, analysis and optimization.

[0039] As a further improvement of the above scheme, the error elimination method includes verifying the validity of the connection object model, ensuring that each connection object is correctly defined in the netlist, checking the completeness of the netlist number, ensuring that each component is connected to at least one valid wire, eliminating isolated straight lines and suspended components, and correcting the incorrect connection in the circuit diagram.

[0040] The technical scheme produces the beneficial effects that the accuracy and reliability of the netlist are effectively improved, avoiding incorrect connections in circuit diagram analysis and ensuring that each connection in the netlist meets the expected design.

[0041] As a further improvement of the above scheme, the output content in JSON format includes a component list, a wire list, a special port list and a correspondence between the netlist number and the actual number, ensuring consistency with the number in the circuit diagram.

[0042] The technical scheme produces the beneficial effects that the output JSON format netlist has good scalability and easy processing, facilitating data reading and processing by subsequent circuit simulation, analysis and optimization tools, improving work efficiency and data compatibility.

[0043] Compared with the prior art, the technical scheme of the present application has the following specific technical effects:

[0044] 1. Breakthrough in fine identification of ports

[0045] For the fine recognition of the ports of components, the application innovatively combines component category information and local feature extraction. For example, for an operational amplifier, the ports can be accurately located and the directions determined within the bounding box. Compared with the prior art, the method can more accurately identify the port position and direction, providing high-precision data for subsequent circuit topology structure construction, and effectively solving the problems of ambiguity and inaccuracy in the prior art in port recognition.

[0046] 2. High-precision wire recognition

[0047] The wire recognition of the application fuses Hough line detection, greedy algorithm and jumper processing. First, the image is subjected to edge detection to extract pixel points, and then converted to Hough space to determine the line parameters. For jumpers, the processing method of combining convolution kernel and deep learning model is innovatively adopted. First, the short line segments in the image are extracted by Hough line detection, and then the short line segments close to each other and in the same direction are merged into complete wires by setting a distance threshold between the end points through the greedy algorithm. Compared with the prior art, the method can more accurately identify the complex wire connection relationship in the circuit diagram, especially when dealing with wires with occlusion and interference, and effectively solves the problems in wire recognition in the prior art, providing a reliable data basis for circuit topology structure construction.

[0048] 3. Precise matching and topology structure construction

[0049] The matching algorithm is innovatively designed to determine the connection relationship according to the bounding box of the component and the position of the port, and to determine the connection of the wire and the port according to the wire coordinates, thereby constructing a topology structure that accurately reflects the connection relationship and electrical characteristics of the circuit diagram. Compared with the prior art, the method greatly improves the matching efficiency and the accuracy of the topology structure construction, solves the difficult problem of complex connection relationship determination, and lays a solid foundation for netlist generation.

[0050] 4. High-quality netlist generation and verification optimization

[0051] When generating the circuit netlist, the application integrates component, port and wire information to form a standardized data structure, assigns a unique identifier, and performs comprehensive verification and optimization, including connection relationship legality check and redundant information exclusion. Compared with the prior art, the generated netlist is of higher quality and more complete data, can accurately reflect the circuit connection and characteristics, and provides reliable data support for subsequent circuit simulation, analysis and optimization, effectively solving the problems of inaccuracy and incompleteness in the prior art netlist generation technology.

[0052] 5. Deep learning model multi-stage reasoning innovation

[0053] The application innovatively applies a deep learning model to multiple stages of circuit diagram analysis, including component identification, port identification and jumper processing, fully utilizes the advantages of the deep learning model in image recognition and feature extraction, and improves the accuracy and efficiency of circuit diagram analysis through a multi-stage inference mechanism compared with the prior art relying on a single deep learning model or a traditional image processing algorithm. BRIEF DESCRIPTION OF DRAWINGS

[0054] Figure 1 The overall architecture of the circuit netlist generation system is shown.

[0055] Figure 2 The complete workflow of the circuit netlist generation is shown.

[0056] Figure 3 The specific implementation process of the component and port modules is shown.

[0057] Figure 4 The specific process of wire recognition is shown, which uses a greedy algorithm and a deep learning step.

[0058] Figure 5 The functional identification process is shown.

[0059] Figure 6 The component symbol recognition result of the circuit diagram is shown, wherein (a) is the original circuit diagram, (b) is the component identification diagram, and (c) is the fine port identification diagram.

[0060] Figure 7 The device connection relationship recognition result is shown, wherein (a) is the original image, (b) is the graph after removing the OCR text, and (c) is the final wire recognition display.

[0061] Figure 8 The recognition of three kinds of circuit nodes by the trained model is shown, wherein (a) is the recognition result of the wire interconnection, (b) and (c) are the recognition results of two different formats of jumper connection.

[0062] Figure 9 The straight line overflow fitting algorithm combined with the boundary and device internal detection flowchart is shown.

[0063] Figure 10 The straight line overflow fitting algorithm combined with the boundary and device internal detection example result is shown, wherein (a) is the mos tube connection determination result, and (b) is the resistance connection determination result.

[0064] Figure 11 The generated JSON format netlist information example is shown Figure 1 , wherein (a) is the result display diagram of the analog circuit diagram recognition, and (b) is the generated netlist result display diagram.

[0065] Figure 12 An example of the generated JSON format netlist information Figure 2 , where (a) is a display diagram of the result after recognizing the analog circuit diagram, and (b) is a display diagram of the generated netlist result.

[0066] Figure 13 An example of the generated JSON format netlist information Figure 3 , where (a) is a display diagram of the result after recognizing the analog circuit diagram, and (b) is a display diagram of the generated netlist result. DETAILED DESCRIPTION

[0067] In order for those skilled in the art to better understand the technical solutions, the present application will be described in detail below in conjunction with embodiments. The description in this part is only exemplary and explanatory, and should not have any limiting effect on the protection scope of the present application.

[0068] I. System architecture and module composition

[0069] As shown in Figure 1 , the overall architecture of the circuit netlist generation system supporting multi-stage inference of deep learning models is shown:

[0070] 1. Image input module: Obtain image data of analog circuit diagrams through optical scanning equipment or digital cameras, supporting common image formats such as JPEG, PNG, BMP, etc. This module provides raw image data input for the entire system and is the starting point for system work.

[0071] 2. Image preprocessing module: connected to the image input module, pre-processes the image data. Mainly includes: converting color images to grayscale images, performing binaryzation processing (threshold value 120-150, greater than 255 white, less than or equal to 0 black), and preliminarily extracting line and graphic information; using Gaussian filter algorithm for denoising; using OCR technology to recognize and filter out text information, obtaining a pure binary image containing only circuit diagram lines and graphic symbols. The pre-processed image data is used for subsequent component and wire recognition.

[0072] 3. Component recognition module: based on the YOLOv5 deep learning model, it can accurately recognize common components such as resistors, capacitors, diodes, transistors, MOS tubes, and operational amplifiers, and output their categories and position coordinates. This model is trained on a large number of labeled circuit diagram image data, and can learn the characteristics and category information of different components. During actual recognition, the pre-processed image is input, and the model outputs the position coordinates and category of the component region. The recognition result is passed to the port fine recognition module.

[0073] 4. Port fine identification module: using two-stage YOLO algorithm, the second stage uses YOLOv5m model to accurately locate the ports of components, and the recognition accuracy reaches more than 98.5%. Through the coordinate matching algorithm, the ports are accurately associated with the components they belong to. First, use the YOLOv5 model for preliminary identification to determine the approximate position range of the components, then input the image of the region into the YOLOv5m model for fine identification to accurately determine the position coordinates of the component ports, and based on the coordinate matching algorithm, determine which component the port belongs to, realize the accurate association of the port and the component it belongs to. After completing the fine identification of the port, the port information is transmitted to the netlist automatic generation module.

[0074] 5. Connection wire identification module: based on Hough transform algorithm, the angle range is 0°-180°, and the detection threshold is set between 100-150, which can detect the connection relationship of the wires. When identifying the circuit diagram, first use the Hough transform algorithm to detect the straight lines in the image, cover the wires in different directions, and filter out the straight line segments that meet the wire characteristics by setting the threshold. Then, use the greedy algorithm to process the detected straight line segments, set the distance threshold between the endpoints, and combine the short line segments that are close and consistent in direction into complete wires, thereby realizing accurate identification of complex wire connection relationships, especially when dealing with wires with occlusion and interference. For special cross wires and cross-line structures, a pre-trained deep learning model is used for identification. This model is trained based on a large number of related circuit diagram image data and can accurately distinguish the cross connection and cross-line connection relationship between wires, such as accurately identifying a wire that is not connected across from another component, and recording the start and end coordinates of the wire and the connection relationship. The identified wire connection relationship is then transmitted to the netlist automatic generation module.

[0075] 6. Netlist automatic generation module: with the help of straight line overflow fitting algorithm and boundary detection algorithm, the automatic matching of component ports and connection wires is realized, and a standard format netlist file is generated, supporting mainstream netlist formats such as JSON. After the identification of components, ports and wires is completed, taking one port of a resistor [x3, y3] and the wire connected to it as an example, the straight line overflow fitting algorithm determines the connection between the wire and the port according to the coordinate information of the port and the wire, and the boundary detection algorithm determines which port of which component the other end of the wire is connected to, thereby realizing the automatic matching of component ports and connection wires. Finally, all matching results are arranged and packaged according to the requirements of JSON format, generating a netlist file containing component information, port information and wire connection relationship, etc. This file can clearly and accurately reflect the circuit topology structure and can be directly read and analyzed by circuit simulation software for subsequent simulation analysis.

[0076] 7. Function Identification Module: Based on a voting mechanism, the module outputs the circuit function identification results by determining whether specific components and specific netlist structures exist in the circuit. For example, when it is identified that the circuit contains components such as operational amplifiers, resistors, and capacitors, and the netlist structure conforms to the characteristics of a filter circuit, such as a typical filter circuit topology where the input of an operational amplifier is connected to a resistor and capacitor to form a filter network, and the output feedback is connected to the input, the voting mechanism in the function identification module votes on each key feature according to the preset filter function judgment rules. When a certain number of votes is met, the circuit is judged to have a filtering function, and further judged to have a low-pass filtering function based on the filter component parameters and connection method. This function information is added to the netlist file, providing circuit designers with more comprehensive circuit information to assist in circuit design and optimization.

[0077] like Figures 2-7 As shown, this embodiment provides a circuit netlist generation method that supports multi-stage reasoning of a deep learning model, and the specific steps are as follows:

[0078] 1. Image Acquisition

[0079] Use an optical scanning device or digital camera to scan or photograph the circuit diagram to obtain an image of the circuit diagram. The image resolution must be no less than 300dpi to ensure that the details in the circuit diagram are clearly presented, providing a high-quality image foundation for subsequent recognition processing.

[0080] 2. Image Preprocessing: De-noising, grayscaling, binarization, edge detection, and morphological operations are performed on the circuit diagram image. De-noising uses a Gaussian filter with a 3×3 kernel; grayscaling uses the formula GRAY = 0.299×R + 0.587×G + 0.114×B; binarization uses the Otsu method to automatically determine the threshold; edge detection uses the Sobel operator; morphological operations include erosion and dilation, with a 3×3 rectangle as the structuring element to remove noise and close broken lines.

[0081] 3. Component Identification: Use the YOLOv5 model to identify components in preprocessed images. Collect common component image data and annotate bounding box coordinates and category information. The annotation format is:

[0082] [x_center,y_center,width,height,class_id]

[0083] The dataset was split into training and validation sets with a ratio of 8:2. The YOLOv5 model was used for training, with a learning rate of 0.01, 300 iterations, and a batch size of 16. Hyperparameters were adjusted during training to optimize performance. After training, the model was tested on the validation set, with a minimum accuracy of 90% and a minimum recall of 85%.

[0084] 4. Port fine identification

[0085] According to the bounding box coordinates and category information of the component, the port fine identification of the component is performed. Taking an operational amplifier as an example, the possible position and direction of the port are determined according to the category information. Within the bounding box of the operational amplifier, local feature extraction is performed on the image, and the specific position and direction of the port are determined by using a template matching algorithm. In the template matching algorithm, the template image is a pre-defined operational amplifier port feature image, and the matching threshold is set to 0.8. The center coordinates of the port are calculated, and are associated with the bounding box coordinates of the component to form the corresponding relationship between the port and the component. For other types of components, similar template matching or other traditional image processing algorithms are used for port fine identification.

[0086] 5. Wire identification

[0087] Wire identification is performed on the image from which the text and component boxes are removed.

[0088] (1) Combination of Hough line detection and greedy algorithm

[0089] Firstly, edge detection is performed on the image to extract the edge pixel points in the image. The Canny edge detection algorithm is used, with the threshold 1 being 50 and the threshold 2 being 150. The edge pixel points are converted to the Hough space, and the voting numbers of different line parameters are counted by using an accumulator array. The size of the accumulator array is set to 180x180, the angle resolution is set to 1 degree, and the distance resolution is set to 1 pixel. According to the size of the voting number, the straight line in the image is determined, and the start and end point coordinates of the straight line are obtained, with the requirement that the minimum length of the straight line is 10 pixels and the maximum gap is 3 pixels.

[0090] Subsequently, the greedy algorithm is used to optimize the detected straight lines. The specific steps are as follows:

[0091] Step one: initialize the parameters of the greedy algorithm, including setting the distance threshold (such as δ pixels) and the angle threshold (such as θ degrees) between the end points, which are used to judge whether the short line segments can be combined.

[0092] Step two: perform end point screening on the short line segments obtained by Hough line detection, and extract the start and end point coordinates of each short line segment.

[0093] Step three: construct a neighborhood relationship table, detect and record the pairs of short line segments that are adjacent and have the same direction according to the distance threshold δ and the angle threshold θ. Specifically, the distance between the end points of each short line segment and other short line segments and the included angle between the line segments are calculated.

[0094] Step four: According to the strategy of the greedy algorithm, select a pair of short line segments with the maximum merging potential for merging operation. For example, the longest pair of short line segments that meet the conditions can be selected, or the pair of short line segments that can generate the largest possible complete conductor can be selected.

[0095] Step five: Update the adjacency table, remove the merged short line segments, and add the newly merged long conductor. At the same time, recalculate the adjacency related to the new long conductor.

[0096] Step six: Repeat steps three to five, continuously merging short line segments until no pair of short line segments that meet the distance and angle threshold conditions can be found. The final output conductor is a combination of multiple original Hough line segments, representing a Net in the circuit.

[0097] Through the application of the above greedy algorithm, the broken line or the conductor composed of multiple segments in the circuit diagram can be effectively processed, ensuring the integrity and accuracy of the conductor identification.

[0098] (2) Jump wire processing

[0099] A trained deep learning model is used to distinguish different types of node connections. Image data of current nodes, cross nodes, and jumper nodes in the circuit diagram are collected, and the class information of the nodes is labeled. A convolutional neural network (CNN) model is used for training, and the model structure includes 3 convolutional layers and 2 fully connected layers. The filter sizes of the convolutional layers are 3x3, 5x5, and 7x7, the step is 1, and the padding method is same; the number of neurons in the fully connected layers is 128 and 3 respectively. After training, the nodes in the circuit diagram are classified and identified to determine the connection mode of the nodes, and the conductors are processed accordingly.

[0100] 7. Matching and topology construction

[0101] (1) Port and component matching

[0102] According to the bounding box coordinates of the components and the position information of the ports, the connection relationship between the ports and the components is determined. The distance between the center coordinates of the port and the center coordinates of the component bounding box is calculated, and if the distance is less than a set threshold (e.g. 10 pixels), it is considered that the port belongs to the component.

[0103] (2) Conductor and port matching

[0104] According to the start and end coordinates of the conductor, the connection relationship between the conductor and the port is determined. The distance between the start and end coordinates of the conductor and the center coordinates of the port is calculated, and if the distance is less than a set threshold (e.g. 5 pixels), it is considered that the conductor is connected to the port. The topology of the circuit diagram is constructed, including nodes, edges, and connection relationships. Each node represents a port or a connection point, each edge represents a conductor, and the connection relationship represents the electrical connection between nodes.

[0105] 8. Netlist generation

[0106] (1) Netlist data integration

[0107] Integrate the type of components, port connection information, and wire connection information to form a netlist data structure. Assign a unique identifier to each component and wire, using a combination of letters and numbers, such as R1, C1, Q1, etc. The netlist data structure uses a dictionary format, with the key being the component identifier and the value being the type and port connection information of the component; the key is the wire identifier, and the value is the starting and ending coordinates of the wire and the connected port information.

[0108] (2) Netlist verification and optimization

[0109] Verify and optimize the netlist data, including checking the legality of the connection relationship, eliminating redundant information, etc. Check if each component's port is connected correctly, and if the wire is connected to a valid port, eliminate non-existent components or port information.

[0110] 9. Error elimination

[0111] (1) Connection object model verification

[0112] Verify the validity of the connection object model to ensure that each connection object is correctly defined in the netlist. Check if the number and type of each component's port meet its electrical characteristics, such as a resistor should have two ports, and a capacitor should also have two ports, etc. If the model of a connection object is not defined or incomplete, the connection object is considered invalid and is removed from the netlist.

[0113] (2) Netlist number integrity check

[0114] Check the integrity of the netlist number to ensure that each component is connected to at least one valid wire. Traverse each component in the netlist and check if its port connection information contains a valid wire identifier. Eliminate isolated straight lines and suspended components, and correct the incorrect connections in the circuit diagram.

[0115] 10. Netlist output

[0116] Output the corrected netlist in JSON format. The output content of the JSON format includes:

[0117] (1) Component list

[0118] Each component contains type, identifier, and port connection information. For example: { "R1": { "type": "Resistor", "pins": { "pos": "net1", "neg": "net2"}}, "C1": { "type": "Capacitor", "pins": { "pos": "net3", "neg": "net4"}}}.

[0119] (2) Wire list

[0120] Each wire contains start and end coordinates and connected port information. For example: { "W1": { "start": [x1, y1], "end": [x2, y2], "net": "net1"}}.

[0121] (3) Special port list

[0122] Including port information of power and ground connections such as VDD and GND. For example: { "VDD": { "net": "net5"}, "GND": { "net": "net6"}}.

[0123] (4) Netlist number correspondence

[0124] Explicit netlist number and actual number correspondence to ensure consistency with the number in the circuit diagram. For example: { "net1": "VCC", "net2": "GND", "net3": "IN", "net4": "OUT"}.

[0125] Through the above steps, the embodiment realizes a circuit netlist generation method supporting multi-stage inference of deep learning models. This method can accurately identify components, ports and wires in the circuit diagram, construct the topological structure of the circuit diagram, generate accurate circuit netlist, and output in JSON format, providing reliable data support for subsequent circuit simulation, analysis and optimization. At the same time, this method has strict verification and optimization in each step to ensure the accuracy and integrity of the netlist, meeting the needs of high-precision circuit analysis.

[0126] As shown in Figure 3 , the specific implementation process of the component and port modules is as follows:

[0127] 1. Data preparation: 2200 pieces of json format data are provided for model training.

[0128] 2. Data conversion and import: Convert json data to txt file and import into YOLOv5 model.

[0129] 3. Model training and validation: Train the YOLOv5 model using the training data and test the model's recognition effect on the validation set to ensure that the model can accurately identify the components in the circuit diagram.

[0130] 4. Supplementary recognition: Additional recognition processing is performed for specific information such as adders, operational amplifier inputs, arrows, labels, etc. to improve the comprehensiveness and accuracy of the model.

[0131] As shown in Figure 4 , the specific process of wire recognition is demonstrated, which uses two steps of greedy algorithm and deep learning. The specific steps are as follows:

[0132] 1. Read coordinate information: Read the coordinates of the components identified by the YOLO model and the coordinates of the OCR text recognition.

[0133] 2. Pre-process the image: Pre-process the image to enhance the feature extraction effect.

[0134] 3. Pixel traversal and algorithm processing:

[0135] Traverse the black pixels in the image.

[0136] Apply the greedy algorithm for path planning and recognition.

[0137] Perform path processing to extract complete path information.

[0138] 4. Path output: Output the recognized path information to provide a basis for subsequent netlist generation.

[0139] As shown in Figure 5 , the recognition verification and function judgment process of the method of the present application is demonstrated, and the specific steps are as follows:

[0140] 1. Verify the connection relationship: Determine whether the connection mode of the MOS tube identified is correct, including the connection of the source (S), gate (G), and drain (D).

[0141] 2. Recognize specific components: Determine whether the circuit only contains BIT, SIGN, DIDO, and other specific components to determine the type and function of the circuit.

[0142] 3. Judge the connection of operational amplifier: Identify the components connected to the output port of the operational amplifier to further analyze the function of the circuit.

[0143] 4. Function recognition and output: Output the corresponding function label such as comparator, LOGIC, etc. according to the recognition result to provide a basis for the function recognition of the circuit.

[0144] Figure 6The example diagram of the circuit diagram component symbol recognition result shows the recognition result of the model on the components and connection relationships in the circuit diagram through different colors or marks, and intuitively presents the recognition effect of the model.

[0145] The detailed implementation process of the present application is as follows:

[0146] 1. Overall framework

[0147] The design structure of the framework is shown in Figure 1 The overall framework of the present system relies on the cooperative operation of three core modules of port recognition, wire recognition and netlist output, and aims to realize the automatic analysis of analog circuit diagrams through computer vision and deep learning technology.

[0148] Specifically, for the component recognition problem in the circuit diagram, due to the variety of elements involved in the circuit diagram and the different symbol representations, the connection lines often cross or block the component symbols, in addition, there may be additional annotation information in the diagram, these factors make the recognition task more complex. Therefore, it is particularly important to use deep learning models (such as YOLOv5, YOLOv8, etc.) for component recognition. These models perform well in image classification and object detection, and can efficiently recognize various components in the circuit diagram. Through data enhancement techniques (such as rotation, scaling, cropping, etc.), the diversity of the training data set is enriched, and the generalization ability of the model is further improved. In addition, the introduction of attention mechanisms or region proposal networks (RPN) and other technologies helps to improve the recognition accuracy of component boundaries and connection points.

[0149] When recognizing the connection relationship between components, the circuit diagram may use cross-line or node annotation methods with bridges, and the line shape is various and irregular, which increases the difficulty of connection relationship determination. At the same time, due to different drawing styles in the circuit diagram, the line width may not be consistent, which further affects the judgment of connection integrity. Therefore, it is necessary to combine image processing techniques (such as Hough transform, edge detection, etc.) to extract line information, and design optimization algorithms for post-processing of the extracted line information, such as smoothing, denoising, etc. Further, using graph neural network (GNN) and other technologies, the topological structure of the circuit diagram can be constructed to accurately reflect the connection relationship between components.

[0150] Through the above methods, the entire framework can realize efficient automatic analysis of analog circuit diagrams, accurately extract component and connection information, and provide reliable data basis for subsequent netlist generation and circuit analysis.

[0151] 2. Port recognition

[0152] 2.1 Two-stage YOLO port recognition (port and component matching algorithm, specific position coordinate algorithm)

[0153] In the port identification task, this study adopts a two-stage YOLO identification method to improve the accuracy and speed of port identification. First, the YOLO neural network is used to identify all components and ports in the circuit diagram, which quickly and preliminarily determines the location of circuit components in the circuit diagram and extracts their coordinate information. The results of this stage provide preliminary data support for the subsequent netlist generation. Through manual verification of the identification results, the recognition accuracy reaches 98.5%.

[0154] To achieve accurate netlist generation at the port level, especially in the identification of directional components such as diodes, transistors, MOS tubes, and operational amplifiers, we propose a two-stage port identification method based on YOLO.

[0155] Existing mainstream methods usually perform secondary identification by cropping the region of interest (ROI) based on preliminary identification, and then extract port information. However, when the number of ports to be identified in the circuit diagram exceeds 10, the overall calculation time will significantly increase.

[0156] To balance the accuracy and efficiency of identification, we propose an improved two-stage YOLO identification algorithm, as follows:

[0157] In the first stage, we use the YOLOv5 model to preliminarily identify the components in the entire circuit diagram, identifying the locations of all components.

[0158] In the second stage, we perform fine identification of the ports at the component level. For this purpose, we re-construct the data set at the port level, and separately increase the YOLOv5m model to optimize the accuracy and efficiency of port identification. In the construction of the data set, we re-design the port identification framework through the summary and analysis of 2216 circuit diagrams, and increase the training data of the second-stage model according to the characteristics of different types of components.

[0159] After optimizing the data set, the circuit diagram identified by the first-stage YOLO is pre-processed and input into the second-stage YOLOv5m model for port identification, obtaining the corresponding port information.

[0160] The port information in this stage and the component identification results in the first stage are associated through a coordinate matching algorithm. To effectively solve the problem of intersection between the port identification frame and the component identification frame, we have strictly constrained the port identification frame during the construction of the data set, ensuring that it is always located within the identification frame of the corresponding component, thereby avoiding the possibility of overlapping identification.

[0161] In the implementation of port matching, we use double for loop to match each bounding box. Specifically, we first determine the possible port area according to the bounding box of each component, and then use double loop to traverse all the identified component information to find the matching coordinates of the port in the current component box. By calculating whether the center point of the port is located in the component box, we further confirm the matching relationship between the port and the component. The formula is as shown in the formula.

[0162] Two sets of box data can be obtained by twice yolo recognition, denoted as , The center point of box2 is:

[0163]

[0164] Given the four corner coordinates of box1 , we judge whether the center point of box2 is in box1 by the following conditions:

[0165]

[0166] where and are the x and y coordinates of the center point of box2. Through this algorithm, we effectively combine the two-stage YOLO recognition and coordinate matching process, greatly reducing the computational complexity.

[0167] After completing the matching of components and ports, we use coordinate operation algorithm to further calculate the accurate position of each port relative to the component box.

[0168] For each different component , there are different ports that have been matched. At this time, box2 is located inside box1. In order to determine the orientation of box2 relative to box1, we need to compare the upper, lower, left and right distances.

[0169] Upper distance:

[0170]

[0171] Lower distance:

[0172]

[0173] Left distance:

[0174]

[0175] Right distance:

[0176] ​

[0177] After calculating the distances of the four sides, we can determine the position of box2 based on the smallest two distances. Calculate the smallest two distances to determine the orientation:

[0178]

[0179] For example, when identifying MOS tubes, we determine the orientation of the component by calculating the distances of the gate, source, and drain relative to the frame, and finally obtain the accurate positions of each port (such as gate, source, drain, etc.) in the circuit diagram based on the characteristics of the component and the distance relationship between the ports. This process effectively converts the position of each port into precise coordinate values and stores them in a dictionary.

[0180] The port identification of other circuit components also follows similar algorithm steps to ensure accurate extraction of port information.

[0181] Through this two-stage YOLO port identification method, combined with coordinate matching and accurate positioning algorithm, we can efficiently and accurately extract the position information of each component and its port in the circuit diagram, providing solid data support for subsequent netlist generation and circuit analysis.

[0182] 3. Wire identification

[0183] 3.1 Preprocessing and component exclusion

[0184] In the circuit topology graph, the connection of wires is usually represented as horizontal and vertical straight lines, so wire identification is crucial for the structural analysis of circuit diagrams. In this study, to accurately identify the wire connections in the circuit diagram, we combined optical character recognition (OCR) technology and the component identification results of the YOLO model to remove the text and component information in the circuit diagram, thereby reducing the impact of these interferences on subsequent straight line detection.

[0185] OCR technology is mainly used to identify the text labels (such as VDD, GND, etc.) in the circuit diagram, which may interfere with the identification of wires. At the same time, the YOLO model is used to identify the components in the circuit diagram and remove their position boxes. Through these two steps of processing, we can effectively exclude the text and component information in the circuit diagram, and provide a clean circuit diagram for subsequent wire detection, only retaining the wire connection information.

[0186] After performing OCR text recognition, the device boxes identified by YOLO and the character boxes identified by OCR are removed from the original circuit diagram at the same time, leaving only isolated straight lines. This processing greatly simplifies the detection process of the wires, enabling the Hough line detection algorithm to more accurately extract the connection lines in the circuit diagram.

[0187] 3.2 Hough Line Detection and Applications

[0188] After filtering out the noise through OCR and YOLO recognition, we apply the Hough Transform algorithm to detect the remaining isolated lines. Hough Transform is a classic image processing technique widely used for geometric shape recognition in images, especially for line detection. In this study, Hough Transform helps us identify the connection lines between components in the circuit diagram, further revealing the topology of the circuit.

[0189] Since we have removed all the text and component boxes in the preprocessing stage, the Hough line detection algorithm only detects isolated lines in the image. This method has the advantage of avoiding interference caused by text and component blocking, making the line detection more accurate.

[0190] Hough Transform maps each point in the image space to the parameter space, finding the peak in the parameter space to determine the straight line in the image. In the parameter space, each straight line in the image space corresponds to a point, and by finding the intersection of these points, we can identify the connection lines in the circuit diagram.

[0191] 3.3 Jumper Processing

[0192] In the circuit topology diagram, there are usually three ways to cross the wires:

[0193] (a) Two wires connected at a current node.

[0194] (b) Two wires cross but do not connect.

[0195] (c) Similar to (b), two wires cross but do not connect, which is a cross-line.

[0196] To distinguish between these three ways of connecting nodes, we use a deep learning algorithm:

[0197] The deep learning solution uses a trained model to identify different types of node connections. Through machine learning, the model can automatically learn the features in the circuit diagram and distinguish node types. The advantage of this method is high accuracy and low computational cost, especially in complex circuit diagrams.

[0198] The deep learning method can more accurately identify different nodes in the circuit diagram by training the model, with lower computational resource consumption. This significantly improves the recognition accuracy and efficiency. As shown in Figure 8 , the trained model recognizes the three types of circuit nodes shown in the figure.

[0199] 3.4. Innovative Method Combining YOLO and Hough Transform

[0200] The innovation of this study lies in the organic combination of three technologies: component recognition using the YOLO model, character filtering using OCR, and Hough line detection. By using YOLO for component recognition, removing text interference using OCR, and extracting connections of wires through Hough transformation, a high-efficiency and accurate processing flow is formed.

[0201] This combination solves the problem of detecting complex connection lines in circuit diagrams, especially in cases where there is occlusion or interference in the circuit diagram. By removing interference first and then extracting straight lines, the detection accuracy is significantly improved. In addition, Hough transformation only focuses on isolated straight lines during processing, rather than parts that are occluded by text or component boxes, ensuring accurate extraction of circuit diagram connection lines.

[0202] This method not only effectively improves the analysis accuracy of circuit diagrams, but also provides strong data support for subsequent circuit netlist generation and circuit function module recognition.

[0203] 4. Netlist output

[0204] 4.1, Coordinate matching

[0205] 4.1.1 Wire and component coordinate matching

[0206] In circuit diagram analysis, after completing node category determination, the next task is to determine the connection of wires to each node to distinguish the connection relationship between current branches and modules. This study proposes a method based on "straight line overflow fitting algorithm" to determine the connection relationship between wires and ports by detecting pixels in different regions around devices.

[0207] Specifically, this method is based on a machine learning model that detects pixels near devices and approximates the set of these pixels as a straight line. The straight line selected by the algorithm is the wire connected to the device.

[0208] Although the machine learning model can effectively identify the wires connected to the device, overfitting problems may occur during model training. In this study, this problem is reflected when the four corner regions of the detection box have no wires. The model may rely on specific patterns overfitting in the training data, resulting in reduced recognition accuracy in these regions and affecting the final determination result.

[0209] To eliminate this defect, we designed a boundary detection algorithm that can handle special cases such as when no wires are detected. By detecting the distance of pixels to the boundary of the region, the direction of the wire can be further determined.

[0210] In addition, some wires may pass through the inside of the device, affecting the recognition result. To solve this problem, we further expand the detection area to cover the inside of the device.

[0211] Through the above-optimized straight-line overflow fitting algorithm, combined with boundary and internal device detection, the connection relationship between the wire and the device can be more accurately determined. Finally, the algorithm is executed according to the flow shown in Figure 9 , and the example results are shown in Figure 10 .

[0212] 4.2 Port and wire matching

[0213] Once the wire and device connection is determined, the next step is to match the connection point coordinates with the port coordinates. This process is completed by calculating the distance between the points. Specifically, we use the following mathematical formula to calculate the Euclidean distance between the connection point and the port .

[0214]

[0215] where, is the coordinate of the connection point, is the coordinate of the port.

[0216] We set a threshold , if the calculated distance is less than the threshold , it is considered that the wire is connected to the port, that is:

[0217]

[0218] The threshold is set based on the minimum value of the component box to ensure the accuracy of the determination result. Through this port and wire matching, we finally get a dictionary containing the connection relationship between the wire and the component port. The dictionary stores the connection information as the value with the netlist number as the key. These information provides reliable data support for subsequent circuit analysis and netlist generation.

[0219] 5. Exclude error netlist and output format

[0220] In the process of circuit diagram analysis, in order to ensure the accuracy and completeness of the generated netlist, a series of steps are taken to exclude errors in the netlist. Finally, the corrected netlist is output in JSON format to ensure data scalability and facilitate subsequent processing. The specific process includes the following steps:

[0221] 5.1 Exclude incorrect connections

[0222] First, by validating the effectiveness of the connection object model, we ensure that each connection object is correctly defined in the netlist. If the model of a connection object is not defined or incomplete, the connection object is considered invalid and is removed from the netlist. This step effectively avoids incorrect connections in the circuit diagram parsing and ensures that each connection in the netlist conforms to the expected design.

[0223] Secondly, after completing the validation of the connection objects, we check the integrity of the netlist numbering. We ensure that each component in the netlist is connected to at least one valid wire, thereby eliminating isolated lines and dangling components. Isolated lines and dangling components are incorrect connections in the circuit diagram and should not appear in a valid netlist. Through this exclusion process, the connection relationships in the netlist are corrected to the accurate circuit structure.

[0224] 5.2 Netlist Output

[0225] After completing the error exclusion, the final generated netlist will be output in JSON format. Since the netlist numbering is not renumbered during error exclusion, the original netlist numbering will remain unchanged, ensuring consistency with the numbering in the circuit diagram. However, in some cases, if the connection in the netlist involves VDD or GND, the netlist numbering will directly use VDD and GND as the connection numbering. Specifically, when the port connection in the netlist is identified as "VDD" or "GND", the system will automatically use it as the netlist numbering to correspond to the power and ground connections in the circuit diagram.

[0226] An example of the generated JSON format netlist information is shown as Figures 11-13 As shown in the final output netlist, it contains the type of each component (such as NMOS, PMOS, etc.) and its corresponding port connection information. Each port connection is associated with the corresponding network number (such as net4, net5, etc.). If the connection is to VDD or GND, the corresponding netlist numbering is "VDD" or "GND".

[0227] 5.3 Summary

[0228] Through the above steps, we ensure that the generated netlist is accurate and all invalid connections are excluded. The final netlist retains the original netlist numbering and is output in JSON format. In particular, when the netlist is connected to VDD or GND, VDD and GND are directly used as the netlist numbering. This output format guarantees the structured and efficient processing of the netlist, suitable for subsequent circuit simulation, analysis and optimization tasks.

[0229] It should be noted that in this text, the terms: including, containing and any other variants are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. The principles and embodiments of the technical solutions of the present application are described by applying specific examples. The above example is only used to help understand the method of the present application and its core idea. The above is only the preferred embodiment of the present application. It should be noted that due to the limitation of language expression, there are infinite specific structures objectively. For ordinary skilled persons in the art, without departing from the principles of the present application, some improvements, refinements or changes can be made, and the above technical features can be combined in a proper way; these improvements, refinements, changes or combinations, or without improvement, the concept and technical solutions of the present application are directly applied to other occasions, which should be regarded as the protection scope of the present application.

Claims

1. A circuit netlist generation method supporting multi-stage reasoning of deep learning models, characterized in that: The following steps are involved: Step 1: Obtain an image of the circuit diagram using an optical scanning device or a digital camera; Step 2: Preprocess the image, including denoising, grayscale, binarization, edge detection and morphological operations; Step 3: Use the deep learning model YOLOv5 to identify components in the preprocessed image and determine the bounding box coordinates and category information of the components; Step 4: Based on the bounding box coordinates and category information of the component, the component port is finely identified, including determining the position and orientation of the port; Step 5: Use optical character recognition technology to identify the text in the circuit diagram to eliminate the interference of text on wire identification; Step 6: Perform wire recognition on the image, including Hough line detection and wire jump processing, to determine the starting and ending coordinates of the wire; Step 7: Match the identification results of components, ports, and wires to construct the topology of the circuit diagram; Step 8: Generate a circuit netlist based on the topological structure, including component types, port connection information, and wire connection information; Step 9: Troubleshoot the generated netlist, including troubleshooting incorrect connections and checking the integrity of the netlist numbering; Step 10: Export the corrected netlist in JSON format to ensure data scalability and facilitate subsequent processing.

2. A circuit netlist generation method supporting multi-stage reasoning of a deep learning model according to claim 1, characterized in that: In step three, the training process of the deep learning model YOLOv5 includes: collecting component image data in the circuit diagram, marking the bounding box coordinates and category information of the components, dividing the marked data set into a training set and a validation set, using the training set to train the YOLOv5 model, and testing it on the validation set to obtain the model's precision and recall rate indicators.

3. The circuit netlist generation method supporting multi-stage reasoning of a deep learning model according to claim 1, characterized in that: In step 4, the method for fine port identification includes: For each identified component, determine the possible position and direction of the port based on its category information; Extract local features from the image within the bounding box of the component and use deep learning models or traditional image processing algorithms to determine the specific location and orientation of the port; The center coordinates of the port are calculated and associated with the bounding box coordinates of the component to form a corresponding relationship between the port and the component.

4. A circuit netlist generation method supporting multi-stage reasoning of a deep learning model according to claim 1, characterized in that: In step five, the optical character recognition technology uses an OCR tool to recognize the text in the circuit diagram, including character recognition and position positioning of the text, and removes the recognized text information from the image to avoid interference with wire recognition.

5. The circuit netlist generation method supporting multi-stage reasoning of a deep learning model according to claim 1, characterized in that: In step six, the Hough line detection method includes: Perform edge detection on the image with text and component frames removed, and extract edge pixels in the image; Convert edge pixels to Hough space and count the votes for different line parameters using the accumulator array; Determine the straight line in the image based on the number of votes and obtain the coordinates of the starting and ending points of the straight line; The Hough line detection method is divided into two stages: Stage 1: initial line extraction; Perform edge detection on the image; Use probabilistic Hough transform to detect all possible straight line segments; Get the endpoint coordinates of each line; Phase 2: Greedy coupling as wire; Set a distance threshold and use a greedy algorithm to merge line segments that are close to each other and have the same direction into one line.

6. A circuit netlist generation method supporting multi-stage reasoning of a deep learning model according to claim 1, characterized in that: In step six, the jumper processing method includes: Design specific convolution kernels to detect different types of node connections in circuit diagrams, including current nodes, cross nodes, and cross-line nodes; Alternatively, a trained deep learning model can be used to automatically learn features in the circuit diagram and distinguish node types; Determine the node connection method based on the detection results and process the wires accordingly.

7. The circuit netlist generation method supporting multi-stage reasoning of a deep learning model according to claim 1, characterized in that: In step seven, the matching method includes: Determine the connection relationship between the port and the component based on the bounding box coordinates of the component and the position information of the port; Determine the connection relationship between the wire and the port based on the starting and ending coordinates of the wire; Construct the topological structure of the circuit diagram, including nodes, edges and connection relationships.

8. The circuit netlist generation method supporting multi-stage reasoning of a deep learning model according to claim 1, characterized in that: In step eight, the method for generating a circuit netlist includes: Integrate the component type, port connection information and wire connection information to form a netlist data structure; Assign unique identifiers to each component and wire to ensure the uniqueness and accuracy of the netlist; Verify and optimize the netlist data, including checking the legitimacy of connection relationships and eliminating redundant information.

9. The circuit netlist generation method supporting multi-stage reasoning of a deep learning model according to claim 1, characterized in that: In step nine, the error troubleshooting method includes: Verify the validity of the connection object model to ensure that each connection object is correctly defined in the netlist; Check the integrity of the netlist number to ensure that each component is connected to at least one valid wire; Eliminate isolated lines and dangling components, and correct incorrect connections in the circuit diagram.

10. The circuit netlist generation method supporting multi-stage reasoning of a deep learning model according to claim 1, characterized in that: In step 10, the output content in JSON format includes: Component list, each component contains type, identifier and port connection information; A list of wires, each containing the start and end coordinates and the connected port information; Special port list, including VDD and GND power and ground connection port information; The correspondence between the netlist numbers and the actual numbers ensures that they are consistent with the numbers in the circuit diagram.

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