Equipment power supply assembly and electronic equipment

Abstract

The invention discloses an equipment power supply assembly and electronic equipment, and relates to the technical field of power supply management, a control circuit outputs a first pulse width modulation signal to control a first rectification circuit so as to rectify an alternating current into a direct current of a first target voltage, and outputting a second pulse width modulation signal through the control circuit to control the second rectification circuit so as to rectify the direct current of the first target voltage into the direct current of the second target voltage. Thus, the first rectifying circuit is adopted as a preceding-stage rectifying module of the PSU, the first rectifying circuit is composed of a plurality of transistors, a traditional diode does not need to be used, and due to the fact that the on resistance of the transistors is low, heat generation can be reduced, conduction loss is further reduced, and the overall efficiency of the PSU is effectively improved; meanwhile, the second rectifying circuit is adopted as a post-stage rectifying module of the PSU, the number of windings needed by the transformer can be reduced, the size of the PSU can be further reduced, and the system integration degree is improved.

Description

Technical Field

[0001] The present application relates to the field of power management technology, and in particular to a device power supply component and an electronic device. Background Art

[0002] As the performance of servers like storage and artificial intelligence continues to improve, overall server power consumption has also increased significantly, placing increasing demands on the power of PSUs (Power Supply Units). In related technologies, the front-end rectification of general-purpose PSUs typically uses a diode bridge rectifier combined with a boost-type power factor correction (PFC) circuit. However, due to the large forward voltage drop of the diode, the power loss of the rectifier bridge increases as the PSU input power increases. This not only reduces the overall efficiency of high-power PSUs, but also places higher demands on the cooling system, resulting in a larger PSU. Summary of the Invention

[0003] The present application provides a device power supply assembly and an electronic device to at least solve the problem of low efficiency and large size of PSU in the related art.

[0004] The present application provides a device power supply component including: a first rectifier circuit for rectifying alternating current into direct current of a first target voltage; a second rectifier circuit for rectifying direct current of the first target voltage into direct current of a second target voltage, wherein the first target voltage is greater than the second target voltage, and the first rectifier circuit and the second rectifier circuit both include multiple transistors; a control circuit for outputting a first pulse width modulation signal and a second pulse width modulation signal, using the first pulse width modulation signal to control the multiple transistors of the first rectifier circuit, and using the second pulse width modulation signal to control the multiple transistors of the second rectifier circuit.

[0005] The present application also provides an electronic device, comprising: the aforementioned device power supply component.

[0006] The present application controls the first rectifier circuit by outputting a first pulse width modulation signal through the control circuit to rectify the alternating current into direct current of a first target voltage, and controls the second rectifier circuit by outputting a second pulse width modulation signal through the control circuit to rectify the direct current of the first target voltage into direct current of a second target voltage. Thus, the first rectifier circuit is used as the front-stage rectifier module of the PSU. This circuit is composed of multiple transistors and does not require the use of traditional diodes. Since the on-resistance of the transistors is low, heat generation can be reduced, thereby reducing conduction losses, thereby effectively improving the overall efficiency of the PSU. At the same time, the second rectifier circuit is used as the back-stage rectifier module of the PSU, which can reduce the number of windings required for the transformer, helping to further reduce the size of the PSU and improve system integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0008] Figure 1 is a block diagram of a power supply assembly of a device according to some embodiments of the present application; Figure 2 is a circuit diagram of a first rectifier circuit according to some embodiments of the present application; Figure 3 is a block diagram of a second rectifier circuit according to some embodiments of the present application; Figure 4 is a circuit diagram of a second rectifier circuit according to some embodiments of the present application; Figure 5 is a circuit diagram of a controller according to some embodiments of the present application; Figure 6 is a circuit diagram of a clock sub-circuit according to some embodiments of the present application; Figure 7 is a circuit diagram of an indicator light sub-circuit according to some embodiments of the present application; Figure 8 is a circuit diagram of a reset sub-circuit according to some embodiments of the present application; Figure 9 is a circuit diagram of a programming sub-circuit according to some embodiments of the present application; Figure 10 is a circuit diagram of a communication sub-circuit according to some embodiments of the present application; Figure 11 is a circuit diagram of a first sampling sub-circuit according to some embodiments of the present application; Figure 12is a circuit diagram of a second sampling sub-circuit according to some embodiments of the present application; Figure 13 is a circuit diagram of a third sampling sub-circuit according to some embodiments of the present application; Figure 14 is a circuit diagram of a fourth sampling sub-circuit according to some embodiments of the present application; Figure 15 is a circuit diagram of a fifth sampling sub-circuit according to some embodiments of the present application; Figure 16 is a block diagram of a driving circuit according to some embodiments of the present application; Figure 17 is a circuit diagram of a first driving circuit according to some embodiments of the present application; Figure 18 is a block diagram of a second driving circuit according to some embodiments of the present application; Figure 19 is a circuit diagram of a second driving circuit A according to some embodiments of the present application; Figure 20 is a circuit diagram of a second driving circuit B according to some embodiments of the present application; Figure 21 is a circuit diagram of a second driving circuit C according to some embodiments of the present application; Figure 22 is a circuit diagram of a second driving circuit D according to some embodiments of the present application; Figure 23 is an AND gate logic circuit diagram according to some embodiments of the present application; Figure 24 is a circuit diagram of a first overcurrent protection circuit according to some embodiments of the present application; Figure 25 is a circuit diagram of a second overcurrent protection circuit according to some embodiments of the present application; Figure 26 is a circuit diagram of a third overcurrent protection circuit according to some embodiments of the present application; Figure 27 is a circuit diagram of a fourth overcurrent protection circuit according to some embodiments of the present application; Figure 28 is a circuit diagram of a fifth overcurrent protection circuit according to some embodiments of the present application; Figure 29 is a circuit diagram of a reference voltage circuit according to some embodiments of the present application; Figure 30 is a circuit diagram of an auxiliary power supply circuit according to some embodiments of the present application; Figure 31 is a block diagram of an electronic device according to some embodiments of the present application. DETAILED DESCRIPTION

[0009] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0010] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0011] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0012] The device power supply assembly and electronic device according to the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0013] Reference Figure 1 The device power supply assembly 10 of the embodiment of the present application includes: a first rectifier circuit 2 for rectifying alternating current into direct current of a first target voltage; a second rectifier circuit 3 for rectifying direct current of the first target voltage into direct current of a second target voltage, wherein the first target voltage is greater than the second target voltage, and the first rectifier circuit 2 and the second rectifier circuit 3 each include multiple transistors; and a control circuit 1 for outputting a first pulse width modulation signal and a second pulse width modulation signal, controlling the multiple transistors of the first rectifier circuit 2 using the first pulse width modulation signal and controlling the multiple transistors of the second rectifier circuit 3 using the second pulse width modulation signal. The multiple transistors of the first rectifier circuit 2 and the second rectifier circuit 3 may be MOS transistors (Metal-Oxide-Semiconductor Field-Effect Transistors), which are not specifically limited here.

[0014] Specifically, the control circuit 1 transmits a first pulse width modulation signal, such as a PWM modulation wave (Pulse Width Modulation, pulse width modulation), to the first rectifier circuit 2. The first rectifier circuit 2 adjusts the operating mode of multiple transistors in the first rectifier circuit 2 based on the first pulse width modulation signal, thereby controlling the flow of energy to achieve power conversion, so as to rectify AC power (such as 220V AC power) into DC power of a first target voltage, such as 400V DC power.

[0015] After the first rectifier circuit 2 generates direct current of the first target voltage, the control circuit 1 transmits a second pulse width modulation signal, such as a PWM modulation wave, to the second rectifier circuit 3. The second rectifier circuit 3 adjusts the operating mode of multiple transistors in the second rectifier circuit 3 based on the second pulse width modulation signal, thereby controlling the flow of energy to achieve power conversion and rectifying the direct current of the first target voltage into direct current of the second target voltage, such as 12V direct current.

[0016] The present application controls the first rectifier circuit by outputting a first pulse width modulation signal through the control circuit to rectify the alternating current into direct current of a first target voltage, and controls the second rectifier circuit by outputting a second pulse width modulation signal through the control circuit to rectify the direct current of the first target voltage into direct current of a second target voltage. Thus, the first rectifier circuit is used as the front-stage rectifier module of the PSU. This circuit is composed of multiple transistors and does not require the use of traditional diodes. Since the on-resistance of the transistors is low, heat generation can be reduced, thereby reducing conduction losses, thereby effectively improving the overall efficiency of the PSU. At the same time, the second rectifier circuit is used as the back-stage rectifier module of the PSU, which can reduce the number of windings required for the transformer, helping to further reduce the size of the PSU and improve system integration.

[0017] In some embodiments, reference Figure 2 The first rectifier circuit 2 includes a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4 and an inductor U4, wherein the gates of the first transistor Q1, the second transistor Q2, the third transistor Q3 and the fourth transistor Q4 are respectively input with a first pulse width modulation signal, the drain of the first transistor Q1 and the drain of the second transistor Q2 are connected to a DC bus of a first target voltage, the source of the third transistor Q3 and the fourth transistor Q4 are respectively grounded, one end of the primary winding U41 of the inductor U4 is connected to a phase line of an alternating current, the other end of the primary winding U41 of the inductor U4 is connected to the source of the first transistor Q1 and the drain of the third transistor Q3, and the neutral line of the alternating current is connected to the source of the second transistor Q2 and the drain of the fourth transistor Q4.

[0018] In some embodiments, the secondary winding U42 of the inductor U4 is connected to a first current sampling resistor R14 , and the DC bus of the first target voltage is connected to a voltage divider subcircuit 21 , which is used to divide the first target voltage.

[0019] For example, refer to Figure 2 and Figure 5 The control circuit 1 includes four output pins of the first pulse width modulation signal, such as pin 42#, pin 43#, pin 26# and pin 27#, wherein pin 26# outputs the first pulse width modulation signal MCU_PWM_PWM1, pin 42# outputs the first pulse width modulation signal MCU_PWM_PWM2, pin 43# outputs the first pulse width modulation signal MCU_PWM_PWM3, and pin 27# outputs the first pulse width modulation signal MCU_PWM_PWM4.

[0020] The first pulse width modulation signal MCU_PWM_PWM1 outputted from pin 26# of the control circuit 1 will be transmitted to the gate of the first transistor Q1 for controlling the operating mode of the first transistor Q1. The first pulse width modulation signal MCU_PWM_PWM2 outputted from pin 42# of the control circuit 1 will be transmitted to the gate of the third transistor Q3 for controlling the operating mode of the third transistor Q3. The first pulse width modulation signal MCU_PWM_PWM3 outputted from pin 43# of the control circuit 1 will be transmitted to the gate of the second transistor Q2 for controlling the operating mode of the second transistor Q2. The first pulse width modulation signal MCU_PWM_PWM4 outputted from pin 27# of the control circuit 1 will be transmitted to the gate of the fourth transistor Q4 for controlling the operating mode of the fourth transistor Q4. Thus, the flow of energy can be controlled to achieve power conversion. In conjunction with the inductor U4, the input alternating current, such as AC_L and AC_N, can be converted into direct current of a first target voltage and transmitted to the DC bus.

[0021] When current flows through inductor U4, the secondary winding generates a mutual induction current. This current then flows through first current sampling resistor R14, generating an AC voltage across first current sampling resistor R14, such as IL_N and IL_P. The AC input current can be determined based on the voltage across first current sampling resistor R14. First current sampling resistor R14 can be 50Ω, without specific limitation.

[0022] The voltage dividing sub-circuit 21 includes a resistor R171 and a resistor R157 , and is configured to divide the first target voltage, for example, into DC_400V_P (high voltage) and DC_400V_N (low voltage).

[0023] The AC input voltage (e.g., AC_L and AC_N), the voltage across the first current sampling resistor R14 (e.g., IL_N and IL_P), and the divided DC voltage of the first target voltage (e.g., DC_400V_P and DC_400V_N) are input into the corresponding sampling circuit to output the AC input voltage sampling signal ADC_AC_VIN, the AC input current sampling signal ADC_AC_IIN, and the DC output voltage sampling signal ADC_DC_400V_VOUT.

[0024] Furthermore, the AC input voltage sampling signal ADC_AC_VIN, the AC input current sampling signal ADC_AC_IIN, and the DC output voltage sampling signal ADC_DC_400V_VOUT are input to the control circuit 1. For example, the AC input voltage sampling signal ADC_AC_VIN is input to AD sampling pin 11#, the AC input current sampling signal ADC_AC_IIN is input to AD sampling pin 14# or pin 20#, and the DC output voltage sampling signal ADC_DC_400V_VOUT is input to AD sampling pin 10#. Based on the AC input voltage sampling signal ADC_AC_VIN, the AC input current sampling signal ADC_AC_IIN, and the DC output voltage sampling signal ADC_DC_400V_VOUT, the control circuit 1 regenerates a first pulse-width modulation signal and transmits it to the first rectifier circuit 2. The control circuit 1 then re-controls the transistors of the first rectifier circuit 2 to stabilize the voltage on the DC bus at approximately the first target voltage (e.g., 400V).

[0025] In this way, the first rectifier circuit is used as the pre-stage rectifier module of the PSU. The circuit is composed of multiple transistors and does not require the use of traditional diodes. Since the on-resistance of the transistors is low, it can reduce heat generation and thus reduce conduction losses, thereby effectively improving the overall efficiency of the PSU.

[0026] In some embodiments, reference Figure 3 The second rectifier circuit 3 includes a first rectifier module 31, a second rectifier module 32 and a first transformer 33, wherein the first rectifier module 31 is connected to the primary winding 331 of the first transformer, the second rectifier module 32 is connected to the secondary winding 332 of the first transformer, and the transistors of the first rectifier module 31 and the second rectifier module 32 are respectively input with a second pulse width modulation signal.

[0027] Specifically, after the first rectifier circuit 2 generates direct current of the first target voltage, the control circuit 1 transmits the second pulse width modulation signal to the second rectifier circuit 3, for example, transmits the second pulse width modulation signal A to the first rectifier module 31, and transmits the second pulse width modulation signal B to the second rectifier module 32. The first rectifier module 31 and the second rectifier module 32 adjust the operating modes of multiple transistors in the first rectifier module 31 and the second rectifier module 32 based on the second pulse width modulation signal A and the second pulse width modulation signal B, thereby controlling the flow of energy to achieve power conversion and rectifying the direct current of the first target voltage into direct current of the second target voltage, for example, 12V direct current.

[0028] In some embodiments, reference Figure 4 The first rectifier module 31 includes a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7 and an eighth transistor Q8, wherein the drains of the fifth transistor Q5 and the sixth transistor Q6 are respectively connected to the DC bus of the first target voltage, the sources of the seventh transistor Q7 and the eighth transistor Q8 are respectively grounded, the source of the fifth transistor Q5 and the drain of the seventh transistor Q7 are connected to the first end 1 of the primary winding 331 of the first transformer, and the source of the sixth transistor Q6 and the drain of the eighth transistor Q8 are connected to the second end 2 of the primary winding 331 of the first transformer.

[0029] In some embodiments, continue to refer to Figure 4 The second rectifier module 32 includes a ninth transistor Q9, a tenth transistor Q10, an eleventh transistor Q11, and a twelfth transistor Q12, wherein the drains of the ninth transistor Q9 and the tenth transistor Q10 respectively output direct current of the second target voltage, the sources of the eleventh transistor Q11 and the twelfth transistor Q12 are respectively grounded, the source of the tenth transistor Q10 and the drain of the twelfth transistor Q12 are connected to the third end 3 of the secondary winding 332 of the first transformer, and the source of the ninth transistor Q9 and the drain of the eleventh transistor Q11 are connected to the fourth end 4 of the secondary winding 332 of the first transformer.

[0030] For example, refer to Figure 4 and Figure 5 The control circuit 1 includes four output pins for the second pulse width modulation signal, such as pin 41#, pin 23#, pin 39# and pin 38#, wherein pin 41# outputs the second pulse width modulation signal MCU_SYN_PWM1, pin 23# outputs the second pulse width modulation signal MCU_SYN_PWM2, pin 39# outputs the second pulse width modulation signal MCU_SYN_PWM3, and pin 38# outputs the second pulse width modulation signal MCU_SYN_PWM4.

[0031] The second pulse width modulation signal MCU_SYN_PWM1 outputted by pin 41# of the control circuit 1 is transmitted to the gate of the fifth transistor Q5 for controlling the operating mode of the fifth transistor Q5. The second pulse width modulation signal MCU_SYN_PWM2 outputted by pin 23# of the control circuit 1 is transmitted to the gate of the seventh transistor Q7 for controlling the operating mode of the seventh transistor Q7. The second pulse width modulation signal MCU_SYN_PWM3 outputted by pin 39# of the control circuit 1 is transmitted to the gate of the sixth transistor Q6 for controlling the operating mode of the sixth transistor Q6. The second pulse width modulation signal MCU_SYN_PWM4 outputted by pin 38# of the control circuit 1 is transmitted to the gate of the eighth transistor Q8 for controlling the operating mode of the eighth transistor Q8. Thus, the flow of energy can be controlled to achieve power conversion, thereby converting the first target voltage direct current into alternating current. The alternating current passes through the primary winding 331 of the first transformer, thereby generating alternating current through mutual induction in the secondary winding 332 of the first transformer, thereby transferring energy to the secondary.

[0032] Furthermore, the second pulse width modulation signal MCU_SYN_PWM1 outputted by pin 41# of the control circuit 1 is also transmitted to the gate of the ninth transistor Q9 for controlling the operating mode of the ninth transistor Q9. The second pulse width modulation signal MCU_SYN_PWM2 outputted by pin 23# of the control circuit 1 is also transmitted to the gate of the eleventh transistor Q11 for controlling the operating mode of the eleventh transistor Q11. The second pulse width modulation signal MCU_SYN_PWM3 outputted by pin 39# of the control circuit 1 is also transmitted to the gate of the tenth transistor Q10 for controlling the operating mode of the tenth transistor Q10. The second pulse width modulation signal MCU_SYN_PWM4 outputted by pin 38# of the control circuit 1 is also transmitted to the gate of the twelfth transistor Q12 for controlling the operating mode of the twelfth transistor Q12. Thus, the flow of energy can be controlled to achieve power conversion, and the alternating current generated by the mutual inductance of the secondary winding 332 of the first transformer can be converted into direct current of the second target voltage.

[0033] In some embodiments, the drain of each of the ninth transistor Q9 and the tenth transistor Q10 is connected to a second current sampling resistor R169 .

[0034] Specifically, refer to Figure 4 The 12V DC current generates a voltage drop across the second current sampling resistor R169, namely, the DC voltages DC_12V and DC_12V_R across the second current sampling resistor R169. The DC current can be determined based on the voltages across the second current sampling resistor R169. The second current sampling resistor R169 can be 0.1 mΩ, which is not specifically limited here.

[0035] Furthermore, the DC voltages DC_12V and DC_12V_R across the second current sampling resistor R169 are input to corresponding slave sampling circuits to output a DC output voltage sampling signal ADC_DC_12V_VOUT and a DC output current sampling signal ADC_DC_12V_IOUT. The DC output voltage sampling signal ADC_DC_12V_VOUT and the DC output current sampling signal ADC_DC_12V_IOUT are input to control circuit 1. For example, the DC output voltage sampling signal ADC_DC_12V_VOUT is input to AD sampling pin 8#, and the DC output current sampling signal ADC_DC_12V_IOUT is input to AD sampling pin 9#. The control circuit 1 regenerates a second pulse width modulation signal based on the DC output voltage sampling signal ADC_DC_12V_VOUT and the DC output current sampling signal ADC_DC_12V_IOUT, and transmits it to the second rectifier circuit 3, thereby re-controlling the transistors of the second rectifier circuit 3 so that the output voltage of the second rectifier circuit 3 is stabilized at around the second target voltage (e.g., 12V).

[0036] In this way, using the second rectifier circuit as the post-rectifier module of the PSU can reduce the number of windings required for the transformer, help further reduce the size of the PSU, and improve system integration.

[0037] In some embodiments, a capacitor and a resistor are connected in parallel across the drain and source of each transistor in the first rectifier circuit 2 and the second rectifier circuit 3 .

[0038] For example, refer to Figure 2 The first rectifier circuit 2 includes a first transistor Q1, a second transistor Q2, a third transistor Q3, and a fourth transistor Q4. A capacitor C19 and a resistor R17 are connected in parallel between the drain and source of the first transistor Q1. A capacitor C20 and a resistor R20 are connected in parallel between the drain and source of the second transistor Q2. A capacitor C27 and a resistor R27 are connected in parallel between the drain and source of the third transistor Q3. A capacitor C28 and a resistor R28 are connected in parallel between the drain and source of the fourth transistor Q4. The capacitors and resistors connected in parallel between the drain and source of each transistor can absorb the peak voltage when the transistors are switched. Capacitors C19, C27, C20, and C28 can be 1 nF, and resistors R17, R27, R20, and R28 can be 47 Ω. These are not specifically limited here.

[0039] For example, refer to Figure 4The second rectifier circuit 3 includes a first rectifier module 31 and a second rectifier module 32. The first rectifier module 31 includes a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, and an eighth transistor Q8. A capacitor C62 and a resistor R82 are connected in parallel between the drain and source of the fifth transistor Q5. A capacitor C63 and a resistor R89 ​​are connected in parallel between the drain and source of the sixth transistor Q6. A capacitor C71 and a resistor R104 are connected in parallel between the drain and source of the seventh transistor Q7. A capacitor C70 and a resistor R105 are connected in parallel between the drain and source of the eighth transistor Q8. The capacitors and resistors connected in parallel between the drain and source of each transistor can absorb spike voltages during transistor switching. Capacitors C62, C70, C63, and C71 can be 1 nF, and resistors R82, R89, R104, and R105 can be 47 Ω. These are not specifically limited here.

[0040] Continue to refer to Figure 4 The second rectifier module 32 includes a ninth transistor Q9, a tenth transistor Q10, an eleventh transistor Q11, and a twelfth transistor Q12. A capacitor C64 and a resistor R87 are connected in parallel between the drain and source of the ninth transistor Q9. A capacitor C65 and a resistor R93 are connected in parallel between the drain and source of the tenth transistor Q10. A capacitor C73 and a resistor R108 are connected in parallel between the drain and source of the eleventh transistor Q11. A capacitor C72 and a resistor R109 are connected in parallel between the drain and source of the twelfth transistor Q12. The capacitors and resistors connected in parallel between the drain and source of each transistor can absorb spike voltages during transistor switching. Capacitors C64, C65, C73, and C72 can be 1 nF, and resistors R87, R93, R108, and R109 can be 47 Ω, without specific limitations.

[0041] In some embodiments, a clamping diode is connected in parallel to the gate of each transistor in the first rectifier circuit 2 and the second rectifier circuit 3 .

[0042] For example, refer to Figure 2 The first rectifier circuit 2 includes a first transistor Q1, a second transistor Q2, a third transistor Q3 and a fourth transistor Q4, wherein the gate of the first transistor Q1 is connected in parallel with a clamping diode D4, the second transistor Q2 is connected in parallel with a clamping diode D5, the gate of the third transistor Q3 is connected in parallel with a clamping diode D8, and the gate of the fourth transistor Q4 is connected in parallel with a clamping diode D9. The clamping diodes connected in parallel to the gates of each transistor prevent the driving voltage from being too high and breaking through the transistor.

[0043] Reference Figure 4The second rectifier circuit 3 includes a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, an eighth transistor Q8, a ninth transistor Q9, a tenth transistor Q10, an eleventh transistor Q11 and a twelfth transistor Q12, wherein the fifth transistor Q5 is connected in parallel with a clamping diode D23, the sixth transistor Q6 is connected in parallel with a clamping diode D24, the seventh transistor Q7 is connected in parallel with a clamping diode D31, the eighth transistor Q8 is connected in parallel with a clamping diode D32, the ninth transistor Q9 is connected in parallel with a clamping diode D25, the tenth transistor Q10 is connected in parallel with a clamping diode D26, the eleventh transistor Q11 is connected in parallel with a clamping diode D33, and the twelfth transistor Q12 is connected in parallel with a clamping diode D34. The clamping diodes connected in parallel to the gates of each transistor prevent the transistor from being broken down due to excessive driving voltage.

[0044] In some embodiments, the control circuit 1 includes a controller 11, wherein the controller 11 is provided with multiple pins, including one or more combinations of output pins for pulse width modulation signals, data sampling pins, fault input pins, and output pins for indicator light control signals. The controller 11 may be an STM32 microcontroller, without specific limitation.

[0045] Exemplarily, the control circuit 1 includes a controller 11, and the controller 11 is as follows: Figure 5 As shown, the controller 11 includes output pins for pulse width modulation signals, such as an output pin for a first pulse width modulation signal and an output pin for a second pulse width modulation signal, wherein the output pins for the first pulse width modulation signal include pin 42#, pin 43#, pin 26#, and pin 27#, and the output pins for the second pulse width modulation signal include pin 41#, pin 23#, pin 39#, and pin 38#.

[0046] The controller 11 also includes data sampling pins, such as AD sampling pin 11#, AD sampling pin 14#, AD sampling pin 20#, sampling pin 10#, AD sampling pin 9# and AD sampling pin 8#, which are used to collect the voltage sampling signal ADC_AC_VIN, AC input current sampling signal ADC_AC_IIN, DC output voltage sampling signal ADC_DC_400V_VOUT, DC output current sampling signal ADC_DC_12V_IOUT and DC output voltage sampling signal ADC_DC_12V_VOUT output by the sampling circuit 4.

[0047] The controller 11 further includes a fault input pin, such as pin 52#, which immediately stops power output when a circuit fault signal is detected by the pin.

[0048] The controller 11 also includes an output pin for an indicator light control signal. Pin 57# is a control pin for LED2 - a sub-circuit 13 for indicating the working state of the controller 11 , and pin 33# is a control pin for LED3 - a sub-circuit 13 for indicating the working alarm of the controller 11 .

[0049] In some embodiments, the control circuit 1 further includes one or more combinations of a clock subcircuit 12 , an indicator light subcircuit 13 , a reset subcircuit 14 , a burning subcircuit 15 and a communication subcircuit 16 .

[0050] Exemplarily, the control circuit 1 further includes a clock subcircuit 12, referring to Figure 5 and Figure 6 , the clock sub-circuit 12 is connected to pin 5# and pin 6# of the controller 11.

[0051] The control circuit 1 further includes an indicator light sub-circuit 13, for example, an LED2-controller working status indicator light sub-circuit 131 and an LED3-working alarm indicator light sub-circuit 132. Figure 5 and Figure 7 LED2 - Controller Working Status Indicator Subcircuit 131 is connected to pin 57# of controller 11. When the device power supply is functioning normally, pin 57# controls LED2 - Main Control Chip Working Status Indicator to remain lit. LED3 - Working Alarm Indicator Subcircuit 132 is connected to pin 33# of controller 11. When the circuit is functioning normally, pin 33# controls LED3 - Working Alarm Indicator to flash at a low frequency. When a circuit fault occurs, pin 33# controls LED3 - Working Alarm Indicator to flash at a high frequency.

[0052] The control circuit 1 also includes a reset subcircuit 14, referring to Figure 5 and Figure 8 The reset sub-circuit 14 is connected to pin 7# of the controller 11. After the reset button SW1 is pressed, the reset sub-circuit 14 will output a low level to the controller 11 to reset the control.

[0053] The control circuit 1 also includes a programming sub-circuit 15, referring to Figure 5 and Figure 9 The connector J1 of the programming sub-circuit 15 can be connected to an unoccupied pin of the controller 11, such as pin 15#, for programming or debugging the controller 11.

[0054] The control circuit 1 further includes a communication sub-circuit 16, which includes an asynchronous serial communication sub-circuit 161 and a synchronous serial communication sub-circuit 162. Figure 5 and Figure 10The asynchronous serial communication sub-circuit 161 is connected to pin 16# and pin 17# of the controller 11. When the controller 11 needs to send data, the data is output from pin 16# and transmitted to pin U2_TX of the asynchronous serial communication sub-circuit 161; when the asynchronous serial communication sub-circuit 161 needs to send data, the data is output from pin U2_RX of the asynchronous serial communication sub-circuit 161 and transmitted to pin 17# of the controller 11.

[0055] Continue to refer to Figure 5 and Figure 10 The synchronous serial communication sub-circuit 162 is connected to pins 58# and 59# of the controller 11. When the pin SCL of the synchronous serial communication sub-circuit 162 is at a high level, the pin SDA jumps from a high level to a low level, indicating that the communication starts; when the pin SCL is at a high level, the pin SDA jumps from a low level to a high level, indicating that the communication ends.

[0056] In some embodiments, the device power supply assembly 10 further includes: a sampling circuit for collecting one or more of the first target voltage, the AC input current, the AC input voltage, the second target voltage, and the DC current.

[0057] Specifically, the AC input voltage (e.g., AC_L and AC_N), the voltage across the first current sampling resistor R14 (e.g., IL_N and IL_P), and the divided DC voltage of the first target voltage (e.g., DC_400V_P and DC_400V_N) can be input into the corresponding sampling circuit 4 to output the AC input voltage sampling signal ADC_AC_VIN, the AC input current sampling signal ADC_AC_IIN, and the DC output voltage sampling signal ADC_DC_400V_VOUT.

[0058] The second target DC voltages DC_12V and DC_12V_R at both ends of the second current sampling resistor R169 can also be input into corresponding sampling circuits to output a DC output voltage sampling signal ADC_DC_12V_VOUT and a DC output current sampling signal ADC_DC_12V_IOUT.

[0059] In some embodiments, the sampling circuit includes at least one sampling sub-circuit, wherein the sampling sub-circuit is composed of an operational amplifier, a diode, a resistor, and a capacitor.

[0060] Specifically, the sampling circuit may include a first sampling sub-circuit 41, a second sampling sub-circuit 42, a third sampling sub-circuit 43, a fourth sampling sub-circuit 44, and a fifth sampling sub-circuit 45. Each sampling sub-circuit is respectively used to sample the AC input voltage (e.g., AC_L and AC_N), the voltage across the first current sampling resistor R14 (e.g., IL_N and IL_P), the divided voltage of the DC voltage of the first target voltage (e.g., DC_400V_P and DC_400V_N), and the second target DC voltage across the second current sampling resistor R169 (e.g., DC_12V and DC_12V_R), to output corresponding sampling signals, and input the corresponding sampling signals into the control circuit 1 to adjust the first pulse width modulation signal and the second pulse width modulation signal.

[0061] Exemplarily, the first sampling sub-circuit 41 is as follows: Figure 11 As shown, the first sampling sub-circuit 41 includes an operational amplifier U19.1, a diode D18, a resistor R63, a resistor R64, a resistor R65, a resistor R66, a resistor R61, a resistor R68, a transformer U9 and a capacitor C54. An AC input voltage (such as AC_L and AC_N) can be input into the first sampling sub-circuit 41 to output an AC input voltage sampling signal ADC_AC_VIN.

[0062] The second sampling sub-circuit 42 is as follows Figure 12 As shown, the second sampling sub-circuit 42 includes an operational amplifier U24.1, a diode D16, a resistor R47, a resistor R49, a resistor R51, a resistor R53, and a capacitor C46. The voltage across the first current sampling resistor R14 (e.g., IL_N and IL_P) can be input into the second sampling sub-circuit 42 to output an AC input current sampling signal ADC_AC_IIN.

[0063] The third sampling sub-circuit 43 is as follows Figure 13 As shown, the third sampling sub-circuit 43 includes an operational amplifier U23.1, a diode D17, resistors R56, R57, R50, R59, and a capacitor C50. The divided voltage of the DC voltage of the first target voltage (e.g., DC_400V_P and DC_400V_N) can be input into the third sampling sub-circuit 43 to output a DC output voltage sampling signal ADC_DC_400V_VOUT.

[0064] The fourth sampling sub-circuit 44 is as follows Figure 14As shown, the fourth sampling sub-circuit 44 includes an operational amplifier U20.1, a diode D36, a resistor R114, a resistor R119, a resistor R116, a capacitor C81, and a capacitor C82. A DC voltage of a second target voltage (e.g., DC_12V) can be input into the fourth sampling sub-circuit 44 to output a DC output voltage sampling signal ADC_DC_12V_VOUT.

[0065] The fifth sampling sub-circuit 45 is as follows Figure 15 As shown, the fifth sampling sub-circuit 45 includes an operational amplifier U21.1, a diode D39, resistors R128, R129, R124, R170, and a capacitor C93. The second target DC voltage (e.g., DC_12V and DC_12V_R) across the second current sampling resistor R169 can be input into the fifth sampling sub-circuit 45 to output a DC output current sampling signal ADC_DC_12V_IOUT.

[0066] In some embodiments, the device power supply component 10 further includes: a driving circuit 5 for driving multiple transistors of the first rectifier circuit 2 according to the first pulse width modulation signal, and driving multiple transistors of the second rectifier circuit 3 according to the second pulse width modulation signal.

[0067] Specifically, refer to Figure 16 The driving circuit 5 includes a first driving circuit 51 and a second driving circuit 52. The first driving circuit 51 drives the plurality of transistors of the first rectifier circuit 2 according to the first pulse width modulation signal. Specifically, the first driving circuit 51 includes a first driving circuit A and a first driving circuit B. The first driving circuit A is as follows: Figure 17 As shown, the first driving circuit A is used to drive the first transistor Q1 and the third transistor Q3 according to the first pulse width modulation signal MCU_PWM_PWM1 and the first pulse width modulation signal MCU_PWM_PWM2 respectively; the first driving circuit B is as shown Figure 17 As shown, the first driving circuit B is used to drive the second transistor Q2 and the fourth transistor Q4 according to the first pulse width modulation signal MCU_PWM_PWM3 and the first pulse width modulation signal MCU_PWM_PWM4 respectively.

[0068] The second driving circuit 52 is used to drive the plurality of transistors of the second rectifier circuit 3 according to the second pulse width modulation signal. Figure 18 The second driving circuit 52 includes a second driving circuit A, a second driving circuit B, a second driving circuit C and a second driving circuit D. The second driving circuit A is as follows Figure 19As shown, the second driving circuit A is used to drive the fifth transistor Q5 and the seventh transistor Q7 according to the second pulse width modulation signal MCU_SYN_PWM1 and the second pulse width modulation signal MCU_SYN_PWM2 respectively; the second driving circuit B is as shown Figure 20 As shown, the second driving circuit B is used to drive the sixth transistor Q6 and the eighth transistor Q8 according to the second pulse width modulation signal MCU_SYN_PWM3 and the second pulse width modulation signal MCU_SYN_PWM4 respectively; the second driving circuit C is as shown Figure 21 As shown, the second driving circuit C is used to drive the ninth transistor Q9 and the eleventh transistor Q11 according to the second pulse width modulation signal MCU_SYN_PWM1 and the second pulse width modulation signal MCU_SYN_PWM2 respectively; the second driving circuit D is as shown Figure 22 As shown, the second driving circuit D is used to drive the tenth transistor Q10 and the twelfth transistor Q12 according to the second pulse width modulation signal MCU_SYN_PWM3 and the second pulse width modulation signal MCU_SYN_PWM4 respectively.

[0069] In some embodiments, in order to immediately shut down the drive signal when overcurrent and overvoltage occur to protect the multiple transistors of the first rectifier circuit 2 from further damage, it is necessary to pre-process the first pulse width modulation signal MCU_PWM_PWM1, the first pulse width modulation signal MCU_PWM_PWM2, the first pulse width modulation signal MCU_PWM_PWM3 and the first pulse width modulation signal MCU_PWM_PWM4.

[0070] For example, refer to Figure 23 , the first pulse width modulation signal MCU_PWM_PWM1, the first pulse width modulation signal MCU_PWM_PWM2, the first pulse width modulation signal MCU_PWM_PWM3 and the first pulse width modulation signal MCU_PWM_PWM4 are input into the AND gate logic chip U7, and at the same time, the 12V DC overvoltage protection signal DC_12V_OVP, the 12V DC overcurrent protection signal DC_12V_OCP, the 400V DC overvoltage protection signal DC_400V_OVP, the AC overcurrent protection signal L_IOUT_OCP and the AC overvoltage protection signal AC_OVP are also input into the AND gate logic chip U7 to output the first pulse width modulation signal that has undergone overcurrent protection and overvoltage protection, for example, the first pulse width modulation signal PWM_PWM1, the first pulse width modulation signal PWM_PWM2, the first pulse width modulation signal PWM_PWM3 and the first pulse width modulation signal PWM_PWM4.

[0071] Then the first pulse width modulation signal PWM_PWM1 and the first pulse width modulation signal PWM_PWM2 are input into the first driving circuit A to drive the first transistor Q1 and the third transistor Q3 respectively; the first pulse width modulation signal PWM_PWM3 and the first pulse width modulation signal PWM_PWM4 are input into the first driving circuit B to drive the second transistor Q2 and the fourth transistor Q4 respectively.

[0072] The DC output voltage sampling signal ADC_DC_400V_VOUT is input into the first overcurrent protection circuit to output a 400V DC overvoltage protection signal DC_400V_OVP. The first overcurrent protection circuit is as follows: Figure 24 As shown; the AC input current sampling signal ADC_AC_IIN is input into the second overcurrent protection circuit to output the AC overcurrent protection signal L_IOUT_OCP, the second overcurrent protection circuit is as shown Figure 25 As shown; the voltage sampling signal ADC_AC_VIN is input into the first overvoltage protection circuit to output the AC overvoltage protection signal AC_OVP, the first overvoltage protection circuit is as shown Figure 26 As shown; the DC output voltage sampling signal ADC_DC_12V_VOUT is input into the second overvoltage protection circuit to output a 12V DC overvoltage protection signal DC_12V_OVP, the second overvoltage protection circuit is as shown Figure 27 As shown; the DC output current sampling signal ADC_DC_12V_IOUT is input into the third overcurrent protection circuit to output a 12V DC overcurrent protection signal DC_12V_OCP. The third overcurrent protection circuit is as shown Figure 28 shown.

[0073] In some embodiments, the device power supply component 10 further includes: a reference voltage circuit 6 , which is composed of a plurality of operational amplifiers and is used to provide a reference voltage to the device power supply component 10 .

[0074] Specifically, refer to Figure 29 The reference voltage circuit 6 includes an operational amplifier U17 and an operational amplifier U18, which are used to provide a reference voltage to the device power supply component 10, for example, providing a 1.5V reference voltage to the first sampling sub-circuit 41, the second sampling sub-circuit 42, the third sampling sub-circuit 43 and the fifth sampling sub-circuit 45.

[0075] In some embodiments, the device power supply assembly 10 further includes: an auxiliary power supply circuit 7, referring to Figure 30, including one or more of a rectifier bridge BR1, a pulse width modulation controller U22, a thirteenth transistor Q13, a second transformer T1, a voltage regulator V1 and an optocoupler PC1, wherein the alternating current becomes direct current after passing through the rectifier bridge, and the pulse width modulation controller U22 outputs a third pulse width modulation signal to control the on and off of the thirteenth transistor to convert the direct current into an alternating voltage. The alternating voltage is coupled to multiple secondary windings by the primary winding of the second transformer and rectified into direct current by the subsequent diode. The optocoupler PC1 and the voltage regulator V1 form a feedback loop. When the voltage of P3V3 changes, the internal resistance of the voltage regulator V1 changes, so it can be given as a feedback signal to the pulse width modulation controller U22 for adjusting the duty cycle of the third pulse width modulation signal. The pulse width modulation controller U22 adjusts the duty cycle of the third pulse width modulation signal based on the voltage value fed back by the optocoupler to complete the closed loop, thereby stabilizing the output and obtaining working voltages such as 12V and 3.3V. In summary, the present application controls the first rectifier circuit by outputting a first pulse width modulation signal through the control circuit to rectify the alternating current into direct current of a first target voltage, and controls the second rectifier circuit by outputting a second pulse width modulation signal through the control circuit to rectify the direct current of the first target voltage into direct current of a second target voltage. In this way, the first rectifier circuit is used as the front-stage rectifier module of the PSU. The circuit is composed of multiple transistors and does not require the use of traditional diodes. Since the on-resistance of the transistors is low, the heat generation can be reduced, thereby reducing the conduction loss, thereby effectively improving the overall efficiency of the PSU. At the same time, the second rectifier circuit is used as the rear-stage rectifier module of the PSU, which can reduce the number of windings required for the transformer, helping to further reduce the size of the PSU and improve the system integration.

[0076] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0077] Reference Figure 31 , an embodiment of the present application further provides an electronic device 100 , comprising: the aforementioned device power supply component 10 .

[0078] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0079] The above is a detailed introduction to a device power supply component and an electronic device provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A device power supply assembly, characterized in that: include: a first rectifier circuit, configured to rectify the alternating current into direct current of a first target voltage; a second rectifier circuit, configured to convert and rectify the direct current of the first target voltage into direct current of a second target voltage, wherein the first target voltage is greater than the second target voltage, and the first rectifier circuit and the second rectifier circuit each include a plurality of transistors; The control circuit is used to output a first pulse width modulation signal and a second pulse width modulation signal, use the first pulse width modulation signal to control multiple transistors of the first rectifier circuit, and use the second pulse width modulation signal to control multiple transistors of the second rectifier circuit.

2. The device power supply assembly according to claim 1, characterized in that: The first rectifier circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and an inductor, wherein the first pulse width modulation signal is input to the gate of each of the first transistor, the second transistor, the third transistor, and the fourth transistor, the drain of the first transistor and the drain of the second transistor are connected to a DC bus of a first target voltage, the source of the third transistor and the fourth transistor are grounded, one end of the primary winding of the inductor is connected to a phase line of an alternating current, the other end of the primary winding of the inductor is connected to the source of the first transistor and the drain of the third transistor, and the neutral line of the alternating current is connected to the source of the second transistor and the drain of the fourth transistor.

3. The device power supply assembly according to claim 2, characterized in that: The secondary winding of the inductor is connected to a first current sampling resistor, and the DC bus of the first target voltage is connected to a voltage dividing sub-circuit, and the voltage dividing sub-circuit is used to divide the first target voltage.

4. The device power supply assembly according to claim 1, characterized in that: The second rectifier circuit includes a first rectifier module, a second rectifier module and a first transformer, wherein the first rectifier module is connected to the primary winding of the first transformer, the second rectifier module is connected to the secondary winding of the first transformer, and the transistors of the first rectifier module and the second rectifier module are respectively input with the second pulse width modulation signal.

5. The device power supply assembly according to claim 4, characterized in that: The first rectifier module includes a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor, wherein the drains of the fifth transistor and the sixth transistor are respectively connected to the DC bus of the first target voltage, the sources of the seventh transistor and the eighth transistor are respectively grounded, the source of the fifth transistor and the drain of the seventh transistor are connected to the first end of the primary winding of the first transformer, and the source of the sixth transistor and the drain of the eighth transistor are connected to the second end of the primary winding of the first transformer.

6. The device power supply assembly according to claim 4, characterized in that: The second rectifier module includes a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor, wherein the drains of the ninth transistor and the tenth transistor respectively output direct current of the second target voltage, the sources of the eleventh transistor and the twelfth transistor respectively are grounded, the source of the tenth transistor and the drain of the twelfth transistor are connected to the third end of the secondary winding of the first transformer, and the source of the ninth transistor and the drain of the eleventh transistor are connected to the fourth end of the secondary winding of the first transformer.

7. The device power supply assembly according to claim 6, characterized in that: The drain of each of the ninth transistor and the tenth transistor is connected to a second current sampling resistor.

8. The device power supply assembly according to any one of claims 1 to 7, characterized in that: A capacitor and a resistor are connected in parallel across the drain and source of each transistor in the first rectifier circuit and the second rectifier circuit.

9. The device power supply assembly according to any one of claims 1 to 7, characterized in that: A clamping diode is connected in parallel to the gate of each transistor of the first rectifier circuit and the second rectifier circuit.

10. The device power supply assembly according to claim 1, characterized in that: The control circuit includes a controller, wherein the controller is provided with a plurality of pins, and the pins include one or more combinations of output pins for pulse width modulation signals, data sampling pins, fault input pins, and output pins for indicator light control signals.

11. The device power supply assembly according to claim 10, characterized in that: The control circuit further includes one or more combinations of a clock subcircuit, an indicator light subcircuit, a reset subcircuit, a burning subcircuit and a communication subcircuit.

12. The device power supply assembly according to claim 1, characterized in that: Also includes: The sampling circuit is used to collect one or more of the first target voltage, the input current of the alternating current, the input voltage of the alternating current, the second target voltage and the current of the direct current.

13. The device power supply assembly according to claim 12, characterized in that: The sampling circuit includes at least one sampling sub-circuit, wherein the sampling sub-circuit is composed of an operational amplifier, a diode, a resistor, and a capacitor.

14. The device power supply assembly according to claim 1, characterized in that: Also includes: The driving circuit is configured to drive the plurality of transistors of the first rectifier circuit according to the first pulse width modulation signal, and to drive the plurality of transistors of the second rectifier circuit according to the second pulse width modulation signal.

15. The device power supply assembly according to claim 1, characterized in that: Also includes: A reference voltage circuit, which is composed of a plurality of operational amplifiers and is used to provide a reference voltage to the device power supply component.

16. An electronic device, characterized in that: include: The device power supply assembly according to any one of claims 1 to 15.

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