High-speed DC motor drive system based on analog switches and FPGA

Abstract

The present invention relates to the field of DC motor drive technology, and provides a high-speed DC motor drive system based on analog switches and FPGAs, including a control module, a drive module, and a feedback module. By implementing this solution, on the one hand, a sampling resistor is connected in series on each side of the DC motor of the middle bridge arm of the full-bridge power circuit, and high-precision bidirectional current measurement of the DC motor and improved reliability of the drive system are achieved through full-path detection and common-mode suppression without adding additional delay and power consumption. On the other hand, the common-mode input voltage of the operational amplifier is reduced by using analog switches and limiting diodes, and there is no need to be restricted by high common-mode voltage, so that an operational amplifier with faster response speed can be selected. On the other hand, the FPGA has a built-in fault detection unit and a redundancy check unit, which improves the safety and reliability of the system by working in conjunction with dual sampling resistors, limiting diodes, and analog switches.

Description

Technical Field

[0001] The present invention relates to the technical field of direct current motor driving, and in particular to a high-speed direct current motor driving system based on an analog switch and an FPGA. Background Art

[0002] When using PWM (Pulse Width Modulation) to drive a MOSFET to control a DC motor, a voltage spike is generated between the drain and source of the MOSFET due to the resonance between the current stored in the parasitic inductance of the circuit and substrate wiring when the MOSFET is turned on, and the parasitic capacitance. This voltage spike has a significant impact on current sampling and control.

[0003] Currently, the conventional solution to reducing the impact of voltage spikes on current sampling is to use an LC+RC filter circuit in series with the MOSFET's SW or an RCD snubber circuit. However, the introduction of inductance increases control delay, hindering rapid control response. The damping effect provided by resistors requires high power at high frequencies and speeds, making selection difficult and introducing power loss. Furthermore, the high drive voltage of the motor results in a high voltage across the sampling resistor, which places a high common-mode input requirement on the operational amplifier, hindering the selection of an amplifier with high speed and fast response performance.

[0004] In order to reduce the impact of voltage spikes on current sampling, while not increasing control delay due to the introduction of inductors, not causing power loss due to the introduction of resistors, and not increasing the high common-mode input requirements of the operational amplifier, it is necessary to develop a high-speed DC motor drive system that can not only solve the impact of voltage spikes on current sampling and improve the quality of current sampling, but also reduce the delay of the drive circuit by introducing passive components such as inductors and resistors, and reduce the voltage across the sampling resistor. Summary of the Invention

[0005] Based on the above situation, the main purpose of the present invention is to provide a high-speed DC motor drive system based on analog switches and FPGA, which can achieve high-precision current sampling while improving the DC motor drive efficiency.

[0006] The technical solutions adopted by the present invention to solve the technical problems are as follows:

[0007] The present invention provides a high-speed DC motor drive system based on analog switches and FPGA, which includes a control module, a drive module and a feedback module.

[0008] The control module is used to output a PWM signal to the drive module to control the forward and reverse rotation of the DC motor according to the current sampling data provided by the feedback module, and to trigger the feedback module to perform current sampling according to the signal of the analog switch output by the DC motor forward and reverse rotation; the control module includes an FPGA.

[0009] The drive module is used to control different switch tube combinations of the full-bridge power circuit according to the PWM signal output by the control module, so as to achieve the polarity reversal of the DC motor terminal voltage, thereby controlling the bidirectional flow of current; the drive module includes a full-bridge power circuit.

[0010] The feedback module is used to capture the complete current waveform of the DC motor in real time; the feedback module includes a dual sampling resistor, a limiting diode array, an analog switch array, and a differential operational amplifier.

[0011] The dual sampling resistor is composed of a sampling resistor connected in series on each side of the DC motor on the middle bridge arm of the full-bridge power circuit.

[0012] The limiting diode array, the analog switch array, and the differential operational amplifier are connected between the dual sampling resistors and the FPGA, and are used to work together with the dual sampling resistors, the full-bridge power circuit, and the FPGA to improve the current sampling accuracy.

[0013] Furthermore, the limiting diode array is used to limit the voltage across the sampling resistor to prevent it from exceeding the common-mode input voltage of the differential operational amplifier, and includes four limiting diodes; the analog switch array is used to switch the analog switches according to the control signal sent by the FPGA to select different sampling resistor channels and realize the switching and selection of the current sampling signal, and includes two analog switches.

[0014] Furthermore, the two common-mode input terminals of the differential operational amplifier are respectively connected to the input terminal of an analog switch, and the output terminal is connected to the FPGA, so as to implement differential operation and calculate the actual current flowing through the sampling resistor.

[0015] Furthermore, one end of two of the four limiting diodes is respectively connected to the bridge arm side of the two sampling resistors, and the other end is connected to the output end of an analog switch, and one end of the other two of the four limiting diodes is respectively connected to the DC motor side of the two sampling resistors, and the other end is connected to the output end of another analog switch.

[0016] Furthermore, the input terminal of each analog switch is connected to the output terminal of the differential operational amplifier, and the output terminal of each analog switch is connected to the limiting diode array.

[0017] Furthermore, the control simulation includes a dual-channel switching logic module. When the FPGA detects the DC motor steering switching instruction, it triggers the analog switch to switch the current sampling channel at the current zero point. Specifically, it includes: detecting the direction of the DC motor winding current through dual sampling resistors; when the current direction changes, the analog switch channel is switched after a delay of one PWM cycle to avoid current loop oscillation caused by sudden changes in the sampling signal.

[0018] Furthermore, the FPGA has a built-in ADC, and the ADC and analog switch work together using a 2:1 multiplexer to switch to different current sampling channels in a time-sharing manner; the control module further includes: an ADC trigger synchronization unit, which starts ADC sampling at the center point or trough of the PWM waveform and synchronizes it with the analog switch switching signal; a hardware overcurrent protection unit, which immediately blocks the PWM output and resets the analog switch to a safe path if any current sampling value exceeds the threshold.

[0019] Furthermore, the full-bridge power circuit is composed of four power switch tubes Q1, Q2, Q3 and Q4 to form an H-bridge topology, wherein: Q1 and Q4 form a first diagonal switch group, and Q2 and Q3 form a second diagonal switch group; the drive module responds to the PWM signal of the control module and changes the polarity of the motor terminal voltage by alternately turning on the first or second diagonal switch group.

[0020] Furthermore, the FPGA also includes a fault detection unit for monitoring the current sampling data provided by the feedback module in real time to detect whether there is an abnormal situation. When an abnormal situation is detected, the FPGA can output a control signal to quickly shut down the power devices in the drive module, cut off the power supply of the DC motor, and output an alarm signal.

[0021] Furthermore, the FPGA also includes a redundancy check unit, which is used to simultaneously collect dual sampling resistance data and compare the difference between the two through the FPGA when the motor is running in steady state. If the deviation exceeds a threshold, a sampling fault alarm is triggered.

[0022] The beneficial effects of the present invention include:

[0023] First, the present invention connects two sampling resistors in series on both sides of the DC motor of the middle bridge arm of the full-bridge power circuit, so that the full-bridge circuit can capture the real DC motor current in real time when driving the motor to rotate in two directions, overcoming the defect that traditional low-side sampling cannot detect the high-side freewheeling current. At the same time, the dual sampling resistors are symmetrically arranged on both sides of the DC motor, and their common-mode noise is automatically offset in the differential amplifier circuit, thereby realizing high-precision bidirectional current measurement of the DC motor and improving the reliability of the drive system through full-path detection and common-mode suppression without increasing additional delay and power consumption.

[0024] Secondly, the present invention reduces the common-mode input voltage of the operational amplifier (i.e., the voltage across the sampling resistor on the low-voltage side) by using analog switches and limiting diodes, eliminating the need to be limited by high common-mode voltage and allowing the selection of an operational amplifier with a faster response speed.

[0025] Thirdly, the present invention improves system safety and reliability by integrating the fault detection unit and the redundancy check unit in the FPGA into a coordinated operation with the dual sampling resistor, the limiting diode and the analog switch. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Schematic diagram of the structure of a high-speed DC motor drive system provided by an embodiment of the present invention.

[0027] Figure 2 This is a workflow diagram of the high-speed DC motor drive system provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0028] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0029] Current DC motor drive systems are susceptible to voltage spikes, resulting in low sampling accuracy. Adding capacitors or resistors to the drive circuit hinders rapid control response and introduces power loss. Therefore, a high-speed DC motor drive system is required to meet the following core requirements: high-precision current sampling, highly reliable system operation, low hardware cost, and fast hardware response. This solution combines the flexibility of an FPGA with the reliability of full-bridge dual-resistor sampling to develop a high-speed DC motor drive system that meets the most demanding motor drive requirements.

[0030] Please refer to Figure 1 In order to meet the motor drive requirements of high-precision current sampling, high-reliability system operation, low hardware cost and fast hardware response, this application provides a high-speed DC motor drive system based on analog switches and FPGA, including a control module, a drive module and a feedback module.

[0031] The control module is used to output a PWM signal for controlling the forward and reverse rotation of the DC motor to the drive module according to the current sampling data provided by the feedback module, and to trigger the feedback module to perform current sampling according to the signal of the analog switch output by the DC motor for forward and reverse rotation. The control module includes an FPGA.

[0032] The drive module is used to control different switch tube combinations of the full-bridge power circuit according to the PWM signal output by the control module, to achieve the polarity reversal of the DC motor terminal voltage, thereby controlling the bidirectional flow of current. The drive module includes a full-bridge power circuit.

[0033] The feedback module includes a dual sampling resistor, a limiting diode array, an analog switch array, and a differential operational amplifier.

[0034] Specifically, the following is a specific embodiment of the DC motor drive system to achieve the following functions:

[0035] (1) The control module (FPGA) can generate bipolar PWM signals to control the forward and reverse rotation of the motor, switch the analog switch according to the direction of the motor, and trigger the feedback module to sample the current, process the feedback data in real time, and dynamically adjust the control parameters.

[0036] (2) The drive module (full-bridge power circuit) can achieve the reverse polarity of the motor terminal voltage and control the bidirectional flow of current by switching the switch tube combination, and support zero voltage switching to reduce switching losses.

[0037] (3) The feedback module can collect motor current and voltage signals in real time and provide high-precision feedback data.

[0038] In order to achieve full-path detection and common-mode suppression, the feedback module used in this application is used to capture the complete current waveform of the DC motor in real time. The dual sampling resistor is composed of a sampling resistor connected in series on each side of the DC motor on the middle bridge arm of the full-bridge power circuit. The limiting diode array, analog switch array, and differential operational amplifier are connected between the dual sampling resistor and the FPGA, which are used to work together with the dual sampling resistor, full-bridge power circuit, and FPGA to improve the current sampling accuracy.

[0039] Specifically, the following is a specific embodiment of a dual sampling resistor connected in series on the motor side. In the DC motor drive system provided by this embodiment, the dual sampling resistors are connected in series at both ends of the DC motor in the middle of the bridge arm of the full-bridge power circuit. This embodiment features full current path coverage, meaning that regardless of the motor's forward, reverse, or freewheeling phases, the current flows through one of the two sampling resistors, ensuring no sampling blind spots. Due to its symmetrical layout, the PCB trace lengths, widths, and heat dissipation designs of the two sampling resistors are identical, reducing temperature drift differences, improving sampling synchronization, and offsetting common-mode interference introduced by voltage jumps at the bridge arm midpoint.

[0040] The current detection logic of the embodiment of the motor side double sampling resistor series is based on time-sharing multiplexing technology, specifically: FPGA controls the analog switch array to select the effective sampling resistor according to the direction of the motor. For example, in the forward mode, when Q1 / Q4 is turned on, the FPGA closes the corresponding analog switch to collect the current. Figure 1 The voltage drop of the sampling resistor on the right side, Figure 1 The signal of the sampling resistor on the left is shielded to avoid interference; in the inversion mode, when Q2 / Q3 is turned on, the FPGA closes another analog switch to collect Figure 1 The voltage drop of the left sampling resistor, Figure 1 The signal of the sampling resistor on the right is shielded.

[0041] The synchronization timing of the embodiment of the dual sampling resistors in series on the motor side is as follows: the ADC sampling moment is aligned with the PWM center to avoid MOSFET switching noise, and a blanking time (such as 200ns) is inserted after switching the analog switch to wait for the signal to stabilize.

[0042] The common-mode noise suppression design of this embodiment of the motor-side dual sampling resistor series connection is as follows: Since the bridge arm midpoint voltage jumps sharply during the switching process (for example, from 0V to the bus voltage), the following measures are required: a. Use a high common-mode rejection op amp in the differential operational amplifier configuration; b. Use a limiting diode clamp to prevent voltage spikes from damaging the op amp.

[0043] To prevent the voltage across the sampling resistor from exceeding the common-mode input voltage of the operational amplifier, this solution uses a limiting diode array to limit the voltage across the sampling resistor. The limiting diode array includes four limiting diodes. The analog switch array switches the analog switches according to the control signal sent by the FPGA to select different sampling resistor channels and realize the switching and selection of the current sampling signal. It includes two analog switches.

[0044] One end of two of the four limiting diodes is respectively connected to the bridge arm side of the two sampling resistors, and the other end is connected to the output end of an analog switch. One end of the other two of the four limiting diodes is respectively connected to the DC motor side of the two sampling resistors, and the other end is connected to the output end of another analog switch.

[0045] To implement differential operations and calculate the actual current flowing through the sampling resistor, the two common-mode inputs of the differential operational amplifier are each connected to the input of an analog switch, and the output is connected to the FPGA. The input of each analog switch is connected to the output of the differential operational amplifier, and the output of each analog switch is connected to a limiting diode.

[0046] Specifically, the following is a specific implementation example of sampling resistor voltage limiting and analog switch switching, which is used to prevent the voltage across the sampling resistor from exceeding the common-mode input voltage range of the differential operational amplifier (such as ±12V), thereby avoiding saturation or damage to the operational amplifier.

[0047] The hardware components of this embodiment of sampling resistor voltage limiting and analog switch switching are as follows: the limiting diode array is composed of 4 high-speed switching diodes.

[0048] The working principle of the sampling resistor voltage limiting and analog switch switching embodiment is: a. Under normal working conditions, when Figure 1 The voltage across the sampling resistor on the right is within the range of ±0.1V (corresponding to ±20A current), and the limiting diode is cut off, which does not affect signal transmission; b. During overvoltage protection, if Figure 1 If the voltage across the right sampling resistor is greater than +5V (such as a MOSFET switching spike), Q1 turns on and clamps the voltage to +5V. Figure 1 The voltage across the sampling resistor on the right is less than -5V, Q4 is turned on, and the voltage is clamped to -5V.

[0049] The purpose of setting up an analog switch array is to switch different sampling resistor channels according to FPGA control signals to achieve time-sharing multiplexing of single ADC resources. The following is a specific embodiment of the analog switch array, including:

[0050] (1) The hardware of the analog switch array is composed of two four-channel analog switches.

[0051] (2) The working principle of the analog switch array is synchronous switching timing, that is, the FPGA switches the analog switch within the PWM dead time (such as 500ns) to avoid the switch tube action interfering with the sampling; after the analog switch is switched, the ADC sampling is started again after a delay of 200ns. The delay time is used to wait for the signal to stabilize.

[0052] (3) The anti-crosstalk design of the analog switch array uses the unselected analog switch channel to be grounded and controlled by FPGA to reduce the influence of parasitic capacitance.

[0053] This sampling resistor voltage limiting and analog switch switching embodiment uses a limiting diode array for hardware-level overvoltage protection and dynamic analog switch switching to achieve time-sharing multiplexing of the ADC and ensure sampling purity; and uses FPGA precise timing control to achieve synchronization with the PWM dead time to avoid interference, thereby realizing a highly reliable and low-cost current sampling solution.

[0054] To dynamically switch analog switch channels during DC motor direction switching using an FPGA, the control simulation includes a dual-channel switching logic module. Upon detecting a DC motor direction switching command, the FPGA triggers the analog switch to switch the current sampling channel at the current zero crossing point. Specifically, this involves detecting the DC motor winding current direction using dual sampling resistors. When the current direction changes, the analog switch channel is switched after a delay of one PWM cycle to avoid current loop oscillations caused by sudden changes in the sampling signal.

[0055] The following is a specific embodiment of achieving dynamic channel switching through analog switching, which specifically includes the following hardware modules: (1) Control module, which is responsible for receiving steering instructions, detecting current direction, generating PWM signals, and controlling analog switch switching through FPGA. (2) Sampling module, which uses dual sampling resistors to detect positive and negative currents through independent resistors, eliminating the influence of parasitic resistance. (3) Differential amplifier, which amplifies the current signal and suppresses common-mode noise. (4) Limiting diode, which uses TVS diode to clamp the signal within the ±5V range. (5) Analog switch array, which is controlled by FPGA to switch sampling channels.

[0056] The embodiment of realizing dynamic channel switching by simulating the beginning also includes the following switching strategies:

[0057] (1) Delay control and analog switch switching delay mechanism: When a steering command is detected, the FPGA records the current PWM cycle counter value and delays the triggering of analog switch switching by one complete PWM cycle. The reason for adopting the delay mechanism is to avoid sampling mutations caused by the current not crossing zero during switching. Through FPGA control, it ensures that switching is only executed at the beginning of the next PWM cycle.

[0058] (2) The analog switch switching logic is as follows: a. Use the analog switch to control the sampling channel switching timing design to realize the current channel closing; b. Open the new channel after a delay of 1μs; c. Control the IN pin level through the MOS tube to avoid cross conduction.

[0059] In order to achieve high-precision current sampling and nanosecond-level safety protection for high-speed DC motor drives, the FPGA has a built-in ADC. The ADC and analog switch use a 2:1 multiplexer to switch to different current sampling channels in a time-sharing manner. The control module of the analog switch array further includes: (1) an ADC trigger synchronization unit, which is used to start ADC sampling at the center point or valley moment of the PWM waveform and synchronize with the analog switch switching signal; (2) a hardware overcurrent protection unit, which is used to immediately block the PWM output and reset the analog switch to a safe path when the current sampling value of any channel exceeds the threshold.

[0060] Specifically, the following is a specific embodiment of current sampling and protection based on the built-in ADC and analog switch of FPGA. This embodiment adopts the "built-in ADC of FPGA + 2:1 analog switch multiplexing + hardware overcurrent protection" solution to achieve high-precision current sampling and nanosecond-level safety protection for high-speed DC motor drive. Its hardware components are as follows: (1) FPGA integrated ADC; (2) analog switch, using a 2:1 multiplexer; (3) current sampling resistor.

[0061] To achieve forward and reverse control of the DC motor through a full-bridge power circuit, combined with dynamic switching logic and protection mechanisms to ensure efficient and reliable operation, the full-bridge power circuit consists of four power switches Q1, Q2, Q3, and Q4 forming an H-bridge topology. Q1 and Q4 form the first diagonal switch group, while Q2 and Q3 form the second diagonal switch group. The drive module responds to the PWM signal from the control module and changes the polarity of the motor terminal voltage by alternately turning on the first or second diagonal switch group.

[0062] Specifically, the following is an embodiment of a full-bridge power circuit design based on an H-bridge topology, including:

[0063] (1) The circuit consists of power switch tubes, which use MOSFET to form an H-bridge, where Q1 and Q3 are upper arm switches, and Q2 and Q4 are lower arm switches.

[0064] (2) The freewheeling paths include: a. Diode freewheeling, i.e. the body diodes D1-D4 of Q1-Q4 provide a freewheeling path for the inductor current when the switch tube is turned off; b. MOSFET freewheeling, i.e. by actively turning on Q3-Q2 (or Q1-Q4) to form a low-impedance freewheeling loop, accelerating the current decay.

[0065] (3) The drive module logic and PWM control are as follows: a. The drive signal is generated using a dual-arm complementary PWM mode, that is, Q1 and Q2 share a set of complementary PWM (PWM1 / PWMN1), and Q3 and Q4 share another set of complementary PWM (PWM2 / PWMN2). The PWM frequency is generated by the FPGA.

[0066] (4) The direction control logic is: during forward rotation, Q1 and Q4 are turned on, Q2 and Q3 are turned off, and the current path is Vbat→Q1→motor M→Q4→GND; during reverse rotation, Q2 and Q3 are turned on, Q1 and Q4 are turned off, and the current path is Vbat→Q3→motor M→Q2→GND.

[0067] (5) Dead time management: FPGA inserts a 200ns to 500ns dead time when switching between the upper and lower bridge arms to prevent shoot-through short circuits. The dead time is dynamically adjusted based on the drive voltage. That is, when the voltage fluctuation exceeds ±10%, the dead time is extended by 20%.

[0068] In order to monitor current sampling data in real time, identify abnormal conditions, trigger the shutdown of power devices and output alarm signals, the FPGA also includes a fault detection unit. The fault detection unit is used to monitor the current sampling data provided by the feedback module in real time and detect whether there are abnormal conditions. When an abnormal condition is detected, the FPGA can output a control signal to quickly shut down the power devices in the drive module, cut off the power supply of the DC motor, and output an alarm signal.

[0069] Specifically, the following is an embodiment of a fault detection unit based on an FPGA. The core modules of this embodiment include: (1) a data acquisition module, which is used to receive current sampling data from the feedback module (converted into digital signals via an ADC); (2) an anomaly detection module, which is used to analyze the current data in real time and determine anomalies based on the FPGA logic circuit; and (3) a fault response module, which is used to control the drive module to shut down the power device and trigger an alarm signal.

[0070] The key technologies implemented in this embodiment of the fault detection unit include:

[0071] (1) Current sampling and preprocessing. The data acquisition method is to detect the forward and reverse currents through dual sampling resistors, and then input them into the ADC after amplification by the differential amplifier. The sampling frequency is designed to be 1MHz to meet the dynamic response requirements when the PWM cycle is 10kHz. The preprocessing logic includes: a. The filtering device uses the FPGA embedded FIR filter to eliminate high-frequency noise; b. The normalization scheme is to convert the ADC output value into the actual current value.

[0072] (2) Abnormal detection algorithm, including: a. Threshold detection, using overcurrent protection, that is, if the current exceeds the preset threshold (such as 5A), the shutdown signal is triggered; b. Undercurrent detection, if the current is lower than the set value (such as 0.1A), it is judged as a motor stall or disconnection; c. Sudden change detection, including differential calculation and sliding window statistics, in which the differential calculation is judged as an instantaneous short circuit or load sudden change by the current difference between two consecutive sampling points exceeding the threshold (such as Δ1>2A); the sliding window statistics is calculated by calculating the standard deviation of the latest 10 sampling points. If the standard deviation exceeds the threshold (such as σ>0.5A), an abnormal alarm is triggered.

[0073] (3) Fault response control, including: a. Power device shutdown, when the PWM signal is disabled, a low-level PWM signal is sent to the driver module to force the shutdown of all power switch tubes (Q1-Q4); b. Driver chip control, directly controlling the enable pin of the driver chip through GPIO (such as pulling the EN pin low); c. Alarm output, including hardware alarm and communication alarm, among which the hardware alarm is realized by driving the buzzer and LED indicator light, and the communication alarm is realized by sending the fault code to the host computer.

[0074] (4) Reliability enhancement design, including: a. Redundant detection, using dual sampling resistor sampling, collecting current data through two independent sampling resistors, and comparing the consistency of the results; b. Self-test logic, verifying the normality of the current sampling link by regularly sending test signals to the feedback module; c. Fault recovery, using automatic reset, after the fault is resolved, the FPGA restarts the drive module after a delay of 1 second to prevent misjudgment of transient faults; d. Log recording, recording the fault time, type and current waveform fragments through the FPGA internal RAM.

[0075] In order to achieve redundant verification of dual-resistance current sampling and ensure the reliability of current detection during steady-state operation of the motor, the FPGA also includes a redundant verification unit. The redundant verification unit is used to simultaneously collect dual-sampling resistor data and compare the difference between the two through the FPGA when the motor is running in steady state. If the deviation exceeds the threshold, a sampling fault alarm is triggered.

[0076] The following is a specific embodiment of the design of a dual-resistance redundancy check unit based on FPGA. By comparing the difference between the current data of the two channels in real time, if the deviation exceeds the threshold, a fault alarm is triggered. The specific implementation is as follows:

[0077] (1) Hardware architecture and module division. The core modules are: a. voltage signal acquisition of two independent sampling resistors; b. FPGA control unit, which is responsible for data acquisition, difference calculation, threshold comparison and alarm control; c. alarm output module, including buzzer, LED indicator and communication interface.

[0078] (2) Key technology implementation: Through dual-resistance sampling and synchronous control, the hardware design uses sampling resistors connected in series in the forward and reverse circuits of the motor windings, and then amplified by a differential amplifier and input into the ADC. Its synchronous control logic includes: a. FPGA controls the ADC to use a ping-pong cache strategy to ensure that dual-channel data is collected at the same time point; b. Difference calculation and threshold comparison, using data processing logic for normalization processing, converting the ADC output value into the actual current value, and its threshold is set to dynamically adjust according to the rated current of the motor; c. Steady-state detection logic, by monitoring the current fluctuation amplitude, such as the standard deviation σ of 100 consecutive sampling points < 0.1A, to determine whether the motor has entered a steady state.

[0079] (3) Alarm and fault response, including: a. Hardware alarm, achieved by driving the buzzer and LED indicator; b. Software alarm, achieved by sending fault codes through the communication interface; c. Power device shutdown, by sending a low-level PWM signal to the driver module to force the H-bridge power tube to turn off; d. Anti-interference and reliability design, the filtering algorithm uses a sliding average filter to eliminate ADC noise; e. Redundancy check, using dual-channel cross-validation, if any channel data is abnormal, such as ADC communication timeout, it automatically switches to the other channel for sampling; f. Self-test mechanism, using regular injection of test current to verify the consistency of the two channels, and triggering the system self-test alarm when the error exceeds the threshold.

[0080] Please refer to Figure 2 The following is another specific embodiment of the high-speed DC motor drive system of this solution. This embodiment provides an improved full-bridge drive circuit design, including:

[0081] (1) Two sampling resistors are placed in the middle arm of the full-bridge drive at the same time, so that the full-bridge circuit can collect current when the drive motor rotates in both directions.

[0082] (2) This solution provides a differential amplifier circuit design based on analog switches and limiting diodes. The circuit includes: a. Two analog switches controlled by FPGA, which can switch the sampling resistor according to the forward and reverse rotation of the motor, so that the current collected by the sampling resistor is the current after filtering by the DC motor inductor; b. The limiting diode limits the voltage across the sampling resistor to prevent it from exceeding the common-mode input voltage of the operational amplifier; c. The FPGA is used to output PWM signals for controlling the forward and reverse rotation of the motor and switching the analog switch channels, including pwm1~4, which respectively control the four switch tubes Q1~4; d. The operational amplifier is used to implement differential operations and calculate the actual current flowing through the sampling resistor.

[0083] The full-bridge drive circuit operates as follows: a. The FPGA outputs a PWM signal for controlling the motor's forward and reverse rotation based on the received voltage command value. It also outputs square-wave signals pwm-select1 and pwm-select2 for switching the analog switch channels based on the motor's forward and reverse rotation. b. Two sampling resistors simultaneously sample the current flowing through the motor. At any given moment, one sampling resistor is on the high-voltage side (the current is not filtered by the motor inductor) and the other is on the low-voltage side (the current is filtered by the motor inductor). c. The analog switch is controlled by the square-wave signal, so that the two common-mode inputs of the operational amplifier are always connected to the two ends of the low-voltage sampling resistor. The limiting diode is used to ensure that the voltage at the common-mode input of the operational amplifier does not exceed the limit.

[0084] The beneficial effects of this embodiment include:

[0085] (1) The improved drive circuit acquires the current after motor inductance filtering, achieving better sampling and control effects without increasing additional delay and power consumption.

[0086] (2) The use of analog switches and limiting diodes makes the common-mode input voltage of the operational amplifier (i.e., the voltage across the sampling resistor on the low-voltage side) smaller, so it does not need to be limited by the high common-mode voltage, allowing the selection of an operational amplifier with faster response speed.

[0087] (3) Using FPGA to control the drive circuit can better achieve the synchronization of motor forward and reverse rotation and analog open-loop switching.

[0088] (4) The A, B, C, and D ports of the four limiting diodes correspond to the A, B, C, and D ports of the two sampling resistors respectively; the Vbat port of the full-bridge power circuit is used for the positive input of the DC power supply and to provide energy for the H-bridge, and the GND port is the power ground, forming a loop with Vbat; the built-in ADC port of the FPGA is the sampling port, and the power amplifier end of the differential operational amplifier is the sampling end. The two are connected and work together to realize current sampling, ADC conversion, and closed-loop control.

[0089] The high-speed DC motor drive system of this embodiment has the following specific working process: a. The FPGA outputs a PWM signal to control the forward and reverse rotation of the motor and outputs a square signal to switch the analog switch; b. The sampling resistor simultaneously samples the current flowing through the motor; c. The analog switch is controlled by the square wave signal, so that the two common-mode input terminals of the operational amplifier are always connected to the two ends of the low-voltage side sampling resistor; d. The operational amplifier performs differential processing for subsequent signal processing and sampling.

[0090] Those skilled in the art can make various other corresponding changes and deformations based on the technical solutions and concepts described above, and all of these changes and deformations should fall within the scope of protection of the claims of the present invention.

[0091] It should be noted that the embodiments described above are only some of the embodiments of the present invention, rather than all of the embodiments. The singular forms "a," "an," "the," and "it" used in the embodiments and the appended claims are intended to include the plural forms as well, unless the context clearly indicates otherwise.

Claims

1. High-speed DC motor drive system based on analog switch and FPGA, characterized by: The high-speed DC motor drive system includes a control module, a drive module and a feedback module; The control module is used to output a PWM signal to the driving module to control the forward and reverse rotation of the DC motor according to the current sampling data provided by the feedback module, and trigger the feedback module to perform current sampling according to the signal of the analog switch output by the DC motor; the control module includes an FPGA; The driving module is used to control different switch tube combinations of the full-bridge power circuit according to the PWM signal output by the control module to achieve polarity reversal of the DC motor terminal voltage, thereby controlling the bidirectional flow of current; the driving module includes a full-bridge power circuit; The feedback module is used to capture the complete current waveform of the DC motor in real time; the feedback module includes a dual sampling resistor, a limiting diode array, an analog switch array, and a differential operational amplifier; The dual sampling resistors are composed of a sampling resistor connected in series on each side of the DC motor on the middle bridge arm of the full-bridge power circuit; The limiting diode array, analog switch array, and differential operational amplifier are connected between the dual sampling resistor and the FPGA, and are used to work together with the dual sampling resistor, the full-bridge power circuit, and the FPGA to improve the current sampling accuracy; The limiting diode array is used to limit the voltage across the sampling resistor to prevent it from exceeding the common-mode input voltage of the differential operational amplifier, and includes four limiting diodes; The analog switch array is used to switch the analog switches according to the control signal sent by the FPGA to select different sampling resistor channels and realize the switching and selection of the current sampling signal, and includes two analog switches; The two common-mode input terminals of the differential operational amplifier are each connected to the input terminal of an analog switch, and the output terminal is connected to the FPGA to implement differential operation and calculate the actual current flowing through the sampling resistor; One end of two of the four limiting diodes is respectively connected to the bridge arm side of the two sampling resistors, and the other end is connected to the output end of an analog switch; one end of the other two of the four limiting diodes is respectively connected to the DC motor side of the two sampling resistors, and the other end is connected to the output end of another analog switch; An input terminal of each analog switch is connected to an output terminal of a differential operational amplifier, and an output terminal of each analog switch is connected to a limiting diode array.

2. The high-speed DC motor drive system according to claim 1, characterized in that: The analog switch array includes a dual-channel switching logic module. When the FPGA detects a DC motor direction switching instruction, it triggers the analog switch to switch the current sampling channel at the current zero-crossing point. Specifically, the module detects the direction of the DC motor winding current through dual sampling resistors. When the current direction changes, the analog switch channel is switched after a delay of one PWM cycle to avoid current loop oscillation caused by sudden changes in the sampling signal.

3. The high-speed DC motor drive system according to claim 2, characterized in that: The FPGA has a built-in ADC, and the ADC and the analog switch cooperate with a 2:1 multiplexer to switch to different current sampling channels in a time-sharing manner; The control module further comprises: ADC trigger synchronization unit: starts ADC sampling at the center point or valley of the PWM waveform and synchronizes it with the analog switch switching signal; Hardware overcurrent protection unit: If any current sampling value exceeds the threshold, the PWM output is immediately blocked and the analog switch is reset to a safe path.

4. The high-speed DC motor drive system according to claim 1, characterized in that: The full-bridge power circuit is composed of four power switch tubes Q1, Q2, Q3 and Q4 to form an H-bridge topology, wherein: Q1 and Q4 form the first diagonal switch group, and Q2 and Q3 form the second diagonal switch group; The driving module responds to the PWM signal of the control module and changes the polarity of the motor terminal voltage by alternately turning on the first or second diagonal switch group.

5. The high-speed DC motor drive system according to claim 1, characterized in that: The FPGA also includes a fault detection unit, which is used to monitor the current sampling data provided by the feedback module in real time and detect whether there is an abnormal situation. When an abnormal situation is detected, the FPGA can output a control signal to quickly shut down the power devices in the drive module, cut off the power supply of the DC motor, and output an alarm signal.

6. The high-speed DC motor drive system according to claim 1 or 5, characterized in that: The FPGA also includes a redundancy check unit, which is used to simultaneously collect dual sampling resistance data and compare the difference between the two through the FPGA when the motor is running in a steady state. If the deviation exceeds a threshold, a sampling fault alarm is triggered.

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