A dynamic comparator operating at low power supply voltage

Abstract

The present invention discloses a dynamic comparator operating under low power supply voltage, comprising a first-stage preamplifier, a second-stage latch and a clock generation circuit, which can solve the problem of limited amplitude of the comparator input signal under low power supply voltage. DD Under power supply, it can correctly compare the amplitude of 2×V DD The present invention utilizes a fully dynamic operating mode, eliminating the need for a high-voltage power supply. Furthermore, the present invention utilizes a fully dynamic operating mode, eliminating the need for static current consumption and making it suitable for low-power comparator designs. Furthermore, the present invention requires only one externally applied clock signal; the clocks controlling the comparator's operation are all generated by its internal clock generation circuitry, eliminating the need for multiple clocks generated by an external signal generator or field-programmable gate array, simplifying the design.

Description

Technical Field

[0001] The invention belongs to the technical field of analog integrated circuit design, and in particular relates to a dynamic comparator operating under low power supply voltage. Background Art

[0002] Comparators convert the magnitude of an input analog signal into a discrete digital signal. They are widely used in circuits such as analog-to-digital converters, in-memory computing, and power management. They are indispensable circuit modules in fields such as artificial intelligence, the Internet of Things, biomedicine, and communications. As semiconductor processing advances into the deep submicron era, traditional comparator structures, such as open-loop comparators, closed-loop comparators, and latches, are no longer able to meet current requirements for low power consumption and high precision. Consequently, comparators are trending from single-stage to multi-stage structures, and from static to dynamic operating modes. Furthermore, the reduction in power supply voltage brought about by advanced processing reduces the comparator's power consumption while also reducing the input signal range it can handle, limiting its applications.

[0003] Regarding the design of comparators under low power supply voltages, the existing literature [Li Cong. Design of a Low-Voltage 12-bit 5MSPS SAR ADC [D]. Liaoning: Liaoning University, 2021] studies a differential amplifier with a cross-coupled transistor as the load for the pre-amplifier in the comparator. This avoids the problem of the MOS (metal oxide semiconductor) transistors in traditional cascode amplifiers failing to operate in the saturation region at low power supply voltages, resulting in amplification failure. However, this research focuses on how to ensure the normal operation of the transistors in the comparator under low power supply voltages and does not consider the problem that the ADC (analog-to-digital converter) quantization range is reduced due to low power supply voltage, which limits the ADC's application scenarios. The literature [Hou Hongyu. Research and Design of Digital Pixels in Infrared Readout Circuits [D]. Liaoning: Dalian University of Technology, 2024] designs an open-loop comparator consisting of two operational amplifiers. By cascading the two amplifiers, the gain and accuracy of the comparator are increased. However, the operational amplifiers used in this research have static power consumption, which is not conducive to low-power comparator design. Summary of the Invention

[0004] In view of the above, the present invention provides a dynamic comparator operating at a low power supply voltage to solve the problem of reduced maximum input signal range caused by low voltage, and is suitable for low power comparator design.

[0005] A dynamic comparator operating at a low power supply voltage, comprising:

[0006] The first stage pre-amplifier is used to amplify the differential input signal;

[0007] The second stage latch is used to compare the amplified differential input signal and generate a comparison result;

[0008] The clock generation circuit is used to generate two sets of non-overlapping clock signals and raise the amplitude of the clock signals to twice the power supply voltage to control the working states of the first-stage pre-amplifier and the second-stage latch.

[0009] Furthermore, the first-stage pre-amplifier includes two NMOS transistors M1 and M2, two PMOS transistors M3 and M4, two reset switches S8 and S9, and a first capacitor power supply network, wherein the source of M1 is connected to the source of M2 and connected to the ground rail of the first capacitor power supply network, the source of M3 is connected to the source of M4 and connected to the power rail of the first capacitor power supply network, the drain of M1 is connected to the drain of M3 and one end of S8 as the inverting output end of the first-stage pre-amplifier, the drain of M2 is connected to the drain of M4 and one end of S9 as the non-inverting output end of the first-stage pre-amplifier, and the other end of S8 is connected to the other end of S9 and connected to the power supply voltage V DD The gate of M1 is connected to the gate of M3 as the positive input terminal of the first stage pre-amplifier, the gate of M2 is connected to the gate of M4 as the negative input terminal of the first stage pre-amplifier, and the on and off of S8 and S9 are controlled by the clock signal Φ 22 control.

[0010] Furthermore, the first capacitor power supply network is based on a charge pump circuit structure, including two capacitors C1 and C2 with equal capacitance and seven switches S1 to S7, wherein the upper plate of C1 is connected to one end of S1 and one end of S3, the lower plate of C1 is connected to one end of S2 and one end of S4, the upper plate of C2 is connected to the other end of S4 and one end of S6, the lower plate of C2 is connected to one end of S5 and one end of S7, and the other end of S1 and the other end of S6 are connected to the power supply voltage V DD , the other end of S2 and the other end of S7 are grounded, the other end of S3 serves as the power rail of the first capacitor power supply network, the other end of S5 serves as the ground rail of the first capacitor power supply network, and the on-off of S1 and S2 is controlled by the clock signal Φ 12 Control, S4 is turned on and off by the clock signal Φ 11 Control, the on and off of S3 and S5 are controlled by the clock signal Φ 21 Control, the on and off of S6 and S7 are controlled by the clock signal Φ 22 control.

[0011] Furthermore, the second-stage latch includes four NMOS transistors M5, M8, M11 and M12, four PMOS transistors M6, M7, M9 and M10 and a second capacitor power supply network, wherein the source of M5 is connected to the source of M8, the source of M11 and the source of M12 and is grounded, the source of M6 is connected to the source of M9 and is connected to the power rail of the second capacitor power supply network, and the drain of M5 is connected to the drain of M7, the drain of M8, the gate of M9 and the gate of M11 as the positive phase of the second-stage latch. The output terminal, the drain of M10 is connected to the drain of M11, the drain of M12, the gate of M6 and the gate of M8 as the inverting output terminal of the second-stage latch, the gate of M7 is connected to the inverting output terminal of the first-stage pre-amplifier as the inverting input terminal of the second latch, the gate of M10 is connected to the non-inverting output terminal of the first-stage pre-amplifier as the non-inverting input terminal of the second latch, the drain of M6 is connected to the source of M7, the drain of M9 is connected to the source of M10, and the gate of M5 and the gate of M12 are connected to the clock signal Φ 22 .

[0012] Furthermore, the second capacitor power supply network is based on a charge pump circuit structure, including two capacitors C3 and C4 with equal capacitance and four switches S10~S13, wherein the upper plate of C3 is connected to one end of S10 and one end of S12, the lower plate of C3 is connected to one end of S11 and one end of S13, and the upper plate of C4 is connected to the other end of S13 and connected to the power supply voltage V DD , the lower plate of C4 is connected to the other end of S11 and grounded, and the other end of S10 is connected to the power supply voltage V DD The other end of S12 serves as the power rail of the second capacitor power supply network. The on-off of S10 and S11 is controlled by the clock signal Φ 12 Control, the on and off of S12 is controlled by the clock signal Φ 21 Control, S13 is turned on and off by the clock signal Φ 11 control.

[0013] Furthermore, the clock signal Φ 11 and Φ 12 Phase complementary and with a certain dead time, the clock signal Φ 21 and Φ 22 Phase complementary and there is a certain dead time, and Φ 11 The rising edge is earlier than Φ 22 The falling edge of

[0014] Furthermore, the clock generation circuit includes two inverters INV1 and INV2, four NAND gates NAND1 to NAND4, four delay modules D1 to D4 and four clock raising modules L1 to L4, wherein the input end of INV1 is connected to the first input end of NAND1 and is connected to the external clock CK, the output end of INV1 is connected to the first input end of NAND2, the output end of NAND1 is connected to the input end of D1, the output end of D1 is connected to the second input end of NAND2 and the input end of L1 and generates the clock CK 12 The output of NAND2 is connected to the input of D2, and the output of D2 is connected to the second input of NAND1, the input of L2, the input of INV2 and the first input of NAND3 to generate the clock CK 11 The output of INV2 is connected to the first input of NAND4, the output of NAND3 is connected to the input of D3, the output of D3 is connected to the second input of NAND4 and the input of L3 and generates the clock CK 22 The output of NAND4 is connected to the input of D4, and the output of D4 is connected to the second input of NAND3 and the input of L4 to generate the clock CK 21 , the output terminals of L1~L4 correspond to the output clock signal Φ 12 , Φ 11 , Φ 22 , Φ 21 .

[0015] Furthermore, the clock boost modules L1 to L4 all operate at a power supply voltage V DD Next, it is used to input the clock CK 12 , CK 11 , CK 22 , CK 21 The amplitude of the power supply voltage V DD Raised to 2×V DD Then they are used as clock signals Φ 12 , Φ 11 , Φ 22 , Φ 21 And output.

[0016] Furthermore, the clock lifting modules L1 to L4 have the same structure, including a capacitor C, three NMOS transistors Q2, Q4 and Q5, and four PMOS transistors Q1, Q3, Q6 and Q7, wherein the gate of Q1 is connected to the gate of Q2, the source of Q4, the source of Q5 and one end of C as the input end of the clock lifting module, and the source of Q1 and the source of Q7 are connected to the power supply voltage V DD, the source of Q2 is grounded, the drain of Q1 is connected to the drain of Q2, the gate of Q3, the gate of Q4, the gate of Q5 and the gate of Q6, the drain of Q7 is connected to the source of Q6, the other end of C and the source of Q3, the drain of Q5 is connected to the drain of Q6 and the gate of Q7, and the drain of Q3 is connected to the drain of Q4 as the output end of the clock lifting module.

[0017] The dynamic comparator of the present invention can solve the problem of limited amplitude of the comparator input signal under low power supply voltage. DD Under power supply, it can correctly compare the amplitude of 2×V DD The present invention utilizes a fully dynamic operating mode, eliminating the need for a high-voltage power supply. Furthermore, the present invention utilizes a fully dynamic operating mode, eliminating the need for static current consumption and making it suitable for low-power comparator designs. Furthermore, the present invention requires only one externally applied clock signal; the clocks controlling the comparator's operation are all generated by its internal clock generation circuitry, eliminating the need for multiple clocks generated by an external signal generator or field-programmable gate array, simplifying the design. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 The figure is a schematic diagram of the overall structure of the dynamic comparator working under low power supply voltage of the present invention.

[0019] Figure 2 Schematic diagram of the circuit structure of the first-stage pre-amplifier in an embodiment of the present invention.

[0020] Figure 3 Schematic diagram of the circuit structure of the second-stage latch in an embodiment of the present invention.

[0021] Figure 4 1 is a schematic diagram of the structure of a clock generating circuit and the timing of generating a clock signal in an embodiment of the present invention.

[0022] Figure 5 Schematic diagram of the circuit structure of the clock boost module in an embodiment of the present invention.

[0023] Figure 6 The comparison amplitude of the dynamic comparator in the embodiment of the present invention is 2 times V DD Schematic diagram of the waveforms of key signals under input signals. DETAILED DESCRIPTION

[0024] In order to describe the present invention more specifically, the technical solution of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0025] like Figure 1As shown, the dynamic comparator operating at a low power supply voltage of the present invention includes a first-stage preamplifier, a second-stage latch, and a clock generation circuit, wherein the first-stage preamplifier is used to amplify the differential input signals VIP and VIN, the second-stage latch is used to compare the amplified differential input signals VP and VN and generate comparison results VOP and VON, and the clock generation circuit is used to generate two sets of non-overlapping clock signals Φ 12 and Φ 11 , Φ 22 and Φ 21 And raise the clock signal amplitude to 2 times the power supply voltage to control the operation of the comparator.

[0026] like Figure 2 As shown, the first-stage pre-amplifier in this embodiment includes two NMOS transistors M1 and M2, two PMOS transistors M3 and M4, two reset switches S8 and S9, and a first capacitor power supply network, wherein the sources of M1 and M2 are short-circuited and connected to the ground rail of the first capacitor power supply network, the sources of M3 and M4 are short-circuited and connected to the power rail of the first capacitor power supply network, the drains of M1 and M3 and one end of S8 are short-circuited as the inverting output end of the pre-amplifier to generate a signal VN, the drains of M2 and M4 and one end of S9 are short-circuited as the non-inverting output end of the pre-amplifier to generate a signal VP, the gates of M1 and M3 are short-circuited as the non-inverting input end of the pre-amplifier to receive the signal VIP, the gates of M2 and M4 are short-circuited as the inverting input end of the pre-amplifier to receive the signal VIN, the other end of S8 and the other end of S9 are short-circuited and connected to the power supply voltage V DD connected, switches S8 and S9 are controlled by the clock signal Φ 22 control.

[0027] The first capacitor power supply network is combined with a charge pump circuit structure, including two capacitors C1 and C2 of equal capacitance and seven switches S1 to S7. The upper plate of C1 is connected to one end of S1 and S3, the lower plate of C1 is connected to one end of S2 and S4, the upper plate of C2 is connected to the other end of S4 and one end of S6, the lower plate of C2 is connected to one end of S5 and S7, and the other end of S1 and S6 is connected to V DD , the other end of S2 and S7 is connected to the power supply ground GND, the other end of S3 and S5 is connected to the amplifier tube, S1 and S2 are controlled by the clock Φ 12 Control, S4 is controlled by clock Φ 11 Control, S3 and S5 are controlled by clock Φ 21 Control, S6 and S7 are controlled by clock Φ 22 control.

[0028] like Figure 3As shown, the second-stage latch in this embodiment includes four NMOS transistors M5, M8, M11 and M12, four PMOS transistors M6, M7, M9 and M10 and a second capacitor power supply network, wherein the sources of M5, M8, M11 and M12 are short-circuited and connected to the ground rail of the capacitor power supply network and connected to the power ground GND, the sources of M6 and M9 are short-circuited and connected to the power rail of the capacitor power supply network, and the drains of M5, M7, M8 and the gates of M9 and M11 are short-circuited as the positive phase output terminal of the latch to generate Signal VOP, the drains of M10, M11, M12 and the gates of M6 and M8 are short-circuited as the inverting output of the latch to generate signal VON, the gate of M7 is connected to the inverting output of the first stage pre-amplifier as the inverting input of the latch and receives the signal VN, the gate of M10 is connected to the positive input of the latch and receives the signal VP, the drain of M6 is connected to the source of M7, the drain of M9 is connected to the source of M10, and the gates of M5 and M12 are driven by the clock Φ 22 control.

[0029] The second capacitor power supply network is combined with a charge pump circuit structure, including two capacitors C3 and C4 of equal capacitance and four switches S10~S13, where the upper plate of C3 is connected to one end of S10 and S12, the lower plate of C3 is connected to one end of S11 and S13, and the upper plate of C4 is short-circuited with the other end of S13 and connected to the power supply voltage V DD The lower plate of C4 is short-circuited with the other end of S11 and connected to the power ground GND. The other end of S10 is connected to V DD , the other end of S12 is connected to the latch, S10 and S11 are driven by the clock Φ 12 Control, S12 is controlled by clock Φ 21 Control, S13 is controlled by clock Φ 11 control.

[0030] like Figure 4 As shown, the clock generation circuit in this embodiment includes two inverters INV1 and INV2, four NAND gates NAND1 to NAND4, four delay modules D1 to D4 and four clock raising modules L1 to L4, wherein the input end of INV1 is connected to the first input end of NAND1 and is connected to the external clock CK, the output end of INV1 is connected to the first input end of NAND2, the output end of NAND1 is connected to the input end of D1, the output end of D1 is connected to the second input end of NAND2 and the input end of L1 and generates the clock CK 12 The output of NAND2 is connected to the input of D2, and the output of D2 is connected to the second input of NAND1, the input of L2, the input of INV2 and the first input of NAND3 to generate the clock CK 11The output of INV2 is connected to the first input of NAND4, the output of NAND3 is connected to the input of D3, the output of D3 is connected to the second input of NAND4 and the input of L3 and generates the clock CK 22 The output of NAND4 is connected to the input of D4, and the output of D4 is connected to the second input of NAND3 and the input of L4 to generate the clock CK 21 , the output terminals of L1~L4 generate the clock signal Φ 12 , Φ 11 , Φ 22 , Φ 21 .

[0031] After being stimulated by the external clock CK, the clock generation circuit generates two sets of non-overlapping clocks Φ with an amplitude of 2 times the power supply voltage through the clock boost module. 11 and Φ 12 , Φ 21 and Φ 22 , used to control the first-stage pre-amplifier and the second-stage latch.

[0032] Φ 22 Must be in Φ 11 After the rising edge arrives, it falls again to avoid the short circuit between the lower plate of C1 and the upper plate of C2 in the floating state to generate 0.5×V DD The voltage should generate 2×V DD The capacitor supply network power rail is reduced to 1.5×V DD and -0.5×V DD , causing the comparator to fail. Φ 11 , Φ 12 and Φ 22 The high and low levels must come in sequence, otherwise V DD The path to GND causes a short circuit in the power supply and generates a large current.

[0033] The clock boost module operates at a power supply voltage V DD voltage, used to change the clock amplitude from V DD Raised to 2×V DD , to control the switches in the preamplifier and latch to conduct correctly. Figure 5 As shown, the clock raising module in this embodiment includes a capacitor C, three NMOS transistors Q2, Q4 and Q5 and four PMOS transistors Q1, Q3, Q6 and Q7, wherein the gate of Q1 is connected to the gate of Q2, the source of Q4, the source of Q5 and one end of C as the input end of the clock raising module to receive the input signal CK IN , the source of Q1 and the source of Q7 are connected to the power supply voltage V DD, the source of Q2 is grounded, the drain of Q1 is connected to the drain of Q2, the gate of Q3, the gate of Q4, the gate of Q5 and the gate of Q6, the drain of Q7 is connected to the source of Q6, the other end of C and the source of Q3, the drain of Q5 is connected to the drain of Q6 and the gate of Q7, and the drain of Q3 is connected to the drain of Q4 as the output end of the clock lifting module to generate the output signal CK OUT Input signal CK IN The amplitude is V DD Clock signal, output signal CK OUT The amplitude is 2×V DD The input and output signals have the same period, duty cycle and phase.

[0034] like Figure 6 As shown, this embodiment implements a dynamic comparator operating at a low power supply voltage of 0.6V through a first-stage pre-amplifier, a second-stage latch, and a clock generation circuit. This can correctly compare input signals with an amplitude of 1.2V and output a 1.2V digital signal result. This proves that the dynamic comparator and its clock generation circuit designed in the present invention effectively solve the problem of low-voltage power supply limiting the input signal amplitude. It does not require a high-voltage power supply and only requires one external clock, eliminating the need for complex off-chip control clock generation, thereby simplifying the design. In addition, the present invention adopts a fully dynamic operating mode, does not consume static current, and is suitable for low-voltage comparator design.

[0035] The above description of the embodiments is intended to facilitate understanding and application of the present invention by those skilled in the art. It is apparent that those skilled in the art can readily make various modifications to the above embodiments and apply the general principles described herein to other embodiments without requiring creative effort. Therefore, the present invention is not limited to the above embodiments. Any improvements or modifications made by those skilled in the art based on the disclosure of the present invention should fall within the scope of protection of the present invention.

Claims

1. A dynamic comparator operating at a low power supply voltage, characterized in that: include: The first stage pre-amplifier is used to amplify the differential input signal; The second stage latch is used to compare the amplified differential input signal and generate a comparison result; A clock generation circuit, configured to generate two sets of non-overlapping clock signals and raise the amplitude of the clock signals to twice the power supply voltage to control the operating states of the first-stage pre-amplifier and the second-stage latch; The first-stage preamplifier includes two NMOS transistors M1 and M2, two PMOS transistors M3 and M4, two reset switches S8 and S9, and a first capacitor power supply network, wherein the source of M1 is connected to the source of M2 and connected to the ground rail of the first capacitor power supply network, the source of M3 is connected to the source of M4 and connected to the power rail of the first capacitor power supply network, the drain of M1 is connected to the drain of M3 and one end of S8 as the inverting output end of the first-stage preamplifier, the drain of M2 is connected to the drain of M4 and one end of S9 as the non-inverting output end of the first-stage preamplifier, and the other end of S8 is connected to the other end of S9 and connected to the power supply voltage V DD The gate of M1 is connected to the gate of M3 as the positive input terminal of the first stage pre-amplifier, the gate of M2 is connected to the gate of M4 as the negative input terminal of the first stage pre-amplifier, and the on and off of S8 and S9 are controlled by the clock signal Φ 22 control; The first capacitor power supply network is based on a charge pump circuit structure, including two capacitors C1 and C2 with equal capacitance and seven switches S1 to S7, wherein the upper plate of C1 is connected to one end of S1 and one end of S3, the lower plate of C1 is connected to one end of S2 and one end of S4, the upper plate of C2 is connected to the other end of S4 and one end of S6, the lower plate of C2 is connected to one end of S5 and one end of S7, and the other end of S1 and the other end of S6 are connected to the power supply voltage V DD The other end of S2 and the other end of S7 are grounded, the other end of S3 serves as the power rail of the first capacitor power supply network, and the other end of S5 serves as the ground rail of the first capacitor power supply network. The on-off of S1 and S2 is controlled by the clock signal Φ 12 Control, S4 is turned on and off by the clock signal Φ 11 Control, the on and off of S3 and S5 are controlled by the clock signal Φ 21 Control, the on and off of S6 and S7 are controlled by the clock signal Φ 22 control.

2. The dynamic comparator operating at a low power supply voltage according to claim 1, wherein: The second-stage latch includes four NMOS transistors M5, M8, M11 and M12, four PMOS transistors M6, M7, M9 and M10 and a second capacitor power supply network, wherein the source of M5 is connected to the source of M8, the source of M11 and the source of M12 and is grounded, the source of M6 is connected to the source of M9 and is connected to the power rail of the second capacitor power supply network, and the drain of M5 is connected to the drain of M7, the drain of M8, the gate of M9 and the gate of M11 as the positive phase output of the second-stage latch The drain of M10 is connected to the drain of M11, the drain of M12, the gate of M6 and the gate of M8 as the inverting output terminal of the second-stage latch, the gate of M7 is connected to the inverting output terminal of the first-stage pre-amplifier as the inverting input terminal of the second latch, the gate of M10 is connected to the non-inverting output terminal of the first-stage pre-amplifier as the non-inverting input terminal of the second latch, the drain of M6 is connected to the source of M7, the drain of M9 is connected to the source of M10, and the gate of M5 and the gate of M12 are connected to the clock signal Φ 22 .

3. The dynamic comparator operating at a low power supply voltage according to claim 2, wherein: The second capacitor power supply network is based on a charge pump circuit structure, including two capacitors C3 and C4 with equal capacitance and four switches S10~S13, wherein the upper plate of C3 is connected to one end of S10 and one end of S12, the lower plate of C3 is connected to one end of S11 and one end of S13, and the upper plate of C4 is connected to the other end of S13 and connected to the power supply voltage V DD , the lower plate of C4 is connected to the other end of S11 and grounded, and the other end of S10 is connected to the power supply voltage V DD The other end of S12 serves as the power rail of the second capacitor power supply network. The on-off of S10 and S11 is controlled by the clock signal Φ 12 Control, the on and off of S12 is controlled by the clock signal Φ 21 Control, S13 is turned on and off by the clock signal Φ 11 control.

4. The dynamic comparator operating at a low power supply voltage according to claim 3, wherein: The clock signal Φ 11 and Φ 12 Phase complementary and with a certain dead time, the clock signal Φ 21 and Φ 22 Phase complementary and there is a certain dead time, and Φ 11 The rising edge is earlier than Φ 22 The falling edge of 5. The dynamic comparator operating at a low power supply voltage according to claim 4, wherein: The clock generation circuit includes two inverters INV1 and INV2, four NAND gates NAND1~NAND4, four delay modules D1~D4 and four clock raising modules L1~L4, wherein the input end of INV1 is connected to the first input end of NAND1 and connected to the external clock CK, the output end of INV1 is connected to the first input end of NAND2, the output end of NAND1 is connected to the input end of D1, the output end of D1 is connected to the second input end of NAND2 and the input end of L1 and generates the clock CK 12 The output of NAND2 is connected to the input of D2, and the output of D2 is connected to the second input of NAND1, the input of L2, the input of INV2 and the first input of NAND3 to generate the clock CK 11 The output of INV2 is connected to the first input of NAND4, the output of NAND3 is connected to the input of D3, the output of D3 is connected to the second input of NAND4 and the input of L3 and generates the clock CK 22 The output of NAND4 is connected to the input of D4, and the output of D4 is connected to the second input of NAND3 and the input of L4 to generate the clock CK 21 , the output terminals of L1~L4 correspond to the output clock signal Φ 12 , Φ 11 , Φ 22 , Φ 21 .

6. The dynamic comparator operating at a low power supply voltage according to claim 5, wherein: The clock boost modules L1 to L4 all operate at a power supply voltage V DD Next, it is used to input the clock CK 12 , CK 11 , CK 22 , CK 21 The amplitude of the power supply voltage V DD Raised to 2×V DD Then they are used as clock signals Φ 12 , Φ 11 , Φ 22 , Φ 21 And output.

7. The dynamic comparator operating at a low power supply voltage according to claim 5, wherein: The clock lifting modules L1 to L4 have the same structure, including a capacitor C, three NMOS transistors Q2, Q4 and Q5, and four PMOS transistors Q1, Q3, Q6 and Q7. The gate of Q1 is connected to the gate of Q2, the source of Q4, the source of Q5 and one end of C as the input end of the clock lifting module, and the source of Q1 and the source of Q7 are connected to the power supply voltage V DD , the source of Q2 is grounded, the drain of Q1 is connected to the drain of Q2, the gate of Q3, the gate of Q4, the gate of Q5 and the gate of Q6, the drain of Q7 is connected to the source of Q6, the other end of C and the source of Q3, the drain of Q5 is connected to the drain of Q6 and the gate of Q7, and the drain of Q3 is connected to the drain of Q4 as the output end of the clock lifting module.

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