Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a semiconductor layer; forming a gate structure and a doped region in the semiconductor layer; forming a first contact layer on the surface of the gate structure; forming an insulating layer on the surfaces of the semiconductor layer, the doped region and the first contact layer; forming a first contact hole exposing the first contact layer in the insulating layer; and forming a second contact layer in the first contact hole. According to the manufacturing method, electric sparks can be prevented from being generated on the surface of the gate structure, and the service life of the semiconductor device is prolonged.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] When manufacturing semiconductor devices, the gate structure and doped regions are connected to the device's terminals via metal wiring on the surface of an insulating film. The gate structure and doped regions are connected to their respective metal wiring using a contact process, a fundamental design element of nearly all semiconductor devices.

[0003] In the contact process of connecting the doped region to the metal wiring, nickel needs to be deposited on the surface of the doped region, and a nickel-silicide contact layer is formed on the surface of the doped region through an annealing process, thereby reducing the resistivity of the doped region surface.

[0004] However, if nickel is also deposited on the surface of the gate polysilicon, it will penetrate unevenly into the gate polysilicon, causing structural inhomogeneities in the interface region. This in turn affects the consistency of electrical properties in the interface region, potentially leading to localized electric field enhancement. During the high-temperature annealing process to form nickel-silicide, these uneven electrical properties can lead to sparking, causing damage to the semiconductor device and causing reliability issues. Summary of the Invention

[0005] In view of the above problems, the purpose of this application is to provide a semiconductor device and a manufacturing method thereof, which can avoid the generation of electric sparks and improve the reliability of the semiconductor device.

[0006] According to one aspect of the present application, a method for manufacturing a semiconductor device is provided, which includes: providing a semiconductor layer; forming a gate structure and a doped region in the semiconductor layer; forming a first contact layer on the surface of the gate structure; forming an insulating layer on the surfaces of the semiconductor layer, the doped region and the first contact layer; forming a first contact hole in the insulating layer to expose the first contact layer; and forming a second contact layer in the first contact hole.

[0007] Optionally, the manufacturing method further includes: forming a second contact hole in the insulating layer to expose the doped region; and forming a third contact layer in the second contact hole, wherein the first contact hole and the second contact hole are formed simultaneously, and the third contact layer and the second contact layer are formed simultaneously.

[0008] Optionally, the manufacturing method further includes: forming a first conductive plug on the second contact layer; and forming a second conductive plug on the third contact layer.

[0009] Optionally, the first contact layer has a thickness of at least 100 angstroms.

[0010] Optionally, forming a first contact layer on the surface of the gate structure includes: depositing a first metal, the first metal covering the semiconductor layer and the dielectric layer on the surface of the doped region and the gate structure; annealing the first metal; and removing the first metal that has not reacted with the gate structure.

[0011] Optionally, the first contact layer includes a titanium-silicon compound or a tantalum-silicon compound.

[0012] Optionally, the temperature for annealing the first metal is T, 700°C≤T≤950°C.

[0013] Optionally, the method for forming the second contact layer and the third contact layer includes: depositing a second metal in the first contact hole and the second contact hole; and annealing the second metal.

[0014] Optionally, the second contact layer and the third contact layer include nickel-silicide.

[0015] Optionally, the gate structure includes a trench gate structure or a planar gate structure.

[0016] Optionally, the method for forming the trench gate type gate structure includes: forming a trench in the semiconductor layer; forming a trench gate in the trench; and forming a surface gate electrically connected to the trench gate on the surface of the semiconductor layer, wherein the first contact hole is located above the surface gate.

[0017] According to another aspect of the present application, a semiconductor device is provided, comprising: a semiconductor layer; a gate structure and a doped region located in the semiconductor layer; a first contact layer located on the surface of the gate structure; an insulating layer located on the surface of the semiconductor layer, the doped region and the first contact layer, the insulating layer having a first contact hole exposing the first contact layer; and a second contact layer located in the first contact hole.

[0018] Optionally, the insulating layer further has a second contact hole exposing the doped region, and the second contact hole has a third contact layer.

[0019] Optionally, the second contact layer and the third contact layer include nickel-silicide.

[0020] Optionally, a first conductive plug is provided on the second contact layer, and a second conductive plug is provided on the third contact layer.

[0021] Optionally, the first contact layer includes a titanium-silicon compound or a tantalum-silicon compound.

[0022] Optionally, the first contact layer has a thickness of at least 100 angstroms.

[0023] In the embodiments of the present application, when forming the second contact layer, such as nickel-silicide, the first contact layer, such as a titanium-silicon compound or a tantalum-silicon compound, isolates and protects the gate structure. During the formation of the second contact layer, the nickel element cannot directly contact or react with the gate structure, thereby preventing sparks from forming on the gate structure surface. This prevents damage to the device caused by sparks on the gate structure surface, thereby improving the reliability of the semiconductor device.

[0024] Furthermore, since the first contact layer can block the second contact layer and the gate structure, the first contact hole and the second contact hole can be formed simultaneously through a single patterning process, and metal contacts of the gate structure and the doped region can be formed simultaneously in the first contact hole and the second contact hole, which can not only ensure the reliability of the semiconductor device, but also simplify the manufacturing process of the semiconductor device and reduce production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:

[0026] Figure 1 A schematic flow chart showing a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0027] Figure 2A A schematic structural diagram showing a semiconductor layer according to some embodiments;

[0028] Figure 2B A schematic cross-sectional view of a semiconductor layer after depositing a first metal according to some embodiments is shown;

[0029] Figure 2C A schematic cross-sectional view showing a semiconductor layer after a first contact layer is formed in some embodiments;

[0030] Figure 2D A schematic cross-sectional view of a semiconductor layer after a first contact hole and a second contact hole are formed in some embodiments is shown;

[0031] Figure 2E A schematic cross-sectional view showing a semiconductor layer after forming a semiconductor device according to some embodiments;

[0032] Figure 3 Schematic structural diagrams showing semiconductor layers of other embodiments;

[0033] Figures 4A-4EA schematic cross-sectional view of a semiconductor layer after a planar gate structure is formed according to some embodiments is shown. DETAILED DESCRIPTION

[0034] Various embodiments of the present application will be described in more detail below with reference to the accompanying drawings. In each of the drawings, identical elements are represented by identical or similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale.

[0035] It should be noted that, in this article, relational terms such as first and second are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element.

[0036] In addition, in the various methods and processes of the present application, the size of the step numbers does not mean the order of execution, nor does it constitute any limitation on the implementation process of the embodiments of the present application.

[0037] Figure 1 Schematic flow chart of the method for manufacturing a semiconductor device according to an embodiment of the present application is shown. Figure 1 As shown, the manufacturing method includes:

[0038] Step S11, providing a semiconductor layer;

[0039] Step S12, forming a gate structure and a doped region in the semiconductor layer;

[0040] Step S13, forming a first contact layer on the surface of the gate structure;

[0041] Step S14, forming an insulating layer on the surfaces of the semiconductor layer, the doped region and the first contact layer;

[0042] Step S15, patterning the insulating layer to form a first contact hole exposing the first contact layer and a second contact hole exposing the doped region;

[0043] Step S16, forming a second contact layer in the first contact hole, and forming a third contact layer in the second contact hole;

[0044] Step S17 , forming a first conductive plug filling the first contact hole on the second contact layer, and forming a second conductive plug filling the second contact hole on the third contact layer.

[0045] In the embodiments of the present application, when forming the second contact layer, such as nickel-silicide, the first contact layer, such as a titanium-silicon compound or a tantalum-silicon compound, isolates and protects the gate structure. During the formation of the second contact layer, the nickel element cannot directly contact or react with the gate structure, thereby preventing sparks from forming on the gate structure surface. This prevents damage to the device caused by sparks on the gate structure surface, thereby improving the reliability of the semiconductor device.

[0046] Furthermore, since the first contact layer can block the second contact layer and the gate structure, the first contact hole and the second contact hole can be formed simultaneously through a single patterning process, and metal contacts of the gate structure and the doped region can be formed simultaneously in the first contact hole and the second contact hole, which can not only ensure the reliability of the semiconductor device, but also simplify the manufacturing process of the semiconductor device and reduce production costs.

[0047] Taking trench gate semiconductor devices as an example, Figures 2A to 2E The cross-sectional view of the semiconductor layer after some steps of the manufacturing method of some embodiments of the present application are shown in FIG. Figures 2A to 2E The manufacturing method disclosed in this application is described in detail.

[0048] The semiconductor layer provided in step S11 may be Figure 2A As shown. Figure 2A The semiconductor layer 110 is made of a material such as silicon carbide (SiC) or silicon (Si), and has a surface 10 and a bottom surface 20 opposite to each other.

[0049] exist Figure 2A In the diagram, the first, second, and third directions are three directions that intersect with each other. The first direction is the Z direction or its opposite direction, i.e., the direction between surface 10 and bottom surface 20. The second direction is the X direction or its opposite direction, and the third direction is the Y direction or its opposite direction. The plane defined by the second and third directions is parallel to surface 10 and bottom surface 20. In a preferred embodiment, the first, second, and third directions are perpendicular to each other.

[0050] In the following, along Figure 2A The cross-sectional view taken along line A-A' is Figures 2B to 2E Example of a cross-section plot in .

[0051] In step S12 , a doped region and a gate structure are formed in the semiconductor layer.

[0052] Combine Figure 2A and Figure 2BThe doped region 130 may be located in the third region III on the surface 10 and extend downward into the semiconductor layer 110. The doped region 130 may be formed by implanting ions into the third region III.

[0053] In some embodiments, the semiconductor layer 110 further includes a drift region of a first doping type. Prior to forming the doped region 130, a plurality of body regions of a second doping type may be formed, for example, by ion implantation. The doped region 130 is formed in the body region. The first doping type is one of N-type and P-type, and the second doping type is the other of N-type and P-type.

[0054] Taking an N-type metal-oxide-semiconductor field-effect transistor (MOSFET) as an example, the doped region 130 in this example is an N-type doped source region. Before forming the source region, the method for manufacturing the semiconductor device may further include forming a drift region with N-type doping in the semiconductor layer and forming a body region with P-type doping in the drift region, with the source region formed in the body region.

[0055] The step of forming a trench gate structure may include: forming a trench in a semiconductor layer; and forming a trench gate in the trench. In some embodiments, the step of forming the trench gate structure may further include: forming a surface gate on a surface of the semiconductor layer electrically connected to the trench gate. The surface gate may serve as a bus line of the trench gate structure.

[0056] For example, a trench gate structure including a trench gate and a surface gate can be formed by referring to the following steps.

[0057] refer to Figure 2A , at least one first trench I arranged along the second direction, i.e., the X direction, and extending along the third direction, i.e., the Y direction, and at least one second trench II extending along the second direction can be formed in the semiconductor layer 110, and each second trench II is connected to at least a portion of the first trench I. The first trench gate of the semiconductor device is formed in these first trenches I, and the second trench gate is formed in these second trenches. In the second direction, the doped region 130 is adjacent to the first trench I, i.e., the first trench gate; in the third direction, the doped region 130 is adjacent to the second trench II, i.e., the second trench gate. Figure 2A , two first trenches I and a second trench II connecting the two first trenches I are shown as an example. The first trench I and the second trench II can be formed, for example, by etching.

[0058] Combine Figure 2BAfter the trenches are formed, a dielectric layer 140 is formed on the surface 10 of the semiconductor layer 110, the surface of the doped region 130, and the walls and bottom of the first trench I and the second trench II. In other words, the projection of the dielectric layer 140 on the surface 10 covers the entire surface 10 of the semiconductor layer 110.

[0059] After forming the dielectric layer 140, the first trench I and the second trench II are filled with conductive material. The portion of the conductive material in the first trench I, i.e. Figure 2B The portion within the dotted line frame forms the gate conductor layer 152 of the first trench gate 150, and the portion of the dielectric layer 140 in the first trench I forms the gate dielectric layer 151 of the first trench gate 150. The portion of the conductive material layer in the second trench II forms the gate conductor layer of the second trench gate, and the portion of the dielectric layer 140 in the second trench II forms the gate dielectric layer of the second trench gate. Because the second trench II is connected to at least a portion of the first trench I, the conductive material filling the first trench I and second trench II is also connected, thus achieving electrical connection between the second trench gate and the corresponding first trench gate 150.

[0060] Afterwards, the conductive material layer is patterned to remove the conductive material from the surface 10 in areas other than the first region IV. The conductive material remaining in the first region IV forms the gate conductor layer 162 of the surface gate 160. The first region IV is the portion outside the third region III and the first trench I, and overlaps with the second trench II in the second region V. The gate conductor layer 162 of the surface gate 160 and the gate conductor layer of the second trench gate are connected to the second region V. Figure 2B As shown in the dotted box, in the first region IV, the dielectric layer 140 except the second region V forms the gate dielectric layer 161 of the surface gate 160 .

[0061] The dielectric layer 140 may be made of silicon oxide, and thus the gate dielectric layer 151 of the first trench gate 150, the gate dielectric layer of the second trench gate, and the gate dielectric layer 161 of the surface gate 160 are all made of silicon oxide. The conductive material may be polysilicon, and thus the gate conductor layer 152 of the first trench gate 150, the gate conductor layer of the second trench gate, and the gate conductor layer 162 of the surface gate 160 are all made of polysilicon.

[0062] Step S13 , forming a first contact layer on the surface of the gate structure, may include: depositing a first metal; annealing the first metal; and removing unreacted first metal.

[0063] refer to Figure 2B The deposited first metal 170 covers the gate structure and the dielectric layer 140 on the surface of the semiconductor layer 110 and the doped region 130 , wherein the gate structure may include the first trench gate 150 , the second trench gate and the surface gate 160 as described above.

[0064] The first metal 170 can be made of a metal material that is highly compatible with the aforementioned conductive materials. For example, when the conductive material is polysilicon, titanium (Ti) or tantalum (Ta) can be used for the first metal 170. This ensures good interface properties between the first metal 170 and the gate structure, forming a uniform interface region with consistent electrical properties and a uniform structure.

[0065] In a preferred embodiment, the thickness of the first metal 170 needs to ensure that the thickness of the subsequently formed first contact layer is at least 100 angstroms (Å). By increasing the thickness of the first metal 170 , the protection capability of the first metal 170 on the gate structure can be improved.

[0066] After depositing the first metal 170, an annealing process is performed. This annealing process allows the first metal 170 to form a stable compound at the interface between the gate structure and the semiconductor layer 110. Due to the barrier provided by the dielectric layer 140, regions outside the gate structure in the semiconductor layer 110 do not react with the first metal 170, and thus, no corresponding compound is formed.

[0067] The annealing temperature may be selected according to the material of the first metal 170 . For example, for the first metal 170 made of Ti or Ta, the annealing temperature is in the range of 700° C. to 950° C.

[0068] refer to Figure 2C After annealing, the first metal 170 that has not reacted with the gate structure can be removed by a removal process. The removal process of the first metal 170 includes, for example, wet chemical etching. The compound generated by the reaction of the first metal 170 with the gate structure and retained forms a first contact layer on the surface of the gate structure. The first contact layer may, for example, include a first contact layer 171a located on the surface of the first trench gate 150, a first contact layer located on the surface of the second trench gate, and a first contact layer 171b located on the surface of the surface gate 160. When the first metal 170 is Ti or Ta, the first contact layer includes a titanium-silicon compound or a tantalum-silicon compound. In the subsequent manufacturing process, the first contact layer plays a protective role for the gate structure.

[0069] The insulating layer 180 formed in step S14 covers the surface 10 of the semiconductor layer 110, the first contact layer, and the surface of the doped region 130. The insulating layer 180 serves as an inter-layer dielectric (ILD) layer, and can be made of, for example, an oxide material.

[0070] refer to Figure 2D In step S15, a first contact hole VII is formed in the insulating layer 180 to expose the first contact layer. It should be noted that in the gate structure having the surface gate 160, as shown in FIG. Figure 2DAs shown, the first contact hole VII is located above the surface gate 160. That is, the first contact hole VII exposes the first contact layer 171b covering the surface gate 160.

[0071] It should be noted that, in a preferred embodiment, the first contact hole VII is provided in the overlapping region of the surface gate 160 and the second trench gate, that is, Figure 2A Therefore, in a preferred embodiment, Figures 2B to 2E The cross section is not taken along a straight line extending in the first direction, but is taken along the line AA' shown in FIG. 2 , which has a bend at the edge of the first region IV.

[0072] Furthermore, in some embodiments, the first contact hole VII and the second contact hole VI exposing the doped region 130 can be formed simultaneously by a single patterning process. Figure 2D The first contact hole VII and the second contact hole VI can be formed simultaneously by the following steps: forming an initial photoresist layer on the surface of the insulating layer 180; opening the initial photoresist layer above the surface gate 160 and the doped region 130 through exposure and development to obtain a patterned photoresist layer 200; etching the insulating layer 180 using the patterned photoresist layer 200 as a mask to form the second contact hole VI exposing the doped region 130 and the first contact hole VII exposing the first contact layer 171b; and removing the patterned photoresist layer 200.

[0073] Combine Figure 2D and Figure 2E Step S16, forming a second contact layer 173 in the first contact hole VII, may include: depositing a second metal in the first contact hole VII and annealing the second metal. The second metal deposited in the first contact hole VII reacts with the silicon element in the first contact layer 171b to form the second contact layer 173. During the formation of the second contact layer 173, the first contact layer 171b protects the gate conductor layer 162 of the planar gate 160, preventing contact or reaction between the gate conductor layer 162 and the second metal. Protected by the first contact layer 171b, sparks are prevented from being generated on the surface of the gate conductor layer 162, thereby preventing damage to the gate structure and improving the reliability of the semiconductor device. Furthermore, the first contact layer 171b forms an ohmic contact on the surface of the gate structure, thereby reducing the contact resistance on the gate structure surface. The subsequent formation of the second contact layer 173 can further reduce the contact resistance on the gate structure surface.

[0074] In the aforementioned embodiment of simultaneously forming the first contact hole VII and the second contact hole VI, the second metal can also be deposited in the second contact hole VI during the formation of the second contact layer 173. The second metal deposited in the second contact hole VI reacts with the silicon in the doped region 130, thereby forming the third contact layer 172 in the second contact hole VI. The third contact layer 172 can reduce the contact resistance on the surface of the doped region. In other words, the second contact layer 173 and the third contact layer 172 can be formed simultaneously by depositing the second metal.

[0075] Further references Figure 2E The second metal may be made of nickel, for example, and the second contact layer 173 and the third contact layer 172 may be made of nickel-silicon compounds. When nickel reacts with the doped region 130, it consumes less silicon, which is beneficial for improving the electrical performance of the semiconductor device.

[0076] During the formation of second contact layer 173 and third contact layer 172, the second metal penetrates downward into doped region 130, resulting in the lower surface of third contact layer 172 being lower than surface 10 of semiconductor layer 110. In first contact hole VII, the presence of first contact layer 171b isolates gate conductor layer 162 from the second metal, ensuring that the surface of gate conductor layer 162 maintains a uniform structure and consistent electrical properties.

[0077] Further references Figure 2E After forming the second contact layer 173 and the third contact layer 172, the manufacturing steps may further include step S17 of forming a first conductive plug on the second contact layer 173 to fill the first contact hole VII. The first conductive plug electrically connects the surface gate 160 to the corresponding metal wiring to form a first connection structure 192 to provide electrical signals to the surface gate 160 when the semiconductor device is operating. Since the surface gate 160 is electrically connected to the corresponding first trench gate 150 via the second trench gate, these electrical signals are also provided to the second trench gate and the first trench gate 150.

[0078] In step S17, a second conductive plug filling the second contact hole VI is formed on the third contact layer 172, and the doped region 130 is electrically connected to the corresponding metal wiring through the second conductive plug to form a second connection structure 191 to provide an electrical signal to the doped region 130 when the semiconductor device is working.

[0079] Furthermore, in some embodiments, Figure 2E As shown, a third connection structure 120 is also formed on the bottom surface 20. Taking MOSFET as an example, the second connection structure 191 is a source metal structure, the first connection structure 192 is a gate metal structure, and the third connection structure 120 is a drain metal structure.

[0080] It should be noted that the above Figures 2A to 2EThe embodiment of FIG. 1 is merely an exemplary embodiment of a method for electrically connecting the surface gate and the trench gate. It should be understood that the manufacturing method of the present application is not limited thereto, and the trench gate and the surface gate may also be electrically connected in other connection methods. For example, Figure 3 Schematic structural diagrams of the semiconductor layer 210 according to some other embodiments of the present application are shown.

[0081] like Figure 3 In the embodiment shown, the relative positional relationship between the surface 30, the bottom surface 40 and the first direction, the second direction and the third direction of the semiconductor layer 210 is as follows: Figure 2A The semiconductor layer 110 is shown in FIG. Similarly, a plurality of first trenches Q2 are formed in the semiconductor layer 210, arranged along the second direction and extending along the third direction. Trench gates of the semiconductor device are formed in these first trenches Q2. A doped region is formed in the first region Q1. In the second direction, the doped region is adjacent to the first trenches Q2, and therefore adjacent to the trench gates.

[0082] In which, on the semiconductor layer 210, by patterning the conductive material, a surface gate is formed in the second region Q3 of the surface 30. The second region Q3 is the region outside the first region Q1 and overlaps with the trench gate, that is, the first trench Q2, in the third region Q4. In some embodiments, reference Figure 3 The second region Q3 is adjacent to the first region Q1 in a third direction, i.e., the Y direction or the opposite direction of the Y direction. The surface gate can be formed by patterning the conductive material after filling the dielectric layer with the conductive material. The conductive material on the dielectric layer except for the second region Q3 is removed. The conductive material in the second region Q3 forms the gate conductor layer of the surface gate, and the conductive material in the first trench Q2 forms the gate conductor layer of the trench gate. The gate conductor layer of the surface gate is connected to the gate conductor layer of the trench gate in the third region Q4, thereby achieving electrical connection between the surface gate and the trench gate. The surface gate can be used as a busline for the trench gate.

[0083] Afterwards, the semiconductor device can be manufactured by referring to the subsequent steps in the above embodiment. Figure 3 As shown in the semiconductor layer 210, since the surface gate is formed in a region outside the doped region, the first contact hole and the second contact hole should be located in different planes in the third direction. Figure 3 The second contact hole is located in the cross section taken along line BB' and exposes the doped region. The first contact hole is located in the cross section taken along line CC' and exposes the fourth region Q5 on the surface gate, and preferably, the fourth region Q5 does not overlap with the trench gate.

[0084] In the above Figures 2A to 3In the embodiments, the gate structure formed is a trench gate structure as an example. However, the manufacturing method provided in this application can also be applied to the manufacture of a planar gate semiconductor device, that is, the gate structure formed in step S12 can also be a planar gate structure. Specifically, Figures 4A-4E A schematic cross-sectional view of a planar gate semiconductor device prepared by a semiconductor manufacturing method according to an embodiment of the present application is shown. Figure 1 and Figures 4A-4E , the fabrication of a planar gate semiconductor device may include:

[0085] Step S11: providing a semiconductor layer.

[0086] The semiconductor layer 310 provided in this step is made of, for example, silicon carbide (SiC), silicon (Si), etc. Figure 4A The relative positional relationship between the surface 50, bottom surface 60 and the first, second and third directions of the semiconductor layer 310 is Figure 2A The semiconductor layer 110 is shown to be uniform.

[0087] In step S12 , a doped region 330 and a gate structure 340 are formed in the semiconductor layer.

[0088] The doped region 330 may be formed by a process such as ion implantation, and extends from the surface 50 of the semiconductor layer 310 into the semiconductor layer 310 .

[0089] In some embodiments, the semiconductor layer 310 further includes a drift region of a first doping type. Prior to forming the doped region 330, a plurality of body regions of a second doping type may be formed, for example, by ion implantation. The doped region 330 is formed in the body region. The first doping type is one of N-type and P-type, and the second doping type is the other of N-type and P-type.

[0090] The gate structure 340 is a planar gate structure located on the surface of the semiconductor layer 310 , and includes a stacked gate conductor layer 342 and a gate dielectric layer 341 .

[0091] The planar gate structure 340 can be formed by referring to any related technology. For example, in some embodiments, the steps of forming the planar gate structure may include: forming a dielectric layer 400 on the surface 50 of the semiconductor layer 310; depositing a conductive material on the dielectric layer 400; and patterning the conductive material to form a gate conductor layer 342 of the planar gate. Figure 4A The dielectric layer 400 in the dotted box forms the gate dielectric layer 341 of the planar gate.

[0092] In step S13 , a first contact layer 351 is formed on the surface of the gate structure 340 .

[0093] In step S13, the first contact layer 351 may be formed by depositing a first metal. Figure 4B The deposited first metal covers the gate conductor layer 342 and the portion of the dielectric layer 400 other than the gate conductor layer 342. That is, the projection of the first metal on the surface 50 overlaps with the projection of the dielectric layer 400 on the surface 50. Thereafter, the first metal is annealed, and the first metal in contact with the gate conductor layer 342 reacts with the gate conductor layer 342, thereby forming a stable compound on the surface of the gate conductor layer 342. After annealing, the first metal that has not reacted with the gate conductor layer 342 is removed, and the compound formed by the reaction between the first metal and the gate conductor layer 342 is retained to form the first contact layer 351. Due to the barrier of the dielectric layer 400, the first metal that has not contacted the gate conductor layer 342 will not react with the silicon in the substrate, and the unreacted first metal is removed after annealing.

[0094] The first metal 170 is made of, for example, Ti or Ta. Accordingly, the first contact layer 351 is formed of titanium silicide or tantalum silicide. The annealing temperature can be selected based on the material of the first metal 170. For example, for a first metal 170 made of Ti or Ta, the annealing temperature is within a range of 700°C to 950°C.

[0095] In a preferred embodiment, the thickness of the first contact layer 351 is also at least 100 angstroms.

[0096] In step S14, an insulating layer 360 is formed on the surfaces of the semiconductor layer 310, the doped region 330, and the first contact layer 351. Specifically, in the embodiment of the present application, the insulating layer 360 covers the surfaces of the dielectric layer 400 and the first contact layer 350. In other words, the projection of the insulating layer 360 on the surface 50 of the semiconductor layer 310 covers the entire surface 50. The insulating layer 360 serves as an interlayer dielectric (ILD) and can be made of, for example, an oxide material.

[0097] refer to Figure 4C In step S15, the insulating layer 360 is patterned to form a first contact hole P1 exposing the first contact layer 350 and a second contact hole P2 exposing the doped region 330. In a preferred embodiment, the first contact hole P1 and the second contact hole P2 can be formed simultaneously through a single patterning process. Similar to the embodiment in which the gate structure is a trench gate type, the patterning of the insulating layer 360 can also be achieved through a photolithography process, which will not be further described here.

[0098] refer to Figure 4D In step S16, a second contact layer 352 is formed in the first contact hole P1, and a third contact layer 370 is formed in the second contact hole P2.

[0099] The formation of the second contact layer 352 may include depositing a second metal in the first contact hole P1 and annealing the second metal. The second metal deposited in the first contact hole P1 reacts with silicon in the first contact layer 351 to form the second contact layer 352.

[0100] In some embodiments, the second metal is nickel, for example, and the second contact layer 352 is nickel-silicide. During the deposition of the second nickel metal, the first contact layer 351 protects the gate conductor layer 342 from direct contact with the second nickel metal. Therefore, during the deposition of the second nickel metal, no sparks are generated on the surface of the gate conductor layer 342, thereby preventing damage to the gate structure 340 and improving the life of the semiconductor device.

[0101] In the embodiment described above where the first contact hole P1 and the second contact hole P2 are formed simultaneously, the second metal is also deposited in the second contact hole P2 and reacts with the silicon in the doped region to form a third contact layer 370. The third contact layer 370 is made of the same material as the second contact layer 352. The third contact layer 370 can reduce the contact resistance on the surface of the doped region 330.

[0102] Forming the first contact hole P1 and the second contact hole P2 simultaneously through one patterning process, and then depositing the second metal to simultaneously form the second contact layer 352 and the third contact layer 370 can simplify the manufacturing process of the semiconductor device and help save manufacturing costs.

[0103] Likewise, since the second metal nickel penetrates into the doped region 330 during the process of forming the third contact layer 370 , the contact surface between the third contact layer 370 and the doped region 330 is lower than the surface 50 of the semiconductor layer 310 .

[0104] refer to Figure 4E In step S17, a first conductive plug is formed on the second contact layer 352 to fill the first contact hole P1, and a second conductive plug is formed on the third contact layer 370 to fill the second contact hole P2. The first conductive plug electrically connects the gate structure 340 to the corresponding metal wiring to form a first connection structure 390, thereby providing an electrical signal to the gate structure 340 during operation of the semiconductor device. The second conductive plug electrically connects the doped region 330 to the corresponding metal wiring to form a second connection structure 380, thereby providing an electrical signal to the doped region 330 during operation of the semiconductor device.

[0105] Furthermore, in some embodiments, Figure 4E As shown, a third connection structure 320 is also formed on the bottom surface 60. Taking MOSFET as an example, the second connection structure 380 is a source metal structure, the first connection structure 390 is a gate metal structure, and the third connection structure 120 is a drain metal structure.

[0106] The present application also provides a semiconductor device. The semiconductor device includes: a semiconductor layer; a gate structure and a doped region located within the semiconductor layer; a first contact layer located on a surface of the gate structure; an insulating layer located on surfaces of the semiconductor layer, the doped region, and the first contact layer, the insulating layer having a first contact hole therein exposing the first contact layer; and a second contact layer located within the first contact hole.

[0107] The first contact layer may include a titanium-silicon compound or a tantalum-silicon compound. The first contact layer may have a thickness of at least 100 angstroms. The second contact layer may include a nickel-silicon compound.

[0108] Furthermore, the insulating layer includes a second contact hole exposing the doped region and a third contact layer located within the second contact hole. The third contact layer can reduce the contact resistance on the surface of the doped region, thereby improving the performance of the semiconductor device. The third contact layer can be made of the same material as the second contact layer.

[0109] Furthermore, the semiconductor device may further include a first conductive plug located in the first contact hole and a second conductive plug located in the second contact hole, so as to provide an electrical signal to the gate structure through the first conductive plug and to the doped region through the second conductive plug.

[0110] The semiconductor device may be a trench gate semiconductor device, and its cross-sectional view is as shown in FIG. Figure 2E The semiconductor device may also be a planar gate type semiconductor device, the cross-sectional view of which is shown in FIG. Figure 4E In some embodiments, the semiconductor device can be manufactured according to the manufacturing method described above.

[0111] It should be noted that in the above Figures 2A to 4E In the embodiment, the formation of each component is also used as an example and should not limit the manufacturing method and semiconductor device of the present application.

[0112] The embodiments of the present application are as described above, and these embodiments do not describe all details in detail, nor do they limit the present application to specific embodiments. Obviously, based on the above description, many modifications and variations can be made. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The scope of protection of the present application shall be based on the scope defined by the claims of the present application.

Claims

1. A method for manufacturing a semiconductor device, wherein: include: providing a semiconductor layer; forming a gate structure and a doped region in the semiconductor layer; forming a first contact layer on the surface of the gate structure; forming an insulating layer on surfaces of the semiconductor layer, the doped region, and the first contact layer; forming a first contact hole in the insulating layer exposing the first contact layer; as well as A second contact layer is formed in the first contact hole.

2. The manufacturing method according to claim 1, wherein The manufacturing method further comprises: forming a second contact hole in the insulating layer exposing the doped region; and forming a third contact layer in the second contact hole, The first contact hole and the second contact hole are formed simultaneously, and the third contact layer and the second contact layer are formed simultaneously.

3. The manufacturing method according to claim 2, wherein: The manufacturing method further comprises: forming a first conductive plug on the second contact layer; and A second conductive plug is formed on the third contact layer.

4. The manufacturing method according to any one of claims 1 to 3, wherein: The thickness of the first contact layer is at least 100 angstroms.

5. The manufacturing method according to any one of claims 1 to 3, wherein: The forming of a first contact layer on the surface of the gate structure comprises: Depositing a first metal, wherein the first metal covers the semiconductor layer, the dielectric layer on the surface of the doped region, and the gate structure; annealing the first metal; and The first metal that has not reacted with the gate structure is removed.

6. The manufacturing method according to claim 5, wherein: The first contact layer includes a titanium-silicon compound or a tantalum-silicon compound.

7. The manufacturing method according to claim 6, wherein: The temperature for annealing the first metal is T, 700°C≤T≤950°C.

8. The manufacturing method according to claim 2, wherein: The method for forming the second contact layer and the third contact layer includes: depositing a second metal in the first contact hole and the second contact hole; and The second metal is annealed.

9. The manufacturing method according to claim 8, wherein: The second contact layer and the third contact layer include nickel-silicide.

10. The manufacturing method according to any one of claims 1 to 3, wherein: The gate structure includes a trench gate structure or a planar gate structure.

11. The manufacturing method according to claim 10, wherein: The method of forming the trench gate structure includes: forming a trench in the semiconductor layer; forming a trench gate in the trench; and forming a surface gate electrically connected to the trench gate on the surface of the semiconductor layer; Wherein, the first contact hole is located above the surface gate.

12. A semiconductor device, wherein: include: semiconductor layer; a gate structure and a doped region located in the semiconductor layer; a first contact layer located on a surface of the gate structure; an insulating layer located on surfaces of the semiconductor layer, the doped region, and the first contact layer, wherein the insulating layer has a first contact hole exposing the first contact layer; as well as A second contact layer is located in the first contact hole.

13. The semiconductor device according to claim 12, wherein The insulating layer further has a second contact hole exposing the doped region, and the second contact hole has a third contact layer.

14. The semiconductor device according to claim 13, wherein The second contact layer and the third contact layer include nickel-silicide.

15. The semiconductor device according to claim 13, wherein The second contact layer has a first conductive plug thereon, and the third contact layer has a second conductive plug thereon.

16. The semiconductor device according to any one of claims 12 to 15, wherein: The first contact layer includes a titanium-silicon compound or a tantalum-silicon compound.

17. The semiconductor device according to any one of claims 12 to 15, wherein: The thickness of the first contact layer is at least 100 angstroms.

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