Double-channel GaN high-electron-mobility transistor with MIS grid and preparation method of double-channel GaN high-electron-mobility transistor

Abstract

The invention discloses a double-channel GaN high-electron-mobility transistor with an MIS grid and a preparation method thereof. The double-channel GaN high-electron-mobility transistor comprises a substrate, and a buffer layer, a first p-type gallium nitride layer, a first heterostructure layer, a second heterostructure layer, a u-gallium nitride layer and a second p-type gallium nitride layer which are sequentially stacked on one side of the substrate, the second heterostructure layer comprises a second channel layer and a second barrier layer which are stacked; the grid electrode of the transistor comprises a first grid electrode, a second grid electrode and a third grid electrode. The first grid electrode is electrically connected with the first p-type gallium nitride layer; the second gate comprises a gate dielectric layer and gate metal which are stacked, and at least part of the gate dielectric layer is electrically connected with the second channel layer; the third grid electrode is electrically connected with the second p-type gallium nitride layer. According to the invention, three different grid electrodes are cooperated to control a plurality of channels, so that the enhancement mode of the transistor device is realized, and the reliability and the safety of the device are improved at the same time.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a double-channel GaN high electron mobility transistor with an MIS gate and a preparation method thereof. Background Art

[0002] Compared to the current mainstream Si material devices, GaN material devices have shown great advantages in the field of power electronic devices due to their superior material properties and heterostructure with AlGaN. In the AlGaN / GaN heterostructure, due to spontaneous polarization and piezoelectric polarization, a two-dimensional electron gas with high concentration and high room temperature mobility can be spontaneously generated inside the device. As a wide bandgap semiconductor, the bandgap width of GaN material of 3.39eV enables GaN devices to theoretically operate at high temperatures of 1000℃. The high thermal conductivity also ensures the stability of the device in high temperature environments. GaN material devices have a critical breakdown field strength ten times that of Si, allowing GaN devices to operate at higher voltages. Their excellent breakdown characteristics make the on-resistance of GaN devices much lower than that of Si devices at the same rated operating voltage. At the same time, the mobility of the 2DEG generated in the AlGaN / GaN heterostructure has been improved, and the saturation current has increased. However, the actual application parameters of GaN heterojunction devices are still far from reaching the theoretical limit. Under high-voltage environments, current GaN devices find it difficult to achieve ultra-high voltage devices above 3000V.

[0003] The voltage rating of GaN power devices is not limited by their breakdown voltage, but rather by the dynamic resistance degradation experienced after high-voltage operation. Dynamic resistance degradation stems from the extremely slow response of deep energy-level traps on the device surface. Once filled with electrons, they take a long time to recover. These negative surface charges repel electrons in the channel, causing dynamic resistance degradation. Currently, a common method for increasing device voltage resistance is to add field plates to GaN devices. This disperses the peak electric field across different regions, reducing the trap density and thus improving the device's ability to withstand higher voltages. To achieve even higher voltage resistance, multiple field plates can be incorporated into a single device structure. After nearly 20 years of research, the industry generally adopts a structure of three to four field plates, which can keep dynamic resistance degradation within acceptable levels for 650V GaN power devices. For higher voltage devices, the number of required field plates increases proportionally. Each additional field plate requires an additional lithography pass. Achieving ultra-high voltage GaN power devices exceeding 3000V requires dozens of additional lithography passes, significantly increasing process cost and operational complexity, limiting scalable manufacturing.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to ordinary technicians in this field. Summary of the Invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a dual-channel GaN high electron mobility transistor with MIS gate and a method for manufacturing the same. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] In a first aspect, the present invention provides a dual-channel GaN high electron mobility transistor with an MIS gate, comprising a substrate, and a buffer layer, a first p-type gallium nitride layer, a first heterostructure layer, a second heterostructure layer, a u-gallium nitride layer, and a second p-type gallium nitride layer stacked in sequence on one side of the substrate; an orthographic projection of the first p-type gallium nitride layer on the substrate is located within the orthographic projection of the first heterostructure layer on the substrate;

[0007] The second heterostructure layer includes a second channel layer and a second barrier layer stacked on the first heterostructure layer;

[0008] The GaN high electron mobility transistor also includes a gate, which includes a first gate, a second gate, and a third gate; the first gate is electrically connected to the first p-type gallium nitride layer; the second gate includes a stacked gate dielectric layer and a gate metal, the orthographic projection of the gate metal on the substrate is located within the orthographic projection of the gate dielectric layer on the substrate, and at least a portion of the gate dielectric layer is electrically connected to the second channel layer; and the third gate is electrically connected to the second p-type gallium nitride layer.

[0009] In one embodiment of the present invention, the gate dielectric layer is made of HfO 2 or Al 2 O 3 .

[0010] In one embodiment of the present invention, the first heterostructure layer includes a first channel layer and a first barrier layer stacked on the first p-type gallium nitride layer;

[0011] The first channel layer and the second channel layer are both made of GaN, and the first barrier layer and the second barrier layer are both made of AlInN; or, the first channel layer and the second channel layer are both made of GaN, the first barrier layer is made of AlGaN, and the second barrier layer is made of AlN.

[0012] In one embodiment of the present invention, at least two of the first gate, the second gate and the third gate are electrically connected.

[0013] In one embodiment of the present invention, it also includes a source and a drain; the source is in ohmic contact with the first channel layer, the first barrier layer, the second channel layer or the second barrier layer; the drain is in ohmic contact with the first channel layer, the first barrier layer, the second channel layer or the second barrier layer.

[0014] In one embodiment of the present invention, the orthographic projection of the gate dielectric layer on the base substrate coincides with the orthographic projection of the buffer layer on the base substrate, and does not coincide with the orthographic projections of the first gate, the third gate, the source, and the drain on the base substrate.

[0015] In a second aspect, the present invention provides a method for preparing the above-mentioned double-channel GaN high electron mobility transistor with MIS gate, the method comprising the following steps:

[0016] S10, obtaining a base substrate, and forming a buffer layer on one side of the base substrate;

[0017] S20, forming a gallium nitride layer on an upper side of the buffer layer, and doping a portion of the gallium nitride layer by ion implantation to form a first p-type gallium nitride layer, wherein an orthographic projection of the first p-type gallium nitride layer on the base substrate at least partially overlaps with an orthographic projection of a predetermined gate region on the base substrate;

[0018] S30, forming a first heterostructure layer, a second channel layer, and a second barrier layer in sequence on the first p-type gallium nitride layer;

[0019] S40: sequentially forming a u-gallium nitride layer and a second p-type gallium nitride layer on the upper side of the second barrier layer, and etching the u-gallium nitride layer and the second p-type gallium nitride layer to expose a predetermined source region, a predetermined drain region, and a portion of a predetermined gate region; the second p-type gallium nitride layer at least partially covers the u-gallium nitride layer, and an orthographic projection of the second p-type gallium nitride layer on the substrate at least partially overlaps with an orthographic projection of the predetermined gate region on the substrate;

[0020] At the same time, etching a MIS gate groove in the preset gate region, wherein the MIS gate groove exposes a portion of the second channel layer;

[0021] S50, after the etching of step S40 is completed, a gate dielectric layer is formed on the side away from the substrate; the gate dielectric layer is etched to expose the preset source region, the preset drain region, the preset first gate region and the preset third gate region;

[0022] S60, forming a source electrode and a drain electrode in a preset source region and a preset drain region, respectively, wherein the preset source region and the preset drain region are located on both sides of the u-gallium nitride layer;

[0023] S70, forming a passivation layer, wherein the passivation layer completely covers the source electrode, the drain electrode, the gate dielectric layer, the u-type gallium nitride layer, and the second p-type gallium nitride layer; etching the passivation layer to form a gate groove;

[0024] Etching a first groove, a second groove, and a third groove at the bottom of the gate groove; the first groove exposes at least a portion of the first p-type gallium nitride layer; the second groove exposes the gate dielectric layer corresponding to the MIS gate groove; and the third groove exposes at least a portion of the second p-type gallium nitride layer;

[0025] Gate metals are deposited in the first groove, the second groove, the third groove, and the gate groove respectively to form a gate, thereby obtaining a double-channel GaN high electron mobility transistor with an MIS gate.

[0026] In one embodiment of the present invention, in step S60, forming the source and drain includes the following steps:

[0027] S601, forming a first photoresist mask on the upper side of the gate dielectric layer, wherein the first photoresist mask exposes the second barrier layer corresponding to the preset source region and the preset drain region;

[0028] S602, forming a Ti / Al / Ni / Au source / drain metal stack in the predetermined source region and the predetermined drain region using an electron beam evaporation process; wherein the thickness of Ti is 15-25 nm, the thickness of Al is 110-130 nm, the thickness of Ni is 40-50 nm, and the thickness of Au is 50-60 nm;

[0029] S603 , after the electron beam evaporation is completed, the source and drain metal stack is subjected to rapid thermal annealing for 20 to 35 seconds in a nitrogen atmosphere at 860 to 875° C. to obtain the source and drain electrodes.

[0030] In one embodiment of the present invention, in step S70, forming the gate includes the following steps:

[0031] S701, forming a second photoresist mask on the upper side of the passivation layer, and etching using inductively coupled plasma to form a gate groove;

[0032] S702, forming a third photoresist mask in the gate groove, and performing etching using inductively coupled plasma to form a first groove, a second groove, and a third groove;

[0033] S703 , using an electron beam evaporation process to form Ni / Au gate metal in the first groove, the second groove, the third groove and the gate groove, wherein the thickness of Ni is 15-25 nm and the thickness of Au is 180-220 nm; obtaining a gate.

[0034] In one embodiment of the present invention, the material of the substrate is sapphire; the material of the buffer layer is GaN; the material of the passivation layer is SiN;

[0035] The first heterostructure layer includes a first channel layer and a first barrier layer that are stacked; the materials of the first channel layer and the second channel layer are both GaN, and the materials of the first barrier layer and the second barrier layer are both AlInN; or, the materials of the first channel layer and the second channel layer are both GaN, the material of the first barrier layer is AlGaN, and the material of the second barrier layer is AlN.

[0036] Compared with the prior art, the present invention has the following beneficial effects:

[0037] 1. The dual-channel GaN high electron mobility transistor device with MIS gate provided by the present invention uses a first gate, a second gate, and a third gate to control the channel in the transistor respectively. The first gate is electrically connected to the first p-type gallium nitride layer, and the carrier concentration of the channel between the first heterostructure layer is regulated by the first gate. The second gate uses the MIS gate to regulate the channel carrier concentration at the interface of the second heterostructure layer. The third gate is electrically connected to the second p-type gallium nitride layer, and the concentration of 2DHG at the interface between the u-gallium nitride layer and the second barrier layer is controlled by the second p-type gallium nitride layer. By depleting carriers in each channel respectively through the three gates, the transistor device is enhanced, thereby reducing the circuit complexity and cost of the transistor, while improving the safety and system reliability of the circuit in high-power switching applications.

[0038] 2. In the preparation method of the transistor device provided by the present invention, the first gate and the third gate use p-GaN to control the carrier depletion in the channel, and simple ion implantation can be used to achieve gate control and transistor enhancement effect, and the preparation process is simple. The second gate adopts the MIS gate structure, which improves the gate reliability of the device. The MIS gate structure uses high dielectric constant materials to significantly reduce leakage current and gate tunneling effect, improve the stability of the device under high temperature or high electric field, reduce interface state charge accumulation, and reduce the risk of device performance degradation. Using different types of gates to coordinately control each channel can not only enable the transistor to achieve enhancement mode, but also improve the reliability of the gate, while simplifying the preparation process, which is conducive to the large-scale production of transistor devices.

[0039] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 1 is a cross-sectional schematic diagram of a double-channel GaN high electron mobility transistor with an MIS gate provided by an embodiment of the present invention;

[0041] Figure 2 is another cross-sectional schematic diagram of a double-channel GaN high electron mobility transistor with an MIS gate provided by an embodiment of the present invention;

[0042] Figure 3 1 is a top view of a double-channel GaN high electron mobility transistor with an MIS gate provided by an embodiment of the present invention (the passivation layer and the gate dielectric layer are not shown);

[0043] Figure 4 yes Figure 3 Schematic diagram of the cross section along AA;

[0044] Figure 5 yes Figure 3 Schematic cross-section along the middle BB;

[0045] Figure 6 4 is a cross-sectional schematic diagram corresponding to S10 in a method for preparing a dual-channel GaN high electron mobility transistor with a MIS gate provided by an embodiment of the present invention;

[0046] Figure 7 4 is a cross-sectional schematic diagram corresponding to S40 in a method for preparing a dual-channel GaN high electron mobility transistor with a MIS gate provided by an embodiment of the present invention;

[0047] Figure 8 4 is a cross-sectional schematic diagram corresponding to S50 in a method for preparing a dual-channel GaN high electron mobility transistor with a MIS gate provided by an embodiment of the present invention;

[0048] Figure 9 4 is a cross-sectional schematic diagram corresponding to S60 in a method for preparing a dual-channel GaN high electron mobility transistor with a MIS gate provided by an embodiment of the present invention;

[0049] Figure 10 It is a cross-sectional schematic diagram corresponding to S70 in a method for preparing a dual-channel GaN high electron mobility transistor with a MIS gate provided by an embodiment of the present invention.

[0050] Description of reference numerals:

[0051] SBT-substrate; Buf-buffer layer; PN1-first p-type gallium nitride layer; CL1-first channel layer; BL1-first barrier layer; CL2-second channel layer; BL2-second barrier layer; UN-u-gallium nitride layer; PN2-second p-type gallium nitride layer; SE-source; DE-drain; GE-gate; GE1-first gate; GE2-second gate; GM-gate metal; GIL-gate dielectric layer; GE3-third gate; PAL-passivation layer; 1-MIS gate groove; 2-gate groove; 21-first groove; 22-second groove; 23-third groove. DETAILED DESCRIPTION

[0052] In order to further illustrate the technical means and effects adopted by the present invention to achieve the predetermined purpose of the invention, the following is a detailed description of a dual-channel GaN high electron mobility transistor with an MIS gate and a preparation method thereof proposed in accordance with the present invention, in combination with the accompanying drawings and specific embodiments.

[0053] The aforementioned and other technical contents, features, and effects of the present invention are clearly presented in the following detailed description of the specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a deeper and more specific understanding of the technical means and effects adopted by the present invention to achieve the intended purpose can be obtained. However, the accompanying drawings are provided for reference and illustration purposes only and are not intended to limit the technical solutions of the present invention.

[0054] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include," "comprise," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements, but also other elements not explicitly listed.

[0055] The term "u-GaN" refers to undoped intrinsic GaN.

[0056] The terms "upper" and "lower" and other designations of orientation or positional relationships are based on the orientation or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific manner. Therefore, they should not be construed as limitations on the present invention. In the present invention, the side away from the substrate is "upper," and the side closer to the substrate is "lower."

[0057] The embodiment of the present invention provides a double-channel GaN high electron mobility transistor with MIS gate, such as Figure 1 and Figure 2As shown, the GaN high electron mobility transistor includes a substrate SBT, and a buffer layer Buf, a first p-type gallium nitride layer PN1, a first heterostructure layer, a second heterostructure layer, a u-gallium nitride layer UN, a second p-type gallium nitride layer PN2 and a passivation layer PAL stacked in sequence on one side of the substrate SBT; wherein the orthographic projection of the first p-type gallium nitride layer PN1 on the substrate SBT is located within the orthographic projection range of the first heterostructure layer on the substrate SBT; the second heterostructure layer includes a second channel layer CL2 and a second barrier layer B stacked on the first heterostructure layer. L2; the GaN high electron mobility transistor also includes a gate GE, which includes a first gate GE1, a second gate GE2 and a third gate GE3; the first gate GE1 is electrically connected to the first p-type gallium nitride layer PN1; the second gate GE2 is an MIS gate, which includes a stacked gate dielectric layer GIL and a gate metal GM, the orthographic projection of the gate metal GM on the substrate SBT is located within the orthographic projection range of the gate dielectric layer GIL on the substrate SBT, and at least a portion of the gate dielectric layer is electrically connected to the second channel layer; the third gate GE3 is electrically connected to the second p-type gallium nitride layer PN2.

[0058] The GaN high electron mobility transistor provided in this embodiment forms a u-GaN layer UN by growing it on the upper side of the second barrier layer BL2, generating 2DHG (Two-Dimensional Hole Gas) at the interface between the u-GaN layer UN and the second barrier layer BL2. A 2DEG is generated at the interface between the second channel layer CL2 and the second barrier layer BL2. The 2DHG between the u-GaN layer UN and the second barrier layer BL2 and the 2DEG between the second channel layer CL2 and the second barrier layer BL2 form a polarized superjunction structure, exhibiting a field plate-like effect. This effectively dissipates the electric field near the drain terminal and the gate edge, thereby achieving an ultra-high breakdown voltage.

[0059] In this embodiment, a GaN high electron mobility transistor device uses a first gate GE1, a second gate GE2, and a third gate GE3 to control the channel in the transistor. The first gate GE1 is electrically connected to the first p-type gallium nitride layer PN1, and the carrier concentration of the channel between the first heterostructure layers is regulated by the first gate GE1. For example, by regulating the first gate GE1, the carriers in the channel between the first heterostructure layers are depleted at zero gate voltage, thereby turning on when a positive gate voltage is applied to the second gate GE2. The second gate GE2 uses a MIS gate, including a gate dielectric layer GIL and a gate metal GM; the gate dielectric layer GIL of the MIS gate is used to regulate the channel carrier concentration at the interface of the second heterostructure layer. The third gate GE3 is electrically connected to the second p-type gallium nitride layer PN2, and the concentration of 2DHG at the interface between the u-gallium nitride layer UN and the second barrier layer BL2 is controlled through the second p-type gallium nitride layer PN2. In this way, by depleting carriers in each channel through three gates, the transistor device achieves enhancement mode, thereby reducing the complexity and cost of the circuit using the transistor, while also improving the safety and system reliability of the circuit in high-power switching applications. The GaN high electron mobility transistor provided by the present invention achieves enhancement mode and ultra-high breakdown voltage, and has a high current drive capability.

[0060] In the transistor device provided by the present invention, the first gate GE1 and the third gate GE3 use p-GaN to control the depletion of carriers in the channel. Gate control and the enhancement effect of the transistor can be achieved by simple ion implantation, and the preparation process of the first gate GE1 and the third gate GE3 is simple. The second gate GE2 adopts an MIS gate structure, which can improve the gate reliability of the device. The MIS gate structure uses high dielectric constant materials to significantly reduce leakage current and gate tunneling effect, improve the stability of the device under high temperature or high electric field, reduce interface state charge accumulation, and reduce the risk of device performance degradation. The use of different types of gates for coordinated control can not only enable the transistor to achieve enhancement mode, but also improve the reliability of the gate, while simplifying the preparation process.

[0061] In one example, the gate dielectric layer GIL is made of HfO2. Using a material with a high dielectric constant to prepare the gate dielectric layer GIL can provide a stronger gate control capability at the same thickness. The gate dielectric layer GIL can also be made of other materials, such as Al2O3.

[0062] In one example, Figure 2 As shown, the lower surface of the first p-type gallium nitride layer PN1 contacts the upper surface of the buffer layer Buf, and the upper surface and side surfaces of the first p-type gallium nitride layer PN1 are both covered in the first heterostructure layer and contact the first heterostructure layer.

[0063] In one example, the upper side of the gate is flush with the upper side of the passivation layer PAL.

[0064] In one embodiment of the present invention, the first heterostructure layer includes a first channel layer CL1 and a first barrier layer BL1 stacked on a first p-type gallium nitride layer PN1; the materials of the first channel layer CL1 and the second channel layer CL2 are both GaN, and the materials of the first barrier layer BL1 and the second barrier layer BL2 are both AlInN. In this embodiment, the GaN high electron mobility transistor device adopts a dual-channel (a channel is formed between the first channel layer CL1 and the first barrier layer BL1, and another channel is formed between the second channel layer CL2 and the second barrier layer BL2) structure, so that two parallel two-dimensional electron gas paths can be formed between the source and the drain, increasing the total carrier surface density of the transistor device. The carriers are distributed in parallel in the two channels, thereby improving the carrier mobility. In this way, the formation of two parallel channel paths greatly reduces the resistance between the source and the drain, so that the transistor device has a smaller on-state resistance and a larger current driving capability. In this embodiment, a dual channel is formed by two AlInN / GaN heterojunction structures.

[0065] In another embodiment of the present invention, the first heterostructure layer includes a first channel layer CL1 and a first barrier layer BL1 stacked on a first p-type gallium nitride layer PN1. Both the first channel layer CL1 and the second channel layer CL2 are made of GaN, the first barrier layer BL1 is made of AlGaN, and the second barrier layer BL2 is made of AlN. In this embodiment, a dual channel is formed using AlGaN / GaN heterojunction and AlN / GaN heterojunction structures.

[0066] In one embodiment of the present invention, at least two of the first gate GE1, the second gate GE2, and the third gate GE3 are electrically connected. That is, the first gate GE1 and the second gate GE2 may be electrically connected and controlled by the same gate voltage, while the third gate GE3 may be independently controlled using a different gate voltage. Alternatively, the first gate GE1 and the third gate GE3 may be electrically connected and controlled by the same gate voltage, while the second gate GE2 may be independently controlled using a different gate voltage. Alternatively, the first gate GE1, the second gate GE2, and the third gate GE3 may all be controlled using the same gate voltage, thereby reducing circuit complexity.

[0067] For example, Figure 3 Illustrated is a top view of a double-channel GaN high electron mobility transistor with a MIS gate (passivation layer not shown). Figure 3 The three dotted lines in the corresponding area of ​​the middle gate GE are the corresponding area of ​​the first gate GE1, the corresponding area of ​​the second gate GE2 and the corresponding area of ​​the third gate GE3 (corresponding to the first groove 21 ( Figure 10(not shown), second groove 22 and third groove 23). Figure 3 After cutting along the AA line, Figure 4 shown; along Figure 3 After cutting along the BB line, Figure 5 As shown. Understandably. Figure 3-Figure 5 This is a layout of the first gate GE1 , the second gate GE2 and the third gate GE3 . In other implementations, other layouts may also be used.

[0068] In one embodiment of the present invention, it further includes a source electrode SE and a drain electrode DE; the source electrode SE is in ohmic contact with the first channel layer CL1, the first barrier layer BL1, the second channel layer CL2 or the second barrier layer BL2; the drain electrode DE is in ohmic contact with the first channel layer CL1, the first barrier layer BL1, the second channel layer CL2 or the second barrier layer BL2.

[0069] In one embodiment of the present invention, the orthographic projection of the gate dielectric layer GIL on the substrate SBT overlaps with the orthographic projection of the buffer layer Buf on the substrate SBT, and does not overlap with the orthographic projections of the first gate electrode GE1, the third gate electrode GE3, the source electrode SE, and the drain electrode DE on the substrate SBT. In this way, the gate dielectric layer GIL covers the area except for the source electrode SE, the drain electrode DE, the first gate electrode GE1, and the third gate electrode GE3, further reducing leakage.

[0070] The present invention also provides a method for preparing the dual-channel GaN high electron mobility transistor with MIS gate. Figures 6-10 , including the following steps:

[0071] S10, such as Figure 6 As shown, a substrate SBT is obtained, and a buffer layer Buf is formed on one side of the substrate SBT.

[0072] Exemplarily, in step S10, the material used for the substrate SBT is sapphire.

[0073] For example, in step S10 , the buffer layer Buf is made of GaN and is formed by growing the buffer layer Buf on the substrate SBT using a MOCVD (Metal-organic Chemical Vapor Deposition) process.

[0074] S20, such as Figure 7As shown, a gallium nitride layer is formed on the upper side of the buffer layer Buf, and a portion of the gallium nitride layer is doped by ion implantation to form a first p-type gallium nitride layer PN1. The orthographic projection of the first p-type gallium nitride layer PN1 on the substrate SBT at least partially overlaps with the orthographic projection of the predetermined gate region on the substrate SBT.

[0075] For example, in step S20, the ion implantation is to dope Mg in the GaN layer, and the concentration of Mg doping is (1-3)×10 19 cm -3 For example, the Mg doping concentration can be 1×10 19 cm -3 , 1.5×10 19 cm -3 , 2×10 19 cm -3 , 2.5×10 19 cm -3 or 3×10 19 cm -3 .

[0076] Illustratively, in step S20, after ion doping is performed on a partial region of the gallium nitride layer, a first p-type gallium nitride layer PN1 is formed in the ion-doped region. For the region that is not ion-doped, if the material used for the first channel layer CL1 in the first heterostructure layer is GaN, the region is retained, and the first channel layer CL1 is further formed on the upper side of the first p-type gallium nitride layer PN1. The undoped gallium nitride layer and the first channel layer CL1 cover the side surfaces and the upper surface of the first p-type gallium nitride layer PN1. If the material used for the first channel layer CL1 is other materials, the undoped region can be etched away, and then the first channel layer CL1 is formed integrally. The channel layer covers the side surfaces and the upper surface of the first p-type gallium nitride layer PN1.

[0077] S30, such as Figure 7 As shown, a first heterostructure layer, a second channel layer CL2 and a second barrier layer BL2 are sequentially formed on the first p-type gallium nitride layer PN1.

[0078] In one example, the first heterostructure layer includes a first channel layer CL1 and a first barrier layer BL1 stacked in sequence; the materials of the first channel layer CL1 and the second channel layer CL2 are both GaN, and the materials of the first barrier layer BL1 and the second barrier layer BL2 are both AlInN.

[0079] In another example, the materials of the first channel layer CL1 and the second channel layer CL2 are both GaN, the material of the first barrier layer BL1 is AlGaN, and the material of the second barrier layer BL2 is AlN.

[0080] S40, such as Figure 7As shown, a u-GaN layer UN and a second p-type GaN layer PN2 are sequentially formed on the second barrier layer BL2. The u-GaN layer UN and the second p-type GaN layer PN2 are etched to expose a predetermined source region, a predetermined drain region, and a portion of a predetermined gate region. The second p-type GaN layer PN2 at least partially covers the u-GaN layer UN, and the orthographic projection of the second p-type GaN layer PN2 on the substrate SBT at least partially overlaps with the orthographic projection of the predetermined gate region on the substrate SBT. Simultaneously, a MIS gate groove 1 is etched in the predetermined gate region, exposing a portion of the second channel layer CL2.

[0081] For example, the Mg doping concentration in the second p-type gallium nitride layer PN2 is (1-3)×10 19 cm -3 For example, in the second p-type gallium nitride layer PN2, the Mg doping concentration may be 1×10 19 cm -3 , 1.5×10 19 cm -3 , 2×10 19 cm -3 , 2.5×10 19 cm -3 or 3×10 19 cm -3 .

[0082] S50, such as Figure 8 As shown, after etching in step S40 is completed, a gate dielectric layer GIL is formed on the side away from the substrate SBT. The gate dielectric layer GIL is etched to expose the predetermined source region, predetermined drain region, predetermined first gate region, and predetermined third gate region. In other words, the etched gate dielectric layer GIL covers all areas except the predetermined source region, predetermined drain region, predetermined first gate region, and predetermined third gate region. This prevents gate leakage and improves transistor device performance.

[0083] S60, such as Figure 9 As shown, a source electrode SE and a drain electrode DE are formed in the preset source region and the preset drain region respectively. The preset source region and the preset drain region are located on both sides of the u-gallium nitride layer UN.

[0084] In one embodiment, the specific steps of S60 include:

[0085] S601, forming a first photoresist mask on the upper side of the gate dielectric layer GIL, wherein the first photoresist mask exposes the second barrier layer BL2 corresponding to the preset source region and the preset drain region;

[0086] Exemplarily, step S601 is specifically as follows: using a spinner to spin the photoresist at a speed of 5000 rpm to obtain a photoresist with a thickness of 0.8 μm; then baking it in a high-temperature oven at a temperature of 80°C for 10 minutes, and using an NSR1755I7A photolithography machine to photolithography the baked photoresist to obtain a first photoresist mask, wherein the first photoresist mask is a mask pattern having a preset source region and a preset drain region (exposing the preset source region and the preset drain region).

[0087] S602. Using the first photoresist mask as a mask, an electron beam evaporation process is used to sequentially form Ti / Al / Ni / Au in a preset source region and a preset drain region to obtain a source-drain metal stack; wherein the thickness of Ti is 15 to 25 nm, the thickness of Al is 110 to 130 nm, the thickness of Ni is 40 to 50 nm, and the thickness of Au is 50 to 60 nm.

[0088] Exemplarily, step S602 is specifically as follows: using an Ohmiker-50 electron beam evaporation table to produce the source electrode SE and the drain electrode DE at an evaporation rate of 0.1 nm / s, the source and drain metals are selected from Ti / Al / Ni / Au in sequence, wherein the thickness of Ti is 20 nm, the thickness of Al is 120 nm, the thickness of Ni is 45 nm, and the thickness of Au is 55 nm; after the evaporation of the source and drain ohmic contact metal is completed, the metal is stripped to obtain a complete source and drain metal stack.

[0089] S603 , after the electron beam evaporation is completed, the source-drain metal stack is subjected to rapid thermal annealing for 20 to 35 seconds in a nitrogen atmosphere at 860 to 875° C. to obtain a source electrode SE and a drain electrode DE.

[0090] Exemplarily, step S603 specifically includes: using an RTP500 rapid thermal annealing furnace to perform rapid thermal annealing for 30 seconds in an N2 atmosphere at 870°C to alloy the source-drain metal stack to complete the fabrication of the source SE and the drain electrode.

[0091] In another embodiment of the present invention, the drain electrode DE and the source electrode SE form ohmic contacts with the first channel layer CL1, the first barrier layer BL1, or the second channel layer CL2, or the second barrier layer BL2. Thus, step S601 further includes: etching using an inductively coupled plasma using a first photoresist mask to form source and drain trenches; and step S602 includes: forming Ti / Al / Ni / Au in the source and drain trenches in sequence to form a source-drain metal stack; wherein the thickness of Ti is 15-25 nm, the thickness of Al is 110-130 nm, the thickness of Ni is 40-50 nm, and the thickness of Au is 50-60 nm.

[0092] S70, such as Figure 10As shown, a passivation layer PAL is formed, and the passivation layer PAL completely covers the source electrode SE, the drain electrode DE, the gate dielectric layer GIL, the u-gallium nitride layer UN and the second p-type gallium nitride layer PN2; the passivation layer PAL is etched to form a gate groove 2. A first groove 21 ( Figure 10 The first groove 21 exposes at least a portion of the first p-type gallium nitride layer PN1; the second groove 22 exposes the gate dielectric layer GIL corresponding to the MIS gate groove 1; and the third groove 23 exposes at least a portion of the second p-type gallium nitride layer PN2. Gate metal GM is deposited in the first groove 21, the second groove 22, the third groove 23, and the gate groove 2, respectively, to form the gate GE, thereby obtaining a dual-channel GaN high electron mobility transistor with an MIS gate.

[0093] In one example, S70 includes the following steps:

[0094] S701 , forming a second photoresist mask on the upper side of the passivation layer PAL, and performing etching using inductively coupled plasma to form a gate groove 2 .

[0095] Exemplarily, step S701 is specifically as follows: a positive resist is spun on the surface of the passivation layer PAL at a rotation speed of 5000 rpm to obtain a photoresist with a thickness of 0.8 μm, and then baked in a high-temperature oven at a temperature of 80°C for 10 minutes, and then a second photoresist mask is obtained by photolithography using an NSR1755I7A photolithography machine; an ICP98c inductively coupled plasma etcher is used to etch away the passivation layer PAL of the preset gate area at an etching rate of 0.5 nm / s in CF4 plasma to form a gate groove 2.

[0096] S702 , forming a third photoresist mask in the gate groove 2 , and performing etching using inductively coupled plasma to form a first groove 21 , a second groove 22 , and a third groove 23 .

[0097] Exemplarily, step S702 specifically comprises: using a spinner to spin at a speed of 5000 rpm to obtain a photoresist with a thickness of 0.8 μm; baking in a high-temperature oven at 80°C for 10 minutes, and exposing using an NSR1755I7A photolithography machine to form a third photoresist mask; and dry etching using an ICP98c inductively coupled plasma etcher based on the third photoresist mask to obtain a first groove 21, a second groove 22, and a third groove 23. The first groove is formed by first etching the passivation layer using an inductively coupled plasma etcher with CF4 plasma at an etching rate of 0.5 nm / s, and then etching using Cl2 plasma at an etching rate of 1 nm / s to obtain the first groove. The second and third grooves are formed by etching the passivation layer using an inductively coupled plasma etcher with CF4 plasma at an etching rate of 0.5 nm / s to obtain the second and third grooves.

[0098] S703 , using an electron beam evaporation process to form a Ni / Au gate metal stack in the first groove 21 , the second groove 22 , the third groove 23 and the gate groove 2 to obtain a gate GE; wherein the Ni thickness is 15 to 25 nm, and the Au thickness is 180 to 220 nm.

[0099] Exemplarily, step S703 is specifically as follows: using an Ohmiker-50 electron beam evaporation table to evaporate the gate metal GM at an evaporation rate of 0.1 nm / s, the gate metal GM is selected from Ni / Au in sequence, wherein the Ni thickness is 20 nm and the Au thickness is 200 nm; after the evaporation is completed, metal stripping is performed to obtain the gate GE.

[0100] Exemplarily, the material of the passivation layer PAL is SiN.

[0101] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A dual-channel GaN high electron mobility transistor with an MIS gate, characterized in that: The invention comprises a base substrate, and a buffer layer, a first p-type gallium nitride layer, a first heterostructure layer, a second heterostructure layer, a u-gallium nitride layer, a second p-type gallium nitride layer, and a passivation layer stacked in sequence on one side of the base substrate; an orthographic projection of the first p-type gallium nitride layer on the base substrate is located within the orthographic projection of the first heterostructure layer on the base substrate; and the second heterostructure layer comprises a second channel layer and a second barrier layer stacked on the first heterostructure layer. The GaN high electron mobility transistor further includes a gate, the gate including a first gate, a second gate, and a third gate; the first gate is electrically connected to the first p-type gallium nitride layer; the second gate includes a stacked gate dielectric layer and a gate metal, the orthographic projection of the gate metal on the substrate is located within the orthographic projection of the gate dielectric layer on the substrate, and at least a portion of the gate dielectric layer is electrically connected to the second channel layer; The third gate is electrically connected to the second p-type gallium nitride layer.

2. The dual-channel GaN high electron mobility transistor with MIS gate according to claim 1, characterized in that: The material of the gate dielectric layer is HfO2 or Al2O3.

3. The dual-channel GaN high electron mobility transistor with MIS gate according to claim 1 or 2, characterized in that: The first heterostructure layer includes a first channel layer and a first barrier layer stacked together; The first channel layer and the second channel layer are both made of GaN, and the first barrier layer and the second barrier layer are both made of AlInN; or, the first channel layer and the second channel layer are both made of GaN, the first barrier layer is made of AlGaN, and the second barrier layer is made of AlN.

4. The dual-channel GaN high electron mobility transistor with MIS gate according to claim 3, characterized in that: At least two of the first gate, the second gate and the third gate are electrically connected.

5. The dual-channel GaN high electron mobility transistor with MIS gate according to claim 4, characterized in that: It also includes a source and a drain; the source is in ohmic contact with the first channel layer, the first barrier layer, the second channel layer or the second barrier layer; the drain is in ohmic contact with the first channel layer, the first barrier layer, the second channel layer or the second barrier layer.

6. The dual-channel GaN high electron mobility transistor with MIS gate according to claim 5, characterized in that: The orthographic projection of the gate dielectric layer on the base substrate coincides with the orthographic projection of the buffer layer on the base substrate, and does not coincide with the orthographic projections of the first gate, the third gate, the source, and the drain on the base substrate.

7. A method for preparing a dual-channel GaN high electron mobility transistor with a MIS gate according to claim 6, characterized in that: The following steps are involved: S10, obtaining a base substrate, and forming a buffer layer on one side of the base substrate; S20, forming a gallium nitride layer on the buffer layer, and doping a portion of the gallium nitride layer by ion implantation to form a first p-type gallium nitride layer, wherein an orthographic projection of the first p-type gallium nitride layer on the base substrate at least partially overlaps with an orthographic projection of a predetermined gate region on the base substrate; S30, forming a first heterostructure layer, a second channel layer, and a second barrier layer in sequence on the first p-type gallium nitride layer; S40, sequentially forming a u-gallium nitride layer and a second p-type gallium nitride layer on the upper side of the second barrier layer, and etching the u-gallium nitride layer and the second p-type gallium nitride layer to expose a predetermined source region, a predetermined drain region, and a portion of a predetermined gate region; The second p-type gallium nitride layer at least partially covers the u-gallium nitride layer, and an orthographic projection of the second p-type gallium nitride layer on the base substrate at least partially overlaps with an orthographic projection of the preset gate region on the base substrate; At the same time, etching a MIS gate groove in the preset gate region, wherein the MIS gate groove exposes a portion of the second channel layer; S50: After the etching in step S40 is completed, a gate dielectric layer is formed on the side away from the substrate; Etching the gate dielectric layer to expose the preset source region, the preset drain region, the preset first gate region, and the preset third gate region; S60, forming a source electrode and a drain electrode in a preset source region and a preset drain region, respectively, wherein the preset source region and the preset drain region are located on both sides of the u-gallium nitride layer; S70, forming a passivation layer, wherein the passivation layer completely covers the source electrode, the drain electrode, the gate dielectric layer, the u-type gallium nitride layer, and the second p-type gallium nitride layer; etching the passivation layer to form a gate groove; Etching a first groove, a second groove, and a third groove at the bottom of the gate groove; wherein the first groove exposes at least a portion of the first p-type gallium nitride layer; The second groove exposes the gate dielectric layer corresponding to the MIS gate groove; The third groove exposes at least a portion of the second p-type gallium nitride layer; Gate metals are deposited in the first groove, the second groove, the third groove, and the gate groove respectively to form a gate, thereby obtaining a double-channel GaN high electron mobility transistor with an MIS gate.

8. The method for preparing a dual-channel GaN high electron mobility transistor with a MIS gate according to claim 7, wherein: In step S60, forming the source and drain includes the following steps: S601, forming a first photoresist mask on the upper side of the gate dielectric layer, wherein the first photoresist mask exposes the second barrier layer corresponding to the preset source region and the preset drain region; S602, forming a Ti / Al / Ni / Au source / drain metal stack in the predetermined source region and the predetermined drain region using an electron beam evaporation process; wherein the thickness of Ti is 15-25 nm, the thickness of Al is 110-130 nm, the thickness of Ni is 40-50 nm, and the thickness of Au is 50-60 nm; S603 , after the electron beam evaporation is completed, the source and drain metal stack is subjected to rapid thermal annealing for 20 to 35 seconds in a nitrogen atmosphere at 860 to 875° C. to obtain the source and drain electrodes.

9. The method for preparing a dual-channel GaN high electron mobility transistor with a MIS gate according to claim 7, wherein: In step S70, forming the gate includes the following steps: S701, forming a second photoresist mask on the upper side of the passivation layer, and etching using inductively coupled plasma to form a gate groove; S702, forming a third photoresist mask in the gate groove, and performing etching using inductively coupled plasma to form a first groove, a second groove, and a third groove; S703 , using an electron beam evaporation process to form Ni / Au gate metal in the first groove, the second groove, the third groove and the gate groove, wherein the thickness of Ni is 15-25 nm and the thickness of Au is 180-220 nm; obtaining a gate.

10. The method for preparing a dual-channel GaN high electron mobility transistor with a MIS gate according to any one of claims 7 to 9, characterized in that: The material of the substrate is sapphire; the material of the buffer layer is GaN; the material of the passivation layer is SiN; The first heterostructure layer includes a first channel layer and a first barrier layer that are stacked; the materials of the first channel layer and the second channel layer are both GaN, and the materials of the first barrier layer and the second barrier layer are both AlInN; or, the materials of the first channel layer and the second channel layer are both GaN, the material of the first barrier layer is AlGaN, and the material of the second barrier layer is AlN.

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