Three-dimensional semiconductor device and manufacturing method thereof

Abstract

A three-dimensional semiconductor device is provided. The device includes a first active region on a substrate, the first active region including a first source / drain pattern connected to a first channel pattern; a second active region stacked on the first active region and including a second source / drain pattern connected to the second channel pattern; a gate electrode disposed on the first channel pattern and the second channel pattern; and a first ferroelectric pattern interposed between the substrate and the first channel pattern. The first channel pattern includes a first semiconductor pattern and a second semiconductor pattern spaced apart from each other in a vertical direction perpendicular to a top surface of the substrate. The first ferroelectric pattern is interposed between the substrate and the first semiconductor pattern. The gate electrode includes a first gate electrode interposed between the first semiconductor pattern and the second semiconductor pattern.

Description

Technical Field

[0001] The present disclosure relates to a three-dimensional semiconductor device and a manufacturing method thereof, and in particular, to a three-dimensional semiconductor device including a field effect transistor and a manufacturing method thereof. Background Art

[0002] Semiconductor devices include integrated circuits composed of metal oxide semiconductor field effect transistors (MOSFETs). To meet the growing demand for semiconductor devices with small pattern sizes and reduced design rules, MOSFETs are being actively scaled down. Scaling down MOSFETs can lead to degradation in the operating performance of semiconductor devices. Various research efforts are underway to overcome the technical limitations associated with scaling down semiconductor devices and achieve high-performance semiconductor devices. Summary of the Invention

[0003] One or more embodiments provide a three-dimensional semiconductor device with improved reliability.

[0004] One or more embodiments provide a method of fabricating a three-dimensional semiconductor device with improved reliability.

[0005] According to one aspect of the embodiment, a three-dimensional semiconductor device includes: a first active region on a substrate, the first active region including a first channel pattern and a first source / drain pattern connected to the first channel pattern; a second active region stacked on the first active region, the second active region including a second channel pattern and a second source / drain pattern connected to the second channel pattern; a gate electrode disposed on the first and second channel patterns; and a first ferroelectric pattern interposed between the substrate and the first channel pattern. The first channel pattern includes a first semiconductor pattern and a second semiconductor pattern spaced apart from each other in a vertical direction perpendicular to the top surface of the substrate. The first ferroelectric pattern is interposed between the substrate and the first semiconductor pattern and disposed on one side of the first source / drain pattern. The gate electrode includes a first gate electrode interposed between the first and second semiconductor patterns.

[0006] According to another aspect of the embodiment, a three-dimensional semiconductor device includes: a first active region on a substrate, the first active region including a first channel pattern and a first source / drain pattern arranged on the opposite side of the first channel pattern, wherein the first channel pattern includes a plurality of lower semiconductor patterns spaced apart from each other in a vertical direction perpendicular to a top surface of the substrate; a second active region stacked on the first active region, the second active region including a second channel pattern and a second source / drain pattern arranged on the opposite side of the second channel pattern; gate electrodes arranged on the first channel pattern and the second channel pattern, the gate electrodes including a first gate electrode between the first source / drain patterns, a second gate electrode between the second source / drain patterns, and an outer gate electrode on the second channel pattern; and a first ferroelectric pattern inserted between the lowest lower semiconductor pattern among the plurality of lower semiconductor patterns and the substrate and between the first source / drain patterns.

[0007] According to another aspect of the embodiment, a three-dimensional semiconductor device includes: a substrate including an active pattern; a lower insulating layer arranged on the active pattern; a first active region on the lower insulating layer, the first active region including a first channel pattern and a first source / drain pattern arranged on the opposite side of the first channel pattern, the first channel pattern including a first semiconductor pattern and a second semiconductor pattern spaced apart from the first semiconductor pattern in a vertical direction perpendicular to the top surface of the substrate; a second active region stacked on the first active region, the second active region including a second channel pattern and a second source / drain pattern arranged on the opposite side of the second channel pattern, the second channel pattern including a third semiconductor pattern and a fourth semiconductor pattern spaced apart from the third semiconductor pattern in the vertical direction; a gate electrode arranged on the first channel pattern and the second channel pattern and extending in the vertical direction; an intermediate insulating layer interposed between the first channel pattern and the second channel pattern; a first ferroelectric pattern interposed between the substrate and the first semiconductor pattern and between the first source / drain patterns; and a second ferroelectric pattern provided on the fourth semiconductor pattern and interposed between the second source / drain patterns. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects and features will become more apparent from the following description of the embodiments with reference to the accompanying drawings.

[0009] Figure 1 is a plan view illustrating a three-dimensional semiconductor device according to an embodiment.

[0010] Figure 2A 、 Figure 2B 、 Figure 2C and Figure 2D According to the implementation method, Figure 1 Cross-sectional views taken along lines AA', BB', CC' and DD'.

[0011] Figure 3A 、 Figure 3B 、 Figure 4A 、 Figure 4B 、 Figure 5A 、 Figure 5B 、 Figure 6A 、 Figure 6B 、 Figure 7A 、 Figure 7B 、 Figure 8A 、 Figure 8B 、 Figure 9A 、 Figure 9B 、 Figure 10A 、 Figure 10B 、 Figure 11A 、 Figure 11B 、 Figure 12A 、 Figure 12B 、 Figure 13A 、 Figure 13B 、 Figure 14A 、 Figure 14B 、 Figure 15A 、 Figure 15B 、 Figure 16A and Figure 16B is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment.

[0012] Figures 17 to 26 are along Figure 1 1 is a cross-sectional view taken along line AA′ of FIG. 1 to illustrate a three-dimensional semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0013] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Throughout the specification, identical parts are represented by identical reference numerals, and their repeated description is omitted. It will be understood that when an element or layer is referred to as "on" another element or layer, "connected to" or "coupled to" another element or layer, it can be directly on another element or layer, connected to or coupled to another element or layer, or there can be an intermediate element or layer. On the contrary, when an element is referred to as "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there is no intermediate element or layer. The embodiments described herein are example embodiments, and therefore, the present disclosure is not limited thereto, and can be realized in various other forms. Each embodiment provided in the following description does not exclude that one or more features of another example or another embodiment that is also provided herein or is not provided herein but is consistent with the present disclosure are associated.

[0014] Figure 1 is a plan view illustrating a three-dimensional semiconductor device according to an embodiment. Figures 2A to 2D are along Figure 1 Cross-sectional views taken along lines AA', BB', CC' and DD'.

[0015] refer to Figure 1 and Figures 2A to 2D , a substrate 100 including an active pattern AP and a device isolation layer ST may be provided. The active pattern AP may be defined by a trench TR formed in an upper portion of the substrate 100. The active pattern AP may be a vertical protrusion of the substrate 100. When viewed in a plan view, the active pattern AP may have a strip shape extending in the second direction D2. The device isolation layer ST may fill the trench TR. The device isolation layer ST may include a silicon oxide layer. The top surface of the device isolation layer ST may be coplanar with or lower than the top surface of the active pattern AP. The device isolation layer ST may not cover the first channel pattern CH1 and the second channel pattern CH2 to be described below. In an embodiment, the device isolation layer ST may be formed of or include, for example, silicon oxide. The substrate 100 may be a semiconductor substrate formed of or including silicon, germanium, silicon germanium, or a compound semiconductor material. In an embodiment, the substrate 100 may be a silicon wafer.

[0016] A lower insulating layer BDI may be disposed on the active pattern AP. The lower insulating layer BDI may be formed of or include at least one of insulating materials (eg, silicon oxide, silicon nitride, and / or silicon oxynitride).

[0017] A first active region AR1 and a second active region AR2 may be sequentially stacked on the lower insulating layer BDI. One of the first active region AR1 and the second active region AR2 may be a p-type metal oxide semiconductor field effect transistor (MOSFET) (PMOSFET) region, and the other of the first active region AR1 and the second active region AR2 may be an n-type metal oxide semiconductor field effect transistor (NMOSFET) region. Each of the MOSFETs in the first active region AR1 and the second active region AR2 may be vertically stacked to form a three-dimensional stacked transistor.

[0018] The first active region AR1 may include a first channel pattern CH1 and first source / drain patterns SD1 disposed on both sides (ie, opposite sides) of the first channel pattern CH1. The first channel pattern CH1 may be interposed between the first source / drain patterns SD1. The first channel pattern CH1 may connect the first source / drain patterns SD1 to each other.

[0019] The first channel pattern CH1 may include a first semiconductor pattern SP1 and a second semiconductor pattern SP2 stacked in sequence. The first semiconductor pattern SP1 and the second semiconductor pattern SP2 may be spaced apart from each other in a vertical direction D3 perpendicular to the top surface of the substrate 100. In an embodiment, the first channel pattern CH1 may include three or more semiconductor patterns spaced apart from each other in the vertical direction D3. The semiconductor patterns in the first channel pattern CH1 may be referred to as lower semiconductor patterns. The first direction D1 and the second direction D2 may be parallel to the top surface of the substrate 100 and may not be parallel to each other. The third direction D3 may be a vertical direction D3 perpendicular to the top surface of the substrate 100. The first direction D1, the second direction D2, and the third direction D3 may be orthogonal to each other.

[0020] Each of the first and second semiconductor patterns SP1 and SP2 may be formed of or include at least one of silicon (Si), germanium (Ge), or silicon germanium (SiGe). In an embodiment, each of the first and second semiconductor patterns SP1 and SP2 may be formed of or include crystalline silicon.

[0021] The first source / drain pattern SD1 may be disposed on the top surface of the lower insulating layer BDI. Each of the first source / drain patterns SD1 may be an epitaxial pattern formed by a selective epitaxial growth (SEG) process. The top surface of the first source / drain pattern SD1 may be higher than the top surface of the second semiconductor pattern SP2 of the first channel pattern CH1. In this regard, the top surface of the first source / drain pattern SD1 may be higher than the top surface of the uppermost lower semiconductor pattern among the lower semiconductor patterns of the first channel pattern CH1.

[0022] The first source / drain pattern SD1 may be doped to have a first conductivity type. The first conductivity type may be an n-type or a p-type. The first source / drain pattern SD1 may be formed of or include silicon (Si) and / or silicon germanium (SiGe).

[0023] A first interlayer insulating layer 110 may be disposed on the first source / drain pattern SD1 , may cover the first source / drain pattern SD1 , and may include a second interlayer insulating layer 120 and a second active region AR2 .

[0024] The second active region AR2 may include a second channel pattern CH2 and second source / drain patterns SD2 disposed on both sides (i.e., opposite sides) of the second channel pattern CH2. The second channel pattern CH2 may vertically overlap the first channel pattern CH1. The second source / drain patterns SD2 may vertically overlap the first source / drain patterns SD1, respectively. The second channel pattern CH2 may be interposed between the second source / drain patterns SD2. The second channel pattern CH2 may connect the second source / drain patterns SD2 to each other.

[0025] The second channel pattern CH2 may include a third semiconductor pattern SP3 and a fourth semiconductor pattern SP4 stacked in sequence. The third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 may be spaced apart from each other in the vertical direction D3. In an embodiment, the second channel pattern CH2 may include three or more semiconductor patterns spaced apart from each other in the vertical direction D3. The semiconductor patterns in the second channel pattern CH2 may be referred to as upper semiconductor patterns. Each upper semiconductor pattern may be formed of or include the same semiconductor material as the lower semiconductor pattern.

[0026] An intermediate insulating layer MDI may be interposed between the first channel pattern CH1 and the second channel pattern CH2. The intermediate insulating layer MDI may be spaced apart from the first source / drain pattern SD1. The intermediate insulating layer MDI may be spaced apart from the second source / drain pattern SD2. That is, the intermediate insulating layer MDI may not be connected to any of the source / drain patterns. The intermediate insulating layer MDI may be formed of or include at least one of insulating materials (e.g., silicon oxide, silicon nitride, and / or silicon oxynitride).

[0027] The second source / drain pattern SD2 may be disposed on the top surface of the first interlayer insulating layer 110. Each second source / drain pattern SD2 may be an epitaxial pattern formed by an SEG process. The top surface of the second source / drain pattern SD2 may be higher than the top surface of the fourth semiconductor pattern SP4 of the second channel pattern CH2. In other words, the top surface of the second source / drain pattern SD2 may be higher than the top surface of the uppermost upper semiconductor pattern among the upper semiconductor patterns of the second channel pattern CH2.

[0028] The second source / drain pattern SD2 may be doped to have a second conductivity type. The second conductivity type may be different from the first conductivity type of the first source / drain pattern SD1. The second source / drain pattern SD2 may be formed of or include silicon germanium (SiGe) and / or silicon (Si).

[0029] The second interlayer insulating layer 120 may cover the second source / drain pattern SD2. A top surface of the second interlayer insulating layer 120 may be coplanar with a top surface of each of first and second active contacts AC1 and AC2, which will be described below.

[0030] The gate electrode GE may be disposed on the first and second channel patterns CH1 and CH2. The gate electrode GE may be a linear pattern extending in the first direction D1 when viewed in a plan view. The gate electrode GE may vertically overlap the first and second channel patterns CH1 and CH2.

[0031] The gate electrode GE may include a first gate electrode GE1 interposed between the first source / drain patterns SD1. The first gate electrode GE1 may vertically overlap the first channel pattern CH1. Specifically, the first gate electrode GE1 may include a first portion PO1 disposed below the first semiconductor pattern SP1, a second portion PO2 interposed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, and a third portion PO3 disposed on the second semiconductor pattern SP2. The third portion PO3 may be interposed between the second semiconductor pattern SP2 and the intermediate insulating layer MDI. In an embodiment, the first gate electrode GE1 may include a lower inner electrode and a lowermost electrode. The lower inner electrode may include a plurality of lower inner electrodes interposed between the lower semiconductor patterns. The lowermost electrode may be interposed between the lowermost lower semiconductor pattern among the lower semiconductor patterns and the lower insulating layer BDI.

[0032] The gate electrode GE may include a second gate electrode GE2 interposed between the second source / drain patterns SD2. The second gate electrode GE2 may vertically overlap the second channel pattern CH2. Specifically, the second gate electrode GE2 may include a fourth portion PO4 disposed below the third semiconductor pattern SP3, a fifth portion PO5 interposed between the third and fourth semiconductor patterns SP3, and a sixth portion PO6 disposed on the fourth semiconductor pattern SP4. The fourth portion PO4 may be interposed between the intermediate insulating layer MDI and the third semiconductor pattern SP3. In an embodiment, the second gate electrode GE2 may include an upper inner electrode and an uppermost electrode. The upper inner electrode may include a plurality of upper inner electrodes interposed between the upper semiconductor patterns. The uppermost electrode may be disposed on the uppermost upper semiconductor pattern among the upper semiconductor patterns.

[0033] The first gate electrode GE1 may be disposed in the first active region AR1. The second gate electrode GE2 may be disposed in the second active region AR2. The first gate electrode GE1 and the second gate electrode GE2 may vertically overlap each other.

[0034] The gate electrode GE may include an external gate electrode OGE. The external gate electrode OGE may extend from the top surface of the device isolation layer ST in the vertical direction D3. The external gate electrode OGE may connect the first gate electrode GE1 and the second gate electrode GE2 to each other.

[0035] The first gate electrode GE1 may include a first work function metal pattern. The second gate electrode GE2 may include a second work function metal pattern. Each of the first work function metal pattern and the second work function metal pattern may be formed of a material containing at least one metal element selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), molybdenum (Mo), and nitrogen (N). The first work function metal pattern and the second work function metal pattern may have different work functions from each other. The outer gate electrode OGE may include at least one of a low-resistance metal (e.g., tungsten (W), ruthenium (Ru), aluminum (Al), titanium (Ti), and tantalum (Ta)).

[0036] The gate electrode GE may be provided on the top surface, the bottom surface, and the opposite side surfaces of each of the first channel pattern CH1 and the second channel pattern CH2. That is, the transistor according to the present embodiment may include a three-dimensional field effect transistor (e.g., a multi-bridge channel FET (MBCFET) or a gate all around FET (GAAFET)) in which the gate electrode GE is provided to three-dimensionally surround the channel pattern.

[0037] The first ferroelectric pattern FE1 may be interposed between the substrate 100 and the first channel pattern CH1. Specifically, the first ferroelectric pattern FE1 may be interposed between the lower insulating layer BDI of the substrate 100 and the first semiconductor pattern SP1 of the first channel pattern CH1. The first ferroelectric pattern FE1 may be interposed between the first source / drain pattern SD1. The first portion PO1 of the first gate electrode GE1 may be interposed between the first semiconductor pattern SP1 and the first ferroelectric pattern FE1. In an embodiment, the first ferroelectric pattern FE1 may be interposed between the lowest lower semiconductor pattern among the lower semiconductor patterns of the first channel pattern CH1 and the lower insulating layer BDI. The first ferroelectric pattern FE1 may be interposed between the lowest electrode among the first gate electrode GE1 and the lower insulating layer BDI. The lowest electrode among the first gate electrode GE1 may be interposed between the lowest lower semiconductor pattern among the lower semiconductor patterns and the lower insulating layer BDI.

[0038] The second ferroelectric pattern FE2 may be disposed on the second channel pattern CH2. Specifically, the second ferroelectric pattern FE2 may be interposed between the fourth semiconductor pattern SP4 of the second channel pattern CH2 and the external gate electrode OGE. The second ferroelectric pattern FE2 may be interposed between the second source / drain pattern SD2. The sixth portion PO6 of the second gate electrode GE2 may be interposed between the second ferroelectric pattern FE2 and the fourth semiconductor pattern SP4. In an embodiment, the second ferroelectric pattern FE2 may be interposed between the uppermost semiconductor pattern among the upper semiconductor patterns of the second channel pattern CH2 and the external gate electrode OGE. The second ferroelectric pattern FE2 may be interposed between the uppermost second gate electrode among the second gate electrode GE2 and the external gate electrode OGE. The uppermost second gate electrode among the second gate electrode GE2 may be interposed between the uppermost semiconductor pattern among the upper semiconductor patterns and the second ferroelectric pattern FE2.

[0039] The first and second ferroelectric patterns FE1 and FE2 may include hafnium oxide containing (or doped with) at least one of zirconium (Zr), silicon (Si), aluminum (Al), or lanthanum (La).

[0040] A pair of gate spacers GS may be disposed on opposite side surfaces of the gate electrode GE, respectively. Figure 2A , gate spacers GS may be respectively disposed on opposite side surfaces of the outer gate electrode OGE located on the second ferroelectric pattern FE2. The gate spacer GS may extend along the gate electrode GE and in the first direction D1. The top surface of the gate spacer GS may be higher than the top surface of the gate electrode GE. The top surface of the gate spacer GS may be coplanar with the top surface of the second interlayer insulating layer 120. The gate spacer GS may be formed of or include at least one of SiCN, SiCON, or SiN. In an embodiment, the gate spacer GS may have a multilayer structure including at least two different materials selected from SiCN, SiCON, and SiN. A pair of pad layers LIN may be respectively provided on opposite side surfaces of each of the third portion PO3 of the first gate electrode GE1 and the fourth portion PO4 of the second gate electrode GE2.

[0041] A gate capping pattern GP may be provided on the top surface of the gate electrode GE. The gate capping pattern GP may extend along the gate electrode GE or in the first direction D1. In an embodiment, the gate capping pattern GP may be formed of or include at least one of SiON, SiCN, SiCON, or SiN.

[0042] The gate insulating layer GI may be interposed between each of the first and second channel patterns CH1 and CH2 and the gate electrode GE. The gate insulating layer GI may include a silicon oxide layer, a silicon oxynitride layer, and / or a high-k dielectric layer. In this regard, the gate insulating layer GI may have a multilayer structure including a silicon oxide layer and a high-k dielectric layer.

[0043] The high-k dielectric layer may be formed of or include at least one high-k dielectric material having a dielectric constant higher than that of silicon oxide. For example, the high-k dielectric material may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0044] A gate contact GC may be provided to penetrate the third interlayer insulating layer 130 and the gate capping pattern GP and may be electrically connected to the gate electrode GE. The gate contact GC may be formed of or include at least one metal material selected from the group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0045] Active contacts AC1 to AC4 may be provided to be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2. Figure 1 The first active contact AC1 and the third active contact AC3 may be disposed so as to face the side surface of the gate electrode GE. The second active contact AC2 and the fourth active contact AC4 may be formed so as to face the opposite side surface of the gate electrode GE. For example, each of the first to fourth active contacts AC1 to AC4 may be formed of or include a doped semiconductor material and / or a metal material. For example, the metal material may be selected from the group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0046] The first to fourth active contacts AC1 to AC4 may extend from the top surface of the second interlayer insulating layer 120 through the second source / drain pattern SD2 to the first source / drain pattern SD1. In an embodiment, the first to fourth active contacts AC1 to AC4 may have bottom surfaces located at the same level. In this regard, the first to fourth active contacts AC1 to AC4 may be formed to have substantially the same depth.

[0047] refer to Figure 1 and Figure 2C, the first active contact AC1 and the third active contact AC3 may be provided to penetrate both the stacked first source / drain pattern SD1 and the second source / drain pattern SD2. The first active contact AC1 and the third active contact AC3 may be respectively provided on both sides (i.e., opposite sides) of the first source / drain pattern SD1. The first active contact AC1 and the third active contact AC3 may be respectively provided on both sides (i.e., opposite sides) of the second source / drain pattern SD2.

[0048] The first active contact AC1 may be electrically connected to the first source / drain pattern SD1 but not to the second source / drain pattern SD2 .The third active contact AC3 may be electrically connected to the second source / drain pattern SD2 but not to the first source / drain pattern SD1 .

[0049] Specifically, an upper separation structure USS may be interposed between the first active contact AC1 and the second source / drain pattern SD2. The upper separation structure USS may cover the side surface of the first active contact AC1. Due to the upper separation structure USS, the first active contact AC1 may not contact the second source / drain pattern SD2 or may be spaced apart from the second source / drain pattern SD2. In this regard, the upper separation structure USS may electrically isolate the first active contact AC1 from the second source / drain pattern SD2. The first active contact AC1 may be coupled to the first source / drain pattern SD1.

[0050] A lower separation structure LSS may be interposed between the third active contact AC3 and the first source / drain pattern SD1. The lower separation structure LSS may cover the side and bottom surfaces of the third active contact AC3. Due to the lower separation structure LSS, the third active contact AC3 may not contact the first source / drain pattern SD1 or may be spaced apart from the first source / drain pattern SD1. In this regard, the lower separation structure LSS may electrically isolate the third active contact AC3 from the first source / drain pattern SD1. The third active contact AC3 may be coupled to the second source / drain pattern SD2.

[0051] Reference Figure 1 and Figures 2A to 2D, the second active contact AC2 and the fourth active contact AC4 can be provided to penetrate the stacked first source / drain pattern SD1 and second source / drain pattern SD2. Due to the upper separation structure USS, the second active contact AC2 can be electrically connected to the first source / drain pattern SD1 but not to the second source / drain pattern SD2. In this regard, the upper separation structure USS can electrically isolate the second active contact AC2 from the second source / drain pattern SD2. Due to the lower separation structure LSS, the fourth active contact AC4 can be electrically connected to the second source / drain pattern SD2 but not to the first source / drain pattern SD1. In this regard, the lower separation structure LSS can electrically isolate the fourth active contact AC4 from the first source / drain pattern SD1.

[0052] According to an embodiment, the first to fourth active contacts AC1 to AC4 arranged in a two-dimensional manner may be respectively coupled to the four source / drain terminals of the stack. For example, the first active contact AC1 may be coupled to the lower source terminal, the third active contact AC3 may be coupled to the upper source terminal, the second active contact AC2 may be coupled to the lower drain terminal, and the fourth active contact AC4 may be coupled to the upper drain terminal.

[0053] A third interlayer insulating layer 130 may be provided on the second interlayer insulating layer 120. A fourth interlayer insulating layer 140 may be provided on the third interlayer insulating layer 130. In an embodiment, a connection line CNL may be provided in the third interlayer insulating layer 130. The connection line CNL may be provided on the first to fourth active contacts AC1 to AC4, respectively.

[0054] The first metal layer M1 may be provided in the fourth interlayer insulating layer 140. The first metal layer M1 may include first to third interconnect lines MI1, MI2, and MI3 sequentially arranged in a first direction D1. The first to third interconnect lines MI1, MI2, and MI3 may extend in parallel with each other in a second direction D2. The first to third interconnect lines MI1, MI2, and MI3 may be formed of or include at least one of a metal material (e.g., copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo)).

[0055] The first metal layer M1 may further include a via VI provided in a lower element thereof. At least one of the first to third interconnect lines MI1, MI2, and MI3 may be electrically connected to at least one of the first to fourth active contacts AC1 to AC4 through the via VI and the connection line CNL. Another one of the first to third interconnect lines MI1, MI2, and MI3 may be electrically connected to the gate contact GC through the via VI.

[0056] Additional metal layers (eg, M2, M3, M4, etc.) may be stacked on the first metal layer M1. The first metal layer M1 and the additional metal layers (eg, M2, M3, M4, etc.) thereon may constitute back-end-of-line (BEOL) layers of a semiconductor device.

[0057] A negative capacitance field effect transistor (NCFET) can be a transistor that includes a ferroelectric material between a gate electrode and a dielectric layer, and thus can have improved subthreshold swing characteristics and a reduced operating voltage. For example, when an external voltage is applied to a ferroelectric pattern, the dipoles in the ferroelectric pattern can move, in which case a negative capacitance effect can occur, wherein the initial polarization state of the ferroelectric pattern changes to a different polarization state. In this case, the total capacitance of the transistor including the ferroelectric material can be increased, thereby improving the subthreshold swing characteristics of the transistor and reducing the operating voltage of the transistor. However, for a related three-dimensional stacked field effect transistor (3DSFET) structure, the space for the ferroelectric material in the lower transistor may be limited.

[0058] According to an embodiment, by means of a process for forming a 3DSFET structure to be described below, the lower transistor can be manufactured to include a first ferroelectric pattern FE1. Therefore, the lower transistor can be manufactured to have an NCFET structure. In an embodiment, depending on the position of the ferroelectric material, the NCFET structure can have a metal-ferroelectric-semiconductor (MFS) structure, a metal-ferroelectric-insulator-semiconductor (MFIS) structure, and a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) structure. Figures 2A to 2D In a consistent embodiment, the lower transistor may have an MFMIS structure, which includes an outer gate electrode OGE, a first ferroelectric pattern FE1, a first gate electrode GE1, a gate insulating layer GI, and a first channel pattern CH1. Therefore, degradation of the interface properties between silicon and the ferroelectric material and the polarization properties of the ferroelectric material can be prevented, thereby improving the electrical characteristics of the three-dimensional semiconductor device.

[0059] Figures 3A to 16B 2 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment. For brevity of description, previously described elements may be identified with the same reference numerals without repeating their repeated description.

[0060] refer to Figure 3A and Figure 3B, a lower sacrificial layer BSL may be formed on the substrate 100. An initial first ferroelectric layer pFE1 may be formed on the lower sacrificial layer BSL. First sacrificial layers SAL1 and a first active layer ACL1 may be alternately stacked on the initial first ferroelectric layer pFE1. The lower sacrificial layer BSL, the initial first ferroelectric layer pFE1, and the first sacrificial layer SAL1 may be formed of or include one of silicon (Si), germanium (Ge), and silicon germanium (SiGe), and the first active layer ACL1 may be formed of or include one of silicon (Si), germanium (Ge), and silicon germanium (SiGe), and may be formed of a material different from that of the lower sacrificial layer BSL, the initial first ferroelectric layer pFE1, and the first sacrificial layer SAL1. For example, the lower sacrificial layer BSL, the initial first ferroelectric layer pFE1, and the first sacrificial layer SAL1 may be formed of or include silicon germanium (SiGe), and the first active layer ACL1 may be formed of or include silicon (Si). The germanium concentration of the lower sacrificial layer BSL may be in a range of 45 at % to 55 at %. In an embodiment, the germanium concentration of the lower sacrificial layer BSL may be 50 at %. The germanium concentration of the initial first ferroelectric layer pFE1 may be in a range of 30 at % to 40 at %. In an embodiment, the germanium concentration of the initial first ferroelectric layer pFE1 may be 35 at %. The germanium concentration of each first sacrificial layer SAL1 may be in a range of 15 at % to 25 at %. In an embodiment, the germanium concentration of each first sacrificial layer SAL1 may be 20 at %.

[0061] An intermediate sacrificial layer MSL may be formed on the uppermost first active layer of the first active layer ACL1. The intermediate sacrificial layer MSL may be formed of or include silicon (Si) or silicon germanium (SiGe). When the intermediate sacrificial layer MSL includes silicon germanium (SiGe), the germanium concentration of the intermediate sacrificial layer MSL may be in a range of 45 at % to 55 at %. In an embodiment, the germanium concentration of the intermediate sacrificial layer MSL may be 50 at %.

[0062] Second sacrificial layers SAL2 and second active layers ACL2 may be alternately stacked on the middle sacrificial layer MSL. Each second sacrificial layer SAL2 may be formed of or include the same material as the first sacrificial layer SAL1, and each second active layer ACL2 may be formed of or include the same material as the first active layer ACL1. The middle sacrificial layer MSL may be interposed between the first sacrificial layer SAL1 and the second sacrificial layer SAL2. An initial second ferroelectric layer pFE2 may be formed on the uppermost second active layer of the second active layers ACL2. The initial second ferroelectric layer pFE2 may be formed of or include at least one of silicon (Si), germanium (Ge), or silicon germanium (SiGe). For example, when the initial second ferroelectric layer pFE2 includes silicon germanium (SiGe), the germanium concentration of the initial second ferroelectric layer pFE2 may be in a range of 30 at% to 40 at%. In one embodiment, the germanium concentration of the initial second ferroelectric layer pFE2 may be 35 at%.

[0063] The stacked pattern STP may be formed by patterning the stacked lower sacrificial layer BSL, the initial first ferroelectric layer pFE1, the first sacrificial layer SAL1, the second sacrificial layer SAL2, the middle sacrificial layer MSL, the first active layer ACL1, the second active layer ACL2, and the initial second ferroelectric layer pFE2. Forming the stacked pattern STP may include forming a hard mask pattern on the initial second ferroelectric layer pFE2 and sequentially etching the layers BSL, pFE1, SAL1, ACL1, MSL, SAL2, ACL2, and pFE2 stacked on the substrate 100 using the hard mask pattern as an etch mask. During formation of the stacked pattern STP, the upper portion of the substrate 100 may be patterned to form trenches TR defining the active pattern AP. The stacked pattern STP may be a stripe pattern extending in the second direction D2.

[0064] The stacked pattern STP may include a lower stacked pattern STP1 on the active pattern AP, an upper stacked pattern STP2 on the lower stacked pattern STP1, a lower sacrificial layer BSL between the active pattern AP and the lower stacked pattern STP1, and a middle sacrificial layer MSL between the lower stacked pattern STP1 and the upper stacked pattern STP2. The lower stacked pattern STP1 may include first sacrificial layers SAL1 and first active layers ACL1 that are alternately stacked. The upper stacked pattern STP2 may include second sacrificial layers SAL2 and second active layers ACL2 that are alternately stacked.

[0065] A device isolation layer ST may be formed on the substrate 100 to fill the trench TR. Specifically, an insulating layer may be formed on the substrate 100 to cover the active pattern AP and the stack pattern STP. The device isolation layer ST may be formed by recessing the insulating layer until the stack pattern STP is exposed.

[0066] refer to Figure 4A and Figure 4B A sacrificial pattern PP may be formed to intersect the stacked pattern STP. The sacrificial pattern PP may be formed in a linear shape extending in the first direction D1. Specifically, forming the sacrificial pattern PP may include forming a sacrificial layer on the substrate 100, forming a hard mask pattern MP on the sacrificial layer, and patterning the sacrificial layer using the hard mask pattern MP as an etching mask. The sacrificial layer may be formed of or include amorphous silicon and / or polycrystalline silicon.

[0067] A pair of gate spacers GS may be formed on opposite side surfaces of the sacrificial pattern PP. Specifically, a spacer layer may be conformally formed on the substrate 100. The spacer layer may cover the sacrificial pattern PP and the hard mask pattern MP. For example, the spacer layer may be formed of or include at least one of SiCN, SiCON, or SiN. The gate spacers GS may be formed by anisotropically etching the spacer layer.

[0068] refer to Figure 5A and Figure 5B , a lower cavity BC and a middle cavity MC may be formed. The lower cavity BC and the middle cavity MC may be formed by a first etching process, which is performed to selectively remove the lower sacrificial layer BSL and the middle sacrificial layer MSL. The first etching process may be performed to etch a silicon germanium (SiGe) layer having a relatively high germanium concentration at a high etching rate. For example, the first etching process may be performed to selectively remove a silicon germanium (SiGe) layer having a germanium concentration in the range of 45 at % to 55 at %. The silicon germanium (SiGe) layer having a relatively low germanium concentration may not be etched by the first etching process. Therefore, after the first etching process, the first sacrificial layer SAL1 and the second sacrificial layer SAL2 as well as the initial first ferroelectric layer pFE1 and the initial second ferroelectric layer pFE2 may remain.

[0069] refer to Figure 6A and Figure 6B , a lower insulating layer BDI and a middle insulating layer MDI may be formed. In an embodiment, the lower insulating layer BDI and the middle insulating layer MDI may be formed by filling the lower cavity BC and the middle cavity MC with an insulating material.

[0070] Thereafter, the first cavity C1 and the second cavity C2 can be formed. The first cavity C1 and the second cavity C2 can be formed by a second etching process that selectively etches the initial first ferroelectric layer pFE1 and the initial second ferroelectric layer pFE2. The second etching process can be performed to etch a silicon germanium (SiGe) layer having a relatively medium germanium concentration at a high etching rate. For example, the second etching process can be performed to selectively remove a silicon germanium (SiGe) layer having a germanium concentration in the range of 30 at % to 40 at %. The silicon germanium (SiGe) layer having a relatively low germanium concentration may not be etched by the second etching process. Therefore, after the second etching process, the first sacrificial layer SAL1 and the second sacrificial layer SAL2 may remain.

[0071] refer to Figure 7A and Figure 7B , the first ferroelectric pattern FE1 and the second ferroelectric pattern FE2 may be formed. The first ferroelectric pattern FE1 and the second ferroelectric pattern FE2 may be formed by a process of filling the first cavity C1 and the second cavity C2 with a ferroelectric material.

[0072] refer to Figure 8A and Figure 8B An etching process may be performed on the stack pattern STP using the gate spacer GS and the hard mask pattern MP as an etching mask. A pair of recesses RS may be formed on both sides (ie, opposite sides) of the sacrificial pattern PP through the etching process.

[0073] Liner layers LIN may be formed on opposite side surfaces of the upper stack pattern STP2, respectively. The liner layers LIN may prevent the upper stack pattern STP2 from being exposed to the recess RS. The liner layers LIN may be formed to expose the lower stack pattern STP1. In an embodiment, the liner layers LIN may be formed of or include silicon nitride.

[0074] refer to Figure 9A and Figure 9B , first source / drain patterns SD1 may be formed in the recess RS, respectively. Specifically, a first SEG process using the exposed side surfaces of the lower stack pattern STP1 as a seed layer may be performed to form the first source / drain pattern SD1. The first source / drain pattern SD1 may be grown using the first active layer ACL1 exposed by the recess RS as a seed layer. In an embodiment, the first SEG process may include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process. The first source / drain pattern SD1 may cover the side surfaces of the first ferroelectric pattern FE1. The bottom surface of the first source / drain pattern SD1 may be coplanar with the bottom surface of the first ferroelectric pattern FE1.

[0075] During the first SEG process, impurities may be in-situ implanted into the first source / drain pattern SD1. Alternatively, impurities may be implanted into the first source / drain pattern SD1 after forming the first source / drain pattern SD1. The first source / drain pattern SD1 may be doped to have a first conductivity type (eg, n-type).

[0076] The first active layer ACL1 interposed between the pair of first source / drain patterns SD1 may constitute a first channel pattern CH1. For example, the first semiconductor pattern SP1 and the second semiconductor pattern SP2 of the first channel pattern CH1 may be formed from the first active layer ACL1. The first channel pattern CH1 and the first source / drain pattern SD1 may constitute a first active region AR1, which is a lower tier of the three-dimensional semiconductor device.

[0077] The side surface of the upper stack pattern STP2 may be covered by the liner layer LIN. That is, during the first SEG process, the second active layer ACL2 of the upper stack pattern STP2 may not be exposed to the outside due to the liner layer LIN. Therefore, during the first SEG process, an additional semiconductor layer may not be grown on the upper stack pattern STP2.

[0078] refer to Figure 10A and Figure 10B , a first interlayer insulating layer 110 may be formed to cover the first source / drain pattern SD1. The first interlayer insulating layer 110 may be recessed to have a top surface lower than a bottom surface of a lowermost second active layer among the second active layers ACL2.

[0079] A portion of the liner layer LIN exposed by the recess RS may be removed. Another portion of the liner layer LIN covered by the first interlayer insulating layer 110 may remain to cover the side surface of the middle insulating layer MDI. Due to the partial removal of the liner layer LIN, the second active layer ACL2 may be exposed to the recess RS.

[0080] Second source / drain patterns SD2 may be formed on opposite side surfaces of the upper stack pattern STP2, respectively. Specifically, a second SEG process using the side surfaces of the upper stack pattern STP2 as a seed layer may be performed to form the second source / drain pattern SD2. The second active layer ACL2 exposed to the recess RS may be used as a seed layer to grow the second source / drain pattern SD2. The second source / drain pattern SD2 may cover the side surfaces of the second ferroelectric pattern FE2. The top surface of the second source / drain pattern SD2 may be located at a level higher than the top surface of the second ferroelectric pattern FE2. The second source / drain pattern SD2 may be doped to have a second conductivity type (e.g., p-type) that is different from the first conductivity type.

[0081] The second active layer ACL2 interposed between the pair of second source / drain patterns SD2 may constitute a second channel pattern CH2. For example, the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 of the second channel pattern CH2 may be formed from the second active layer ACL2. The second channel pattern CH2 and the second source / drain pattern SD2 may constitute a second active area AR2, which is an upper layer of the three-dimensional semiconductor device.

[0082] The second interlayer insulating layer 120 may be formed to cover the hard mask pattern MP, the gate spacer GS, and the second source / drain pattern SD2. In an embodiment, the second interlayer insulating layer 120 may include a silicon oxide layer.

[0083] The second interlayer insulating layer 120 may be planarized to expose the top surface of the sacrificial pattern PP. The planarization of the second interlayer insulating layer 120 may be performed using an etch-back process or a chemical mechanical polishing (CMP) process. The hard mask pattern MP may be completely removed by the planarization process. As a result, the top surface of the second interlayer insulating layer 120 may be coplanar with the top surface of the sacrificial pattern PP and the top surface of the gate spacer GS.

[0084] refer to Figure 11A and Figure 11B , the sacrificial pattern PP may be selectively removed. Due to the removal of the sacrificial pattern PP, an outer region ORG exposing the first and second channel patterns CH1 and CH2 may be formed (eg, see FIG. 1 ). Figure 11B ). The removal of the sacrificial pattern PP may include a wet etching process using an etching solution capable of selectively etching polysilicon.

[0085] The first and second sacrificial layers SAL1 and SAL2 exposed through the outer region ORG may be selectively removed to form first to sixth inner regions IRG1 to IRG6 (see, for example, Figure 11B In detail, the third etching process may be performed to selectively remove the first and second sacrificial layers SAL1 and SAL2 and leave the first to fourth semiconductor patterns SP1 to SP4, the lower insulating layer BDI, the first ferroelectric pattern FE1, the middle insulating layer MDI, and the second ferroelectric pattern FE2.

[0086] Due to the selective removal of the first and second sacrificial layers SAL1 and SAL2 , the first and second semiconductor patterns SP1 and SP2 may remain on the first active region AR1 , and the third and fourth semiconductor patterns SP3 and SP4 may remain on the second active region AR2 .

[0087] The empty space between the first ferroelectric pattern FE1 and the first semiconductor pattern SP1 can be called the first internal region IRG1, the empty space between the first semiconductor pattern SP1 and the second semiconductor pattern SP2 can be called the second internal region IRG2, the empty space between the second semiconductor pattern SP2 and the intermediate insulating layer MDI can be called the third internal region IRG3, the empty space between the intermediate insulating layer MDI and the third semiconductor pattern SP3 can be called the fourth internal region IRG4, the empty space between the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 can be called the fifth internal region IRG5, and the empty space between the fourth semiconductor pattern SP4 and the second ferroelectric pattern FE2 can be called the sixth internal region IRG6.

[0088] refer to Figure 12A and Figure 12B A gate insulating layer GI may be conformally formed on the exposed first to fourth semiconductor patterns SP1 to SP4. A first work function metal layer WF1 may be formed on the gate insulating layer GI. The first work function metal layer WF1 may be formed in the first to sixth inner regions IRG1 to IRG6. Furthermore, the first work function metal layer WF1 may be formed in the outer region ORG to cover the second ferroelectric pattern FE2.

[0089] refer to Figure 13A and Figure 13B The first gate electrode GE1 may be formed by removing a portion of the first work function metal layer WF1. The first work function metal layer WF1 may be removed from all regions except the first to third inner regions IRG1 to IRG3. The portions of the first work function metal layer WF1 remaining in the first to third inner regions IRG1 to IRG3 may constitute first to third portions PO1 to PO3. The first gate electrode GE1 may include first to third portions PO1 to PO3.

[0090] Due to the partial removal of the first work function metal layer WF1, the fourth to sixth inner regions IRG4 to IRG6 can be cleared again. In addition, due to the partial removal of the first work function metal layer WF1, the side surfaces of the first gate electrode GE1 and the first channel pattern CH1 can be exposed to the outside. An outer sacrificial layer 101 can be formed on the exposed side surfaces of the first gate electrode GE1. The top surface of the outer sacrificial layer 101 can be higher than the top surface of the third portion PO3 of the first gate electrode GE1 and can be lower than the top surface of the intermediate insulating layer MDI. The outer sacrificial layer 101 can be formed to prevent the side surfaces of the first gate electrode GE1 and the first channel pattern CH1 from being exposed to the outside. Conversely, the outer sacrificial layer 101 can be formed to expose the fourth to sixth inner regions IRG4 to IRG6.

[0091] refer to Figure 14A and Figure 14B , a second work function metal layer WF2 may be formed on the outer sacrificial layer 101 to fill the fourth to sixth inner regions IRG4 to IRG6. In addition, the second work function metal layer WF2 may cover the second ferroelectric pattern FE2.

[0092] refer to Figure 15A and Figure 15B , a portion of the second work function metal layer WF2 may be removed to form the second gate electrode GE2. Next, the second work function metal layer WF2 may be removed from all regions except the fourth to sixth inner regions IRG4 to IRG6. The portions of the second work function metal layer WF2 remaining in the fourth to sixth inner regions IRG4 to IRG6 may constitute fourth to sixth portions PO4 to PO6. The second gate electrode GE2 may include the fourth to sixth portions PO4 to PO6.

[0093] refer to Figure 16A and Figure 16B , an external gate electrode OGE may be formed. The external gate electrode OGE may cover the exposed side surfaces of the first gate electrode GE1 and the second gate electrode GE2 and may extend from the top surface of the device isolation layer ST in the vertical direction D3. The external gate electrode OGE may cover the second ferroelectric pattern FE2. The first gate electrode GE1, the second gate electrode GE2, and the external gate electrode OGE may constitute the gate electrode GE.

[0094] The outer gate electrode OGE may be recessed to have a reduced height. A gate capping pattern GP may be formed on the recessed outer gate electrode OGE. A planarization process may be performed on the gate capping pattern GP so that the top surface of the gate capping pattern GP is coplanar with the top surface of the second interlayer insulating layer 120.

[0095] Reference Figures 2A to 2DFirst to fourth active contacts AC1 to AC4 may be formed on both sides (i.e., opposite sides) of the gate electrode GE. For example, forming the first to fourth active contacts AC1 to AC4 may include forming first to fourth contact holes, forming an active layer to fill the first to fourth contact holes, and planarizing the active layer to expose the top surface of the second interlayer insulating layer 120. An upper separation structure USS may be formed between the first and second active contacts AC1 and AC2 and the second source / drain pattern SD2, respectively. For example, forming the upper separation structure USS may include selectively performing a wet etching process on the second source / drain pattern SD2 to form a recessed region after forming the first and second contact holes, depositing an insulating material in the first and second contact holes, and performing an anisotropic etching process on the insulating material in the first and second contact holes. A lower separation structure LSS may be formed between the third and fourth active contacts AC3 and AC4 and the first source / drain pattern SD1, respectively. The lower separation structure LSS may be formed using the same process as the upper separation structure USS.

[0096] Reference Figure 1 and Figures 2A to 2D A third interlayer insulating layer 130 may be formed on the second interlayer insulating layer 120. A gate contact GC coupled to the gate electrode GE may be formed to penetrate the third interlayer insulating layer 130 and the gate capping pattern GP. Connection lines CNL connected to the first to fourth active contacts AC1 to AC4, respectively, may be formed in the third interlayer insulating layer 130.

[0097] A fourth interlayer insulating layer 140 may be formed on the third interlayer insulating layer 130. A first metal layer M1 may be formed in the fourth interlayer insulating layer 140. The formation of the first metal layer M1 may include forming first to third interconnection lines MI1 to MI3 in an upper portion of the fourth interlayer insulating layer 140.

[0098] A via VI may be formed below each of the first to third interconnect lines MI1 to MI3. As an example, the via VI may be formed before forming the first to third interconnect lines MI1 to MI3. As another example, the via VI and the first to third interconnect lines MI1 to MI3 may be formed by a dual damascene process.

[0099] A plurality of additional metal layers (eg, M2, M3, M4, etc.) may be formed on the first metal layer M1. The first metal layer M1 and the additional metal layers (eg, M2, M3, M4, etc.) may constitute BEOL layers of the semiconductor device.

[0100] Figures 17 to 26 are along Figure 1 A cross-sectional view taken along line AA' of FIG. 1 is provided to illustrate a three-dimensional semiconductor device according to an embodiment. For the sake of simplicity, the previously referenced Figure 1 and Figures 2A to 2D The described elements may be identified with the same reference numerals without repeating their repeated description.

[0101] refer to Figure 17 Spacer patterns 105 may be provided on the side surfaces of the first gate electrode GE1 and the second gate electrode GE2. Some spacer patterns 105 may be interposed between the first gate electrode GE1 and the first source / drain pattern SD1, while other spacer patterns 105 may be interposed between the second gate electrode GE2 and the second source / drain pattern SD2. The spacer patterns 105 can prevent contamination of the source / drain pattern during the manufacturing process. In this manner, the electrical characteristics and reliability of the three-dimensional semiconductor device can be improved.

[0102] refer to Figure 18 , the first portion PO1 of the first gate electrode GE1 can be omitted. The gate insulating layer GI can be disposed between the first semiconductor pattern SP1 of the first channel pattern CH1 and the first ferroelectric pattern FE1. In this regard, the first gate electrode GE1 can include a smaller portion than the second gate electrode GE2. In an embodiment, the lowermost electrode in the first gate electrode GE1 that contacts the first ferroelectric pattern FE1 can be omitted. In this regard, the lower transistor can have an MFIS structure comprising the outer gate electrode OGE, the first ferroelectric pattern FE1, the gate insulating layer GI, and the first semiconductor pattern SP1. Thus, an NCFET device having an MFIS structure can be implemented, while preventing degradation of the interface characteristics between silicon and the ferroelectric material.

[0103] refer to Figure 19 , the first portion PO1 of the first gate electrode GE1 can be omitted. Furthermore, the gate insulating layer GI between the first ferroelectric pattern FE1 and the first semiconductor pattern SP1 can be omitted. That is, the lower transistor can have an MFS structure consisting of the outer gate electrode OGE, the first ferroelectric pattern FE1, and the first semiconductor pattern SP1. Consequently, an NCFET device can be implemented, improving the subthreshold swing characteristics of the transistor and reducing the operating voltage of the NCFET device.

[0104] refer to Figure 20 , the lower insulating layer BDI can be omitted. Figures 2A to 2D Compared with a consistent embodiment, the number of process operations and manufacturing costs can be reduced.

[0105] refer to Figure 21, the sixth portion PO6 of the second gate electrode GE2 may be omitted. The gate insulating layer GI may be disposed between the fourth semiconductor pattern SP4 of the second channel pattern CH2 and the second ferroelectric pattern FE2. The first gate electrode GE1 may include more portions than the second gate electrode GE2. In an embodiment, the uppermost electrode of the second gate electrode GE2 that contacts the second ferroelectric pattern FE2 may be omitted. In this regard, the upper transistor may have an MFIS structure comprising the outer gate electrode OGE, the second ferroelectric pattern FE2, the gate insulating layer GI, and the fourth semiconductor pattern SP4.

[0106] refer to Figure 22 , the first portion PO1 of the first gate electrode GE1 may be omitted. The gate insulating layer GI may be disposed between the first semiconductor pattern SP1 of the first channel pattern CH1 and the first ferroelectric pattern FE1. Furthermore, the sixth portion PO6 of the second gate electrode GE2 may be omitted. The gate insulating layer GI may be disposed between the fourth semiconductor pattern SP4 of the second channel pattern CH2 and the second ferroelectric pattern FE2. In this regard, the lower transistor and the upper transistor may have an MFIS structure.

[0107] refer to Figure 23 , the first portion PO1 of the first gate electrode GE1 may be omitted. Furthermore, the gate insulating layer GI between the first ferroelectric pattern FE1 and the first semiconductor pattern SP1 may be omitted. The sixth portion PO6 of the second gate electrode GE2 may be omitted. The gate insulating layer GI may be disposed between the fourth semiconductor pattern SP4 of the second channel pattern CH2 and the second ferroelectric pattern FE2. In this regard, the lower transistor may have an MFS structure, and the upper transistor may have an MFIS structure.

[0108] refer to Figure 24 , the sixth portion PO6 of the second gate electrode GE2 may be omitted. In addition, the gate insulating layer GI between the second ferroelectric pattern FE2 and the fourth semiconductor pattern SP4 may be omitted. In this regard, the upper transistor may have an MFS structure of the outer gate electrode OGE, the second ferroelectric pattern FE2, and the fourth semiconductor pattern SP4.

[0109] refer to Figure 25 , the sixth portion PO6 of the second gate electrode GE2 may be omitted. Furthermore, the gate insulating layer GI between the second ferroelectric pattern FE2 and the fourth semiconductor pattern SP4 may be omitted. The first portion PO1 of the first gate electrode GE1 may be omitted. The gate insulating layer GI may be disposed between the first semiconductor pattern SP1 of the first channel pattern CH1 and the first ferroelectric pattern FE1. In this regard, the upper transistor may have an MFS structure, and the lower transistor may have an MFIS structure.

[0110] refer to Figure 26, the sixth portion PO6 of the second gate electrode GE2 can be omitted. Furthermore, the gate insulating layer GI between the second ferroelectric pattern FE2 and the fourth semiconductor pattern SP4 can be omitted. The first portion PO1 of the first gate electrode GE1 can be omitted. Furthermore, the gate insulating layer GI between the first ferroelectric pattern FE1 and the first semiconductor pattern SP1 can be omitted. In this regard, the upper and lower transistors can have an MFS structure.

[0111] In a three-dimensional semiconductor device according to an embodiment, the lower transistor may include a ferroelectric material. Thus, the lower transistor may function as a negative capacitance field-effect transistor (NCFET). In this case, the subthreshold swing characteristics of the transistor may be improved, and the operating voltage of the transistor may be reduced.

[0112] While aspects of the embodiments have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

[0113] This application claims the benefit of Korean Patent Application No. 10-2024-0024476 filed on February 20, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A three-dimensional semiconductor device, comprising: a first active region on a substrate, the first active region including a first channel pattern and a first source / drain pattern connected to the first channel pattern; a second active region stacked on the first active region, the second active region including a second channel pattern and a second source / drain pattern connected to the second channel pattern; a gate electrode disposed on the first channel pattern and the second channel pattern; as well as a first ferroelectric pattern interposed between the substrate and the first channel pattern, wherein the first channel pattern includes a first semiconductor pattern and a second semiconductor pattern spaced apart from each other in a vertical direction perpendicular to a top surface of the substrate, wherein the first ferroelectric pattern is interposed between the substrate and the first semiconductor pattern and is disposed on one side of the first source / drain pattern, and The gate electrode includes a first gate electrode interposed between the first semiconductor pattern and the second semiconductor pattern. 2 . The three-dimensional semiconductor device according to claim 1 , further comprising a gate insulating layer interposed between each of the first and second semiconductor patterns and the first gate electrode. 3 . The three-dimensional semiconductor device according to claim 1 , further comprising a gate insulating layer interposed between each of the first semiconductor pattern and the second semiconductor pattern and the first gate electrode, The first gate electrode comprises: a first portion interposed between the first ferroelectric pattern and the first semiconductor pattern; a second portion interposed between the first semiconductor pattern and the second semiconductor pattern; as well as A third portion is disposed on the second semiconductor pattern.

4. The three-dimensional semiconductor device according to claim 3, further comprising a second ferroelectric pattern disposed on the second channel pattern and on one side of the second source / drain pattern, wherein the second channel pattern includes a third semiconductor pattern and a fourth semiconductor pattern spaced apart from each other in the vertical direction, wherein the gate electrode further includes a second gate electrode and an outer gate electrode, the second gate electrode being interposed between the third semiconductor pattern and the fourth semiconductor pattern, the outer gate electrode being provided on the fourth semiconductor pattern, and The second ferroelectric pattern is interposed between the fourth semiconductor pattern and the outer gate electrode. 5 . The three-dimensional semiconductor device according to claim 4 , wherein the gate insulating layer extends between the third semiconductor pattern and the second gate electrode, between the fourth semiconductor pattern and the second gate electrode, and between the fourth semiconductor pattern and the second ferroelectric pattern.

6. The three-dimensional semiconductor device according to claim 4, wherein the second gate electrode comprises: a fourth portion disposed under the third semiconductor pattern; a fifth portion interposed between the third semiconductor pattern and the fourth semiconductor pattern; as well as a sixth portion interposed between the fourth semiconductor pattern and the second ferroelectric pattern, and The gate insulating layer extends between the third semiconductor pattern and the second gate electrode and between the fourth semiconductor pattern and the second gate electrode. 7 . The three-dimensional semiconductor device according to claim 1 , further comprising a lower insulating layer interposed between the substrate and the first ferroelectric pattern. 8 . The three-dimensional semiconductor device according to claim 1 , further comprising an intermediate insulating layer interposed between the first channel pattern and the second channel pattern.

9. The three-dimensional semiconductor device according to claim 1 , wherein the first source / drain pattern has a first conductivity type, and The second source / drain pattern has a second conductivity type different from the first conductivity type.

10. A three-dimensional semiconductor device comprising: a first active region on a substrate, the first active region including a first channel pattern and first source / drain patterns disposed on opposite sides of the first channel pattern, wherein the first channel pattern includes a plurality of lower semiconductor patterns spaced apart from each other in a vertical direction perpendicular to a top surface of the substrate; a second active region stacked on the first active region, the second active region including a second channel pattern and a second source / drain pattern disposed on an opposite side of the second channel pattern; a gate electrode disposed on the first channel pattern and the second channel pattern, the gate electrode including a first gate electrode between the first source / drain patterns, a second gate electrode between the second source / drain patterns, and an outer gate electrode on the second channel pattern; as well as A first ferroelectric pattern is interposed between a lowermost lower semiconductor pattern among the plurality of lower semiconductor patterns and the substrate and between the first source / drain patterns.

11. The three-dimensional semiconductor device according to claim 10 , wherein the first gate electrode is interposed between the plurality of lower semiconductor patterns, and The three-dimensional semiconductor device further includes a gate insulating layer interposed between each of the plurality of lower semiconductor patterns and the first gate electrode and between the lowermost lower semiconductor pattern among the plurality of lower semiconductor patterns and the first ferroelectric pattern.

12. The three-dimensional semiconductor device according to claim 10, wherein the first gate electrode comprises: a lower inner electrode interposed between the plurality of lower semiconductor patterns; as well as a lowermost electrode interposed between the first ferroelectric pattern and the lowermost lower semiconductor pattern among the plurality of lower semiconductor patterns, and The three-dimensional semiconductor device further includes a gate insulating layer interposed between each of the plurality of lower semiconductor patterns and the first gate electrode.

13. The three-dimensional semiconductor device according to claim 12, further comprising a second ferroelectric pattern disposed on the second channel pattern and interposed between the second source / drain patterns, wherein the second channel pattern includes a plurality of upper semiconductor patterns spaced apart from each other in the vertical direction, wherein the second gate electrode is interposed between the plurality of upper semiconductor patterns, and The second ferroelectric pattern is interposed between an uppermost upper semiconductor pattern among the plurality of upper semiconductor patterns and the outer gate electrode. 14 . The three-dimensional semiconductor device according to claim 13 , wherein the gate insulating layer extends between each of the plurality of upper semiconductor patterns and the second gate electrode and between the uppermost upper semiconductor pattern among the plurality of upper semiconductor patterns and the second ferroelectric pattern.

15. The three-dimensional semiconductor device according to claim 13, wherein the second gate electrode comprises: an upper inner electrode interposed between the plurality of upper semiconductor patterns; as well as an uppermost electrode interposed between the uppermost upper semiconductor pattern among the plurality of upper semiconductor patterns and the second ferroelectric pattern, and wherein the gate insulating layer extends between each of the plurality of upper semiconductor patterns and the second gate electrode.

16. The three-dimensional semiconductor device according to claim 10, further comprising: a lower insulating layer interposed between the substrate and the first ferroelectric pattern; as well as An intermediate insulating layer is interposed between the first channel pattern and the second channel pattern.

17. A three-dimensional semiconductor device comprising: a substrate including an active pattern; a lower insulating layer disposed on the active pattern; a first active region on the lower insulating layer, the first active region including a first channel pattern and a first source / drain pattern disposed on opposite sides of the first channel pattern, the first channel pattern including a first semiconductor pattern and a second semiconductor pattern spaced apart from the first semiconductor pattern in a vertical direction perpendicular to a top surface of the substrate; a second active region stacked on the first active region, the second active region including a second channel pattern and a second source / drain pattern disposed on an opposite side of the second channel pattern, the second channel pattern including a third semiconductor pattern and a fourth semiconductor pattern spaced apart from the third semiconductor pattern in the vertical direction; a gate electrode disposed on the first channel pattern and the second channel pattern and extending in the vertical direction; an intermediate insulating layer interposed between the first channel pattern and the second channel pattern; a first ferroelectric pattern interposed between the substrate and the first semiconductor pattern and between the first source / drain patterns; as well as A second ferroelectric pattern is provided on the fourth semiconductor pattern and interposed between the second source / drain patterns.

18. The three-dimensional semiconductor device according to claim 17 , wherein the gate electrode comprises a first gate electrode between the first semiconductor pattern and the second semiconductor pattern, a second gate electrode between the third semiconductor pattern and the fourth semiconductor pattern, and an external gate electrode disposed on the fourth semiconductor pattern and connected to the first gate electrode and the second gate electrode, The first gate electrode comprises: a first portion interposed between the first ferroelectric pattern and the first semiconductor pattern; a second portion interposed between the first semiconductor pattern and the second semiconductor pattern; as well as a third portion disposed on the second semiconductor pattern, The second gate electrode comprises: a fourth portion disposed under the third semiconductor pattern; a fifth portion interposed between the third semiconductor pattern and the fourth semiconductor pattern; and a sixth portion interposed between the fourth semiconductor pattern and the second ferroelectric pattern, and The three-dimensional semiconductor device further includes a gate insulating layer, which is interposed between the first semiconductor pattern and the first gate electrode, between the second semiconductor pattern and the first gate electrode, between the third semiconductor pattern and the second gate electrode, and between the fourth semiconductor pattern and the second gate electrode.

19. The three-dimensional semiconductor device according to claim 18, further comprising: a first active contact and a second active contact electrically connected to the first source / drain pattern; as well as A third active contact and a fourth active contact are electrically connected to the second source / drain pattern. 20 . The three-dimensional semiconductor device according to claim 19 , further comprising a metal layer on each of the first to fourth active contacts, The metal layer includes an interconnection line electrically connected to the first active contact to the fourth active contact.

Images