Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the structure comprises a substrate which comprises a channel region and source and drain regions located at the two sides of the channel region; the insulating layer is positioned at the top of the substrate in the channel region; the channel structure layer is suspended at the top of the insulating layer, and the channel structure layer comprises one or more channel layers which are arranged at intervals in the longitudinal direction; the device gate structure is positioned above the insulating layer and surrounds and covers the channel structure layer; and the source-drain doping layer is located at the top of the substrate in the source-drain region on the two sides of the device gate structure, and the source-drain doping layer covers the side wall of the channel structure layer. And the risk of generating leakage current in the semiconductor structure is reduced, so that the performance of the semiconductor structure is improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor transistors are moving towards higher component density and higher integration, and semiconductor process nodes are continuously decreasing in accordance with Moore's Law. Transistors, as the most basic semiconductor transistors, are currently widely used. Therefore, as the component density and integration of semiconductor transistors increase, in order to adapt to the reduction of process nodes, the channel length of transistors must be continuously shortened.

[0003] To better adapt to the requirement of scaling down transistor size, semiconductor processes have gradually begun to transition from planar transistors to more efficient three-dimensional transistors, such as FinFETs and Gate-all-around (GAA) transistors. Among them, GAA transistors include vertical GAA transistors and horizontal GAA transistors. In GAA transistors, the gate surrounds the channel area on all sides. Compared with planar transistors, the gate of GAA transistors has stronger control over the channel and can better suppress short channel effects.

[0004] Currently, the performance of gate-all-around (GAA) transistors still needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which are beneficial to further improve the performance of the semiconductor structure.

[0006] To solve the above problems, the present invention provides a semiconductor structure, comprising: a substrate, the substrate including a channel region and source / drain regions located on both sides of the channel region; an insulating layer located on the top of the substrate in the channel region; a channel structure layer suspended on the top of the insulating layer, the channel structure layer including one or more channel layers spaced apart in the vertical direction; a device gate structure located above the insulating layer and surrounding and covering the channel structure layer; and source / drain doping layers located on the top of the substrate in the source / drain regions on both sides of the device gate structure, the source / drain doping layers covering the sidewalls of the channel structure layer.

[0007] Optionally, the insulating layer contains doped ions; or, the insulating layer is an epitaxial growth layer.

[0008] Optionally, the concentration of doping ions in the insulating layer is 3×10 14 cm -2 to 5×10 14 cm-2 .

[0009] Optionally, the doping ions in the insulating layer include boron ions.

[0010] Optionally, the material of the insulating layer includes silicon boride.

[0011] Optionally, the semiconductor structure further includes: an inner wall spacer layer, located between the side wall of the device gate structure directly below the channel layer and the source / drain doping layer; and a bottom isolation layer, located between the source / drain doping layer and the substrate.

[0012] Optionally, the device gate structure includes a gate dielectric layer surrounding the covering channel structure layer, and a gate electrode layer covering the gate dielectric layer; the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3; the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0013] Correspondingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, comprising a channel region and source / drain regions located on both sides of the channel region; forming an insulating layer on top of the substrate in the channel region and the source / drain region; forming a stacked structure on top of the insulating layer, and a gate structure located on the substrate in the channel region and spanning the stacked structure, the gate structure covering part of the top and part of the sidewalls of the stacked structure, the stacked structure comprising one or more channel stacks stacked in sequence in the longitudinal direction, the channel stack comprising a sacrificial layer and a channel layer located on the sacrificial layer; forming grooves located in the source / drain region in the stacked structure and the insulating layer on both sides of the gate structure, the sidewalls of the grooves exposing the stacked structure and the insulating layer; forming a source / drain doping layer in the groove, the source / drain doping layer covering the sidewalls of the stacked structure and the insulating layer.

[0014] Optionally, the step of forming the insulating layer includes: providing a base material layer; doping a portion of the base material layer to form an insulating layer, and using the undoped base material layer as the base; or, the step of forming the insulating layer includes: forming an insulating layer on top of the base through an epitaxial growth process.

[0015] Optionally, the process of performing doping treatment on a partial thickness of the base material layer includes an ion implantation process.

[0016] Optionally, the parameters of the ion implantation process include: doping ions include boron ions; the doping dose is 3×10 14 cm -2 to 5×10 14 cm -2 .

[0017] Optionally, the material of the insulating layer includes silicon boride.

[0018] Optionally, the step of forming grooves in the source / drain regions in the stacked structure and the insulating layer on both sides of the gate structure includes: etching away the stacked structure and the insulating layer in the source / drain regions to form grooves in the source / drain regions.

[0019] Optionally, after forming the groove and before forming the source-drain doping layer, the method further includes: laterally etching a portion of the sacrificial layer exposed on the sidewall of the groove in a direction parallel to the substrate and perpendicular to the extension direction of the gate structure to form an opening, wherein the opening is surrounded by the adjacent channel layer and the remaining sacrificial layer, or the opening is surrounded by the insulating layer, the channel layer adjacent to the insulating layer, and the remaining sacrificial layer; and forming an inner wall sidewall layer in the opening.

[0020] Optionally, the step of forming an inner wall spacer layer in the opening further includes: forming a bottom isolation layer on the top of the substrate in the source and drain regions; in the step of forming the source and drain doping layer, the source and drain doping layer covers the top of the bottom isolation layer.

[0021] Optionally, the step of forming an inner wall sidewall layer in the opening includes: forming an inner wall sidewall material layer on the top and sidewalls of the gate structure, the sidewalls of the stacked structure, the sidewalls of the insulating layer, and the bottom of the groove, and the inner wall sidewall material layer is also filled in the opening; removing the inner wall sidewall material layer from the top and sidewalls of the gate structure, the sidewalls of the insulating layer, and the sidewalls of the channel layer, and the remaining inner wall sidewall material layer located in the opening serves as the inner wall sidewall layer, and the remaining inner wall sidewall material layer located at the bottom of the groove serves as the bottom isolation layer.

[0022] Optionally, the material of the inner wall spacer layer includes one or more of silicon nitride, silicon carbonitride and nitrogen-doped silicon oxide.

[0023] Optionally, after forming the source and drain doping layers, the method for forming the semiconductor structure also includes: forming an interlayer dielectric layer on top of the source and drain doping layers, the interlayer dielectric layer covering the side walls of the gate structure; removing the gate structure, and forming a gate opening in the interlayer dielectric layer; removing the sacrificial layer exposed by the gate opening, and forming a through groove connected to the gate opening under the channel layer; forming a device gate structure in the gate opening and the through groove, the device gate structure surrounds the channel layer, and the device gate structure covers the top of the insulating layer.

[0024] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0025] An embodiment of the present invention provides a method for forming a semiconductor structure, which includes first forming an insulating layer on the top of a substrate in a channel region and a source / drain region, and then forming a stacked structure on top of the insulating layer, as well as a gate structure located on the substrate in the channel region and spanning the stacked structure, wherein the gate structure covers a portion of the top and a portion of the sidewalls of the stacked structure. The stacked structure includes one or more channel stacks stacked in sequence in the vertical direction, and the channel stack includes a sacrificial layer and a channel layer located on the sacrificial layer. Compared with a solution in which the sacrificial layer is removed after the stacked structure is formed and then an insulating layer is formed in the region where the sacrificial layer is removed, the embodiment of the present invention forms the insulating layer before forming the stacked structure, thereby reducing the process difficulty of forming the insulating layer and eliminating the step of removing the sacrificial layer, thereby avoiding the risk of part of the sacrificial layer remaining during the removal of the sacrificial layer, and improving the electrical isolation effect of the insulating layer on adjacent source / drain doped layers, that is, reducing the probability of adjacent source / drain doped layers punching through through the bottom of a subsequently formed device gate structure, thereby reducing the risk of leakage current in the semiconductor structure, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0027] Figures 2 to 14 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0028] Currently, the performance of all-around gate transistors still needs to be improved. Specifically, in the current process for forming all-around gate transistors, a sacrificial layer is first formed on top of the substrate, and then a stacked structure is formed on top of the sacrificial layer. The sacrificial layer is then removed, and an insulating layer is formed in the area where the sacrificial layer is removed. However, during the process of removing the sacrificial layer, the distance between the stacked structure and the substrate is relatively small, resulting in a small process window for removing the sacrificial layer, which increases the difficulty of removing the sacrificial layer and, in particular, increases the probability of the sacrificial layer remaining on the bottom surface of the stacked structure. Subsequently, during the process of filling the insulating layer, the remaining sacrificial layer causes the quality of the insulating layer to be poor, and the insulating layer does not completely fill the area between the stacked structure and the substrate. Accordingly, when the transistor is subsequently put into operation, there is a risk of leakage between adjacent source and drain doped layers through the gaps in the insulating layer, thereby affecting the performance of the semiconductor structure.

[0029] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, including a channel region and source and drain regions located on both sides of the channel region; forming an insulating layer on the top of the substrate in the channel region and the source and drain regions; forming a stacked structure on the top of the insulating layer, and a gate structure located on the substrate in the channel region and spanning the stacked structure, the gate structure covering part of the top and part of the sidewalls of the stacked structure, the stacked structure including one or more channel stacks stacked in sequence in the longitudinal direction, the channel stack including a sacrificial layer and a channel layer located on the sacrificial layer; forming grooves located in the source and drain regions in the stacked structure and the insulating layer on both sides of the gate structure, the sidewalls of the grooves exposing the stacked structure and the insulating layer; forming source and drain doping layers in the grooves, the source and drain doping layers covering the sidewalls of the stacked structure and the insulating layer.

[0030] In an embodiment of the present invention, an insulating layer is first formed on the top of the substrate in the channel region and the source / drain region, and then a stacked structure and a gate structure located on the substrate in the channel region and spanning the stacked structure are formed on top of the insulating layer. The gate structure covers part of the top and part of the sidewall of the stacked structure. The stacked structure includes one or more channel stacks stacked in sequence in the vertical direction. The channel stack includes a sacrificial layer and a channel layer located on the sacrificial layer. Compared with the solution of removing the sacrificial layer after forming the stacked structure and then forming an insulating layer in the area where the sacrificial layer is removed, in an embodiment of the present invention, the insulating layer is formed before forming the stacked structure, which reduces the process difficulty of forming the insulating layer and eliminates the step of removing the sacrificial layer, thereby avoiding the risk of part of the sacrificial layer remaining during the removal of the sacrificial layer, and improving the electrical isolation effect of the insulating layer on adjacent source / drain doped layers, that is, reducing the probability of adjacent source / drain doped layers punching through through the bottom of the subsequently formed device gate structure, thereby reducing the risk of leakage current in the semiconductor structure, thereby improving the performance of the semiconductor structure.

[0031] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0032] Figure 1 FIG. 1 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.

[0033] The semiconductor structure includes: a substrate 200, the substrate 200 includes a channel region 200A and source / drain regions 200B located on both sides of the channel region 200A; an insulating layer 201, located on the top of the substrate 200 in the channel region 200A; a channel structure layer 202, suspended on the top of the insulating layer 201, the channel structure layer 202 includes one or more channel layers 2022 spaced apart in the vertical direction; a device gate structure 266, located above the insulating layer 201 and surrounding and covering the channel structure layer 202; a source / drain doping layer 260, located on the top of the substrate 200 in the source / drain regions 200B on both sides of the device gate structure 266, and the source / drain doping layer 260 covers the sidewalls of the channel structure layer 202.

[0034] It should be noted that, in the process of forming the semiconductor structure, the difficulty of forming the insulating layer 201 is reduced, and the electrical isolation effect of the insulating layer 201 on adjacent source-drain doped layers 260 is improved, that is, the probability of adjacent source-drain doped layers 260 punching through through the bottom of the subsequently formed device gate structure 266 is reduced, thereby reducing the risk of leakage current in the semiconductor structure, thereby improving the performance of the semiconductor structure.

[0035] The substrate 200 is used to provide a process platform for configuring a gate-all-around (GAA) transistor.

[0036] In this embodiment, the base 200 is a silicon substrate. In other embodiments, the substrate material may be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. The substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0037] In this embodiment, the channel region 200A is a region where the device gate structure 266 is disposed, and the source / drain region 200B is a region where the source / drain doping layer 260 is disposed.

[0038] Specifically, the insulating layer 201 has the effect of electrically isolating adjacent source-drain doped layers 260, thereby reducing the probability of adjacent source-drain doped layers 260 punching through the bottom of the subsequently formed device gate structure 266, thereby reducing the risk of leakage current in the semiconductor structure, thereby improving the performance of the semiconductor structure.

[0039] In this embodiment, the insulating layer 201 has doping ions.

[0040] It should be noted that, in the process of forming the semiconductor structure, an ion implantation process is performed to allow the insulating layer 201 to have dopant ions.

[0041] As an example, the doping ions in the insulating layer 201 include boron ions.

[0042] Specifically, the outer layer of the boron ion is 3 electrons, and after doping, it forms a P-type semiconductor. The carriers are holes, and the mobility is low. After doping, a higher electric field strength is required to form leakage current. Therefore, boron doping increases the voltage threshold required for the formation of leakage current and inhibits the formation of leakage current.

[0043] It should be noted that the concentration of doped ions in the insulating layer 201 should not be too large or too small. If the concentration of doped ions in the insulating layer 201 is too large, it is difficult to control the diffusion range of the doped ions, resulting in the setting area of ​​the insulating layer 201 being too large. When the semiconductor structure is in a working state, the heat dissipation effect of the substrate 200 is affected, thereby affecting the performance of the semiconductor structure; if the concentration of doped ions in the insulating layer 201 is too small, it is easy to cause the insulating layer 201 to fail to ensure the electrical isolation effect between adjacent source and drain doped layers 260, increasing the probability of penetration between adjacent source and drain doped layers 260 through the bottom of the device gate structure 266 formed subsequently, thereby affecting the performance of the semiconductor structure. For this reason, in this embodiment, the concentration of doped ions in the insulating layer 201 is 3×10 14 cm -2 to 5×10 14 cm -2 .

[0044] In this embodiment, the material of the insulating layer 201 includes silicon boride.

[0045] Specifically, silicon boride is a dielectric material with good insulation performance, and can electrically isolate adjacent source-drain doped layers 260 formed subsequently, thereby reducing the probability of leakage between adjacent source-drain doped layers 260 .

[0046] In other embodiments, the insulating layer is an epitaxial growth layer, that is, in the process of forming the insulating layer, the insulating layer is formed on top of the substrate through an epitaxial growth process.

[0047] Specifically, the channel structure layer 202 is used as a conductive channel of a transistor.

[0048] In this embodiment, the channel structure layer 202 includes a plurality of channel layers 2022 that are spaced apart from each other, and the stacking direction of the plurality of stacked channel layers 2022 is perpendicular to the substrate surface.

[0049] In this embodiment, the material of the channel structure layer 202 is silicon.

[0050] The device gate structure 266 is used to control the opening and closing of the conductive channel when the device is in operation.

[0051] Specifically, the device gate structure 266 is a metal gate structure.

[0052] In this embodiment, the device gate structure 266 includes a gate dielectric layer surrounding and covering the channel structure layer 202 , and a gate electrode layer covering the gate dielectric layer.

[0053] In this embodiment, the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.

[0054] Specifically, the gate dielectric layer includes a gate oxide layer surrounding and covering the channel layer 2022, and a high-k gate dielectric layer surrounding and covering the gate oxide layer. The high-k gate dielectric layer is made of a high-k dielectric material, which refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide.

[0055] The gate electrode layer is used for subsequent electrical connection to external structures. The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. Specifically, the gate electrode layer may include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer may include only the work function layer.

[0056] In this embodiment, the semiconductor structure further includes a spacer layer 203 located on the sidewall of the device gate structure 266 .

[0057] Specifically, the spacer layer 203 is used to protect the sidewalls of the device gate structure 266 .

[0058] In this embodiment, the spacer layer 203 is a single-layer structure, and the material of the spacer layer 203 is silicon nitride.

[0059] Specifically, the source-drain doping layer 260 is used as the source region and the drain region of the transistor.

[0060] Among them, when the fully enclosed gate transistor is a P-type MOS transistor, the material of the stress layer is Si or SiGe, and the doped ions in the source and drain doping layer 260 are P-type ions; when the fully enclosed gate transistor is an N-type MOS transistor, the material of the stress layer is Si or SiC, and the doped ions in the source and drain doping layer 260 are N-type ions.

[0061] In this embodiment, the semiconductor structure further includes an inner wall spacer 210 located between the sidewall of the device gate structure 266 and the source / drain doping layer 260 directly below the channel layer 2022 .

[0062] Specifically, the inner wall spacer layer 210 can electrically isolate the source-drain doped layer 260 and the device gate structure 266, which is beneficial to increase the distance between the source-drain doped layer 260 and the device gate structure 266, and further beneficial to reduce the parasitic capacitance between the source-drain doped layer 260 and the device gate structure 266.

[0063] In this embodiment, the material of the inner wall spacer layer 210 includes one or more of silicon nitride, silicon carbonitride, and nitrogen-doped silicon oxide.

[0064] It should be noted that silicon nitride, silicon carbonitride and nitrogen-doped silicon oxide are all dielectric materials, so that the inner wall spacer layer 210 can play an electrical isolation role.

[0065] In this embodiment, the semiconductor structure further includes a bottom isolation layer 250 located between the source / drain doped layer 260 and the substrate 200 .

[0066] Specifically, the bottom isolation layer 250 is used to electrically isolate the subsequently formed source-drain doped layer 260 from the substrate 200 , while also reducing the risk of leakage from the adjacent source-drain doped layer 260 through the substrate 200 thereunder, thereby further improving the performance of the semiconductor structure.

[0067] It should be noted that, in the process of forming the semiconductor structure, the inner wall spacer layer 210 and the bottom isolation layer 250 are formed in the same step, which can reduce the number of process steps and lower the process cost.

[0068] It should also be noted that the bottom isolation layer 250 and the inner wall sidewall layer 210 are formed in the same step. Therefore, the material of the bottom isolation layer 250 and the inner wall sidewall layer 210 is the same, and the material of the bottom isolation layer 250 includes one or more of silicon nitride, silicon carbonitride and nitrogen-doped silicon oxide.

[0069] In this embodiment, the semiconductor structure further includes an interlayer dielectric layer 261 , which is located on top of the source / drain doped layer 260 and covers the sidewalls of the device gate structure 266 .

[0070] The interlayer dielectric layer 261 is used to achieve electrical isolation between adjacent devices.

[0071] In this embodiment, the material of the interlayer dielectric layer 261 is silicon oxide.

[0072] Figures 2 to 14 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0073] refer to Figures 2 to 3 , providing a substrate 100 including a channel region 100B and source / drain regions 100A located on both sides of the channel region 100B.

[0074] The substrate 100 is used to provide a process platform for forming a gate-all-around (GAA) transistor.

[0075] In this embodiment, the base 100 is a silicon substrate. In other embodiments, the substrate material may be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0076] In this embodiment, the channel region 100B is a region where a device gate structure is subsequently formed, and the source / drain region 100A is a region where a source / drain doping layer is subsequently formed.

[0077] Continue to refer to Figures 2 to 3 , an insulating layer 101 is formed on the top of the substrate in the channel region 100B and the source / drain region 100A.

[0078] It should be noted that, compared with the solution of removing the sacrificial layer after forming the stacked structure and then forming the insulating layer 101 in the area where the sacrificial layer is removed, the present embodiment forms the insulating layer 101 before the subsequently formed stacked structure, thereby reducing the process difficulty of forming the insulating layer 101 and eliminating the step of removing the sacrificial layer, thus avoiding the risk of part of the sacrificial layer remaining in the process of removing the sacrificial layer, and improving the effect of the insulating layer 101 in electrically isolating adjacent source and drain doped layers, that is, reducing the probability of punchthrough of adjacent source and drain doped layers through the bottom of the subsequently formed device gate structure, thereby reducing the risk of leakage current in the semiconductor structure, thereby improving the performance of the semiconductor structure.

[0079] It should also be noted that the insulating layer 101 is formed before the stacked structure is subsequently formed, thereby avoiding the risk of the process of forming the insulating layer 101 causing damage to the subsequently formed channel layer.

[0080] In this embodiment, the steps of forming the insulating layer 101 include: Figure 2 As shown, a base material layer 199 is provided; Figure 3 As shown, a partial thickness of the base material layer 199 is doped to form the insulating layer 101 , and the base material layer that has not been doped is used as the base 100 .

[0081] It should be noted that, during the process of performing the doping treatment on the base material layer having a partial thickness, an ion-doped layer (not shown) is formed in the base material layer, and the ion-doped layer is used as the insulating layer 101 .

[0082] As an example, the process of doping a portion of the base material layer 199 includes an ion implantation process.

[0083] It should be noted that the ion implantation process has the characteristics of fast process rate and high process controllability. The ion implantation process is used to dope the substrate of the channel area 100B, which can accurately control the formation position of the ion doping layer and the depth of the ion doping layer in the substrate material layer, so that the insulating layer 101 formed in the substrate material layer can play the role of electrical isolation.

[0084] In this embodiment, the doping ions in the ion implantation process include boron ions.

[0085] Specifically, the outer layer of the boron ion is 3 electrons, and after doping, it forms a P-type semiconductor. The carriers are holes, and the mobility is low. After doping, a higher electric field strength is required to form leakage current. Therefore, boron doping increases the voltage threshold required for the formation of leakage current and inhibits the formation of leakage current.

[0086] It should be noted that the doping dose in the ion implantation process should not be too large or too small. If the doping dose is too large, it is difficult to control the diffusion range of the implanted ions, resulting in a too large formation area of ​​the insulating layer 101. When the semiconductor structure is in a working state, the heat dissipation effect of the substrate is affected, thereby affecting the performance of the semiconductor structure. If the doping dose is too small, it is easy to cause the insulating layer 101 to fail to ensure the electrical isolation effect between adjacent source and drain doping layers, increasing the probability of punch-through between adjacent source and drain doping layers through the bottom of the subsequently formed device gate structure, thereby affecting the performance of the semiconductor structure. For this reason, in this embodiment, the doping dose in the ion implantation process is 3×10 14 cm -2 to 5×10 14 cm -2 .

[0087] In this embodiment, the material of the insulating layer 101 includes silicon boride.

[0088] Specifically, silicon boride is a dielectric material with good insulation performance, and can electrically isolate adjacent source and drain doped layers formed subsequently, thereby reducing the probability of leakage between adjacent source and drain doped layers.

[0089] In other embodiments, the step of forming the insulating layer may further include: forming the insulating layer on top of the substrate by an epitaxial growth process.

[0090] refer to Figures 4 and 5A stacked structure 198 is formed on top of the insulating layer 101, as well as a gate structure 104 located on the substrate of the channel region 100B and spanning the stacked structure 198. The gate structure 104 covers part of the top and part of the sidewall of the stacked structure 198. The stacked structure 198 includes one or more channel stacks 102 stacked in sequence in the longitudinal direction. The channel stack 102 includes a sacrificial layer 1021 and a channel layer 1022 located on the sacrificial layer 1021.

[0091] Specifically, the stacked structure 198 is used to provide a conductive channel for the transistor.

[0092] In this embodiment, the stacked structure 198 includes one or more channel stacks 102 stacked in sequence in the longitudinal direction. The channel stack 102 includes a sacrificial layer 1021 and a channel layer 1022 located on the sacrificial layer 1021 .

[0093] In this embodiment, the channel stack 102 is located above the substrate.

[0094] In this embodiment, there are multiple channel stacks 102 , and the stacking direction of the multiple stacked channel stacks 102 is perpendicular to the substrate surface.

[0095] Each channel stack 102 includes a sacrificial layer 1021 and a channel layer 1022 located on the sacrificial layer 1021. The channel stack 102 provides a process foundation for the subsequent formation of the suspended channel layer 1022. Specifically, the sacrificial layer 1021 supports the channel layer 1022, thereby providing a process foundation for the subsequent suspended arrangement of the channel layer 1022. It also occupies a space for the subsequent formation of the device gate structure. The channel layer 1022 is used to provide a conductive channel for the fully enclosed gate transistor.

[0096] In this embodiment, the material of the channel layer 1022 is Si, and the material of the sacrificial layer 1021 is SiGe. During the subsequent removal of the sacrificial layer 1021, SiGe and Si have relatively high etching selectivity. Therefore, by setting the material of the sacrificial layer 1021 to SiGe and the material of the channel layer 1022 to Si, the impact of the sacrificial layer 1021 removal process on the channel layer 1022 can be effectively reduced, thereby improving the quality of the channel layer 1022 and further improving device performance.

[0097] In this embodiment, the gate structure 104 is a dummy gate structure, and the gate structure 104 occupies a space position for a gate structure of a device to be formed subsequently.

[0098] In this embodiment, the gate structure 104 includes a dummy gate layer.

[0099] The material of the dummy gate layer includes polysilicon.

[0100] Continue to refer Figure 6 , a spacer layer 103 is formed on the sidewall of the gate structure 104 .

[0101] Specifically, the spacer layer 103 is used to define the formation area of ​​the source and drain doped layers, and is also used to protect the sidewalls of the gate structure 104 .

[0102] In this embodiment, the step of forming the sidewall layer 103 includes: forming a sidewall material layer (not shown) on the top and sidewalls of the gate structure 104, and on the top of the stacked structure 198 exposed by the gate structure 104; removing the sidewall material layer on the top of the stacked structure 198 exposed by the gate structure 104, and the sidewall material layer on the top of the gate structure 104, and the remaining sidewall material layer located on the sidewall of the gate structure 104 serves as the sidewall layer 103.

[0103] In this embodiment, the spacer layer 103 is a single-layer structure, and the material of the spacer layer 103 is silicon nitride.

[0104] refer to Figure 7 A groove 107 located in the source / drain region 100A is formed in the stacked structure 198 and the insulating layer 101 on both sides of the gate structure 104 , and the sidewall of the groove 107 exposes the stacked structure 198 and the insulating layer 101 .

[0105] The groove 107 provides a space for the subsequent formation of source and drain doping layers.

[0106] As an example, the step of forming a groove 107 located in the source-drain region 100A in the stacked structure 198 and the insulating layer 101 on both sides of the gate structure 104 includes: etching away the stacked structure 198 and the insulating layer 101 in the source-drain region 100A, and forming a groove 107 in the source-drain region 100A.

[0107] Specifically, removing the insulating layer 101 in the source / drain region 100A can further increase the volume of the subsequently formed source / drain doped layer, thereby increasing the channel stress generated by the source / drain doped layer.

[0108] In this embodiment, the process of forming the groove 107 includes a dry etching process.

[0109] Specifically, the dry etching process is an anisotropic dry etching process. The anisotropic dry etching process has better profile controllability, which is beneficial for improving the cross-sectional morphology quality of the groove 107. In addition, the selected anisotropic dry etching process is beneficial for achieving a higher etching selectivity, thereby reducing the probability of causing mis-etching of other film layers.

[0110] refer to Figures 8 and 9, along a direction parallel to the substrate and perpendicular to the extension direction of the gate structure 104, the portion of the sacrificial layer 1021 exposed on the sidewall of the groove 107 is laterally etched to form an opening 108, and the opening 108 is surrounded by the adjacent channel layer 1022 and the remaining sacrificial layer 1021, or the opening 108 is surrounded by the insulating layer 101, the channel layer 1022 adjacent to the insulating layer 101, and the remaining sacrificial layer 1021; an inner wall spacer layer 110 is formed in the opening 108.

[0111] Specifically, the opening 108 provides a spatial position for forming an inner wall sidewall layer 110, so that after the source and drain doping layers are subsequently formed and the device gate structure is formed at the position of the sacrificial layer 1021, the inner wall sidewall layer 110 is located between the source and drain doping layers and the device gate structure. The inner wall sidewall layer 110 can electrically isolate the source and drain doping layers from the device gate structure, which is beneficial to increase the distance between the source and drain doping layers and the device gate structure, and further beneficial to reduce the parasitic capacitance between the source and drain doping layers and the device gate structure.

[0112] It should be noted that, in this embodiment, openings 108 are formed between adjacent channel layers 1022 and between the channel layer 1022 and the insulating layer 101 .

[0113] In this embodiment, the process of laterally etching the exposed portion of the sacrificial layer 1021 on the sidewall of the groove 107 to form the opening 108 includes a wet etching process.

[0114] The wet etching process is an isotropic etching process, so that the sacrificial layer 1021 can be etched in a direction parallel to the substrate and perpendicular to the extension direction of the gate structure 104. The wet etching process can easily achieve a larger etching selectivity, which is beneficial to reducing the difficulty of etching the sacrificial layer 1021 and reducing the probability of damage to other film layer structures.

[0115] Specifically, the inner wall spacer layer 110 can electrically isolate the source and drain doped layers from the device gate structure, which is beneficial to increasing the distance between the source and drain doped layers and the device gate structure, and further beneficial to reducing the parasitic capacitance between the source and drain doped layers and the device gate structure.

[0116] It should be noted that, in this embodiment, the process of forming the inner wall spacer 110 in the opening 108 further includes: forming a bottom isolation layer 150 on the top of the substrate of the source / drain region 100A.

[0117] Specifically, the bottom isolation layer 150 is used to electrically isolate the subsequently formed source / drain doped layers from the substrate, and at the same time, reduces the risk of leakage from adjacent source / drain doped layers through the substrate thereunder, thereby further improving the performance of the semiconductor structure.

[0118] It should be noted that the inner wall spacer layer 110 and the bottom isolation layer 150 are formed in the same step, which can reduce the number of process steps and lower the process cost.

[0119] As an example, the step of forming an inner wall sidewall layer 110 in the opening 108 includes: forming an inner wall sidewall material layer (not shown) on the top and sidewalls of the gate structure 104, the sidewalls of the stacked structure 198, the sidewalls of the insulating layer 101, and the bottom of the groove 107, and the inner wall sidewall material layer is also filled in the opening 108; removing the inner wall sidewall material layer on the top and sidewalls of the gate structure 104, the sidewalls of the insulating layer 101, and the sidewalls of the channel layer 1022, and the remaining inner wall sidewall material layer located in the opening 108 serves as the inner wall sidewall layer 110, and the remaining inner wall sidewall material layer located at the bottom of the groove 107 serves as the bottom isolation layer 150.

[0120] In this embodiment, the material of the inner wall spacer layer 110 includes one or more of silicon nitride, silicon carbonitride, and nitrogen-doped silicon oxide.

[0121] It should be noted that silicon nitride, silicon carbonitride and nitrogen-doped silicon oxide are all dielectric materials, so that the inner wall spacer layer 110 can play an electrical isolation role.

[0122] It should also be noted that the bottom isolation layer 150 and the inner wall sidewall layer 110 are formed in the same step. Therefore, the material of the bottom isolation layer 150 is the same as that of the inner wall sidewall layer 110. The material of the bottom isolation layer 150 includes one or more of silicon nitride, silicon carbonitride and nitrogen-doped silicon oxide.

[0123] refer to Figure 10 , a source-drain doped layer 160 is formed in the groove 107 , and the source-drain doped layer 160 covers the sidewalls of the stacked structure 198 and the insulating layer 101 .

[0124] Specifically, the source-drain doping layer 160 is used as the source region and the drain region of the transistor.

[0125] In this embodiment, the process of forming the source / drain doped layer 160 in the groove 107 includes an epitaxial process.

[0126] Among them, when the fully enclosed gate transistor is a P-type MOS transistor, the material of the stress layer is Si or SiGe, and the doped ions in the source and drain doping layer 160 are P-type ions; when the fully enclosed gate transistor is an N-type MOS transistor, the material of the stress layer is Si or SiC, and the doped ions in the source and drain doping layer 160 are N-type ions.

[0127] It should be noted that, in the step of forming the source-drain doped layer 160 , the source-drain doped layer 160 also covers the top of the bottom isolation layer 150 .

[0128] Specifically, the source-drain doped layer 160 covers the top of the bottom isolation layer 150, so that the bottom isolation layer 150 electrically isolates the adjacent source-drain doped layer 160, and reduces the risk of leakage of the adjacent source-drain doped layer 160 through the substrate thereunder, thereby further improving the performance of the semiconductor structure.

[0129] refer to Figure 11 After forming the source-drain doped layer 160 , the forming method further includes: forming an interlayer dielectric layer 161 on the top of the source-drain doped layer 160 , wherein the interlayer dielectric layer 161 covers the sidewalls of the gate structure 104 .

[0130] The interlayer dielectric layer 161 is used to achieve electrical isolation between adjacent devices.

[0131] In this embodiment, the material of the interlayer dielectric layer 161 is silicon oxide.

[0132] In this embodiment, the steps of forming the interlayer dielectric layer 161 include: forming a dielectric material layer (not shown) on the substrate of the sidewall of the gate structure 104, and the dielectric material layer also covers the top of the gate structure 104; removing the dielectric material layer above the top of the gate structure 104, and the remaining dielectric material layer serves as the interlayer dielectric layer 161.

[0133] refer to Figure 12 , the gate structure 104 is removed, and a gate opening 163 is formed in the interlayer dielectric layer 161 .

[0134] Specifically, the gate opening 163 provides a process window for the subsequent removal of the sacrificial layer 1021 , and also provides a spatial location for the subsequent formation of a device gate structure.

[0135] In this embodiment, the process of removing the gate structure 104 includes a dry etching process.

[0136] refer to Figure 13 After forming the gate opening 163 , the sacrificial layer 1021 exposed by the gate opening 163 is removed, and a through groove 180 communicating with the gate opening 163 is formed below the channel layer 1022 .

[0137] Specifically, the through-grooves 180 provide a spatial location for subsequently forming a device gate structure surrounding the channel layer 1022 .

[0138] As an example, the sacrificial layer 1021 is removed by a wet etching process.

[0139] The wet etching process is an isotropic etching process, so that the sacrificial layer 1021 can be etched in a direction parallel to the substrate and perpendicular to the extension direction of the gate opening 163. The wet etching process can easily achieve a larger etching selectivity, which is beneficial to reducing the difficulty of etching the sacrificial layer 1021 and reducing the probability of damage to other film layer structures.

[0140] It should be noted that the sacrificial layer 1021 is removed after the source and drain doped layer 160 is formed. Therefore, after removing the sacrificial layer 1021, both ends of the channel layer 1022 are connected to the source and drain doped layer 160 and suspended in the gate opening 163, thereby providing a basis for the subsequent device gate structure to surround the channel layer 1022.

[0141] After the sacrificial layer 1021 is removed, the channel layers 1022 are arranged at intervals, and the remaining channel layers 1022 constitute a channel structure layer.

[0142] refer to Figure 14 A device gate structure 166 is formed in the gate opening 163 and the through-groove 180 . The device gate structure 166 surrounds the channel layer 1022 and covers the top of the insulating layer 101 .

[0143] The device gate structure 166 is used to control the opening and closing of the conductive channel when the device is in operation.

[0144] Specifically, the device gate structure 166 is a metal gate structure.

[0145] In this embodiment, the device gate structure 166 includes a gate dielectric layer surrounding and covering the channel structure layer, and a gate electrode layer covering the gate dielectric layer.

[0146] In this embodiment, the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.

[0147] Specifically, the gate dielectric layer includes a gate oxide layer surrounding and covering the channel layer 1022, and a high-k gate dielectric layer surrounding and covering the gate oxide layer. The high-k gate dielectric layer is made of a high-k dielectric material, which refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide.

[0148] The gate electrode layer is used for subsequent electrical connection to external structures. The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. Specifically, the gate electrode layer may include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer may include only the work function layer.

[0149] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: a substrate, the substrate comprising a channel region and source / drain regions located on both sides of the channel region; an insulating layer located on top of the substrate in the channel region; a channel structure layer suspended on top of the insulating layer, the channel structure layer comprising one or more channel layers spaced apart in the longitudinal direction; A device gate structure, located above the insulating layer and surrounding and covering the channel structure layer; The source-drain doped layer is located on the top of the substrate in the source-drain region on both sides of the device gate structure, and the source-drain doped layer covers the sidewalls of the channel structure layer.

2. The semiconductor structure according to claim 1, wherein The insulating layer has doping ions; Alternatively, the insulating layer is an epitaxial growth layer.

3. The semiconductor structure according to claim 2, wherein: The concentration of doping ions in the insulating layer is 3×10 14 cm -2 to 5×10 14 cm -2 .

4. The semiconductor structure according to claim 2, wherein: The doping ions in the insulating layer include boron ions.

5. The semiconductor structure according to claim 1, wherein The insulating layer is made of silicon boride.

6. The semiconductor structure according to claim 1, wherein The semiconductor structure further includes: an inner wall spacer layer, located between the sidewall of the device gate structure and the source / drain doping layer directly below the channel layer; The bottom isolation layer is located between the source-drain doped layer and the substrate.

7. The semiconductor structure according to claim 1, wherein: The device gate structure includes a gate dielectric layer surrounding and covering the channel structure layer, and a gate electrode layer covering the gate dielectric layer; The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3; The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

8. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, comprising a channel region and source / drain regions located on both sides of the channel region; forming an insulating layer on top of the substrate in the channel region and the source / drain region; forming a stacked structure on top of the insulating layer, and a gate structure located on the substrate in the channel region and spanning the stacked structure, wherein the gate structure covers a portion of the top and a portion of the sidewalls of the stacked structure, the stacked structure comprising one or more channel stacks stacked in sequence in a longitudinal direction, the channel stack comprising a sacrificial layer and a channel layer located on the sacrificial layer; forming a groove located in the source / drain region in the stacked structure and the insulating layer on both sides of the gate structure, wherein the sidewalls of the groove expose the stacked structure and the insulating layer; A source-drain doped layer is formed in the groove, and the source-drain doped layer covers the sidewalls of the stacked structure and the insulating layer.

9. The method for forming a semiconductor structure according to claim 8, wherein: The step of forming the insulating layer includes: providing a base material layer; performing a doping treatment on a portion of the base material layer to form an insulating layer, and using the base material layer that has not been doped as a base; Alternatively, the step of forming the insulating layer includes: forming the insulating layer on top of the substrate by an epitaxial growth process.

10. The method for forming a semiconductor structure according to claim 9, wherein: The process of performing doping treatment on a partial thickness of the base material layer includes an ion implantation process.

11. The method for forming a semiconductor structure according to claim 10, wherein: The parameters of the ion implantation process include: the doping ions include boron ions; the doping dose is 3×10 14 cm -2 to 5×10 14 cm -2 .

12. The method for forming a semiconductor structure according to claim 8, wherein: The insulating layer is made of silicon boride.

13. The method for forming a semiconductor structure according to claim 8, wherein: The step of forming grooves in the source / drain regions in the stacked structures and the insulating layer on both sides of the gate structure includes: etching away the stacked structures and the insulating layer in the source / drain regions to form grooves in the source / drain regions.

14. The method for forming a semiconductor structure according to claim 8, wherein: After forming the groove and before forming the source-drain doping layer, the method further includes: laterally etching the portion of the sacrificial layer exposed by the sidewall of the groove in a direction parallel to the substrate and perpendicular to the extension direction of the gate structure to form an opening, wherein the opening is surrounded by the adjacent channel layer and the remaining sacrificial layer, or the opening is surrounded by the insulating layer, the channel layer adjacent to the insulating layer, and the remaining sacrificial layer; and forming an inner wall sidewall layer in the opening.

15. The method for forming a semiconductor structure according to claim 14, wherein: The step of forming an inner wall spacer layer in the opening further includes: forming a bottom isolation layer on the top of the substrate in the source and drain region; In the step of forming the source / drain doping layer, the source / drain doping layer covers the top of the bottom isolation layer.

16. The method for forming a semiconductor structure according to claim 15, wherein: The step of forming an inner wall sidewall layer in the opening includes: forming an inner wall sidewall material layer on the top and sidewalls of the gate structure, the sidewalls of the stacked structure, the sidewalls of the insulating layer, and the bottom of the groove, and the inner wall sidewall material layer is also filled in the opening; removing the inner wall sidewall material layer on the top and sidewalls of the gate structure, the sidewalls of the insulating layer, and the sidewalls of the channel layer, and the remaining inner wall sidewall material layer located in the opening serves as the inner wall sidewall layer, and the remaining inner wall sidewall material layer located at the bottom of the groove serves as the bottom isolation layer.

17. The method for forming a semiconductor structure according to claim 14 or 15, wherein: The material of the inner wall spacer layer includes one or more of silicon nitride, silicon carbonitride and nitrogen-doped silicon oxide.

18. The method for forming a semiconductor structure according to claim 8, wherein: After forming the source-drain doped layer, the method for forming the semiconductor structure further includes: forming an interlayer dielectric layer on top of the source-drain doped layer, wherein the interlayer dielectric layer covers the sidewalls of the gate structure; removing the gate structure and forming a gate opening in the interlayer dielectric layer; removing the sacrificial layer exposed by the gate opening, and forming a through groove communicating with the gate opening below the channel layer; A device gate structure is formed in the gate opening and the through groove, wherein the device gate structure surrounds the channel layer and covers the top of the insulating layer.

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