Single particle radiation resistant reinforced SOI LDMOS device structure and preparation method thereof

Abstract

The invention belongs to the technical field of aerospace microelectronics, and discloses a single particle radiation resistant reinforced SOI LDMOS (silicon on insulator laterally diffused metal oxide semiconductor) device structure and a preparation method thereof, and the SOI LDMOS device structure comprises a well region formed on an SOI substrate and a slowly-changing doping concentration drift region adjacent to the well region; the field oxide layer is positioned on the surface of the slowly-changing doping concentration drift region; the gate structure is arranged across the well region and a part of the field oxide layer, and the gate structure comprises a gate oxide layer and a polycrystalline silicon layer above the gate oxide layer; the source electrode doped region and the body lead-out doped region are formed in the well region; the drain electrode doping region is formed in the slowly-changing doping concentration drift region; wherein the doping concentration of the slowly-changing doping concentration drift region is distributed in a gradient increasing mode from the source electrode to the drain electrode. According to the invention, the transverse field intensity gradient can be reduced, the parasitic triode effect caused by single-particle radiation can be suppressed, and the single-particle burning resistance of the device can be improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of aerospace microelectronics, and in particular relates to a SOI LDMOS device structure reinforced against single particle radiation and a preparation method thereof. Background Art

[0002] In applications with harsh radiation environments, such as aerospace and nuclear power, the radiation resistance of semiconductor devices is a key factor in ensuring stable system operation. Laterally diffused metal oxide semiconductor (LDMOS) devices, as important power devices, are widely used in many electronic systems due to their excellent properties, such as high breakdown voltage and low on-resistance. However, LDMOS devices still have shortcomings in single-event radiation environments.

[0003] Typical conventional LDMOS device structures, such as the radiation-hardened LDMOS transistor disclosed in patent publication number CN113410305A, have optimized device performance to a certain extent, but still have deficiencies in the face of single-event radiation effects. Figure 1 and Figure 2 As shown in the figure, taking an N-type channel LDMOS device as an example, when heavy particles are incident on the LDMOS device, a large number of electron-hole pairs are generated along the particle tracks. Due to the combined effects of drift and diffusion, these unbalanced carriers undergo complex motion. Holes enter the emitter region through the lateral base region of the parasitic bipolar junction transistor (BJT), while electrons flow through the lateral base region to the collector region, generating a transient current. As the voltage drop across the base region (P-well) caused by this transient current increases, when it reaches a certain value, it causes the emitter junction of the parasitic BJT to conduct forward, thereby turning on the parasitic BJT. When the drain-source reverse bias voltage approaches or reaches its breakdown voltage, the collector current of the parasitic BJT undergoes avalanche multiplication. This process creates a positive feedback effect, and the continuous increase in positive feedback current can eventually cause device failure, seriously impacting the normal operation of the entire electronic system. Especially for high-voltage LDMOS devices, due to their inherent operating characteristics, the unbalanced carrier transient current induced by single-event radiation is more likely to cause an increase in the P-well potential. The increase in the P-well potential further accelerates the conduction of the parasitic transistor emitter junction, making the positive feedback effect more intense and greatly increasing the risk of device burning. Summary of the Invention

[0004] To address the problems existing in the prior art, the present invention provides a SOI LDMOS device structure and preparation method with single-event radiation hardening, which can reduce the lateral field intensity gradient, suppress the parasitic triode effect caused by single-event radiation, and thus improve the device's ability to resist single-event burnout.

[0005] In order to solve the above technical problems, the present invention is implemented through the following technical solutions:

[0006] According to a first aspect of the present invention, there is provided a single event radiation hardened SOI LDMOS device structure, comprising:

[0007] A well region formed on an SOI substrate and a gradually varying doping concentration drift region adjacent to the well region;

[0008] a field oxide layer located on the surface of the graded doping concentration drift region;

[0009] a gate structure spanning the well region and a portion of the field oxide layer, the gate structure comprising a gate oxide layer and a polysilicon layer above the gate oxide layer;

[0010] a source doping region and a body lead doping region formed in the well region;

[0011] a drain doping region formed in the graded doping concentration drift region;

[0012] The doping concentration of the gradually varying doping concentration drift region increases gradually from the source to the drain.

[0013] In a possible implementation of the first aspect, the gradually varying doping concentration drift region is formed by a multi-window ion implantation process, the implantation window width gradually increases along the drain direction, and the window spacing gradually decreases.

[0014] In a possible implementation of the first aspect, the SOI LDMOS device structure further includes:

[0015] A dielectric layer covers the gate structure and the field oxide layer.

[0016] In a possible implementation of the first aspect, the SOI LDMOS device structure further includes:

[0017] A metal is formed through the dielectric layer.

[0018] In a possible implementation manner of the first aspect, the field oxide layer covers 60%-80% of the surface of the graded doping concentration drift region.

[0019] In a possible implementation manner of the first aspect, a gate length of the polysilicon layer in the gate structure extends to cover a region 0.5 μm to 1.5 μm from an edge of the field oxide layer.

[0020] According to a second aspect of the present invention, there is provided a method for preparing a single event radiation hardened SOI LDMOS device structure, comprising:

[0021] S1. Provide an SOI substrate;

[0022] S2. forming a well region and an adjacent gradually varying doping concentration drift region on the SOI substrate, wherein the doping concentration of the gradually varying doping concentration drift region increases gradually from the source to the drain;

[0023] S3, forming a field oxide layer on the surface of the graded doping concentration drift region;

[0024] S4, forming a gate structure across the well region and a portion of the field oxide layer, the gate structure comprising a gate oxide layer and a polysilicon layer above the gate oxide layer;

[0025] S5, forming a body-lead doping region in the well region, and forming a drain doping region in the graded doping concentration drift region;

[0026] The formation of the gradually varying doping concentration drift region includes:

[0027] S21, depositing photoresist as a mask on the surface of the drift region, and forming a multi-window ion implantation pattern by a photolithography process, wherein the implantation window width gradually increases along the drain direction, and the window spacing gradually decreases;

[0028] S22, with an injection energy of 60keV to 100keV, 1×10 14 / cm 2 ~5×10 14 / cm 2 Ion implantation is performed with a dose of

[0029] S23, performing high temperature annealing, the annealing temperature is 1000° C. to 1100° C., the time is 30 min to 60 min, and O2 is introduced during the annealing process at a flow rate of 0.1 slm to 0.3 slm.

[0030] In a possible implementation of the second aspect, in step S21, the width and spacing of the injection windows are adjusted according to a device operating voltage requirement.

[0031] In a possible implementation of the second aspect, the method further includes:

[0032] S6. Depositing a dielectric layer on the gate structure and the field oxide layer.

[0033] In a possible implementation of the second aspect, the method further includes:

[0034] S7. Forming a penetrating metal in the dielectric layer.

[0035] Compared with the prior art, the present invention has at least the following beneficial effects:

[0036] The present invention provides a SOI LDMOS device structure with single-particle radiation hardening. By setting the doping concentration of the gradually varying doping concentration drift region to a gradient increasing distribution from the source to the drain, the electric field distribution can be flattened, thereby reducing the peak electric field at the drain end, reducing the probability of avalanche breakdown, and effectively reducing the lateral field intensity gradient in the drift region. During device operation, this doping distribution method can smoothly distribute the electric field within the longer drift region, avoiding the situation where the local electric field is too high, thereby optimizing the electric field distribution characteristics within the device. The electric field homogenization can reduce the current concentration and hot spot formation caused by the local high electric field region when a single particle is incident, thereby suppressing the parasitic triode effect caused by single-particle radiation and improving the device's resistance to single-particle burnout. In other words, the present invention can effectively reduce the impact of non-equilibrium carrier generation under single-particle radiation. Single-particle radiation will generate a large number of non-equilibrium carriers inside the device. The abnormal movement of these carriers may cause the deterioration and failure of the device performance. The present invention reduces the generation and accumulation of non-equilibrium carriers through doping distribution design, thereby improving the working ability of the device in a single-particle radiation environment and enhancing the adaptability of the device to the radiation environment.

[0037] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the specific embodiments. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0039] Figure 1 This is a schematic diagram of a traditional LDMOS transistor (taking an N-type channel LDMOS device as an example).

[0040] Figure 2 This is a schematic diagram of the single-event radiation effect of LDMOS devices (taking N-type channel LDMOS devices as an example).

[0041] Figure 3 The diagram is a structural diagram of a SOI LDMOS device hardened against single-particle radiation according to the present invention.

[0042] In the figure: 1-well region; 2-gradually varying doping concentration drift region; 3-field oxide layer; 4-gate oxide layer; 5-polysilicon layer; 6-source doping region; 7-body lead doping region; 8-drain doping region; 9-dielectric layer; 10-metal. DETAILED DESCRIPTION

[0043] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0044] Example 1: Combination Figure 3 As shown, the process of single event radiation hardened SOI LDMOS device

[0045] (1) Provide an SOI substrate, which includes a substrate layer, a buried oxide layer, and a top silicon layer from bottom to top. It should be noted that the thickness of the top silicon layer is designed according to the device's withstand voltage requirements and is 0.5 μm to 2 μm. For example, the thickness is 1 μm.

[0046] (2) Formation of well region 1. Taking LDNMOS as an example, a P-well pattern window is defined on the top silicon surface by photolithography, and P-type impurities (such as boron) are injected with an injection energy of 100keV to 150keV and a dose of 1×1012 / cm 2 ~1×1013 / cm 2 Then a high-temperature diffusion process is carried out, pushing the well temperature to 1100℃~1150℃ to form a P-well region.

[0047] It should be noted that, for LDPMOS devices, an N-well region needs to be formed accordingly.

[0048] (3) Forming a gradually varying doping concentration drift region 2, specifically as follows:

[0049] Photoresist is deposited on the surface of the drift region, and a multi-window ion implantation pattern is formed through photolithography. The implantation window width increases toward the drain, while the window spacing decreases. The implantation window and spacing must be no less than 1μm, with specific parameters adjusted based on the operating voltage. For example, the source window width is 1μm, the drain window width is 3μm, the source spacing is 2μm, and the drain spacing is 1μm.

[0050] Perform N-type ion implantation (such as phosphorus) with an implantation energy of 100keV to 200keV and a dose of 1×10 14 / cm 2 ~3×10 14 / cm 2 , forming a gradually changing doping concentration drift region 2.

[0051] High-temperature annealing activates the injected impurities and repairs lattice damage. Annealing temperature is 1000°C to 1100°C for 30 to 60 minutes, with an O2 flow rate of 0.1 to 0.3 slm. This process helps improve the surface quality of the drift region.

[0052] (4) A field oxide layer 3 is formed on the surface of the graded doping concentration drift region 2, covering 60% to 80% of the surface of the graded doping concentration drift region 2, with a thickness of 0.5 μm to 1.5 μm.

[0053] (5) Forming a gate structure, specifically as follows:

[0054] Using dry oxidation process, considering the impact of radiation resistance, SiO2 gate oxide layer 4 is grown at 800℃~900℃ with a thickness of

[0055] After the growth of the SiO2 gate oxide layer 4 is completed, it is nitrided and annealed at 850℃~1000℃ for 30min~60min in an N2, NO or N2O atmosphere to form a silicon oxynitride layer. Nitriding can convert the Si-H bonds and Si dangling bonds in the original SiO2 gate oxide layer into stronger Si-N bonds to form silicon oxynitride, thereby improving the reliability of the gate oxide.

[0056] Polysilicon is deposited and doped (eg, phosphorus), and a polysilicon layer 5 is formed by photolithography and etching. The gate length covers the 1 μm to 1.5 μm area at the edge of the field oxide layer.

[0057] (6) Forming the source doping region 6, the drain doping region 8 and the body lead doping region 7

[0058] Perform photolithography and implantation of N-type source doping region 6 and P-type body lead doping region 7 in the P well, with an implantation dose of 1×1015 / cm 2 .

[0059] The N-type drain doping region 8 is photolithographically and implanted in the gradually varying doping concentration drift region 2, with an implantation dose of 1×1015 / cm 2 .

[0060] It should be understood that for an LDPMOS device, a P-type source and drain, and an N-type body doping region need to be formed accordingly.

[0061] (7) Deposit a dielectric layer 9 with a thickness of 0.8 μm to 1.5 μm to cover the gate structure and field oxide layer 3. Form metal 10 through the dielectric layer 9 by photolithography and etching to complete the electrical connection of the source, drain and gate.

[0062] (8) Finally, the passivation layer is deposited and etched to form a complete device.

[0063] Example 2: Single Event Radiation Hardened SOI LDMOS Device Process

[0064] (1) Provide an SOI substrate, which includes a substrate layer, a buried oxide layer, and a top silicon layer from bottom to top. It should be noted that the thickness of the top silicon layer is designed according to the device's withstand voltage requirements and is 0.5 μm to 2 μm. For example, the thickness is 1 μm.

[0065] (2) Well region 1 is formed by defining the P-well pattern window through photolithography and injecting P-type impurities (such as boron) with an injection energy of 100keV to 300keV and a dose of 1×10 12 / cm 2 ~1×10 13 / cm 2 High temperature diffusion process, temperature 1100℃~1150℃, forms the P-well region.

[0066] (3) Forming a gradually varying doping concentration drift region 2, specifically as follows:

[0067] Similar to Example 1, a multi-window ion implantation pattern is formed, and the window width and spacing are adjusted according to voltage requirements.

[0068] N-type ion implantation (such as phosphorus), implantation energy 100keV ~ 300keV, dose 1×10 14 / cm 2 ~5×10 14 / cm 2 .

[0069] High temperature annealing treatment, temperature 1000℃~1100℃, time 30min~60min, O2 flow rate 0.1slm~0.3slm.

[0070] (4) The field oxide layer, gate structure and doping region are formed. The process steps are exactly the same as steps (4) to (6) in Example 1. The difference is that the thickness of the gate oxide layer 4 is adjusted to

[0071] (5) The dielectric layer and metallization are formed in exactly the same manner as step (7) of Example 1 to complete the device packaging.

[0072] Through the above process, a gradually changing doping concentration drift region 2 with a decreasing surface doping concentration gradient can be prepared. The original drift region structure with uniform doping concentration is adjusted to a drift region structure with a gradually increasing doping concentration toward the drain. This can reduce the lateral field strength gradient, suppress the parasitic triode effect caused by single-particle radiation, and thereby improve the device's resistance to single-particle burnout.

[0073] In the description of the present invention, it should be understood that the terms "upper", "lower", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0074] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0075] In the present invention, unless otherwise specified or limited, the terms "connected" and "connection" should be understood in a broad sense. For example, they can mean fixed connection, detachable connection, or integration; mechanical connection, electrical connection, or communication; direct connection or indirect connection through an intermediate medium; internal communication between two elements or interaction between two elements, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0076] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0077] In the present invention, the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction.

[0078] Finally, it should be noted that the above-described embodiments are only specific implementations of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the above-described embodiments, those skilled in the art should understand that any person skilled in the art can modify or easily conceive of changes to the technical solutions described in the above-described embodiments within the technical scope disclosed by the present invention, or replace some of the technical features therein with equivalents. Such modifications, changes, or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A single event radiation hardened SOI LDMOS device structure, characterized in that: include: A well region (1) formed on an SOI substrate and a gradually varying doping concentration drift region (2) adjacent to the well region (1); A field oxide layer (3) located on the surface of the gradually varying doping concentration drift region (2); A gate structure spanning the well region (1) and a portion of the field oxide layer (3), the gate structure comprising a gate oxide layer (4) and a polysilicon layer (5) above the gate oxide layer (4); A source doping region (6) and a body lead doping region (7) formed in the well region (1); a drain doping region (8) formed in the gradually varying doping concentration drift region (2); The doping concentration of the gradually varying doping concentration drift region (2) is distributed in a gradient increasing direction from the source to the drain.

2. The single event radiation hardened SOI LDMOS device structure according to claim 1, wherein: The gradually varying doping concentration drift region (2) is formed by a multi-window ion implantation process, wherein the implantation window width gradually increases along the drain direction, and the window spacing gradually decreases.

3. The single event radiation hardened SOI LDMOS device structure according to claim 1, wherein: The SOI LDMOS device structure further includes: A dielectric layer (9) covering the gate structure and the field oxide layer (3).

4. The single event radiation hardened SOI LDMOS device structure according to claim 3, wherein: The SOI LDMOS device structure further includes: A metal (10) is formed through the dielectric layer (9).

5. The single event radiation hardened SOI LDMOS device structure according to claim 1, wherein: The field oxide layer (3) covers 60%-80% of the surface of the gradually varying doping concentration drift region (2).

6. The single event radiation hardened SOI LDMOS device structure according to claim 1, wherein: The gate length of the polysilicon layer (5) in the gate structure extends to cover a 0.5 μm to 1.5 μm region at the edge of the field oxide layer (3).

7. A method for preparing a single-event radiation-hardened SOI LDMOS device structure, characterized in that: include: S1. Provide an SOI substrate; S2, forming a well region (1) and an adjacent gradually varying doping concentration drift region (2) on the SOI substrate, wherein the doping concentration of the gradually varying doping concentration drift region (2) is distributed in a gradient increasing direction from the source to the drain; S3, forming a field oxide layer (3) on the surface of the gradually varying doping concentration drift region (2); S4, forming a gate structure across the well region (1) and a portion of the field oxide layer (3), wherein the gate structure includes a gate oxide layer (4) and a polysilicon layer (5) above the gate oxide layer (4); S5, forming (6) and a body-lead doping region (7) in the well region (1), and forming a drain doping region (8) in the gradually varying doping concentration drift region (2); The formation of the gradually varying doping concentration drift region (2) includes: S21, depositing photoresist as a mask on the surface of the drift region, and forming a multi-window ion implantation pattern by a photolithography process, wherein the implantation window width gradually increases along the drain direction, and the window spacing gradually decreases; S22, with an injection energy of 60keV to 100keV, 1×10 14 / cm 2 ~5×10 14 / cm 2 Ion implantation is performed with a dose of S23, performing high temperature annealing, the annealing temperature is 1000° C. to 1100° C., the time is 30 min to 60 min, and O2 is introduced during the annealing process at a flow rate of 0.1 slm to 0.3 slm.

8. The method for preparing a single event radiation hardened SOI LDMOS device structure according to claim 1, wherein: In step S21 , the width and spacing of the injection windows are adjusted according to the device operating voltage requirement.

9. The method for preparing a single event radiation hardened SOI LDMOS device structure according to claim 1, wherein: Also includes: S6. Depositing a dielectric layer (9) on the gate structure and the field oxide layer (3).

10. The method for preparing a single event radiation hardened SOI LDMOS device structure according to claim 9, wherein: Also includes: S7. Forming a penetrating metal (10) in the dielectric layer (9).

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