Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes a power gating unit having a p-type metal oxide semiconductor (PMOS) region. The semiconductor device also includes a backside (BS) global power rail. Further, the semiconductor device includes a contact in contact with both the PMOS region and the BS global power rail.

Description

[0001] This application claims the benefit of U.S. Provisional Patent Application Serial No. 63 / 555,956, filed on February 21, 2024, entitled “POWERGATING CELL DESIGN IN BSPDN,” and U.S. Application No. 18 / 732,680, filed on June 4, 2024, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates generally to the field of semiconductor devices, and more particularly, to a semiconductor device having a switching unit. Background Art

[0003] Integrated circuit (IC) devices, chips, and / or blocks may receive power signals and data signals from one or more external sources (e.g., power supplies and data sources) as part of their operation. Some IC devices may receive power signals and data signals via front-side (FS) conductive structures. For example, an IC device may include a FS power distribution network (or power delivery network (PDN)) (FSPDN) having one or more components formed during back-end-of-line (BEOL) processing, and the conductive structures for the data signals may be on the same side of the IC device as the FSPDN. The IC device may include various transistor structures (including, for example, two-dimensional (2D) planar structures, fin field effect transistors (FinFETs), gate-all-around transistors, multi-bridge channel FETs (MBCFETs), and the like). TM ) and stacked transistors (e.g., three-dimensional (3D) stacked transistors)).

[0004] More recently, backside PDNs (BSPDNs) have been developed in which the backside (BS) of the substrate of an IC device serves as a PDN. For example, power rails can be used in the BSPDN of an IC device, and the power rails can be on the side of the substrate opposite the active components (e.g., transistors) of the IC device. Furthermore, conductive structures for data signals can be on the FS of the IC device, and thus the BSPDN and the conductive structures for data signals can be on opposite sides of the IC device.

[0005] An IC device may include multiple units, and the multiple units may include transistors driven by a power supply. However, external power may not be directly supplied to the standard units of the IC device. Instead, the external power may be input to an element called a "power switching unit" (or "switch unit" or "power gating unit") that generates a virtual voltage based on the external power supply voltage. The virtual voltage output from the switch unit is applied to the standard unit. It may be necessary to apply a sufficient virtual voltage to the standard unit for stable driving of the IC device. In addition, it may be necessary to supply a ground voltage to the standard unit.

[0006] An IC device may include multiple switching cells (such as metal oxide semiconductor (MOS)-based switching cells). The IC device may also include non-power switch standard cells placed between the switching cells. A standard cell may be any of a variety of cells used to implement a logic circuit. For example, a standard cell may provide any of a variety of logic gates (such as an AND gate, an OR gate, a NOR gate, an XOR gate, and a NOT gate). Summary of the Invention

[0007] A semiconductor device according to some embodiments herein may include a power gating cell having a p-type MOS (PMOS) region. The semiconductor device may include a global power rail (BS). Furthermore, the semiconductor device may include a contact that contacts both the PMOS and the global power rail (BS). The power gating cell may not have an n-type MOS (NMOS) region.

[0008] According to some embodiments herein, a semiconductor device may include: a power gating unit having a PMOS region. In addition, the semiconductor device may include: a BSPDN having a first power line, a second power line, and a third power line extending longitudinally parallel to each other in a first direction. The second power line may be a global power line between the first power line and the third power line in a second direction perpendicular to the first direction. The semiconductor device may include: a first contact extending longitudinally in the second direction and contacting both the PMOS region and the global power line. The PMOS region may be wider than the first contact in the second direction. The semiconductor device may include: a second contact contacting both the PMOS region and the first power line. In addition, the semiconductor device may include: a third contact contacting the third power line.

[0009] A semiconductor device according to some embodiments herein may include a switching unit including a transistor. The semiconductor device may include a first BS power rail, a second BS power rail, and a third BS power rail, wherein the first BS power rail, the second BS power rail, and the third BS power rail are electrically connected to the transistor. The second BS power rail is a normally-on BS power rail. The semiconductor device may include a first contact in contact with both the normally-on BS power rail and the transistor. The semiconductor device may include a second contact in contact with both the first BS power rail and the transistor. Furthermore, the semiconductor device may include a third contact in contact with both the third BS power rail and the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A is a schematic block diagram of an apparatus according to some embodiments herein.

[0011] Figure 1B yes Figure 1A Schematic block diagram of the switching unit and standard unit of the IC.

[0012] Figure 1C yes Figure 1A Schematic block diagram of the BSPDN of the IC.

[0013] Figure 1D is shown with Figure 1C The P-type metal oxide semiconductor (PMOS) region of the switching unit and Figure 1C Schematic block diagram of the contacts of the BSPDN global power rail.

[0014] Figure 2A 、 Figure 3A 、 Figure 4A and Figure 5A yes Figure 1C Example block diagram of a switch unit.

[0015] Figure 2B 、 Figure 3B 、 Figure 4B and Figure 5B They are Figure 2A 、 Figure 3A 、 Figure 4A and Figure 5A Example floor plan of a switch unit.

[0016] Figure 2C It is along Figure 2B A cross-sectional view taken along line AA'.

[0017] Figure 2D It is along Figure 2B Cross-sectional view along line BB'.

[0018] Figure 3C It is along Figure 3BA cross-sectional view taken along line AA'.

[0019] Figure 3D It is along Figure 3B Cross-sectional view along line BB'.

[0020] Figure 4C It is along Figure 4B A cross-sectional view taken along line AA'.

[0021] Figure 4D It is along Figure 4B Cross-sectional view along line BB'.

[0022] Figure 5C It is along Figure 5B A cross-sectional view taken along line AA'.

[0023] Figure 5D It is along Figure 5B Cross-sectional view along line BB'. DETAILED DESCRIPTION

[0024] Semiconductor devices may include switching cells that can control the power consumption of a block or chip. The performance of the switching cells can therefore be important. The switching cells can transfer the voltage of a global always-on power rail to a local power rail connected to a normal (i.e., non-power switch) standard cell. When the block needs to be turned on, the gate switch can be controlled. Furthermore, switching performance can be enhanced based on the design of the switching cells. For example, a wide contacted poly pitch (CPP) (e.g., 20 to 80 CPP) and / or multi-height cells (i.e., at least double-height cells) can enhance switching performance.

[0025] According to embodiments herein, a semiconductor (e.g., a semiconductor IC) device is provided that includes a switch cell having a PMOS region coupled to a global power rail of a BSPDN. The switch cell may lack an N-type metal oxide semiconductor (NMOS) region (which may not be required for power gating) and, therefore, may have reduced leakage. In contrast, a conventional switch cell may be a complementary MOS (CMOS) switch cell that includes both a PMOS region and an NMOS region, wherein the NMOS region may be closer to the global power rail than the PMOS region, making it difficult to connect the PMOS region to the global power rail and potentially requiring a relatively long contact to be formed between the global power rail and the PMOS region. However, according to embodiments herein, the relatively wide PMOS region may occupy the space conventionally occupied by an NMOS region and, therefore, may be coupled to the global power rail via a relatively short contact (the relatively short contact may contact both the PMOS region and the global power rail). Thus, while conventional CMOS switch cells have PMOS and NMOS regions that share one logic cell, and while a VDD switch cell may have only a conventional (e.g., narrow) PMOS region, a switch cell according to embodiments herein may have no NMOS region (which is typical in CMOS switch cells) and may include a wide PMOS region that occupies the space that would normally be occupied by an NMOS region.

[0026] In some embodiments, the switch cell may have a dual cell height and a single PMOS region, and the single PMOS region may extend continuously from a first single-height region of the switch cell to a second single-height region of the switch cell. In other embodiments, the switch cell may have a dual cell height and two PMOS regions, including a first PMOS region extending along a majority (i.e., greater than 50%) of the height of the first single-height region of the switch cell, and a second PMOS region extending along a majority of the height of the second single-height region of the switch cell.

[0027] Some examples of embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0028] Figure 1A 1 is a schematic block diagram of a semiconductor device 100 according to some embodiments herein. The semiconductor device 100 includes an IC 110 having a normal standard cell 112 (e.g., a block), one or more switch cells 104, and a BSPDN 118. For example, the switch cell 104 may be a PMOS switch cell that includes at least one PMOS transistor and does not include (i.e., has no) NMOS transistors.

[0029] Semiconductor device 100 also includes BS power supply 116 coupled to IC 110. BS power supply 116 may provide power signals at one or more voltage levels to IC 110. As an example, BS power supply 116 may be configured to provide one or more voltages between 0.4 volts and 1.1 volts to BSPDN 118.

[0030] The semiconductor device 100 also includes a controller 114 coupled to the BS power supply 116. The controller 114 may include one or more microprocessors configured to control the operation of the BS power supply 116. For example, the controller 114 may include a microprocessor configured to turn the BS power supply 116 on or off. The controller 114 and the BS power supply 116 may be used to perform chip-level power gating (e.g., turning the entire IC 110 on or off) and / or block-level power gating (e.g., turning individual portions of the IC 110 (such as one or more switching units 104) on or off). Figure 1A As shown in FIG, the controller 114 may be external (ie, outside) the IC 110 including the one or more switching cells 104 and the standard cells 112 .

[0031] Figure 1B is a schematic block diagram of a switch cell 104 and a standard cell 112 of an IC 110. The switch cell 104 includes one or more transistors in (and / or on) a substrate 102. For example, the switch cell 104 may include at least one PMOS transistor (e.g., a p-type field effect transistor (FET) (PFET) 132) in (and / or on) the substrate 102. Because the BSPDN 118 and the switch cell 104 may be on opposite sides of the substrate 102 in the vertical (Z) direction, the BSPDN 118 and the standard cell 112 may be on opposite sides of the substrate 102 in the vertical (Z) direction. Figure 1B The diagram omits BSPDN 118 ( Figure 1A ). The BSPDN 118 is on the BS of the substrate 102 , and the switch unit 104 may be on the FS of the substrate 102 .

[0032] In some embodiments, the switch cell 104 may be between a pair of standard cells 112 in a first horizontal (X) direction and / or a second horizontal (Y) direction. The standard cells 112 may be referred to herein as "normal" standard cells to distinguish them from the switch cell 104. Thus, the standard cell 112 may not be a switch cell and, therefore, may not be configured to transfer the voltage of the global power rail to the local power rail.

[0033] Figure 1C is a schematic block diagram of BSPDN 118 of IC 110. Figure 1CAs shown in FIG, BSPDN 118 includes a local power rail (also referred to as a VDD power rail or a local power line) 128 on the BS of IC 110, at least one global power rail (also referred to as a VDDG power rail, a backside global power rail or a global power line) 148, and a source-supply power rail (also referred to as a VSS power rail or a source-supply power line) 138. Because they are part of BSPDN 118, local power rail 128, one or more global power rails 148, and source-supply power rail 138 may also be referred to herein as "backside" power rails. Each of the "backside" power rails may be connected to substrate 102 (of IC 110). Figure 1B ) are provided on the corresponding metal lines of the BS. To simplify the explanation, Figure 1C The base 102 is omitted from the illustration in FIG.

[0034] The local power rail 128 can provide a virtual voltage (virtual VDD) to the standard cell 112, wherein the virtual voltage is output to the local power rail 128 by the switch unit 104. The virtual voltage can be provided by the switch unit 104 based on the power supplied by an external power source (such as the BS power supply 116 ( Figure 1A )) is generated from a global always-on voltage (VDDG) supplied to global power rail 148. Therefore, local power rail 128 may also be referred to herein as a "normal" or "virtual" (or "virtual voltage") power rail, and global power rail 148 may also be referred to herein as a "always-on" power rail (or always-on backside power rail). Source supply power rail 138 may send power, such as source supply (e.g., negative or ground supply) voltage VSS, to switch unit 104. For example, VSS may be zero volts.

[0035] In some embodiments, the switch cell 104 can overlap the global power rail 148 , the plurality of local power rails 128 , and / or the plurality of source supply power rails 138 in the direction Z. As an example, the switch cell 104 can be a multi-height switch cell vertically overlapping and electrically connected to the global power rail 148 .

[0036] Furthermore, in addition to being electrically connected to the switch cell 104, some of the local power rails 128 may also be electrically connected to a plurality of standard cells 112. As an example, some of the local power rails 128 may extend longitudinally (i.e., be longest) in the direction X and may be electrically connected to two standard cells 112 spaced apart from each other in the direction X.

[0037] Local power rails 128, source supply power rails 138, and global power rails 148 are examples of conductive (e.g., metal) power lines included in BSPDN 118. These power lines can be arranged in various ways. In some embodiments, global power rail 148 can be between a pair of local power rails 128 in direction Y. In other embodiments, global power rail 148 can be between a pair of source supply power rails 138 in direction Y. Therefore, global power rail 148 may be referred to herein as a "second power line" that is between and parallel to a "first power line" and a "third power line," where the first power line and the third power line may be a pair of local power rails 128 or a pair of source supply power rails 138.

[0038] Figure 1D is shown with the switch unit 104 ( Figure 1C ) and the global power rail 148 of the BSPDN 118. A schematic block diagram of a contact 150 is provided. The PMOS region 122 may be, for example, the source / drain (S / D) region of a PMOS transistor (such as PFET 132). The contact 150 may be a conductive (e.g., metal) contact having an upper surface that contacts the lower surface of the PMOS region 122 and a lower surface that contacts the upper surface of the global power rail 148. According to some embodiments, the contact 150 may be part of the BSPDN 118. In some embodiments, the contact 150 may extend longitudinally in the Y direction, which is perpendicular to the X direction.

[0039] Figure 2A 、 Figure 3A 、 Figure 4A and Figure 5A yes Figure 1C An example block diagram of the switch unit 104. Figure 2A 、 Figure 3A 、 Figure 4A and Figure 5A Switching cell 204, switching cell 304, switching cell 404, and switching cell 504 are shown, respectively. Switching cells 204 and 404 each include multiple PMOS regions 122, and switching cells 304 and 504 each include a single PMOS region 122.

[0040] like Figure 2A As shown in Figure 1CThe example switch cell 204 of the switch cell 104 includes a first PMOS region 122a and a second PMOS region 122b between a first local power rail (or first backside local power rail) 128a and a second local power rail (or second backside local power rail) 128b in the direction Y. In some embodiments, the first PMOS region 122a can be part of the first PFET 132a of the switch cell 204 (e.g., the S / D region of the first PFET 132a), and the second PMOS region 122b can be part of the second PFET 132b of the switch cell 204 (e.g., the S / D region of the second PFET 132b). The first local power rail 128a, the second local power rail 128b, and the global power rail 148 can each extend longitudinally parallel to each other in the direction X.

[0041] The switch unit 204 has no NMOS regions. Therefore, no NMOS regions exist between the first local power rail 128 a and the second local power rail 128 b in the direction Y. Instead, the only MOS regions between the first local power rail 128 a and the second local power rail 128 b are the first PMOS region 122 a and the second PMOS region 122 b.

[0042] The global power rail 148 may be between (and electrically connected to) the first PMOS region 122 a and the second PMOS region 122 b in the direction Y. To simplify the description, the term “between” may be used herein with respect to one or more power rails and one or more adjacent PMOS regions 122 to describe the circuitry as shown in the block diagrams (e.g., Figure 2A ) and as shown in plan views (e.g., Figure 2B 1. The one or more horizontal locations of the one or more power rails and the one or more PMOS regions 122 are shown in more detail in a plan view (e.g., FIG. 1 ). However, it will be understood that the BSPDN 118 and the power rails therein are at a different vertical level than the vertical level of the one or more PMOS regions 122. Therefore, the term "between" as used herein with respect to the one or more power rails and the one or more adjacent PMOS regions 122 does not require that the power rails and the one or more adjacent PMOS regions 122 be located at the same vertical level in a cross-sectional view (e.g., FIG. 1 ). Figure 2C and Figure 2D In the cross-sectional view (e.g., FIG), the axis extends in the direction Y through the one or more power rails and the one or more adjacent PMOS regions 122. In contrast, in the plan view and / or block diagram, it is sufficient that the axis extends in the direction Y through the one or more power rails and the one or more adjacent PMOS regions 122.

[0043] According to some embodiments, the global power rail 148 may be located at a center point of the switch cell 204 in the direction Y. The center point is a point along the line CC' between the first PMOS region 122a and the second PMOS region 122b in the direction Y. Therefore, the global power rail 148 may be concentrated in the switch cell 204, and in some embodiments, the global power rail 148 may be the only global power rail 148 in the switch cell 204. The first source supply rail (or first backside source supply rail) 138a and the second source supply rail (or second backside source supply rail) 138b may be aligned with the line CC'. Therefore, the global power rail 148 may be located between the first source supply rail 138a and the second source supply rail 138b in the direction X.

[0044] In some embodiments, the switch cell 204 may be a multi-height cell. For example, the switch cell 204 may have a dual cell height. Thus, the switch cell 204 may have a first single-height region 234a and a second single-height region 234b adjacent to each other in the direction Y. The first PMOS region 122a may be in the first single-height region 234a, and the second PMOS region 122b may be in the second single-height region 234b. As an example, the first PMOS region 122a may extend along a majority of the height of the first single-height region 234a in the direction Y, and the second PMOS region 122b may extend along a majority of the height of the second single-height region 234b in the direction Y.

[0045] The switch unit 204 can transmit the voltage of the global power rail 148 to the first local power rail 128a and / or the second local power rail 128b. For example, the first PMOS region 122a can be configured to transmit the voltage of the global power rail 148 to the first local power rail 128a, and the second PMOS region 122b can be configured to transmit the voltage of the global power rail 148 to the second local power rail 128b.

[0046] Figure 2B 、 Figure 3B 、 Figure 4B and Figure 5B They are Figure 2A 、 Figure 3A 、 Figure 4A and Figure 5A Example plan view of the switch units 204, 304, 404 and 504. Figure 2B, the switch cell 204 can be coupled to the global power rail 148 via a contact 150a. For example, the contact 150a can contact both the first PMOS region 122a and the global power rail 148. Furthermore, the contact 150a can contact both the second PMOS region 122b and the global power rail 148. Thus, the same contact 150a can contact both the PMOS regions 122a and 122b and can couple the PMOS regions 122a and 122b to the global power rail 148. In some embodiments, the switch cell 204 can also be coupled to the global power rail 148 via an additional contact 150d spaced apart from the contact 150a in the direction X. Similar to the contact 150a, the contact 150d can contact the global power rail 148 and both the PMOS regions 122a and 122b.

[0047] Contact 150b may contact both the first PMOS region 122a and the first local power line 128a. Contact 150c may contact both the second PMOS region 122b and the second local power line 128b. The four contacts 150a to 150d, which may serve as direct backside contacts (DBCs), may be referred to herein as a "first" contact, a "second" contact, a "third" contact, and a "fourth" contact, respectively. Furthermore, multiple (e.g., two, three, or more) contacts 150 may contact both the first PMOS region 122a and the first local power line 128a, and multiple contacts 150 may contact both the second PMOS region 122b and the second local power line 128b.

[0048] Local power rails 128a and 128b are at or adjacent opposite ends of the switch cell 204. For example, a first cell boundary 214a of the switch cell 204 may overlap the first local power rail 128a in the direction Z. Similarly, a second cell boundary 214b of the switch cell 204 may overlap the second local power rail 128b in the direction Z. The first PMOS region 122a may have a first end adjacent to the first cell boundary 214a and a second end adjacent to the global power rail 148. The second PMOS region 122b may have a first end adjacent to the global power rail 148 and a second end adjacent to the second cell boundary 214b.

[0049] The gate structures 260 may extend continuously in the direction Y so that they overlap the PMOS regions 122a and 122b, the global power rail 148, and the local power rails 128a and 128b in the direction Z. In contrast, each contact 150 may be relatively short. As an example, each contact 150 may overlap no more than an edge portion of each of the PMOS regions 122a and 122b in the direction Z. For example, each contact 150 may overlap no more than one-quarter of the width of the PMOS region 122 in the direction Y in the direction Z. As an example, the contact 150a may overlap less than one-quarter of the width of the first PMOS region 122a in the direction Y in the direction Z, and overlap less than one-quarter of the width of the second PMOS region 122b in the direction Y in the direction Z. In some embodiments, the gate structure 260 may include four gate structures spaced apart from each other in the direction X.

[0050] Figure 2C It is along Figure 2B A cross-sectional view of line A-A'. Figure 2C As shown in , the first PMOS region 122a may have a first width w1 in direction Y that is wider than the second width w2 of the contact 150a in direction Y. For example, the second width w2 may be less than 75% of the first width w1, or even less than 65% of the first width w1. The global power rail 148 may have a width smaller than the second width w2 in direction Y. The second PMOS region 122b may also have a first width w1. In some embodiments, the switch cell 204 may include only the PMOS region 122 and not an NMOS region. For example, the first PMOS region 122a may be a wide PMOS region that may extend into the space in the switch cell 204 that would conventionally be occupied by an NMOS region (and therefore occupy the space in the switch cell 204 that would conventionally be occupied by an NMOS region). Similarly, the second PMOS region 122b may be a wide PMOS region that may occupy the space in the switch cell 204 that would conventionally be occupied by an NMOS region. In addition, Figure 2C It is also shown that an upper surface of contact 150 a may contact both lower surfaces of the first PMOS region 122 a and the second PMOS region 122 b , and a lower surface of contact 150 a may contact an upper surface of the global power rail 148 .

[0051] The vertical axis 224 extends in the direction Z through the center point of the contact 150a in the direction Y (and the center point of the global power rail 148 in the direction Y). The vertical axis 224 is between the first cell boundary 214a and the second cell boundary 214b (e.g., in the middle of the first cell boundary 214a and the second cell boundary 214b). Although the cell boundaries 214a and 214b are Figure 2Bare shown extending in direction X, but they may also be Figure 2C , extending in direction Z. Thus, cell boundaries 214a and 214b may extend both vertically and horizontally.

[0052] Figure 2D It is along Figure 2B The cross-sectional view of the line B-B'. Figure 2D , the upper surface of contact 150b may contact the lower surface of first PMOS region 122a, and the lower surface of contact 150b may contact the upper surface of first local power rail 128a. Similarly, the upper surface of contact 150c may contact the lower surface of second PMOS region 122b, and the lower surface of contact 150c may contact the upper surface of second local power rail 128b.

[0053] Figure 3A A block diagram of the switch unit 304 is shown. The switch unit 304 is Figure 1C Another example of a switch cell 104. The switch cell 304 includes a single PMOS region 122 between a first local power rail 128a and a second local power rail 128b in the direction Y. The PMOS region 122 may be a PFET 132 ( Figure 1D ) of the S / D region, the PFET 132 may be the only transistor of the switch cell 304. In some embodiments, the PMOS region 122 may extend at least 75% of the distance between the local power rails 128a and 128b in the direction Y. In addition, the switch cell 304 may include only the PMOS region 122 and no NMOS region. For example, the PMOS region 122 may extend into (and thus occupy) the space in the switch cell 304 that would conventionally be occupied by an NMOS region (e.g., one space on each side of the line C-C'). The first local power rail 128a, the second local power rail 128b, and the global power rail 148 ( Figure 1D ) can each extend longitudinally parallel to each other in direction X. Because global power rail 148 is covered by PMOS region 122 in direction Z (or overlaps with PMOS region in direction Z), Figure 3A The diagram in omits the global power rail 148.

[0054] The switch unit 304 has no NMOS region. Therefore, in the direction Y, no NMOS region exists between the first local power rail 128 a and the second local power rail 128 b. Instead, the only MOS region between the first local power rail 128 a and the second local power rail 128 b is the PMOS region 122 .

[0055] Despite Figure 3A Although not visible in the figure, it will be understood that the global power rail 148 is electrically connected to the PMOS region 122. According to some embodiments, the global power rail 148 may be at a center point of the switch cell 304 in the direction Y. The center point is a point along the line CC' between opposite ends of the PMOS region 122 in the direction Y. The first source supply power rail 138a and the second source supply power rail 138b may be aligned with the line CC'. Therefore, the global power rail 148 may be between the first source supply power rail 138a and the second source supply power rail 138b in the direction X.

[0056] In some embodiments, the switch cell 304 may be a multi-height cell. For example, the switch cell 304 may have a double cell height. Thus, the switch cell 304 may have a first single-height region 334a and a second single-height region 334b ​​adjacent to each other in the direction Y. The PMOS region 122 may be in both the first single-height region 334a and the second single-height region 334b. As an example, the PMOS region 122 may extend along a majority of the height of each of the first single-height region 334a and the second single-height region 334b ​​in the direction Y.

[0057] Figure 3B is an exemplary plan view of the switch unit 304 . Figure 3C It is along Figure 3B A cross-sectional view taken along line AA'. Figure 3D It is along Figure 3B Cross-sectional view along line BB'.

[0058] To simplify the explanation, Figure 3B 1 shows a global power rail 148 ( Figure 3C ) and contact 150a ( Figure 3C However, because the PMOS region 122 may overlap the entire upper surface of the global power rail 148 and the entire upper surface of the contact 150a, it will be understood that the global power rail 148 and the contact 150a may not be visible in a plan view.

[0059] The switch unit 304 may be coupled to the global power rail 148 via a contact 150a. For example, the contact 150a may contact both the PMOS region 122 and the global power rail 148. In some embodiments, the switch unit 304 may also be coupled to the global power rail 148 via another contact 150 (e.g., contact 150d) spaced apart from the contact 150a in the direction X. Figure 2B )) coupled to global power rail 148.

[0060] Contact 150b may contact both PMOS region 122 and first local power line 128a. Contact 150c may contact both PMOS region 122 and second local power line 128b. Thus, PMOS region 122 may contact each of contacts 150a through 150c. Thus, PMOS region 122 may extend continuously from contact 150b to contact 150c in direction Y. Furthermore, multiple (e.g., two, three, or more) contacts 150 may contact both PMOS region 122 and first local power line 128a, and multiple contacts 150 may contact both PMOS region 122 and second local power line 128b.

[0061] Local power rails 128a and 128b are at or adjacent to opposite ends of switch cell 304. For example, first cell boundary 314a of switch cell 304 may overlap first local power rail 128a in direction Z. Similarly, second cell boundary 314b of switch cell 304 may overlap second local power rail 128b in direction Z. PMOS region 122 may have a first end adjacent to first cell boundary 314a and a second end adjacent to second cell boundary 314b. Thus, opposite ends of PMOS region 122 may be adjacent to opposite ends of switch cell 304, respectively.

[0062] like Figure 3C As shown in FIG, PMOS region 122 may have a third width w3 in direction Y that is wider than a fourth width w4 of contact 150a in direction Y. In some embodiments, global power rail 148 may also have a fourth width w4. Fourth width w4 may be less than half of third width w3, or even less than one-third of third width w3. Because PMOS region 122 vertically overlaps the entire upper surface of contact 150a, fourth width w4 may be greater than Figure 2C . In addition, the PMOS region 122 is the only PMOS region in contact with the contact 150a. In some embodiments, the switch cell 304 may include only the PMOS region 122 and no NMOS region. For example, the PMOS region 122 may be a wide PMOS region that extends into the space that would normally be occupied by an NMOS region in the switch cell 304 (and thus occupies the space that would normally be occupied by an NMOS region in the switch cell 304). In addition, Figure 3C It is also shown that the entire upper surface of contact 150 a may contact the lower surface of PMOS region 122 , and the lower surface of contact 150 a may contact the upper surface of global power rail 148 .

[0063] The vertical axis 324 extends in the direction Z through the center point of the contact 150a in the direction Y (and the center point of the global power rail 148 in the direction Y). The vertical axis 324 is between the first cell boundary 314a and the second cell boundary 314b (e.g., in the middle of the first cell boundary 314a and the second cell boundary 314b). Although the cell boundaries 314a and 314b are Figure 3B are shown as extending in direction X, but they may also be Figure 3C , extending in direction Z. Thus, cell boundaries 314a and 314b may extend both vertically and horizontally.

[0064] Switching unit 304 can transfer the voltage of global power rail 148 to first local power rail 128a and / or second local power rail 128b. For example, PMOS region 122 can be configured to transfer the voltage of global power rail 148 to first local power rail 128a and / or second local power rail 128b.

[0065] like Figure 3D , an upper surface of contact 150b may contact a lower surface of PMOS region 122, and a lower surface of contact 150b may contact an upper surface of first local power rail 128a. Similarly, an upper surface of contact 150c may contact a lower surface of PMOS region 122, and a lower surface of contact 150c may contact an upper surface of second local power rail 128b.

[0066] Figure 4A and Figure 4B The block diagram and the plan view of the switch unit 404 are shown respectively. The switch unit 404 is Figure 1C Another example of a switch cell 104 is shown in FIG. 404. The switch cell 404 is similar to FIG. 404 except that the source supply power rails 138a and 138b are swapped with the local power rails 128a and 128b. Figure 2A and Figure 2B. Thus, the first PMOS region 122a and the second PMOS region 122b of the switch cell 404 are between the first source supply power rail 138a and the second source supply power rail 138b in the direction Y. The global power rail 148 extends longitudinally in parallel with the source supply power rails 138a and 138b in the direction X. Furthermore, the global power rail 148 is between the first local power rail 128a and the second local power rail 128b in the direction X. The first single height region 434a of the switch cell 404 is similar to the first single height region 234a of the switch cell 204 (the first single height region 434a of the switch cell 404 is similar to the first single height region 234a of the switch cell 204 in that the first PMOS region 122a is therein), and the second single height region 434b of the switch cell 404 is similar to the second single height region 234b of the switch cell 204 (the second single height region 434b of the switch cell 404 is similar to the second single height region 234b of the switch cell 204 in that the second PMOS region 122b is therein).

[0067] The switch cell 404 has no NMOS regions. Therefore, no NMOS regions exist between the first source supply power rail 138 a and the second source supply power rail 138 b in the direction Y. Instead, the only MOS regions between the first source supply power rail 138 a and the second source supply power rail 138 b are the first PMOS region 122 a and the second PMOS region 122 b.

[0068] In addition to the source supply power rails 138a and 138b swapping positions with the local power rails 128a and 128b, Figure 4C and Figure 4D Similar to Figure 2C and Figure 2D . Thus, the first cell boundary 414a may overlap the first source supply power rail 138a in the direction Z, and the second cell boundary 414b may overlap the second source supply power rail 138b in the direction Z. In addition, the upper surface of the contact 150b may contact the lower surface of the first PMOS region 122a, and the lower surface of the contact 150b may contact the upper surface of the first source supply power rail 138a. Similarly, the upper surface of the contact 150c may contact the lower surface of the second PMOS region 122b, and the lower surface of the contact 150c may contact the upper surface of the second source supply power rail 138b. The vertical axis 424 is similar to Figure 2C and Figure 2D The vertical axis 224 in.

[0069] Figure 5A and Figure 5B The block diagram and the plan view of the switch unit 504 are shown respectively. The switch unit 504 is Figure 1CAnother example of a switch cell 104 is shown in FIG. 504. The switch cell 504 is similar to FIG. 504 except that the source supply power rails 138a and 138b are swapped with the local power rails 128a and 128b. Figure 3A and Figure 3B . Thus, the PMOS region 122 of the switch cell 504 is between the first source supply power rail 138a and the second source supply power rail 138b in the direction Y. In addition, the global power rail 148 is between the first local power rail 128a and the second local power rail 128b in the direction X. The first single height region 534a of the switch cell 504 is similar to the first single height region 334a of the switch cell 304, and the second single height region 534b of the switch cell 504 is similar to the second single height region 334b ​​of the switch cell 304. Thus, the PMOS region 122 is in both regions 534a and 534b. In addition, Figure 5B Shows something like Figure 3B Contours 548 and 550 are shown as contours 348 and 350 .

[0070] Switch cell 504 has no NMOS region. Therefore, no NMOS region exists between first source supply rail 138 a and second source supply rail 138 b in direction Y. Instead, the only MOS region between first source supply rail 138 a and second source supply rail 138 b is PMOS region 122 .

[0071] In addition to the source supply power rails 138a and 138b swapping positions with the local power rails 128a and 128b, Figure 5C and Figure 5D Similar to Figure 3C and Figure 3D . Thus, the first cell boundary 514a may overlap the first source supply power rail 138a in the direction Z, and the second cell boundary 514b may overlap the second source supply power rail 138b in the direction Z. In addition, the upper surface of the contact 150b may contact the lower surface of the PMOS region 122, and the lower surface of the contact 150b may contact the upper surface of the first source supply power rail 138a. Similarly, the upper surface of the contact 150c may contact the lower surface of the PMOS region 122, and the lower surface of the contact 150c may contact the upper surface of the second source supply power rail 138b. The vertical axis 524 is similar to Figure 3C and Figure 3D The vertical axis 324 in.

[0072] The semiconductor device 100 ( Figure 1A ) can provide various advantages. These advantages may include the ability to provide a relatively short length of the contact 150 ( Figure 1D ) Switch unit 104 ( Figure 1C ) of the PMOS region 122 ( Figure 1D ) is electrically connected to BSPDN 118 ( Figure 1C ) of the global power rail 148 ( Figure 1D ), which can be beneficial when forming the contact 150 and can improve the performance of the power gated cell (e.g., the switch cell 104). The use of a short contact 150 can be facilitated by having a relatively wide PMOS region 122 so that the PMOS region 122 extends adjacent to the contact 150. For example, the PMOS region 122 can occupy the space that would conventionally be occupied by an NMOS region. In addition, as Figure 3C and Figure 5C As shown in FIG, by using a PMOS region 122 that vertically overlaps the entire upper surface of the contact 150, the length of the contact 150 can be further shortened. Advantages can also include reducing leakage by using a switch cell 104 that includes one or more PMOS regions 122 and does not include any NMOS regions. As a result, the switch cell 104 can provide effective power gating.

[0073] Example embodiments are described herein with reference to the accompanying drawings. Many different forms and embodiments are possible without departing from the teachings of the present disclosure, and thus the disclosure should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete and will convey the scope of the invention to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0074] Example embodiments are described herein with reference to cross-sectional illustrations of idealized embodiments and schematic illustrations of intermediate structures that are exemplary embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the embodiments herein should not be construed as limited to the specific shapes illustrated but are to include deviations in shapes that result, for example, from manufacturing.

[0075] It should also be noted that in some alternative embodiments, the functions / actions indicated in the flowchart blocks may not occur in the order indicated in the flowchart. For example, two blocks shown in succession may actually be executed substantially simultaneously, or blocks may sometimes be executed in reverse order depending on the functions / actions involved. In addition, the functions of a given block of a flowchart and / or block diagram may be separated into multiple blocks, and / or the functions of two or more blocks of a flowchart and / or block diagram may be at least partially integrated. Finally, other blocks may be added / inserted between the blocks shown and / or blocks / operations may be omitted without departing from the scope of the present invention.

[0076] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will also be understood that, unless expressly defined as such herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense.

[0077] The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the disclosure. As used herein, unless the context clearly indicates otherwise, the singular is intended to include the plural. It will also be understood that the terms "comprise" and / or "include" when used in this specification specify the presence of stated features, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups thereof.

[0078] It will be understood that when an element is referred to as being "coupled to," "connected to," or "responsive to" another element, or "on" another element, the element may be directly coupled to, connected to, or responsive to, or on, the other element, or intervening elements may be present. Conversely, when an element is referred to as being "directly coupled to," "directly connected to," or "directly responsive to," or "directly on" another element, there are no intervening elements. As used herein, the term "and / or" includes any one and all combinations of one or more of the associated listed items. In addition, the symbol " / " (for example, when used in the term "source / drain") will be understood to be equivalent to the term "and / or."

[0079] It will be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of the present embodiment, a first element may be referred to as a second element.

[0080] For ease of description, spatially relative terms (such as, "below," "beneath," "lower," "above," "upper," etc.) may be used herein to describe the relationship of one element or feature to another element or features as shown in the drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if the device in the drawings is turned over, an element described as "below" or "beneath" other elements or features would later be oriented "above" the other elements or features. Thus, the term "below" can encompass both above and below orientations. The device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0081] Many different embodiments have been disclosed herein in conjunction with the above description and accompanying drawings. It will be understood that literally describing and illustrating every combination and subcombination of these embodiments would be unduly repetitive and obscure. Therefore, this specification, including the accompanying drawings, should be construed as constituting a complete written description of all combinations and subcombinations of the embodiments described herein, as well as the manner and process of making and using them, and should support claims to any such combination or subcombination.

[0082] The subject matter disclosed above is to be considered illustrative and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments that fall within the scope of the invention. Thus, to the maximum extent allowed by law, the scope is to be determined by the broadest permissible interpretation of the appended claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.

Claims

1. A semiconductor device comprising: a power gating unit including a p-type metal oxide semiconductor region; Backside global power rail; as well as contacts, contacting both the P-type metal oxide semiconductor region and the backside global power rail, The power gate cell does not have an n-type metal oxide semiconductor region.

2. The semiconductor device according to claim 1, wherein The backside global power rail extends longitudinally in a first direction, wherein the contact extends longitudinally in a second direction perpendicular to the first direction, and The P-type metal oxide semiconductor region is wider than the contact member in the second direction.

3. The semiconductor device according to claim 2, further comprising: a first backside local power rail and a second backside local power rail extending longitudinally in parallel with the backside global power rail in a first direction, The backside global power rail is between the first backside local power rail and the second backside local power rail in the second direction.

4. The semiconductor device according to claim 3, further comprising: A second contact contacts both the P-type metal oxide semiconductor region and the first backside local power rail.

5. The semiconductor device according to claim 4, further comprising: a third contact in contact with both the P-type metal oxide semiconductor region and the second backside local power rail, The width of the backside global power rail in the second direction is less than half of the width of the P-type metal oxide semiconductor region in the second direction. The semiconductor device according to claim 4 , wherein: The power gate unit further includes a second P-type metal oxide semiconductor region in contact with the contact member. wherein the width of the backside global power rail in the second direction is less than 75% of the width of the second P-type metal oxide semiconductor region in the second direction; and The semiconductor device further includes a third contact member in contact with both the second P-type metal oxide semiconductor region and the second backside local power rail.

7. The semiconductor device according to claim 2, further comprising: a first backside source supply power rail and a second backside source supply power rail extending longitudinally in parallel with the backside global power rail in a first direction, The backside global power rail is between the first backside source supply power rail and the second backside source supply power rail in the second direction.

8. The semiconductor device according to claim 7, further comprising: A second contact contacts both the P-type metal oxide semiconductor region and the first backside source supply power rail.

9. The semiconductor device according to claim 8, further comprising: a third contact in contact with both the P-type metal oxide semiconductor region and the second backside source supply power rail, The width of the backside global power rail in the second direction is less than half of the width of the P-type metal oxide semiconductor region in the second direction.

10. The semiconductor device according to claim 8, wherein The power gate unit further includes a second P-type metal oxide semiconductor region in contact with the contact member. wherein the width of the backside global power rail in the second direction is less than 75% of the width of the second P-type metal oxide semiconductor region in the second direction, and The semiconductor device further includes a third contact member in contact with both the second P-type metal oxide semiconductor region and the second backside source supply power rail.

11. A semiconductor device comprising: a power gating unit including a p-type metal oxide semiconductor region; a backside power delivery network comprising a first power line, a second power line, and a third power line extending longitudinally parallel to one another in a first direction, wherein the second power line comprises a global power line between the first power line and the third power line in a second direction perpendicular to the first direction; a first contact extending longitudinally in the second direction and contacting both the P-type metal oxide semiconductor region and the global power line, wherein the P-type metal oxide semiconductor region is wider than the first contact in the second direction; a second contact in contact with both the P-type metal oxide semiconductor region and the first power line; and The third contact element contacts the third power line.

12. The semiconductor device according to claim 11, wherein The P-type metal oxide semiconductor region continuously extends from the second contact to the third contact in the second direction.

13. The semiconductor device according to claim 11, further comprising: The second P-type metal oxide semiconductor region is in contact with the first contact and the third contact.

14. The semiconductor device according to claim 11, further comprising: a fourth contact, contacting both the P-type metal oxide semiconductor region and the global power line, The center point of the power gate unit in the second direction overlaps the global power line in a third direction perpendicular to the first direction and the second direction.

15. The semiconductor device according to claim 11, wherein The first power line and the third power line comprise respective local power lines of the backside power delivery network, and Therein, the first contact, the second contact and the third contact are components of a backside power delivery network.

16. The semiconductor device according to claim 11, wherein The first power line and the third power line comprise respective source supply power lines of the backside power delivery network, and Therein, the first contact, the second contact and the third contact are components of a backside power delivery network.

17. A semiconductor device comprising: a switching unit including a transistor; a first backside power rail, a second backside power rail, and a third backside power rail electrically connected to the transistor, wherein the second backside power rail is a normally-on backside power rail; a first contact in contact with both the normally-on backside power rail and the transistor; a second contact in contact with both the first backside power rail and the transistor; and A third contact contacts both the third backside power rail and the transistor.

18. The semiconductor device according to claim 17, wherein The first backside power rail and the third backside power rail include respective local power rails electrically connected to the transistor.

19. The semiconductor device according to claim 17, wherein The first backside power rail and the third backside power rail include respective source supply power rails electrically connected to the transistors.

20. The semiconductor device according to claim 17, wherein The switch unit is a multi-height switch unit with double unit height, Wherein, the transistor is a p-type metal oxide semiconductor transistor, wherein opposite ends of the P-type metal oxide semiconductor transistor are respectively adjacent to opposite ends of the multi-height switch unit; and Among them, the P-type metal oxide semiconductor transistor is the only transistor of the multi-height switch unit.

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