Semiconductor device

Abstract

A semiconductor device may include: a first logic cell and a second logic cell on a substrate and spaced apart from each other in a first direction, and each of the first logic cell and the second logic cell including a PMOSFET region and an NMOSFET region; and a first metal layer and a second metal layer, wherein the first metal layer and the second metal layer are respectively located on the first logic unit and the second logic unit. The first metal layer comprises a first right interconnection line, a second right interconnection line and a third right interconnection line which extend in parallel in the first direction, and the second right interconnection line is located between the first right interconnection line and the third right interconnection line. The second metal layer may include a first left interconnect line. A shortest distance in the first direction between the first right interconnection line and the first left interconnection line is defined as a first distance in a range of 12 nm to 18 nm.

Description

Technical Field

[0001] The inventive concept relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly, to a semiconductor device including a field effect transistor and a method of manufacturing the semiconductor device. Background Art

[0002] Semiconductor devices may include integrated circuits composed of metal oxide semiconductor field-effect transistors (MOSFETs). To meet the growing demand for semiconductor devices with small pattern sizes and reduced design rules, MOSFETs are being aggressively scaled down. However, this MOSFET downsizing can lead to degradation in the operating properties of semiconductor devices. Various research efforts are underway to overcome the technical limitations associated with semiconductor device downsizing and achieve high-performance semiconductor devices. Summary of the Invention

[0003] Aspects of the inventive concept provide a semiconductor device having improved electrical characteristics and reliability.

[0004] Aspects of the present inventive concept provide a method of manufacturing a semiconductor device having improved electrical characteristics and reliability.

[0005] According to aspects of the present inventive concept, a semiconductor device may include: a first logic cell and a second logic cell, the first logic cell and the second logic cell being located on a substrate and spaced apart from each other in a first direction, each of the first logic cell and the second logic cell including a PMOSFET region and an NMOSFET region; and a first metal layer and a second metal layer, the first metal layer being located on the first logic cell and the second metal layer being located on the second logic cell. The first metal layer may include a first right interconnect line, a second right interconnect line, and a third right interconnect line extending parallel to each other in the first direction, the second right interconnect line being located between the first right interconnect line and the third right interconnect line. The second metal layer may include a first left interconnect line. The first right interconnect line may have a first end facing the first left interconnect line. The second right interconnect line may have a second end facing the second logic cell. The third right interconnect line may have a third end facing the second logic cell. The first end and the third end may protrude beyond the second end in the first direction. The shortest distance between the first right interconnect line and the first left interconnect line in the first direction is defined as a first distance within a range of 12 nm to 18 nm.

[0006] According to aspects of the present inventive concept, a semiconductor device may include: a first logic unit located on a substrate, the first logic unit including a PMOSFET region and an NMOSFET region; and a first metal layer located on the first logic unit. The first metal layer may include first and second lower interconnects extending parallel to each other in a first direction and spaced apart from each other. The first lower interconnects may include first and second interconnects adjacent to each other among the first lower interconnects. The second lower interconnects may include a third interconnect located between the first and second interconnects. The first interconnect may include a first left end and a first right end opposite to each other in the first direction. The second interconnect may include a second left end and a second right end opposite to each other in the first direction. The third interconnect may include a third left end and a third right end opposite to each other in the first direction. The first and second left ends may protrude beyond the third left end in the first direction. The first and second right ends may protrude beyond the third right end in the first direction.

[0007] According to various aspects of the present invention, a semiconductor device may include a first unit and a second unit, the first unit and the second unit being located on a substrate and adjacent to each other in a first direction. Each of the first unit and the second unit may include: an active pattern located on the substrate; a device isolation layer located in a trench defining the active pattern; a source / drain pattern located on the active pattern and a channel pattern electrically connected to the source / drain pattern, the channel pattern including a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern sequentially stacked and spaced apart from each other; a gate electrode spanning the channel pattern, the gate electrode including a first portion located between the active pattern and the first semiconductor pattern, a second portion located between the first semiconductor pattern and the second semiconductor pattern, a third portion located between the second semiconductor pattern and the third semiconductor pattern, and a fourth portion located on the third semiconductor pattern. a gate insulating layer located between the channel pattern and the gate electrode; gate spacers located on opposite side surfaces of the fourth portion of the gate electrode; a gate capping pattern located on a top surface of the gate electrode; a first interlayer insulating layer located on the gate capping pattern; an active contact extending in the first interlayer insulating layer and electrically connected to the source / drain pattern; a gate contact extending in the first interlayer insulating layer and electrically connected to the gate electrode; a second interlayer insulating layer located on the first interlayer insulating layer; and a metal layer located in the second interlayer insulating layer and electrically connected to the active contact and the gate contact. The metal layer may include a first metal layer located on the first cell and a second metal layer located on the second cell. The first metal layer may include a first right interconnect line, a second right interconnect line, and a third right interconnect line extending parallel to each other in the first direction. The second right interconnect line may be located between the first right interconnect line and the third right interconnect line. The second metal layer may include a first left interconnect. The first right interconnect may have a first end facing the first left interconnect. The second right interconnect may have a second end facing the second cell. The third right interconnect may have a third end facing the second cell. The first end and the third end may be positioned beyond the second end in the first direction. The shortest distance between the first right interconnect and the first left interconnect in the first direction is defined as a first distance within a range of 12 nm to 18 nm.

[0008] According to aspects of the present inventive concept, a method for manufacturing a semiconductor device may include: forming a first mold layer on a substrate; etching the first mold layer to form a mold pattern extending in a first direction on the substrate; forming spacers on side surfaces of the mold pattern to define first opening lines therebetween; forming a second mold layer in each of the first opening lines; forming a hard mask pattern on the second mold layer; etching the second mold layer using the hard mask pattern as a mask to form an opening exposing the mold pattern; and performing a first etching process on the opening to increase the length of the opening, thereby forming second opening lines. The first opening lines and the second opening lines may be alternately arranged in a second direction perpendicular to the first direction. Each of the second opening lines may have a first end portion. Each of the first opening lines may have a second end portion. The first end portion may protrude beyond the second end portion in the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figures 1 to 3 is a conceptual diagram illustrating a logic unit of a semiconductor device according to some embodiments of the inventive concept.

[0010] Figure 4 is a plan view illustrating a semiconductor device according to some embodiments of the inventive concept.

[0011] 5A to 5D Along the Figure 4 Cross-sectional views taken along line AA′, line BB′, line CC′, and line DD′.

[0012] Figure 6A It shows that they are set in Figure 4 A plan view of first to fifth lower interconnection lines on the first to fifth interconnection tracks.

[0013] Figure 6B It shows Figure 6A A plan view of a comparative example.

[0014] Figure 7A 、 Figure 7B 、 Figure 8A 、 Figure 8B 、 Figure 9A 、 Figure 9B 、 Figure 9C 、 Figure 10A 、 Figure 10B 、 Figure 10C 、 Figure 10D 、 Figure 11A 、 Figure 11B 、 Figure 11C 、 Figure 12A 、 Figure 12B and Figure 12Care cross-sectional views illustrating a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0015] Figure 13A 、 Figure 14A 、 Figure 15A 、 Figure 16A 、 Figure 17A 、 Figure 18A 、 Figure 19A 、 Figure 22A and Figure 25A is a plan view illustrating a method of manufacturing a first metal layer according to some embodiments of the inventive concept.

[0016] Figure 13B 、 Figure 14B 、 Figure 15B 、 Figure 16B 、 Figure 17B 、 Figure 18B 、 Figure 19B 、 Figure 22B and Figure 25B are respectively along Figure 13A 、 Figure 14A 、 Figure 15A 、 Figure 16A 、 Figure 17A 、 Figure 18A 、 Figure 19A 、 Figure 22A and Figure 25A A cross-sectional view taken along line II'.

[0017] Figure 23 and Figure 24 It is along Figure 22A A cross-sectional view taken along line II'.

[0018] Figure 19C 、 Figure 20 and Figure 21 It is along Figure 19A A cross-sectional view taken along line II-II'.

[0019] 26A to 26D are respectively along Figure 4 1 and 2 are cross-sectional views taken along lines AA′, BB′, CC′, and DD′ to illustrate semiconductor devices according to some embodiments of the inventive concept. DETAILED DESCRIPTION

[0020] Example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown. Figures 1 to 3 is a conceptual diagram illustrating a logic unit of a semiconductor device according to some embodiments of the inventive concept.

[0021] refer to Figure 1, a single-height cell SHC may be provided. Specifically, a first power line M1_R1 and a second power line M1_R2 may be provided on the substrate 100. The first power line M1_R1 may be a conductive path provided with a drain voltage VDD (e.g., a power supply voltage). The second power line M1_R2 may be a conductive path provided with a source voltage VSS (e.g., a ground voltage).

[0022] The single-height cell SHC may be defined between the first power line M1_R1 and the second power line M1_R2. The single-height cell SHC may include one PMOSFET region PR and one NMOSFET region NR. That is, the single-height cell SHC may have a CMOS structure disposed between the first power line M1_R1 and the second power line M1_R2.

[0023] Each of the PMOSFET region PR and the NMOSFET region NR may have a first length W1 in the first direction D1. The length of the single height cell SHC in the first direction D1 may be defined as a first height HE1. The first height HE1 may be substantially equal to the distance (e.g., pitch) between the first power line M1_R1 and the second power line M1_R2.

[0024] The single-height cell (SHC) can constitute a single logic unit. In this specification, a logic unit can refer to a logic device configured to perform a specific function (e.g., AND, OR, XOR, XNOR, inverter, etc.). In other words, a logic unit can include transistors constituting the logic device and interconnect lines connecting the transistors to each other.

[0025] refer to Figure 2 , a double height cell DHC can be provided. In detail, a first power line M1_R1, a second power line M1_R2, and a third power line M1_R3 can be provided on the substrate 100. The first power line M1_R1 can be provided between the second power line M1_R2 and the third power line M1_R3. The third power line M1_R3 can be a conductive path provided with a source voltage VSS.

[0026] The double height cell DHC may be defined between the second power line M1_R2 and the third power line M1_R3 . The double height cell DHC may include a first PMOSFET region PR1 , a second PMOSFET region PR2 , a first NMOSFET region NR1 , and a second NMOSFET region NR2 .

[0027] The first NMOSFET region NR1 may be adjacent to the second power line M1_R2. The second NMOSFET region NR2 may be adjacent to the third power line M1_R3. The first PMOSFET region PR1 and the second PMOSFET region PR2 may be adjacent to the first power line M1_R1. When viewed in a plan view, the first power line M1_R1 may be disposed between the first PMOSFET region PR1 and the second PMOSFET region PR2.

[0028] The length of the double height unit DHC in the first direction D1 may be defined as a second height HE2. The second height HE2 may be Figure 1 The first PMOSFET region PR1 and the second PMOSFET region PR2 of the double-height cell DHC may be merged into a single PMOSFET region.

[0029] Therefore, the channel size of the PMOS transistor of the double height cell DHC can be larger than Figure 1 For example, the channel size of the PMOS transistor of the double-height cell DHC may be approximately twice the channel size of the PMOS transistor of the single-height cell SHC. In this case, the double-height cell DHC can operate at a higher speed than the single-height cell SHC. In some embodiments, Figure 2 The double height unit DHC shown can be defined as a multi-height unit. Although not shown, the multi-height unit can include a triple height unit, whose unit height is Figure 1 The single-height unit of the SHC is approximately three times the unit height.

[0030] refer to Figure 3 The first single-height cell SHC1, the second single-height cell SHC2, and the double-height cell DHC may be two-dimensionally arranged on the substrate 100. The first single-height cell SHC1 may be disposed between the first power line M1_R1 and the second power line M1_R2. The second single-height cell SHC2 may be disposed between the first power line M1_R1 and the third power line M1_R3. The second single-height cell SHC2 may be adjacent to the first single-height cell SHC1 in the first direction D1.

[0031] The double height cell DHC may be disposed between the second power line M1_R2 and the third power line M1_R3 . The double height cell DHC may be adjacent to the first and second single height cells SHC1 and SHC2 in the second direction D2 .

[0032] A partition structure DB may be provided between the first single-height cell SHC1 and the double-height cell DHC and between the second single-height cell SHC2 and the double-height cell DHC. The active region of the double-height cell DHC may be electrically separated (i.e., electrically isolated) from the active region of each of the first single-height cell SHC1 and the second single-height cell SHC2 by the partition structure DB.

[0033] Figure 4 is a plan view illustrating a semiconductor device according to some embodiments of the inventive concept. 5A to 5D Along the Figure 4 Cross-sectional views taken along line AA′, line BB′, line CC′, and line DD′.

[0034] refer to Figure 4 and 5A to 5D , a plurality of logic cells LC1 and LC2 may be provided on a substrate 100. The substrate 100 may be a semiconductor substrate formed of or including silicon, germanium, silicon germanium, a compound semiconductor material, etc. As an example, the substrate 100 may be a silicon substrate (e.g., a silicon wafer).

[0035] Single Height Unit SHC (see Figure 1 ) may be disposed on the substrate 100. Logic transistors constituting a logic circuit may be disposed on a single-height cell SHC. For example, the logic cells LC1 and LC2 may both be single-height cells SHC, but the inventive concept is not limited thereto.

[0036] For example, the logic cells LC1 and LC2 may include a first logic cell LC1 and a second logic cell LC2 adjacent to each other in the second direction D2. Logic transistors may be provided in each of the first logic cell LC1 and the second logic cell LC2 to form a logic circuit. Each of the first logic cell LC1 and the second logic cell LC2 may include a PMOSFET region PR and an NMOSFET region NR. The PMOSFET region PR and the NMOSFET region NR may be spaced apart from each other in the first direction D1.

[0037] The first active pattern AP1 and the second active pattern AP2 may be defined by a trench TR formed in the upper portion of the substrate 100. The first active pattern AP1 and the second active pattern AP2 may be disposed on the PMOSFET region PR and the NMOSFET region NR, respectively. The first active pattern AP1 and the second active pattern AP2 may extend in the second direction D2. Each of the first active pattern AP1 and the second active pattern AP2 may be a vertical protrusion of the substrate 100 (e.g., protruding in the third direction D3). For example, the first direction D1 and the second direction D2 may intersect each other and may be substantially parallel to the lower surface of the substrate 100. For example, the third direction D3 may intersect the first direction D1 and the second direction D2 and may be substantially perpendicular to the lower surface of the substrate 100.

[0038] The device isolation layer ST may be disposed in the trench TR (eg, filling the trench TR). The device isolation layer ST may include a silicon oxide layer. The device isolation layer ST may not cover the first channel pattern CH1 and the second channel pattern CH2 to be described below.

[0039] The first channel pattern CH1 may be disposed on the first active pattern AP1. The second channel pattern CH2 may be disposed on the second active pattern AP2. Each of the first channel pattern CH1 and the second channel pattern CH2 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 stacked sequentially. The first to third semiconductor patterns SP1, SP2, and SP3 may be spaced apart from each other in a vertical direction (i.e., a third direction D3).

[0040] Each of the first to third semiconductor patterns SP1, SP2, and SP3 may be formed of or include at least one of silicon (Si), germanium (Ge), or silicon germanium (SiGe). For example, each of the first to third semiconductor patterns SP1, SP2, and SP3 may be formed of or include crystalline silicon. In some embodiments, the first to third semiconductor patterns SP1, SP2, and SP3 may be stacked nanosheets.

[0041] A plurality of first source / drain patterns SD1 may be disposed on the first active pattern AP1. A plurality of first recesses RS1 may be formed in the upper portion of the first active pattern AP1. The first source / drain patterns SD1 may be disposed in each of the first recesses RS1. The first source / drain patterns SD1 may be impurity regions of a first conductivity type (e.g., p-type). A first channel pattern CH1 may be interposed between each pair of first source / drain patterns SD1. In other words, each pair of first source / drain patterns SD1 may be connected to each other via the stacked first to third semiconductor patterns SP1, SP2, and SP3. As used herein, "element A is connected to element B" (or similar language) means that element A is electrically and / or physically connected to element B.

[0042] A plurality of second source / drain patterns SD2 may be disposed on the second active pattern AP2. A plurality of second recesses RS2 may be formed in the upper portion of the second active pattern AP2. The second source / drain patterns SD2 may be disposed in each of the second recesses RS2. The second source / drain patterns SD2 may be impurity regions of the second conductivity type (e.g., n-type). A second channel pattern CH2 may be interposed between each pair of second source / drain patterns SD2. In other words, each pair of second source / drain patterns SD2 may be connected to each other via the stacked first to third semiconductor patterns SP1, SP2, and SP3.

[0043] The first source / drain pattern SD1 and the second source / drain pattern SD2 may be epitaxial patterns formed by a selective epitaxial growth (SEG) process. As an example, a top surface of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be located at substantially the same level as a top surface of the third semiconductor pattern SP3 (i.e., may be substantially coplanar with the top surface of the third semiconductor pattern SP3). In other embodiments, a top surface of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be higher than a top surface of the third semiconductor pattern SP3 (e.g., relative to the lower surface of the substrate 100).

[0044] In some embodiments, the first source / drain patterns SD1 may be formed of or include a semiconductor material (e.g., SiGe) having a lattice constant greater than that of the semiconductor material of the substrate 100. In this case, the pair of first source / drain patterns SD1 may apply compressive stress to the first channel pattern CH1 therebetween. The second source / drain patterns SD2 may be formed of or include the same semiconductor element (e.g., Si) as the substrate 100.

[0045] The side surface of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may have an uneven or embossed shape. In other words, the side surface of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may have a wavy profile. The side surface of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may protrude toward the first to third portions PO1, PO2, and PO3 of the gate electrode GE, which will be described below.

[0046] The gate electrodes GE may be arranged to span the first channel pattern CH1 and the second channel pattern CH2 and extend in a first direction D1. The gate electrodes GE may be arranged at a first pitch P1 in a second direction D2. Each gate electrode GE may vertically overlap the first channel pattern CH1 and the second channel pattern CH2. As used herein, "element A overlaps element B in the X direction" (or similar language) means that there is at least one straight line extending in the X direction and intersecting both elements A and B.

[0047] The gate electrode GE may include a first portion PO1 between the active pattern AP1 or AP2 and the first semiconductor pattern SP1, a second portion PO2 between the first and second semiconductor patterns SP1 and SP2, a third portion PO3 between the second and third semiconductor patterns SP2 and SP3, and a fourth portion PO4 on the third semiconductor pattern SP3.

[0048] refer to Figure 5D The gate electrode GE may be disposed on the top surface TS, the bottom surface BS, and the opposite side surfaces SW of each of the first to third semiconductor patterns SP1, SP2, and SP3. That is, the transistor according to some embodiments may be a three-dimensional field effect transistor (e.g., MBCFET or GAAFET) in which the gate electrode GE is disposed three-dimensionally around a channel pattern.

[0049] refer to Figure 4 and 5A to 5DA pair of gate spacers GS may be disposed on opposing side surfaces of the fourth portion PO4 of the gate electrode GE. The gate spacers GS may extend along the gate electrode GE in the first direction D1. The top surface of the gate spacers GS may be higher than the top surface of the gate electrode GE (e.g., relative to the lower surface of the substrate 100). The top surface of the gate spacers GS may be substantially coplanar with the top surface of the first interlayer insulating layer 110, which will be described below. In some embodiments, the gate spacers GS may be formed of or include at least one of silicon carbon nitride (SiCN), silicon oxycarbide nitride (SiCON), or silicon nitride (SiN). In other embodiments, the gate spacers GS may have a multilayer structure comprising at least two different materials selected from silicon carbon nitride (SiCN), silicon oxycarbide nitride (SiCON), and silicon nitride (SiN).

[0050] A gate capping pattern GP may be disposed on the gate electrode GE. The gate capping pattern GP may extend along the gate electrode GE and in the first direction D1. The gate capping pattern GP may be formed of, or include, a material having an etch selectivity with respect to the first and second interlayer insulating layers 110 and 120, which will be described below. Specifically, the gate capping pattern GP may be formed of, or include at least one of, silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbide nitride (SiCON), or silicon nitride (SiN).

[0051] The gate insulating layer GI may be interposed between the gate electrode GE and the first channel pattern CH1 and between the gate electrode GE and the second channel pattern CH2. The gate insulating layer GI may be located on the top surface TS, the bottom surface BS, and the side surface SW of each of the first to third semiconductor patterns SP1, SP2, and SP3 (e.g., may cover the top surface TS, the bottom surface BS, and the side surface SW of each of the first to third semiconductor patterns SP1, SP2, and SP3). The gate insulating layer GI may be located on the top surface of the device isolation layer ST located below the gate electrode GE (e.g., may cover the top surface of the device isolation layer ST located below the gate electrode GE).

[0052] In some embodiments, the gate insulating layer GI may include a silicon oxide layer, a silicon oxynitride layer, and / or a high-k dielectric layer. The high-k dielectric layer may be formed of at least one high-k dielectric material having a higher dielectric constant than silicon oxide, or include at least one high-k dielectric material having a higher dielectric constant than silicon oxide. For example, the high-k dielectric material may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0053] refer to Figure 4 and 5A to 5D The gate electrode GE may include a first metal pattern and a second metal pattern located on the first metal pattern. The first metal pattern may be disposed on the gate insulating layer GI and may be adjacent to the first to third semiconductor patterns SP1, SP2, and SP3. The first metal pattern may include a work function metal that can be used to adjust the threshold voltage of the transistor. By adjusting the thickness and composition of the first metal pattern, a transistor with a desired threshold voltage can be achieved. For example, the first portion PO1 and the second portion PO2 of the gate electrode GE may be formed of the first metal pattern or the work function metal.

[0054] The first metal pattern may include a metal nitride layer. For example, the first metal pattern may include a layer composed of at least one metal material selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo). In some embodiments, the first metal pattern may also include carbon (C) and / or nitrogen (N). The first metal pattern may include multiple stacked work function metal layers.

[0055] The second metal pattern may be formed of, or include, a metal material having a lower resistance than the first metal pattern. For example, the second metal pattern may be formed of, or include at least one metal material selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta). For example, the third portion PO3 of the gate electrode GE may include a first metal pattern and a second metal pattern located on the first metal pattern.

[0056] A first interlayer insulating layer 110 may be disposed on the substrate 100. The first interlayer insulating layer 110 may be located on (e.g., may cover) the gate spacer GS and the first and second source / drain patterns SD1 and SD2. A top surface of the first interlayer insulating layer 110 may be substantially coplanar with a top surface of the gate capping pattern GP and a top surface of the gate spacer GS. A second interlayer insulating layer 120 may be formed on the first interlayer insulating layer 110 to be located on (e.g., cover) the gate capping pattern GP. In some embodiments, both the first interlayer insulating layer 110 and the second interlayer insulating layer 120 may include a silicon oxide layer.

[0057] A pair of partition structures DB may be provided on both sides of each of the first logic cell LC1 and the second logic cell LC2 to face each other in the second direction D2. For example, the partition structure DB may be provided on the boundary between the first logic cell LC1 and the second logic cell LC2. The partition structure DB may extend in the first direction D1 in parallel with the gate electrode GE.

[0058] The partition structure DB may be provided to penetrate the first and second interlayer insulating layers 110 and 120 (i.e., extend within the first and second interlayer insulating layers 110 and 120) and may extend into the first and second active patterns AP1 and AP2. The partition structure DB may penetrate the first and second channel patterns CH1 and CH2. The partition structure DB may be provided to separate the PMOSFET region PR and NMOSFET region NR of the first logic cell LC1 from the PMOSFET region PR and NMOSFET region NR of the second logic cell LC2.

[0059] Active contacts AC may be provided to penetrate the first interlayer insulating layer 110 and the second interlayer insulating layer 120 and be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively. The active contacts AC may be provided on both sides of the gate electrode GE, respectively. When viewed in a plan view, the active contacts AC may be stripe-shaped patterns extending in the first direction D1.

[0060] The active contact AC may be a self-aligned contact. For example, the active contact AC may be formed by a self-aligned process using the gate capping pattern GP and the gate spacer GS. For example, the active contact AC may cover at least a portion of the side surface of the gate spacer GS. Although not shown, the active contact AC may be located on a portion of the top surface of the gate capping pattern GP (e.g., may cover a portion of the top surface of the gate capping pattern GP).

[0061] Silicide patterns SC may be interposed between the active contact AC and the first source / drain pattern SD1, and between the active contact AC and the second source / drain pattern SD2, respectively. The active contact AC may be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively, through the silicide patterns SC. The silicide patterns SC may be formed of or include at least one of metal silicide materials (e.g., titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide).

[0062] The gate contact GC may be provided to penetrate the second interlayer insulating layer 120 and the gate capping pattern GP and may be electrically connected to the gate electrode GE. Figure 5B As shown, the upper region of each active contact AC adjacent to the gate contact GC may be filled with the upper insulating pattern UIP, thereby preventing process failures (eg, short circuits) that may occur when the gate contact GC contacts the adjacent active contact AC.

[0063] Both the active contact AC and the gate contact GC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM may be formed of or include at least one of metal materials (e.g., aluminum, copper, tungsten, molybdenum, and cobalt). The barrier pattern BM may be disposed on the side surfaces and bottom surfaces of the conductive pattern FM (e.g., covering the side surfaces and bottom surfaces of the conductive pattern FM). In some embodiments, the barrier pattern BM may include a metal layer and a metal nitride layer. The metal layer may be formed of or include at least one of titanium, tantalum, tungsten, nickel, cobalt, or platinum. The metal nitride layer may be formed of or include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), or platinum nitride (PtN).

[0064] The first metal layer M1 may be disposed in the third interlayer insulating layer 130. The first metal layer M1 may include a first power line M1_R1, a second power line M1_R2, first to fifth lower interconnects MI1 to MI5, and a lower via VI1. The lower via VI1 may be disposed below the first power line M1_R1, the second power line M1_R2, and the first to fifth lower interconnects MI1 to MI5. As used herein, the first metal layer M1 on the first logic cell LC1 may be referred to as the first metal layer M1, and the first metal layer on the second logic cell LC2 may be referred to as the second metal layer M1.

[0065] The first and second power lines M1_R1 and M1_R2 may extend in a second direction D2 to cross the first and second logic cells LC1 and LC2 and be parallel to each other. A drain voltage VDD and a source voltage VSS may be applied to the first and second power lines M1_R1 and M1_R2, respectively.

[0066] like Figure 4 As shown, a first cell boundary CB1 extending in the second direction D2 may be defined in each of the first logic cell LC1 and the second logic cell LC2. A second cell boundary CB2 extending in the second direction D2 may be defined on opposite sides of the first cell boundary CB1. A first power line M1_R1, to which the drain voltage VDD is applied, may be disposed on the first cell boundary CB1. In other words, the first power line M1_R1, to which the drain voltage VDD is applied, may extend along the first cell boundary CB1 in the second direction D2. A second power line M1_R2, to which the source voltage VSS (i.e., ground voltage) is applied, may be disposed on the second cell boundary CB2. In other words, the second power line M1_R2, to which the source voltage VSS is applied, may extend along the second cell boundary CB2 in the second direction D2.

[0067] The first to fifth lower interconnect lines MI1 to MI5 may be disposed between the first power line M1_R1 and the second power line M1_R2. Specifically, the first to fifth interconnect tracks MTR1 to MTR5 may be defined between the first power line M1_R1 and the second power line M1_R2. The first to fifth interconnect tracks MTR1 to MTR5 may extend parallel to each other in the second direction D2. The first to fifth lower interconnect lines MI1 to MI5 may be arranged at a first pitch P1 in the first direction D1. Additional interconnect tracks may be disposed between the first power line M1_R1 and the second power line M1_R2. In some embodiments, at least one of the first to fifth interconnect tracks MTR1 to MTR5 may be omitted.

[0068] One or more first lower interconnection lines MI1 may be disposed on the first interconnection track MTR1, one or more second lower interconnection lines MI2 may be disposed on the second interconnection track MTR2, one or more third lower interconnection lines MI3 may be disposed on the third interconnection track MTR3, one or more fourth lower interconnection lines MI4 may be disposed on the fourth interconnection track MTR4, and one or more fifth lower interconnection lines MI5 may be disposed on the fifth interconnection track MTR5.

[0069] The first to fifth lower interconnection lines MI1 to MI5 may extend along the first to fifth interconnection tracks MTR1 to MTR5 in the second direction D2, respectively, and may be parallel to each other. When viewed in a plan view, each of the first to fifth lower interconnection lines MI1 to MI5 may be in a linear or stripe pattern.

[0070] The lower via VI1 may be interposed between the first and second power lines M1_R1 and M1_R2 and the active contact AC (e.g., in the third direction D3). The lower via VI1 may be interposed between the first to fifth lower interconnect lines MI1 to MI5 and the active contact AC and the gate contact GC (e.g., in the third direction D3).

[0071] For example, the first and second power lines M1_R1 and M1_R2 and the first to fifth lower interconnections MI1 to MI5 may be formed of or include at least one of metal materials (e.g., copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo)).

[0072] The first power lines M1_R1 and M1_R2, the first to fifth lower interconnects MI1 to MI5, and the lower via VI1 thereunder of the first metal layer M1 can be formed through separate processes. That is, the first power lines M1_R1 and M1_R2, the first to fifth lower interconnects MI1 to MI5, and the lower via VI1 of the first metal layer M1 can all be formed through a single damascene process.

[0073] The second metal layer M2 may be disposed in the fourth interlayer insulating layer 140. The second metal layer M2 may include upper interconnect lines M2_I. Each upper interconnect line M2_I may be a line or stripe pattern extending in the first direction D1. In other words, the upper interconnect lines M2_I may extend in parallel with each other in the first direction D1.

[0074] The second metal layer M2 may further include an upper via VI2. The upper via VI2 may be disposed below the upper interconnection line M2_1. The upper via VI2 may be interposed between the first and second power lines M1_R1, M1_R2, and the first to fifth lower interconnections MI1 to MI5 of the first metal layer M1 and the upper interconnection line M2_I (e.g., in the third direction D3).

[0075] The upper interconnect M2_1 of the second metal layer M2 and the upper via VI2 thereunder can be formed using the same process and can form a single object (e.g., a monolithic object). For example, the upper interconnect M2_1 and the upper via VI2 of the second metal layer M2 can be formed together using a dual damascene process. The upper interconnect M2_1 can be formed from or include at least one of metal materials (e.g., copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo)).

[0076] In some embodiments, although not shown, additional metal layers (eg, M3, M4, M5, etc.) may be further stacked on the fourth interlayer insulating layer 140. Each stacked metal layer may include a routing line.

[0077] Figure 6A It shows that they are set in Figure 4 A plan view of the first to fifth lower interconnection lines MI1 to MI5 on the first to fifth interconnection tracks MTR1 to MTR5. Figure 6A The interconnection lines of the first metal layer M1 are described in more detail.

[0078] refer to Figure 4 and Figure 6A , the first lower interconnection line MI1 disposed on the first interconnection track MTR1 may include a first right interconnection line MI1a and a first left interconnection line MI1b. The second lower interconnection line MI2 disposed on the second interconnection track MTR2 may include a second right interconnection line MI2a and a second left interconnection line MI2b. The third lower interconnection line MI3 disposed on the third interconnection track MTR3 may include a third right interconnection line MI3a and a third left interconnection line MI3b. The fourth lower interconnection line MI4 disposed on the fourth interconnection track MTR4 may include a fourth right interconnection line MI4a and a fourth left interconnection line MI4b. The fifth lower interconnection line MI5 disposed on the fifth interconnection track MTR5 may include a fifth right interconnection line MI5a and a fifth left interconnection line MI5b.

[0079] like Figure 4As shown, the first right interconnection line MI1a to the fifth right interconnection line MI5a can be set on the first logic cell LC1. For example, the first right interconnection line MI1a to the fifth right interconnection line MI5a can be included in the first metal layer M1 on the first logic cell LC1. The first left interconnection line MI1b to the fifth left interconnection line MI5b can be set on the second logic cell LC2. For example, the first left interconnection line MI1b to the fifth left interconnection line MI5b can be included in the first metal layer M1 (which can also be referred to as the second metal layer M1) on the second logic cell LC2. The third right interconnection line MI3a may include a first separation interconnection line MI3a_1 and a second separation interconnection line MI3a_2. The first separation interconnection line MI3a_1 and the second separation interconnection line MI3a_2 can be separated from each other (for example, in the second direction D2) by the third interlayer insulating layer 130. Figure 6A As shown, in some embodiments, the first separation interconnection line MI3a_1 and the second separation interconnection line MI3a_2 may be omitted. In other words, in some embodiments, the third right interconnection line MI3a may not include a separation interconnection line (ie, may not include a separation portion).

[0080] The first right interconnection line MI1a may be spaced apart from the first left interconnection line MI1b in the second direction D2. The second right interconnection line MI2a may be spaced apart from the second left interconnection line MI2b in the second direction D2. The third right interconnection line MI3a may be spaced apart from the third left interconnection line MI3b in the second direction D2. The fourth right interconnection line MI4a may be spaced apart from the fourth left interconnection line MI4b in the second direction D2. The fifth right interconnection line MI5a may be spaced apart from the fifth left interconnection line MI5b in the second direction D2.

[0081] The first left interconnection line MI1b may correspond to the first right interconnection line MI1a. The second left interconnection line MI2b may correspond to the second right interconnection line MI2a. The third left interconnection line MI3b may correspond to the third right interconnection line MI3a. The fourth left interconnection line MI4b may correspond to the fourth right interconnection line MI4a. The fifth left interconnection line MI5b may correspond to the fifth right interconnection line MI5a.

[0082] The first to fifth right interconnects MI1a to MI5a may have first to fifth lengths W1 to W5, respectively, in the second direction D2. The second length W2 may be greater than the first, third, and fifth lengths W1, W3, and W5 (i.e., longer than the first, third, and fifth lengths W1, W3, and W5). The fourth length W4 may be greater than the first, third, and fifth lengths W1, W3, and W5. As used herein, the second and fourth right interconnects MI2a and MI4a may also be referred to as first lower interconnects. As used herein, the first, third, and fifth right interconnects MI1a, MI3a, and MI5a may also be referred to as second lower interconnects.

[0083] The first right interconnect MI1a may have one end referred to as the first right end EN1a and an opposite end referred to as the first left end EN1b. The second right interconnect MI2a may have one end referred to as the second right end EN2a and an opposite end referred to as the second left end EN2b. The third right interconnect MI3a may have one end referred to as the third right end EN3a and an opposite end referred to as the third left end EN3b. The fourth right interconnect MI4a may have one end referred to as the fourth right end EN4a and an opposite end referred to as the fourth left end EN4b. The fifth right interconnect MI5a may have one end referred to as the fifth right end EN5a and an opposite end referred to as the fifth left end EN5b.

[0084] Each of the first right end EN1a and the first left end EN1b may be the endmost portion of the first right interconnection MI1a. Each of the second right end EN2a and the second left end EN2b may be the endmost portion of the second right interconnection MI2a. Each of the third right end EN3a and the third left end EN3b may be the endmost portion of the third right interconnection MI3a. Each of the fourth right end EN4a and the fourth left end EN4b may be the endmost portion of the fourth right interconnection MI4a. Each of the fifth right end EN5a and the fifth left end EN5b may be the endmost portion of the fifth right interconnection MI5a.

[0085] The first right end EN1a may be opposite to the first left end EN1b in the second direction D2. The second right end EN2a may be opposite to the second left end EN2b in the second direction D2. The third right end EN3a may be opposite to the third left end EN3b in the second direction D2. The fourth right end EN4a may be opposite to the fourth left end EN4b in the second direction D2. The fifth right end EN5a may be opposite to the fifth left end EN5b in the second direction D2.

[0086] The first right position RP1 and the second right position RP2 may be defined on one side of the first logic cell LC1. The first left position LP1 and the second left position LP2 may be defined on opposite sides of the first logic cell LC1. Each of the first right position RP1 and the second right position RP2 and the first left position LP1 and the second left position LP2 may be an imaginary line extending in the first direction D1.

[0087] The first right end EN1a, the third right end EN3a, and the fifth right end EN5a may be located at a first right position RP1. The second right end EN2a and the fourth right end EN4a may be located at a second right position RP2. The second right position RP2 may be spaced apart from the first right position RP1 by a first distance DT1 in the second direction D2. The second right position RP2 may be offset from the first right position RP1 by the first distance DT1 in the second direction D2. The first distance DT1 may be in a range of 2 nanometers (nm) to 10 nm.

[0088] Each of the second right end EN2a and the fourth right end EN4a may protrude relative to the first right end EN1a, the third right end EN3a, and the fifth right end EN5a by a first distance DT1 in the second direction D2. In other words, the second right end EN2a and the fourth right end EN4a may protrude beyond the first right end EN1a, the third right end EN3a, and the fifth right end EN5a in the second direction D2 by a first distance DT1 (e.g., in the range of 2 nm to 10 nm). Each of the second right end EN2a and the fourth right end EN4a may deviate from the first right end EN1a, the third right end EN3a, and the fifth right end EN5a in the second direction D2. In other words, the second right end EN2a and the fourth right end EN4a may be positioned so as to extend beyond the first right end EN1a, the third right end EN3a, and the fifth right end EN5a in the second direction D2.

[0089] The first left end EN1b, the third left end EN3b, and the fifth left end EN5b may be located at a first left position LP1. The second left end EN2b and the fourth left end EN4b may be located at a second left position LP2. The first left position LP1 may be spaced apart from the second left position LP2 by a second distance DT2 in the second direction D2. The first left position LP1 may be offset from the second left position LP2 by a second distance DT2 in the second direction D2. The second distance DT2 may range from 2 nm to 10 nm.

[0090] The second left end EN2b and the fourth left end EN4b may protrude a second distance DT2 relative to the first left end EN1b, the third left end EN3b, and the fifth left end EN5b in the second direction D2. In other words, the second left end EN2b and the fourth left end EN4b may protrude beyond the first left end EN1b, the third left end EN3b, and the fifth left end EN5b by a second distance DT2 (e.g., in the range of 2 nm to 10 nm) in the second direction D2. Each of the second left end EN2b and the fourth left end EN4b may deviate from the first left end EN1b, the third left end EN3b, and the fifth left end EN5b in the second direction D2. In other words, the second left end EN2b and the fourth left end EN4b may exceed the first left end EN1b, the third left end EN3b, and the fifth left end EN5b in the second direction D2. It will be understood that the second direction D2 is included in Figure 4 and Figure 6A The direction of movement is both from left to right and from right to left.

[0091] The first to fifth left interconnection lines MI1b to MI5b may have sixth to tenth lengths in the second direction D2, respectively. The seventh length may be greater than the sixth, eighth, and tenth lengths. The ninth length may be greater than the sixth, eighth, and tenth lengths.

[0092] The first left interconnection line MI1b may include a sixth right end EN1c located at one side thereof. The second left interconnection line MI2b may include a seventh right end EN2c located at one side thereof. The third left interconnection line MI3b may include an eighth right end EN3c located at one side thereof. The fourth left interconnection line MI4b may include a ninth right end EN4c located at one side thereof. The fifth left interconnection line MI5b may include a tenth right end EN5c located at one side thereof.

[0093] The sixth right end EN1c may be the endmost portion of the first left interconnection wire MI1b. The seventh right end EN2c may be the endmost portion of the second left interconnection wire MI2b. The eighth right end EN3c may be the endmost portion of the third left interconnection wire MI3b. The ninth right end EN4c may be the endmost portion of the fourth left interconnection wire MI4b. The tenth right end EN5c may be the endmost portion of the fifth left interconnection wire MI5b.

[0094] The sixth right end EN1c and the first left end EN1b may face each other in the second direction D2. The seventh right end EN2c and the second left end EN2b may face each other in the second direction D2. The eighth right end EN3c and the third left end EN3b may face each other in the second direction D2. The ninth right end EN4c and the fourth left end EN4b may face each other in the second direction D2. The tenth right end EN5c and the fifth left end EN5b may face each other in the second direction D2.

[0095] The sixth to tenth right ends EN1c to EN5c can be configured to have substantially the same characteristics as the first to fifth right ends EN1a to EN5a, respectively. Specifically, each of the seventh to ninth right ends EN2c and EN4c can protrude relative to the sixth to eighth right ends EN3c and EN5c by a first distance DT1 in the second direction D2. In other words, the seventh to ninth right ends EN2c and EN4c can protrude beyond the sixth to eighth right ends EN3c and EN5c in the second direction D2 by a first distance DT1 (e.g., in the range of 2 nm to 10 nm). Each of the seventh to ninth right ends EN2c and EN4c can be offset from the sixth to eighth right ends EN3c and EN5c in the second direction D2. In other words, the seventh to ninth right ends EN2c and EN4c can be positioned so as to extend beyond the sixth to eighth right ends EN3c and EN5c in the second direction D2.

[0096] The shortest distance between the seventh right end EN2c and the second left end EN2b in the second direction D2 may be a first distance TIT1. The first distance TIT1 may be in the range of 12 nm to 18 nm. The shortest distance between the eighth right end EN3c and the third left end EN3b in the second direction D2 may be a second distance TIT2. The second distance TIT2 may be greater than the first distance TIT1.

[0097] The shortest distance between the ninth right end EN4c and the fourth left end EN4b in the second direction D2 may be equal to the first distance TIT1. The shortest distance between the tenth right end EN5c and the fifth left end EN5b in the second direction D2 may be equal to the second distance TIT2. The distances between the first to fifth left ends EN1b to EN5b and the sixth to tenth right ends EN1c to EN5c may increase and decrease in an alternating manner.

[0098] Each of the first to fifth right ends EN1a to EN5a, the first to fifth left ends EN1b to EN5b, and the sixth to tenth right ends EN1c to EN5c may have a semi-elliptical outline (for example, when viewed in a plan view). Each of the first to fifth right ends EN1a to EN5a, the first to fifth left ends EN1b to EN5b, and the sixth to tenth right ends EN1c to EN5c may have a curvature. The curvature of each of the first to fifth right ends EN1a to EN5a, the first to fifth left ends EN1b to EN5b, and the sixth to tenth right ends EN1c to EN5c may be different from Figure 4The curvature of the inner sidewall RSW of the first separation interconnect line MI3a_1 and the second separation interconnect line MI3a_2 may be greater than the curvature of the ends of the first to fifth right ends EN1a to EN5a, the ends of the first to fifth left ends EN1b to EN5b, and the ends of the sixth to tenth right ends EN1c to EN5c.

[0099] Figure 6B It shows Figure 6A A plan view of a comparative example. Figure 6B , all of the first to fifth right interconnection lines MI1 a to MI5 a may have the same length (eg, in the second direction D2 ). Figure 6B The first length W1 to the fifth length W5 may be less than Figure 6A The first to fifth right ends EN1a to EN5a may be located at a first right position RP1. The first to fifth left ends EN1b to EN5b may be located at a first left position LP1.

[0100] The distances from the seventh to tenth right ends EN2c to EN5c to the first to fifth left ends EN1b to EN5b may have substantially the same value (eg, a third distance TIT3). The third distance TIT3 may be greater than Figure 6A The first distance TIT1.

[0101] In some embodiments, the first additional interconnection line and the second additional interconnection line may be respectively interposed between the second right interconnection line MI2a and the third right interconnection line MI3a, and between the fourth right interconnection line MI4a and the fifth right interconnection line MI5a. The first additional interconnection line and the second additional interconnection line may be configured to have substantially the same characteristics as the first right interconnection line MI1a, the third right interconnection line MI3a, and the fifth right interconnection line MI5a. In other embodiments, because the lower interconnection line is formed separately through three different processes, at least one of the three interconnections adjacent to each other may have a length longer than the remaining interconnections.

[0102] according to Figure 6B In a comparative example, when forming the lower interconnects using a multi-patterning technique (MPT), all the lower interconnects can be formed to have the same length. In this case, the distance between the interconnects in the first and second logic cells LC1 and LC2 (i.e., the third distance TIT3) can be greater than or equal to 20 nm.

[0103] On the other hand, Figure 6AAs shown, in some embodiments, the length of the interconnects of the first metal layer M1 can be alternately increased and decreased. Therefore, the first distance TIT1 between adjacent interconnects can be in the range of 12 nm to 18 nm. In this case, the distance between metal lines in the first metal layer M1 can be minimized, thereby increasing the integration density of the semiconductor device. Consequently, the electrical characteristics of the semiconductor device can be improved.

[0104] 7A to 12C is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to some embodiments of the present invention. Figure 7A 、 Figure 8A 、 Figure 9A 、 Figure 10A 、 Figure 11A and Figure 12A corresponds to Figure 4 Cross-sectional view along line AA'. Figure 10B corresponds to Figure 4 Cross-sectional view along line BB'. Figure 9B 、 Figure 10C 、 Figure 11B and Figure 12B corresponds to Figure 4 Cross-sectional view along line CC'. Figure 7B 、 Figure 8B 、 Figure 9C 、 Figure 10D 、 Figure 11C and Figure 12C corresponds to Figure 4 Cross-sectional view along line D-D'.

[0105] refer to Figure 7A and Figure 7B A substrate 100 including a PMOSFET region PR and an NMOSFET region NR may be provided. Active layers ACL and sacrificial layers SAL may be alternately stacked on the substrate 100. The active layers ACL and the sacrificial layers SAL may be formed of or include at least one of silicon (Si), germanium (Ge), or silicon germanium (SiGe), and may be formed of different materials.

[0106] The sacrificial layer SAL may be formed of or include at least one material having an etch selectivity relative to the active layer ACL. For example, the active layer ACL may be formed of or include silicon (Si), and the sacrificial layer SAL may be formed of or include silicon germanium (SiGe). The germanium concentration of each sacrificial layer SAL may range from 10 at% to 30 at%.

[0107] Mask patterns may be formed on the PMOSFET region PR and the NMOSFET region NR, respectively, of the substrate 100. The mask pattern may be a line or stripe pattern extending in the second direction D2.

[0108] A patterning process using the mask pattern as an etching mask may be performed to form trenches TR defining first and second active patterns AP1 and AP2. The first active pattern AP1 may be formed on the PMOSFET region PR. The second active pattern AP2 may be formed on the NMOSFET region NR.

[0109] A stack pattern STP may be formed on each of the first active pattern AP1 and the second active pattern AP2. The stack pattern STP may include active layers ACL and sacrificial layers SAL that are alternately stacked. The stack pattern STP may be formed together with the first active pattern AP1 and the second active pattern AP2 during a patterning process.

[0110] A device isolation layer ST may be formed in the trench TR (e.g., filling the trench TR). Specifically, an insulating layer may be formed on the substrate 100 to cover the first and second active patterns AP1 and AP2 and the stacked pattern STP. The device isolation layer ST may be formed by recessing the insulating layer until the stacked pattern STP is exposed.

[0111] The device isolation layer ST may be formed of or include at least one insulating material (e.g., silicon oxide). The stack pattern STP may be located at a higher level than the device isolation layer ST (e.g., relative to the lower surface of the substrate 100) and may be exposed outside the device isolation layer ST. In other words, the stack pattern STP may protrude vertically above the device isolation layer ST (e.g., in the third direction D3).

[0112] refer to Figure 8A and Figure 8B , sacrificial patterns PP may be formed across the stacked patterns STP on the substrate 100. Each sacrificial pattern PP may be a line or stripe pattern extending in the first direction D1. The sacrificial patterns PP may be arranged at a first pitch in the second direction D2.

[0113] In detail, forming the sacrificial pattern PP may include forming a sacrificial layer on the substrate 100, forming a hard mask pattern MP on the sacrificial layer, and patterning the sacrificial layer using the hard mask pattern MP as an etching mask. The sacrificial layer may be formed of or include polysilicon.

[0114] A pair of gate spacers GS may be formed on opposite side surfaces of each sacrificial pattern PP. Forming the gate spacers GS may include conformally forming a gate spacer layer on the substrate 100 and anisotropically etching the gate spacer layer. In some embodiments, the gate spacer GS may be a multilayer structure including at least two layers.

[0115] refer to Figures 9A to 9C , a first recess RS1 may be formed in the stack pattern STP on the first active pattern AP1. A second recess RS2 may be formed in the stack pattern STP on the second active pattern AP2. During the formation of the first recess RS1 and the second recess RS2, the device isolation layer ST may also be recessed on both sides of each of the first active pattern AP1 and the second active pattern AP2 (for example, see Figure 9B ).

[0116] In detail, the first recess RS1 can be formed by etching the stacked pattern STP on the first active pattern AP1 using the hard mask pattern MP and the gate spacer GS as an etching mask. The first recess RS1 can be formed between the paired sacrificial patterns PP. The formation of the first recess RS1 can additionally include performing a selective etching process on the exposed portions of the sacrificial layer SAL. Each sacrificial layer SAL can be recessed by the selective etching process to form a recessed area IDE. Therefore, the first recess RS1 can be formed to have a wavy inner surface. The second recess RS2 in the stacked pattern STP on the second active pattern AP2 can be formed by the same method as that for the first recess RS1.

[0117] First to third semiconductor patterns SP1, SP2, and SP3 sequentially stacked on regions between adjacent first recesses RS1 may be formed from the active layer ACL, respectively. The first to third semiconductor patterns SP1, SP2, and SP3 between adjacent first recesses RS1 may constitute a first channel pattern CH1. The first to third semiconductor patterns SP1, SP2, and SP3 between adjacent second recesses RS2 may constitute a second channel pattern CH2.

[0118] refer to 10A to 10D , first source / drain patterns SD1 may be formed in the first recess RS1, respectively. Specifically, a SEG process may be performed using the inner surface of the first recess RS1 as a seed layer to form an epitaxial layer in the first recess RS1 (e.g., to form an epitaxial layer filling the first recess RS1). The epitaxial layer may be grown using the first to third semiconductor patterns SP1, SP2, and SP3 exposed by the first recess RS1 and the substrate 100 as seed layers. In some embodiments, the SEG process may include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process.

[0119] In some embodiments, the first source / drain pattern SD1 may be formed of or include a semiconductor material (e.g., SiGe) having a lattice constant greater than that of the semiconductor material of the substrate 100. During the formation of the first source / drain pattern SD1, the first source / drain pattern SD1 may be in-situ doped with p-type impurities (e.g., boron, gallium, or indium). In other embodiments, impurities may be implanted into the first source / drain pattern SD1 after the first source / drain pattern SD1 is formed.

[0120] Second source / drain patterns SD2 may be formed in the second recesses RS2, respectively. In detail, the second source / drain patterns SD2 may be formed by a SEG process using inner surfaces of the second recesses RS2 as a seed layer.

[0121] In some embodiments, the second source / drain pattern SD2 may be formed of or include the same semiconductor element (e.g., Si) as the substrate 100. During the formation of the second source / drain pattern SD2, the second source / drain pattern SD2 may be in-situ doped with n-type impurities (e.g., phosphorus, arsenic, or antimony). In other embodiments, impurities may be implanted into the second source / drain pattern SD2 after the second source / drain pattern SD2 is formed.

[0122] refer to Figures 11A to 11C A first interlayer insulating layer 110 may be formed on the first and second source / drain patterns SD1 and SD2, the hard mask pattern MP, and the gate spacer GS (e.g., the first interlayer insulating layer 110 may be formed to cover the first and second source / drain patterns SD1 and SD2, the hard mask pattern MP, and the gate spacer GS). In some embodiments, the first interlayer insulating layer 110 may include a silicon oxide layer.

[0123] The first interlayer insulating layer 110 may be planarized to expose the top surface of the sacrificial pattern PP. Planarization of the first interlayer insulating layer 110 may be performed using an etch-back process or a chemical mechanical polishing (CMP) process. During the planarization process, all of the hard mask pattern MP may be removed. Thus, the first interlayer insulating layer 110 may be formed to have a top surface coplanar with the top surfaces of the sacrificial pattern PP and the gate spacers GS.

[0124] In some embodiments, the exposed sacrificial pattern PP may be selectively removed. Due to the removal of the sacrificial pattern PP, an outer region ORG (eg, see FIG. 1 ) exposing the first and second channel patterns CH1 and CH2 may be formed. Figure 11C). The removal of the sacrificial pattern PP may include a wet etching process performed using an etching solution capable of selectively etching polysilicon.

[0125] The sacrificial layer SAL exposed through the outer region ORG may be selectively removed to form the inner region IRG (see, for example, Figure 11C In detail, a process of selectively etching the sacrificial layer SAL may be performed to leave the first to third semiconductor patterns SP1, SP2, and SP3 and remove only the sacrificial layer SAL. An etching recipe for the etching process may be selected so as to etch a layer formed to have a relatively high germanium concentration (e.g., a silicon germanium layer) at a high etching rate. For example, an etching process having a high etching rate for a silicon germanium layer having a germanium concentration greater than 10 at% may be selected.

[0126] During the etching process, the sacrificial layer SAL on the PMOSFET region PR and the NMOSFET region NR may be removed. The etching process may be a wet etching process. The etchant material used in the etching process may be selected to quickly remove the sacrificial layer SAL having a relatively high germanium concentration.

[0127] refer to Figure 11C Because the sacrificial layer SAL is selectively removed, only the first to third semiconductor patterns SP1, SP2, and SP3 stacked on each of the first and second active patterns AP1 and AP2 may remain. Empty regions formed by removing the sacrificial layer SAL may form first to third inner regions IRG1, IRG2, and IRG3, respectively.

[0128] In detail, the first inner region IRG1 may be formed between the active pattern AP1 or AP2 and the first semiconductor pattern SP1, the second inner region IRG2 may be formed between the first and second semiconductor patterns SP1 and SP2, and the third inner region IRG3 may be formed between the second and third semiconductor patterns SP2 and SP3.

[0129] refer to Figures 11A to 11C A gate insulating layer GI may be formed on exposed surfaces of the first to third semiconductor patterns SP1, SP2, and SP3 (e.g., the gate insulating layer GI may be formed to cover the exposed surfaces of the first to third semiconductor patterns SP1, SP2, and SP3). The gate insulating layer GI may be formed to surround each of the first to third semiconductor patterns SP1, SP2, and SP3. The gate insulating layer GI may be formed in each of the first to third inner regions IRG1, IRG2, and IRG3. The gate insulating layer GI may be formed in the outer region ORG.

[0130] refer to 12A to 12C, a gate electrode GE may be formed on the gate insulating layer GI. The gate electrode GE may include a first portion PO1, a second portion PO2, and a third portion PO3 formed in the first inner region IRG1, the second inner region IRG2, and the third inner region IRG3, respectively, and a fourth portion PO4 formed in the outer region ORG. The gate electrode GE may be vertically recessed to have a reduced height. A gate capping pattern GP may be formed on the recessed gate electrode GE. Return Reference 5A to 5D , a second interlayer insulating layer 120 may be formed on the first interlayer insulating layer 110. The second interlayer insulating layer 120 may include a silicon oxide layer. An active contact AC may be formed to penetrate the second interlayer insulating layer 120 and the first interlayer insulating layer 110 and may be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2. A gate contact GC may be formed to penetrate the second interlayer insulating layer 120 and the gate capping pattern GP and may be electrically connected to the gate electrode GE.

[0131] The formation of each of the active contact AC and the gate contact GC may include forming a barrier pattern BM and forming a conductive pattern FM on the barrier pattern BM. The barrier pattern BM may be conformally formed and may include a metal layer and a metal nitride layer. The conductive pattern FM may be formed of or include a low-resistance metal material.

[0132] A partition structure DB may be formed on the boundaries of the first logic cell LC1 and the second logic cell LC2, respectively. In some embodiments, the first logic cell LC1 and the second logic cell LC2 may both be single height cells SHC (eg, see Figure 1 and Figure 4 The separation structure DB may penetrate the second interlayer insulating layer 120 and the gate electrode GE and may extend into the active pattern AP1 or AP2. The separation structure DB may include an insulating material (eg, silicon oxide or silicon nitride).

[0133] A third interlayer insulating layer 130 may be formed on the active contact AC and the gate contact GC. A first metal layer M1 may be formed in the third interlayer insulating layer 130. A fourth interlayer insulating layer 140 may be formed on the third interlayer insulating layer 130. A second metal layer M2 may be formed in the fourth interlayer insulating layer 140.

[0134] Figures 13A to 25B 1 is a diagram illustrating a method of forming a first metal layer M1 of a semiconductor device according to some embodiments of the present inventive concept. In detail, Figure 13A 、 Figure 14A 、 Figure 15A 、 Figure 16A 、 Figure 17A 、 Figure 18A 、 Figure 19A 、 Figure 22A and Figure 25A is a plan view illustrating a method of manufacturing a first metal layer according to some embodiments of the inventive concept. Figure 13B 、 Figure 14B 、 Figure 15B 、 Figure 16B 、 Figure 17B 、 Figure 18B 、 Figure 19B 、 Figure 22B and Figure 25B are respectively along Figure 13A 、 Figure 14A 、 Figure 15A 、 Figure 16A 、 Figure 17A 、 Figure 18A 、 Figure 19A 、 Figure 22A and Figure 25A A cross-sectional view taken along line II'. Figure 23 and Figure 24 It is along Figure 22A A cross-sectional view taken along line II'. Figure 19C 、 Figure 20 and Figure 21 It is along Figure 19A A cross-sectional view taken along line II-II'.

[0135] refer to Figure 13A and Figure 13B , a reference Figure 4 and 5A to 5D The logic transistor described above. An interlayer insulating layer IL may be formed on the logic transistor. The interlayer insulating layer IL may correspond to Figure 4 and 5A to 5D A third interlayer insulating layer 130 may be formed on the interlayer insulating layer IL. A first hard mask layer HL1, a first mold layer ML1, a second mold layer ML2, and a second hard mask layer HL2 may be formed on the interlayer insulating layer IL.

[0136] The first hard mask layer HL1 may have an etch selectivity relative to the interlayer insulating layer IL. The first hard mask layer HL1 may be a single layer or may have a multilayer structure including a plurality of stacked layers. In some embodiments, the hard mask layer HL may include at least one of a silicon oxide layer, a silicon nitride layer, or a metal nitride layer. For example, the first hard mask layer HL1 may be formed of or include tetraethyl orthosilicate (TEOS).

[0137] The first mold layer ML1 may have an etch selectivity relative to the first hard mask layer HL1. The first mold layer ML1 and the second mold layer ML2 may be formed of or include different materials. Each of the first mold layer ML1 and the second mold layer ML2 may include at least one of an amorphous silicon layer, an amorphous carbon layer, a spin-on hard mask (SOH) layer, or a spin-on carbon (SOC) layer. For example, the first mold layer ML1 may be a silicon layer, and the second mold layer ML2 may be an SOH layer.

[0138] The second hard mask layer HL2 may have an etch selectivity with respect to the first mold layer ML1. In some embodiments, the second hard mask layer HL2 may be formed of or include at least one of SiON, SiCN, SiCON, or SiN.

[0139] A first mask pattern MAP1 may be formed on the second hard mask layer HL2. A first mask pattern MAP1 may be formed on the second interconnection track MTR2 and the fourth interconnection track MTR4. The first mask pattern MAP1 may be formed on the same surface as previously referenced. Figure 4 The first mask pattern MAP1 may not be formed at positions corresponding to the first power line M1_R1, the second power line M1_R2, the second right interconnection line MI2a, the fourth right interconnection line MI4a, the second left interconnection line MI2b, and the fourth left interconnection line MI4b described above. Figure 4 The first mask pattern MAP1 may have an etch selectivity with respect to the second hard mask layer HL2 at positions corresponding to the first, third, and fifth right interconnection lines MI1a, MI3a, and MI5a, and the first, third, and fifth left interconnection lines MI1b, MI3b, and MI5b.

[0140] refer to Figure 14A and Figure 14B , the first mold layer ML1 may be etched. Although not specifically shown, the second hard mask layer HL2 and the first and second mold layers ML1 and ML2 may be etched through a patterning process using the first mask pattern MAP1 as an etching mask. Thereafter, the second hard mask layer HL2 and the second mold layer ML2 may be removed.

[0141] The first mold layer ML1 may be etched to form a first mold pattern ML1. A plurality of first openings OP1 may be formed between the first mold patterns ML1. The first openings OP1 may be formed to expose the top surface of the first hard mask layer HL1. The first openings OP1 may be formed at the same position as previously described. Figure 4Each first opening OP1 may extend in the second direction D2. An inner side surface of the first opening OP1 in the second direction D2 may have a semi-elliptical profile.

[0142] refer to Figure 15A and Figure 15B A first spacer layer SPC1 may be conformally formed on the first mold pattern ML1 and the first hard mask layer HL1. The first spacer layer SPC1 may cover the inner side surface of the first opening OP1. The first spacer layer SPC1 may cover the top surface and opposite side surfaces of the first mold pattern ML1. The first spacer layer SPC1 may cover the top surface of the first hard mask layer HL1 exposed by the first opening OP1. The first spacer layer SPC1 may be formed of or include at least one of TiO, SiCN, SiCON, or SiN.

[0143] refer to Figure 16A and Figure 16B , a second mask pattern MAP2 may be formed on the first spacer layer SPC1. The second mask pattern MAP2 may include a second opening OP2. The second opening OP2 may have an elliptical profile. The first spacer layer SPC1 on the first opening OP1 may be exposed through the second opening OP2. The second opening OP2 may be used to Figure 4 The third right interconnection line MI3a is divided into a first separation interconnection line MI3a_1 and a second separation interconnection line MI3a_2. The formation of the second opening OP2 may include performing a photolithography process on the second mask pattern MAP2. The photolithography process may include an exposure process performed using extreme ultraviolet (EUV) as a source light. In some embodiments, the process may be omitted. Figure 16A and Figure 16B technology.

[0144] The first opening OP1 exposed by the second opening OP2 may be filled with an insulating material. The first opening OP1 on the third interconnection track MTR3 may be divided into two first openings OP1 by the insulating material.

[0145] refer to Figure 17A and Figure 17B, the separated first openings OP1 on the third interconnection track MTR3 may have inner sidewalls RSW facing each other. Next, the second mask pattern MAP2 may be removed. The first spacer layer SPC1 may be recessed by an etch-back process until the top surface of the first mold pattern ML1 is exposed. As a result of the recessing process, first spacers SPC1 may be formed on the side surfaces of the first mold pattern ML1.

[0146] Due to the first mold pattern ML1 and the first spacers SPC1, the first opening OP1 may form first open lines OL1. Each first open line OL1 may be a space defined between the first spacers SPC1.

[0147] refer to Figure 18A and Figure 18B , a second mold layer ML2 and a second hard mask layer HL2 may be sequentially formed on the first mold pattern ML1 and the first hard mask layer HL1. The second mold layer ML2 and the second hard mask layer HL2 may be formed to have the same Figure 13A The second mold layer ML2 and the second hard mask layer HL2 have substantially the same features. However, Figure 18B The height of the second mold layer ML2 may be greater than Figure 13B The height of the second mold layer ML2 is determined by the thickness of the second mold layer ML2 (eg, in the third direction D3 ).

[0148] A third mask pattern MAP3 may be formed on the second hard mask layer HL2. A third mask pattern MAP3 may be formed on the first interconnection track MTR1, the third interconnection track MTR3, and the fifth interconnection track MTR5. Figure 4 The third mask pattern MAP3 may be omitted from the region corresponding to the first power line M1_R1 and the second power line M1_R2 described above. Figure 4 The third mask pattern MAP3 is omitted in regions corresponding to the second to fourth right interconnection lines MI2a to MI4a to MI2b to MI4b. The third mask pattern MAP3 may vertically overlap the first opening OP1.

[0149] The third mask pattern MAP3 may be formed of or include the same material as the first mask pattern MAP1. The third mask pattern MAP3 may have an etch selectivity with respect to the second hard mask layer HL2.

[0150] refer to Figure 19A and Figure 19B, the second mold layer ML2 may be etched. Specifically, the second hard mask layer HL2 and the second mold layer ML2 may be etched through a patterning process using the third mask pattern MAP3 as an etching mask. Due to the etching of the second mold layer ML2, a third opening OP3 may be formed in the second mold layer ML2. The third opening OP3 may be formed to expose the top surface of the first mold pattern ML1. In some embodiments, at least one third opening OP3 may be formed to expose a portion of the top surface of the first spacer SPC1.

[0151] The third opening OP3 may be formed in the same manner as previously referenced Figure 4 The third openings OP3 may be located at positions corresponding to the first and second power lines M1_R1 and M1_R2, the second right interconnection line MI2a, the fourth right interconnection line MI4a, the second left interconnection line MI2b, and the fourth left interconnection line MI4b. Each third opening OP3 may extend in the second direction D2. The inner side surface of the third opening OP3 in the second direction D2 may have a semi-elliptical profile.

[0152] refer to Figure 19C , wherein the plurality of third openings OP3 may have a first preliminary width PW1 in the second direction D2. The first preliminary width PW1 may be greater than a width of the third openings OP3 in the first direction D1.

[0153] refer to Figure 20 The second hard mask layer HL2 and the second mold layer ML2 can be etched by performing an etching process on the third opening OP3 (e.g., a first etching step). The etching process may be an ion beam etching (IBE) process. A first incident beam L1 of high-energy ions may be incident at a specific angle toward the top surface of the substrate 100. The incident angle of the first incident beam L1 may be a first incident angle θ1 that is acutely angled with the second direction D2. The substrate 100 may be tilted to allow the first incident beam L1 to be incident at the specific angle.

[0154] The first incident light beam L1 may remove sidewall portions EP1 of the second hard mask layer HL2 and the second mold layer ML2. Consequently, the width of the second mold layer ML2 in the second direction D2 may decrease from the first mold width MW1 to the second mold width MW2. The first preliminary width PW1 of the third opening OP3 may increase to the second preliminary width PW2. The third opening OP3 may extend in the second direction D2 (e.g., may be elongated in the second direction D2). In other words, the length of the third opening OP3 in the second direction D2 may increase.

[0155] refer to Figure 21, the second hard mask layer HL2 and the second mold layer ML2 can be etched again by an etching process performed on the third opening OP3 (e.g., a second etching step). The etching process can be an ion beam etching (IBE) process. The second incident beam L2 of high-energy ions can be incident toward the top surface of the substrate 100 at a specific angle. The incident angle of the second incident beam L2 can be a second incident angle θ2 that is acutely angled with the second direction D2. The substrate 100 can be tilted to allow the second incident beam L2 to be incident at a specific angle. The second incident beam L2 can have a sign different from that of the first incident beam L1. Each of the first incident angle θ1 and the second incident angle θ2 can be in the range of 10° to 80°, but the present inventive concept is not limited to this example.

[0156] The second incident light beam L2 may remove opposing sidewall portions EP2 of the second hard mask layer HL2 and the second mold layer ML2. Consequently, the width of the second mold layer ML2 in the second direction D2 may decrease from the second mold width MW2 to a third mold width MW3. The second preliminary width PW2 of the third opening OP3 may increase to a fourth length W4. The third opening OP3 may extend in the second direction D2 (e.g., may be elongated in the second direction D2). In other words, the length of the third opening OP3 in the second direction D2 may increase.

[0157] because Figure 20 and Figure 21 By performing the etching process, the third opening OP3 may form a second opening line having an increased length (eg, in the second direction D2). Figure 22A and Figure 22B The first mold pattern ML1 exposed by such a second opening line OL2 may be etched. Next, the second hard mask layer HL2 may be removed, and then, an upper portion of the second mold layer ML2 may be etched, thereby reducing a height of the second mold layer ML2 (eg, in the third direction D3).

[0158] The second opening lines OL2 and the first opening lines OL1 may be alternately arranged (ie, alternately arranged) in the first direction D1 (eg, see Figure 23 and Figure 24 ). In the second direction D2, the second opening line OL2 may be longer than the first opening line OL1. An end portion of the second opening line OL2 may protrude in the second direction D2 relative to an end portion of the first opening line OL1. In other words, the end portion of the second opening line OL2 may protrude beyond the end portion of the first opening line OL1 in the second direction D2. An opposite end portion of the second opening line OL2 may protrude in the second direction D2 relative to an opposite end portion of the first opening line OL1. In other words, the opposite end portion of the second opening line OL2 may protrude beyond the opposite end portion of the first opening line OL1 in the second direction D2.

[0159] Each end of the first opening line OL1 may be located at one of the first right position RP1 or the first left position LP1. Each end of the second opening line OL2 may be located at one of the second right position RP2 or the second left position LP2.

[0160] refer to Figure 23 , the second mold layer ML2 may be removed to expose the first spacer SPC1 and the first mold pattern ML1. Because the second mold layer ML2 is removed, both the first open line OL1 and the second open line OL2 may be exposed.

[0161] refer to Figure 24 The first hard mask layer HL1 and the interlayer insulating layer IL may be etched by performing an etching process using the first spacer SPC1 and the first mold pattern ML1 as an etching mask. The first spacer SPC1, the first mold pattern ML1, and the first hard mask layer HL1 may be removed. For example, the first mold pattern ML1 exposed by the second open line OL2 may be removed. The first open line OL1 and the second open line OL2 may be formed in the interlayer insulating layer IL.

[0162] refer to Figure 4 、 Figure 25A and Figure 25B , the interconnects of the first metal layer M1 can be formed by filling the first and second opening lines OL1 and OL2 with a conductive material. Specifically, the first right interconnect line MI1a, the third right interconnect line MI3a, the fifth right interconnect line MI5a, the first left interconnect line MI1b, the third left interconnect line MI3b, and the fifth left interconnect line MI5b can be formed by filling the first opening line OL1 with a conductive material. The first and second power lines M1_R1 and M1_R2, the second right interconnect line MI2a, the fourth right interconnect line MI4a, the second left interconnect line MI2b, and the fourth left interconnect line MI4b can be formed by filling the second opening line OL2 with a conductive material.

[0163] In some embodiments, a third opening line may be additionally formed. The interconnect lines of the first metal layer M1 may be separated by the first to third opening lines. The third opening line may be formed to have substantially the same characteristics as the first opening line OL1. The third opening line may have a shorter length (e.g., in the second direction D2) than the second opening line OL2. In some embodiments, a fourth opening line and a fifth opening line may be additionally formed.

[0164] 26A to 26D are respectively along Figure 4 ', line BB', line CC' and line DD' of the cross-sectional view to illustrate the semiconductor device according to some embodiments of the present invention. In the following description, for the sake of brevity, the previous reference Figure 4and 5A to 5D Described elements may be identified by the same reference numerals without repeating their overlapping descriptions.

[0165] The PMOSFET region PR and the NMOSFET region NR may be defined by a second trench TR2 formed in an upper portion of the substrate 100. The second trench TR2 may be located between the PMOSFET region PR and the NMOSFET region NR. The PMOSFET region PR and the NMOSFET region NR may be spaced apart from each other in the first direction D1 with the second trench TR2 interposed therebetween.

[0166] The first active pattern AP1 and the second active pattern AP2 may be disposed on the PMOSFET region PR and the NMOSFET region NR, respectively. The first active pattern AP1 and the second active pattern AP2 may extend parallel to each other in the second direction D2. The first active pattern AP1 and the second active pattern AP2 may be portions of the substrate 100 that protrude in the vertical direction (i.e., in the third direction D3). First trenches TR1 may be defined between adjacent first active patterns AP1 and between adjacent second active patterns AP2. The first trenches TR1 may be shallower than the second trenches TR2.

[0167] The device isolation layer ST may be disposed in the first trench TR1 and the second trench TR2 (eg, filling the first trench TR1 and the second trench TR2). Upper portions of the first active pattern AP1 and the second active pattern AP2 may protrude vertically above the device isolation layer ST (eg, see FIG. 1 ). Figure 26D Each upper portion of the first active pattern AP1 and the second active pattern AP2 may be fin-shaped. The device isolation layer ST may not be located on the upper portions of the first active pattern AP1 and the second active pattern AP2 (e.g., may not cover the upper portions of the first active pattern AP1 and the second active pattern AP2). The device isolation layer ST may be located on the lower side surfaces of the first active pattern AP1 and the second active pattern AP2 (e.g., may cover the lower side surfaces of the first active pattern AP1 and the second active pattern AP2).

[0168] The first source / drain pattern SD1 may be disposed in an upper portion of the first active pattern AP1. The first source / drain pattern SD1 may be an impurity region of a first conductivity type (e.g., p-type). The first channel pattern CH1 may be interposed between the pair of first source / drain patterns SD1. The second source / drain pattern SD2 may be disposed in an upper portion of the second active pattern AP2. The second source / drain pattern SD2 may be an impurity region of a second conductivity type (e.g., n-type). The second channel pattern CH2 may be interposed between the pair of second source / drain patterns SD2. Other features associated with the first source / drain pattern SD1 and the second source / drain pattern SD2 may be the same as those described in reference to FIG. Figure 4 and 5A to 5D The features in the described embodiments are the same or similar.

[0169] The gate electrode GE may be disposed across the first active pattern AP1 and the second active pattern AP2 and extend in the first direction D1. The gate electrode GE may vertically overlap the first channel pattern CH1 and the second channel pattern CH2. Each gate electrode GE may be disposed to face the top surface and the opposite side surfaces of each of the first channel pattern CH1 and the second channel pattern CH2. Figure 26D As shown, the gate electrode GE may be disposed on the first top surface TS1 of the first channel pattern CH1 and at least one first side surface SW1 of the first channel pattern CH1. The gate electrode GE may be disposed on the second top surface TS2 of the second channel pattern CH2 and at least one second side surface SW2 of the second channel pattern CH2. In other words, the transistor according to some embodiments may be a three-dimensional field effect transistor (e.g., a FinFET), in which the gate electrode GE is disposed to three-dimensionally surround the channel patterns CH1 and CH2.

[0170] Features associated with the active contact AC and the gate contact GC and the first metal layer M1 and the second metal layer M2 may be compared to those described in reference Figure 4 and 5A to 5D Features in the described embodiments are the same or similar.

[0171] In semiconductor devices according to some embodiments of the present invention, interconnects of the first metal layer can be formed using a multi-patterning technique. An ion beam etching (IBE) process can be performed to reduce the width of the insulating portion during the insulation process of the interconnects. During the IBE process, ions are incident toward the substrate at an angle of incidence to reduce the length of the insulating portion. This increases the length of the interconnects. Furthermore, in methods of manufacturing semiconductor devices according to some embodiments of the present invention, the ends of the interconnects can protrude in an alternating pattern. This increases the integration density of the semiconductor device and improves the electrical characteristics of the semiconductor device.

[0172] While example embodiments of the inventive concepts have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the scope of the appended claims.

[0173] As used herein, the terms "comprise," "include," "contain," "have," and any other variations thereof indicate the presence of stated features, steps, operations, elements, components, and / or groups, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. Additionally, it will be understood that although the terms "first," "second," "third," and the like may be used herein to describe various elements, these elements should not be limited by these terms. On the contrary, these terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this disclosure.

Claims

1. A semiconductor device, comprising: a first logic cell and a second logic cell, the first logic cell and the second logic cell being located on a substrate and spaced apart from each other in a first direction, and each of the first logic cell and the second logic cell including a PMOSFET region and an NMOSFET region; as well as a first metal layer and a second metal layer, wherein the first metal layer is located on the first logic unit and the second metal layer is located on the second logic unit; The first metal layer includes a first right interconnection line, a second right interconnection line, and a third right interconnection line extending parallel to each other in the first direction, and the second right interconnection line is located between the first right interconnection line and the third right interconnection line. Wherein, the second metal layer includes a first left interconnection line, wherein the first right interconnection line has a first end facing the first left interconnection line, wherein the second right interconnection line has a second end facing the second logic unit, wherein the third right interconnection line has a third end facing the second logic unit, wherein the first end and the third end protrude beyond the second end in the first direction, and The shortest distance between the first right interconnection line and the first left interconnection line in the first direction is defined as a first distance within a range of 12 nm to 18 nm.

2. The semiconductor device according to claim 1, wherein the first right interconnection line having a fourth end opposite to the first end, wherein the second right interconnection line has a fifth end opposite to the second end, wherein the third right interconnection line has a sixth end opposite to the third end, and The fourth end and the sixth end protrude beyond the fifth end in the first direction.

3. The semiconductor device according to claim 1, wherein the first end protrudes beyond the second end by a second distance in the first direction, and The second distance is in the range of 2 nm to 10 nm.

4. The semiconductor device according to claim 1, wherein In the first direction, a length of the second right interconnection line is smaller than a length of the first right interconnection line and a length of the third right interconnection line. The semiconductor device according to claim 1 , wherein The second metal layer further includes a second left interconnection line and a third left interconnection line, and Wherein, in the first direction, the length of the second left interconnection line is smaller than the length of the first left interconnection line and the length of the third left interconnection line. The semiconductor device according to claim 5 , wherein: the first left interconnection line having a seventh end facing the first right interconnection line, wherein the second left interconnection line has an eighth end facing the second right interconnection line, wherein the third left interconnection line has a ninth end facing the third right interconnection line, and The seventh end and the ninth end protrude beyond the eighth end in the first direction.

7. The semiconductor device according to claim 5, wherein The shortest distance between the second right interconnection line and the second left interconnection line in the first direction is defined as a second distance greater than the first distance.

8. The semiconductor device according to claim 7, wherein The third left interconnection line has a ninth end facing the third right interconnection line, and The shortest distance between the third end and the ninth end in the first direction is defined as a third distance that is smaller than the second distance.

9. The semiconductor device according to claim 1, wherein Each of the first end, the second end, and the third end has a semi-elliptical profile when viewed in plan view.

10. A semiconductor device, comprising: A first logic unit, the first logic unit is located on the substrate, and the first logic unit includes a PMOSFET region and an NMOSFET region; as well as a first metal layer, the first metal layer being located on the first logic unit, wherein the first metal layer includes a first lower interconnection line and a second lower interconnection line, the first lower interconnection line and the second lower interconnection line extend parallel to each other in a first direction and are spaced apart from each other, wherein the first lower interconnection lines include a first interconnection line and a second interconnection line adjacent to each other among the first lower interconnection lines, The second lower interconnection line includes a third interconnection line located between the first interconnection line and the second interconnection line. wherein the first interconnection line includes a first left end and a first right end opposite to each other in the first direction, wherein the second interconnection line includes a second left end and a second right end opposite to each other in the first direction, wherein the third interconnection line includes a third left end and a third right end opposite to each other in the first direction, wherein the first left end and the second left end protrude beyond the third left end in the first direction, and The first right end and the second right end protrude beyond the third right end in the first direction.

11. The semiconductor device according to claim 10, wherein The first right end protrudes beyond the third right end by a first distance, and The first distance is in the range of 2 nm to 10 nm.

12. The semiconductor device according to claim 10, wherein In the first direction, a corresponding length of the second lower interconnection line is smaller than a corresponding length of the first lower interconnection line.

13. The semiconductor device according to claim 10, further comprising: a second logic unit, the second logic unit being adjacent to the first logic unit in the first direction; as well as a second metal layer, the second metal layer being located on the second logic unit, Wherein, the second metal layer includes a fourth interconnection line, and The shortest distance between the fourth interconnection line and the first interconnection line in the first direction is in a range from 12 nm to 18 nm.

14. The semiconductor device according to claim 13, wherein The second metal layer further includes a fifth interconnection line, and The shortest distance between the third interconnection line and the fifth interconnection line in the first direction is greater than the shortest distance between the fourth interconnection line and the first interconnection line in the first direction.

15. The semiconductor device according to claim 10, wherein Each of the first, second, and third left ends and the first, second, and third right ends has a semi-elliptical outline when viewed in a plan view.

16. A semiconductor device comprising a first unit and a second unit, the first unit and the second unit being located on a substrate and adjacent to each other in a first direction, in, Each of the first unit and the second unit includes: an active pattern, the active pattern being located on the substrate; a device isolation layer, the device isolation layer being located in the trench defining the active pattern; a source / drain pattern and a channel pattern, the source / drain pattern being on the active pattern, the channel pattern being electrically connected to the source / drain pattern, the channel pattern comprising a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern sequentially stacked and spaced apart from each other; a gate electrode, the gate electrode spanning the channel pattern, and including a first portion located between the active pattern and the first semiconductor pattern, a second portion located between the first semiconductor pattern and the second semiconductor pattern, a third portion located between the second semiconductor pattern and the third semiconductor pattern, and a fourth portion located on the third semiconductor pattern; a gate insulating layer, the gate insulating layer being located between the channel pattern and the gate electrode; gate spacers, the gate spacers being respectively located on opposite side surfaces of the fourth portion of the gate electrode; a gate covering pattern, the gate covering pattern being located on a top surface of the gate electrode; a first interlayer insulating layer, wherein the first interlayer insulating layer is located on the gate capping pattern; an active contact extending in the first interlayer insulating layer and electrically connected to the source / drain pattern; a gate contact extending in the first interlayer insulating layer and electrically connected to the gate electrode; a second interlayer insulating layer located on the first interlayer insulating layer; and a metal layer located in the second interlayer insulating layer and electrically connected to the active contact and the gate contact, The metal layer includes a first metal layer located on the first unit and a second metal layer located on the second unit. wherein the first metal layer includes a first right interconnection line, a second right interconnection line, and a third right interconnection line extending parallel to each other in the first direction, The second right interconnection line is located between the first right interconnection line and the third right interconnection line. Wherein, the second metal layer includes a first left interconnection line, wherein the first right interconnection line has a first end facing the first left interconnection line, wherein the second right interconnection line has a second end facing the second unit, wherein the third right interconnection line has a third end facing the second unit, wherein the first end and the third end are positioned beyond the second end in the first direction, and The shortest distance between the first right interconnection line and the first left interconnection line in the first direction is defined as a first distance within a range of 12 nm to 18 nm.

17. The semiconductor device according to claim 16, wherein The second metal layer further includes a second left interconnection line and a third left interconnection line, and The shortest distance between the second right interconnection line and the second left interconnection line in the first direction is greater than the first distance.

18. The semiconductor device according to claim 17, wherein the first left interconnection line having a seventh end facing the first right interconnection line, wherein the second left interconnection line has an eighth end facing the second right interconnection line, wherein the third left interconnection line has a ninth end facing the third right interconnection line, and The seventh end and the ninth end protrude beyond the eighth end in the first direction.

19. The semiconductor device according to claim 16, wherein the first right interconnection line having a fourth end opposite to the first end, wherein the second right interconnection line has a fifth end opposite to the second end, wherein the third right interconnection line has a sixth end opposite to the third end, and The fourth end and the sixth end protrude beyond the fifth end in the first direction.

20. The semiconductor device according to claim 16, wherein In the first direction, a length of the second right interconnection line is smaller than a length of the first right interconnection line and a length of the third right interconnection line.

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