Wiring board group and method for manufacturing same, and wiring board and method for manufacturing same

Abstract

The wiring substrate group includes: a carrier substrate; a release layer including a first lower surface facing the carrier substrate and a first upper surface on an opposite side of the first lower surface and including a resin; an intermediate layer including a second lower surface facing the first upper surface and a second upper surface on an opposite side of the second lower surface and including a metal; and a plurality of rewiring layers arranged in the first direction and including a third lower surface at least partially facing the second upper surface and a third upper surface on an opposite side of the third lower surface. The rewiring layer includes a first wiring layer constituting a third lower surface. The first wiring layer includes a conductive layer including a metal different from a metal of the intermediate layer and an insulating layer including a resin. The intermediate layer includes an opening exposing the first upper surface.

Description

Technical Field

[0001] Embodiments of the present invention relate to a wiring board assembly and a method for manufacturing the same, a wiring board and a method for manufacturing the same, and a method for manufacturing a redistribution layer. Background Art

[0002] Packaging technology that allows for high-density mounting of multiple semiconductor components with different functions, such as CPUs and memory, on a single substrate has attracted considerable attention. A structure that electrically connects multiple semiconductor components is also known as an interposer. Interposers, for example, include a conductive layer and a wiring layer including an insulating layer. The wiring layer, for example, allows the relocation of semiconductor component pads or terminals to other locations. This wiring layer is also known as a rewiring layer.

[0003] The rewiring layer is formed on a substrate made of a rigid material such as glass. Patent Document 1 discloses a technique for using the rewiring layer, peeled from the substrate, as an interposer. A peeling layer is provided between the substrate and the rewiring layer. During the peeling process, for example, light is irradiated onto the peeling layer. The rewiring layer is then separated from the substrate.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Laid-Open No. 2021-18997

[0007] Patent Document 2: Japanese Patent No. 6014907

[0008] Patent Document 3: Japanese Patent No. 6159820 Summary of the Invention

[0009] The rewiring layer formation process sometimes includes high-temperature steps, such as heating the insulating layer. If the release layer contains moisture or low-molecular-weight components, or if its molecular structure changes over time, gas may be generated within the release layer during the rewiring layer formation process. If this generated gas accumulates at the interface between the release layer and the rewiring layer, there is a risk of unintended delamination of the rewiring layer.

[0010] An object of the first embodiment of the present disclosure is to provide a wiring board group and a method for manufacturing the same, and a wiring board and a method for manufacturing the same, which can effectively solve such problems.

[0011] The first embodiment of the present disclosure relates to the following [1] to

[15] .

[0012] [1] A wiring substrate assembly comprising:

[0013] a carrier substrate;

[0014] a peeling layer including a first lower surface facing the carrier substrate and a first upper surface located on an opposite side of the first lower surface and containing a resin;

[0015] an intermediate layer including a second lower surface facing the first upper surface and a second upper surface located on an opposite side of the second lower surface and comprising metal; and

[0016] a plurality of redistribution layers including a third lower surface at least partially facing the second upper surface and a third upper surface located on the opposite side of the third lower surface, and arranged in a first direction,

[0017] The redistribution layer includes a first wiring layer constituting the third lower surface,

[0018] The first wiring layer includes: a conductive layer containing a metal different from the metal of the intermediate layer; and an insulating layer containing a resin.

[0019] The intermediate layer includes an opening exposing the first upper surface.

[0020] [2] According to the wiring substrate group described in [1], the opening may include a first opening located between the conductive layers of two adjacent rewiring layers in the first direction when viewed from above.

[0021] [3] In the wiring substrate assembly according to [1] or [2], the first opening may have a size of 100 μm or more and 500 μm or less in the first direction.

[0022] [4] In the wiring substrate group according to any one of [1] to [3], a ratio of a size of the first opening in the first direction to an arrangement pitch of the plurality of rewiring layers in the first direction may be greater than or equal to 0.0010 and less than or equal to 0.10.

[0023] [5] According to any one of [1] to [4], the wiring substrate group may also be that the insulating layer includes: a second area located in the area where the conductive layer is distributed when viewed from above; and a first area surrounding the second area when viewed from above, and the opening includes a plurality of second openings overlapping with the second area when viewed from above.

[0024] [6] In the wiring board assembly described in [5], the second opening may have a size of 50 μm or less when viewed from above.

[0025] [7] In the wiring substrate group described in [5] or [6], a ratio of the area of ​​the plurality of second openings to the area of ​​the second region may be greater than or equal to 0.0010 and less than or equal to 0.10.

[0026] [8] According to the wiring substrate group described in any one of [5] to [7], the conductive layer of the first wiring layer may include a plurality of pads located on the third lower surface and located between two adjacent second openings when viewed from above.

[0027] [9] In the wiring substrate group described in any one of [1] to [8], the intermediate layer may include titanium, nickel, molybdenum, tungsten, tantalum, chromium, or an alloy containing these metals, and the conductive layer may include copper or a copper alloy.

[0028]

[10] According to the wiring substrate group described in any one of [1] to [9], a portion of the insulating layer of the first wiring layer may be located in the opening and in contact with the first upper surface of the peeling layer.

[0029]

[11] The wiring board assembly according to any one of [1] to

[10] may further include a semiconductor element located on the third upper surface of the redistribution layer.

[0030]

[12] A method for manufacturing a wiring substrate assembly, comprising:

[0031] A step of preparing a laminate comprising: a carrier substrate; and a release layer including a first lower surface facing the carrier substrate and a first upper surface located opposite to the first lower surface and containing a resin;

[0032] an intermediate layer step of forming an intermediate layer, the intermediate layer including a second lower surface facing the first upper surface and a second upper surface located on the opposite side of the second lower surface and containing metal; and

[0033] a redistribution layer forming step of forming a plurality of redistribution layers arranged in a first direction, the plurality of redistribution layers including a third lower surface at least partially facing the second upper surface and a third upper surface located on an opposite side of the third lower surface;

[0034] The redistribution layer includes a first wiring layer constituting the third lower surface,

[0035] The first wiring layer includes: a conductive layer containing a metal different from the metal of the intermediate layer; and an insulating layer containing a resin.

[0036] The intermediate layer includes an opening exposing the first upper surface.

[0037]

[13] According to the manufacturing method of the wiring substrate group described in

[12] , the rewiring layer forming process may also include: a process of applying a resin solution containing a resin and a solvent on the intermediate layer; and a process of heating the resin solution applied on the intermediate layer.

[0038]

[14] A wiring substrate comprising:

[0039] a carrier substrate;

[0040] a peeling layer including a first lower surface facing the carrier substrate and a first upper surface located on an opposite side of the first lower surface and containing a resin;

[0041] an intermediate layer including a second lower surface facing the first upper surface and a second upper surface located on an opposite side of the second lower surface and comprising metal; and

[0042] a redistribution layer including a third lower surface at least partially facing the second upper surface and a third upper surface located on an opposite side of the third lower surface,

[0043] The redistribution layer includes a first wiring layer constituting the third lower surface,

[0044] The first wiring layer includes: a conductive layer containing a metal different from the metal of the intermediate layer; and an insulating layer containing a resin.

[0045] The insulating layer includes: a second region located in the region where the conductive layer is distributed when viewed from above; and a first region surrounding the second region when viewed from above.

[0046] The intermediate layer includes a plurality of second openings that overlap with the second region in a plan view and expose the first upper surface.

[0047]

[15] A method for manufacturing a wiring substrate, comprising:

[0048] A step of preparing the wiring board assembly described in any one of [1] to

[11] ; and

[0049] The step of dividing the wiring board group along a boundary between two adjacent redistribution layers in a plan view.

[0050] According to the first embodiment of the present disclosure, it is possible to suppress the peeling of the redistribution layer from occurring at an unexpected timing. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 This is a plan view showing the wiring board assembly according to the first embodiment.

[0052] Figure 2 It is along Figure 1A cross-sectional view of a wiring substrate assembly along line II-II.

[0053] Figure 3 It is a cross-sectional view showing an example of a redistribution layer.

[0054] Figure 4 It is a cross-sectional view showing an example of a conductive layer.

[0055] Figure 5A It is a bottom view showing an example of the third upper surface of the intermediate layer and the redistribution layer.

[0056] Figure 5B It is a bottom view showing an example of the third upper surface of the intermediate layer and the redistribution layer.

[0057] Figure 6 It is a cross-sectional view showing the step of forming a release layer.

[0058] Figure 7 It is a cross-sectional view showing the steps of forming the intermediate layer and the seed layer.

[0059] Figure 8 It is a cross-sectional view showing the step of forming the first resist layer.

[0060] Figure 9 It is a cross-sectional view showing the process of forming a plating layer.

[0061] Figure 10 It is a cross-sectional view showing the step of partially removing the seed layer.

[0062] Figure 11 It is a cross-sectional view showing the step of forming the second resist layer.

[0063] Figure 12 It is a cross-sectional view showing the process of partially removing the intermediate layer.

[0064] Figure 13A It is a cross-sectional view showing an example of the first opening of the intermediate layer.

[0065] Figure 13B It is a plan view showing an example of the first opening of the intermediate layer.

[0066] Figure 14 It is a cross-sectional view showing the step of forming an insulating layer.

[0067] Figure 15 It is a cross-sectional view showing the process of dividing the wiring board group.

[0068] Figure 16 It is a cross-sectional view showing a step of cutting a portion of a wiring substrate.

[0069] Figure 17It is a cross-sectional view showing the step of bonding the third upper surface of the redistribution layer to the first member.

[0070] Figure 18 It is a cross-sectional view showing the step of irradiating the release layer with light.

[0071] Figure 19 It is a cross-sectional view showing the process of separating the redistribution layer from the carrier substrate.

[0072] Figure 20 It is a cross-sectional view showing the process of removing the intermediate layer.

[0073] Figure 21 It is a cross-sectional view showing the step of bonding the third lower surface of the redistribution layer to the second member.

[0074] Figure 22 It is a cross-sectional view showing a redistribution layer bonded to the first member and the second member in the first modification.

[0075] Figure 23 It is a diagram showing the step of separating the first member from the rewiring layer in the first modification.

[0076] Figure 24 It is a cross-sectional view showing a step of forming an opening in the intermediate layer in the second modification.

[0077] Figure 25 It is a cross-sectional view showing the step of forming a seed layer in the second modification.

[0078] Figure 26 It is a cross-sectional view showing the step of forming a plating layer in the second modification.

[0079] Figure 27 This is a cross-sectional view showing an example of a wiring board assembly in a third modified example.

[0080] Figure 28 This is a plan view showing an example of the second opening of the intermediate layer in the third modification.

[0081] Figure 29 This is a plan view showing an example of the second opening of the intermediate layer in the third modification.

[0082] Figure 30 This is a plan view showing an example of the first opening and the second opening of the intermediate layer in the fourth modification.

[0083] Figure 31 This is a plan view showing an example of the second opening of the intermediate layer in the fifth modification.

[0084] Figure 32 This is a cross-sectional view showing an example of a wiring board assembly in the fifth modification.

[0085] Figure 33 It is a cross-sectional view showing a step of forming a plating layer in the sixth modification.

[0086] Figure 34 It is a cross-sectional view showing the step of removing the first resist layer in the sixth modification.

[0087] Figure 35 This is a plan view showing an example of the second opening of the intermediate layer in the sixth modification.

[0088] Figure 36 This is a plan view showing an example of the second opening of the intermediate layer in the sixth modification.

[0089] Figure 37 This is a cross-sectional view showing an example of the second opening of the intermediate layer in the seventh modification.

[0090] Figure 38 It is a diagram showing an example of a product equipped with a through-electrode substrate.

[0091] Figure 39 This is a schematic cross-sectional view of a wiring board assembly according to the second embodiment.

[0092] Figure 40 yes Figure 39 A top view of a wiring substrate assembly.

[0093] Figure 41 It means from Figure 39 FIG. 1 is a diagram illustrating a method for manufacturing a redistribution layer of a wiring substrate assembly.

[0094] Figure 42 It means from Figure 39 FIG. 1 is a diagram illustrating a method for manufacturing a redistribution layer of a wiring substrate assembly.

[0095] Figure 43 It means from Figure 39 FIG. 1 is a diagram illustrating a method for manufacturing a redistribution layer of a wiring substrate assembly.

[0096] Figure 44 It means from Figure 39 FIG. 1 is a diagram illustrating a method for manufacturing a redistribution layer of a wiring substrate assembly.

[0097] Figure 45 It means from Figure 39 FIG. 1 is a diagram illustrating a method for manufacturing a redistribution layer of a wiring substrate assembly.

[0098] Figure 46 It means from Figure 39 FIG. 1 is a diagram illustrating a method for manufacturing a redistribution layer of a wiring substrate assembly.

[0099] Figure 47 It means from Figure 39 FIG. 1 is a diagram illustrating a method for manufacturing a redistribution layer of a wiring substrate assembly.

[0100] Figure 48 It means from Figure 39 FIG. 1 is a diagram illustrating a method for manufacturing a redistribution layer of a wiring substrate assembly.

[0101] Figure 49 It means from Figure 39 FIG. 1 is a diagram illustrating a method for manufacturing a redistribution layer of a wiring substrate assembly.

[0102] Figure 50 It means from Figure 39 FIG. 1 is a diagram illustrating a method for manufacturing a redistribution layer of a wiring substrate assembly.

[0103] Figure 51 It means from Figure 39 FIG. 1 is a diagram illustrating a method for manufacturing a redistribution layer of a wiring substrate assembly.

[0104] Figure 52 It means from Figure 39 FIG. 1 is a diagram illustrating a method for manufacturing a redistribution layer of a wiring substrate assembly.

[0105] Figure 53 It means from Figure 39 FIG. 1 is a diagram illustrating a method for manufacturing a redistribution layer of a wiring substrate assembly.

[0106] Figure 54 It means from Figure 39 FIG. 1 is a diagram illustrating a method for manufacturing a redistribution layer of a wiring substrate assembly.

[0107] Figure 55 It means from Figure 39 FIG. 1 is a diagram illustrating a method for manufacturing a redistribution layer of a wiring substrate assembly.

[0108] Figure 56 It is a diagram showing a rewiring layer according to a modification. DETAILED DESCRIPTION

[0109] The structure of the wiring substrate group and its manufacturing method are described in detail with reference to the accompanying drawings. The embodiment shown below is an example of an embodiment of the present disclosure, and the present disclosure is not limited to these embodiments. Terms such as "substrate", "base material", "sheet", and "film" are not distinguished from each other only based on the difference in name. For example, "substrate" is a concept that includes components that can be called sheets or films. "Surface" refers to a surface that is consistent with the plane direction of the plate-like component that is the object when the plate-like component is observed as a whole and in a large area. The normal direction used for the plate-like component refers to the normal direction relative to the surface of the component. Terms such as "parallel", "orthogonal", lengths, angle values, etc. that determine the shape, geometric conditions and their degree used in this specification are not strictly bound by the meaning and are interpreted as including a range of degrees that can be expected to have the same function.

[0110] In this specification, when multiple candidates for upper limit values ​​and multiple candidates for lower limit values ​​are listed for a certain parameter, the numerical range of the parameter can also be constructed by combining any candidate for upper limit value and any candidate for lower limit value. For example, consider the case where it is recorded as "Parameter B is, for example, greater than A1, may be greater than A2, or may be greater than A3. Parameter B is, for example, less than A4, may be less than A5, or may be less than A6." In this case, the numerical range of parameter B can be greater than A1 and less than A4, greater than A1 and less than A5, greater than A1 and less than A6, greater than A2 and less than A4, greater than A2 and less than A5, greater than A2 and less than A6, greater than A3 and less than A4, greater than A3 and less than A5, or greater than A3 and less than A6.

[0111] In the accompanying drawings referred to in this embodiment, the same or similar symbols are used to mark the same parts or parts having the same functions, and their repeated descriptions are sometimes omitted. In addition, for ease of description, the dimensional ratios of the accompanying drawings are sometimes different from the actual ratios, and sometimes a part of the structure is omitted from the accompanying drawings.

[0112] (First embodiment)

[0113] The first embodiment is based on Japanese Patent Application No. 2023-22912 filed on February 16, 2023, and claims the priority thereof. Figure 1 It is a plan view showing an example of the wiring board group 10 according to the first embodiment. Figure 2 yes Figure 1 1 is a cross-sectional view of the wiring substrate group 10 along the II-II line. The wiring substrate group 10 includes a plurality of wiring substrates having the same structure. As described later, the wiring substrate group 10 is divided to obtain a plurality of wiring substrates.

[0114] The wiring substrate assembly 10 has a first direction D1, a second direction D2, and a third direction D3. The first direction D1 and the second direction D2 are included in the plane direction of the wiring substrate assembly 10. The first direction D1 and the second direction D2 are perpendicular to each other. The third direction D3 is the thickness direction of the wiring substrate assembly 10. The third direction D3 is perpendicular to the first direction D1 and the second direction D2.

[0115] Wiring substrate assembly 10 includes carrier substrate 12, release layer 13, intermediate layer 14, and multiple redistribution layers 20. Release layer 13 and intermediate layer 14 are located between carrier substrate 12 and redistribution layers 20 in the thickness direction of wiring substrate assembly 10. Release layer 13 is located on carrier substrate 12. Intermediate layer 14 is located between release layer 13 and redistribution layers 20.

[0116] Each component of the wiring board assembly 10 will be described.

[0117] (Rewiring layer)

[0118] The plurality of redistribution layers 20 have the same configuration as one another. Figure 1 As shown, the plurality of rewiring layers 20 may also have the same structure when viewed from above. Figure 1 As shown, the plurality of redistribution layers 20 may also be regularly arranged in the plane direction of the wiring substrate assembly 10. For example, the plurality of redistribution layers 20 may also be regularly arranged in the first direction D1 and the second direction D2. The first direction D1 and the second direction D2 may also be parallel to the sides of the carrier substrate 12.

[0119] exist Figure 1 In the diagram, symbol P1 represents the arrangement pitch of the redistribution layers 20 in the first direction D1 , and symbol P2 represents the arrangement pitch of the redistribution layers 20 in the second direction D2 .

[0120] Figure 2 as well as Figure 3 This is a cross-sectional view showing an example of a redistribution layer 20. The redistribution layer 20 includes a third lower surface 201 and a third upper surface 202. The third lower surface 201 faces the carrier substrate 12. The third upper surface 202 is located opposite the third lower surface 201. The redistribution layer 20 includes an insulating layer 21 and a plurality of conductive layers 22. The insulating layer 21 may extend in the third direction D3 of the wiring substrate assembly 10 from the third lower surface 201 to the third upper surface 202.

[0121] In this specification, the “lower surface” such as the third lower surface 201 refers to the surface facing the carrier substrate 12 in the wiring substrate assembly 10 . The “upper surface” refers to the surface located opposite to the “lower surface” in the thickness direction.

[0122] A portion of the plurality of conductive layers 22 may also be a pad 24. The pad 24 may also include an upper surface or a lower surface that is not in contact with an insulating material such as the insulating layer 21. For example, when the pad 24 is located on the third lower surface 201 of the redistribution layer 20, the lower surface of the pad 24 is not in contact with the insulating material. For example, when the pad 24 is located on the third upper surface 202 of the redistribution layer 20, the upper surface of the pad 24 is not in contact with the insulating material.

[0123] Part of the plurality of conductive layers 22 may also be wiring 25. Wiring 25 extends along the first direction D1 or the second direction D2. Both the upper and lower surfaces of wiring 25 may be in contact with an insulating material such as insulating layer 21. The insulating material has insulating properties and can be either an organic material or an inorganic material.

[0124] The redistribution layer 20 may also include a plurality of stacked wiring layers. Figure 2 as well as Figure 3 In the illustrated example, the rewiring layer 20 includes a first wiring layer 20A, a second wiring layer 20B, and a third wiring layer 20C. Each of the wiring layers may include an insulating layer 21 and a plurality of conductive layers 22. The first wiring layer 20A may constitute the third lower surface 201 of the rewiring layer 20. The insulating layer 21 of the third wiring layer 20C may constitute the third upper surface 202 of the rewiring layer 20. The wiring board assembly 10 may also include a conductive layer 22 located on the insulating layer 21 of the third wiring layer 20C and constituting a pad 24.

[0125] A portion of the plurality of conductive layers 22 may also be a through-electrode 26. The through-electrode 26 extends along the third direction D3. For example, the through-electrode 26 is located in an opening formed in the insulating layer 21. The through-electrode 26 can electrically connect, for example, two conductive layers 22 of adjacent wiring layers in the third direction D3.

[0126] The redistribution layer 20 has a thickness T1. Thickness T1 is, for example, 30 μm or greater, or 35 μm or greater. Thickness T1 is, for example, 50 μm or less, or 45 μm or less. Thickness T1 is the distance in the third direction D3 from the third lower surface 201 to the third upper surface 202. The dimensions of the components of the wiring substrate assembly 10, such as thickness T1, are calculated based on a cross-sectional image of the wiring substrate assembly 10 taken with a scanning electron microscope.

[0127] The thickness T2 of each of the multiple wiring layers in the redistribution layer 20 is, for example, 4.0 μm or greater, or 6.0 μm or greater. The thickness T2 of each of the multiple wiring layers in the redistribution layer 20 is, for example, 12.0 μm or less, or 10.0 μm or less. The thickness T2 of the multiple wiring layers may be the same or different.

[0128] Figure 42 is a cross-sectional view showing an example of the conductive layer 22. Figure 4 As shown, the conductive layer 22 may include a seed layer 221 and a plating layer 222. The seed layer 221 is a conductive layer formed by physical film formation such as sputtering. The plating layer 222 is a conductive layer formed on the seed layer 221 by electrolytic plating.

[0129] The seed layer 221 may also include a metal material such as copper, nickel, titanium, chromium, or zinc. The seed layer 221 may also include a compound of these metal materials. The seed layer 221 may also include multiple layers. The plating layer 222 may include a metal such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, titanium, chromium, or zinc, or an alloy thereof.

[0130] The conductive layer 22 may also contain a metal different from the metal constituting the intermediate layer 14. For example, the lower surface of the conductive layer 22 may also contain a metal different from the metal constituting the intermediate layer 14 as a main component. Figure 4 In the example shown, the lower surface of the conductive layer 22 is formed of the seed layer 221. The "metal forming the intermediate layer 14" refers to the metal of the main component in the intermediate layer 14. The "main component" refers to the metal or alloy having the highest content.

[0131] For example, when the intermediate layer 14 contains titanium, nickel, molybdenum, tungsten, tantalum, chromium, or an alloy containing these metals as a main component, the conductive layer 22 may also contain copper or a copper alloy as a main component.

[0132] The thickness T3 of the conductive layer 22 is, for example, 0.1 μm or more, 0.5 μm or more, or 1.0 μm or more. The thickness T3 of the conductive layer 22 is, for example, 10.0 μm or less, or 6.0 μm or less.

[0133] The insulating layer 21 comprises an insulating material having insulating properties. The insulating layer 21 may comprise an organic material or an inorganic material. The insulating layer 21 may include a first insulating layer comprising an organic material and a second insulating layer comprising an inorganic material. The organic material may be, for example, polyimide or epoxy resin.

[0134] like Figure 2 As shown, the insulating layer 21 may also extend to span multiple redistribution layers 20. In other words, in the adjacent first and second redistribution layers 20, the insulating layer 21 of the first redistribution layer 20 and the insulating layer 21 of the second redistribution layer 20 may also be connected.

[0135] (Carrier substrate)

[0136] The carrier substrate 12 is a member that supports the redistribution layer 20. Carrier substrate 12 may include, for example, a glass substrate, a quartz substrate, a sapphire substrate, a resin substrate, a silicon substrate, a silicon carbide substrate, an aluminum oxide (Al2O3) substrate, an aluminum nitride (AlN) substrate, a zirconium oxide (ZrO2) substrate, a lithium niobate substrate, or a tantalum niobate substrate. Resin substrates may also include organic materials. For example, resin substrates may include epoxy resin, polyethylene, or polypropylene. The thickness of carrier substrate 12 may be, for example, greater than 100 μm, greater than 200 μm, or greater than 500 μm. The thickness of carrier substrate 12 may be, for example, less than 2 mm, less than 1.5 mm, or less than 1 mm.

[0137] (peel layer)

[0138] The peeling layer 13 facilitates peeling of the rewiring layer 20 from the carrier substrate 12. The peeling layer 13 includes a first lower surface 131 facing the carrier substrate 12 and a first upper surface opposite to the first lower surface 131. The peeling layer 13 contains, for example, resin.

[0139] The release layer 13 is configured so that the adhesion between the release layer 13 and the rewiring layer 20 is reduced by a certain trigger. The trigger may be irradiation of the release layer 13 with light of a specific wavelength. For example, the release layer 13 may be decomposed by irradiation of the release layer 13 with light of a specific wavelength. The trigger may also be heating the release layer 13. For example, the release layer 13 may also contain a thermoplastic resin.

[0140] The thickness T4 of the release layer 13 is, for example, 0.1 μm or more, 0.2 μm or more, or 0.3 μm or more. The thickness T4 of the release layer 13 is, for example, 1.0 μm or less, 0.8 μm or less, or 0.5 μm or less.

[0141] (Middle layer)

[0142] Intermediate layer 14 is a layer located between peeling layer 13 and rewiring layer 20. Intermediate layer 14 includes a second lower surface 141 facing first upper surface 132 of peeling layer 13, and a second upper surface 142 located opposite second lower surface 141. Second upper surface 142 faces third lower surface 201 of rewiring layer 20. Intermediate layer 14 extends to overlap with multiple conductive layers 22 when viewed from above. For example, intermediate layer 14 extends so as to overlap with multiple conductive layers 22 of one first wiring layer 20A when viewed from above.

[0143] Intermediate layer 14 contains metal. As described above, intermediate layer 14 may contain a metal different from the metal constituting the lower surface of conductive layer 22 as a main component. Intermediate layer 14 is preferably configured so that the adhesion of intermediate layer 14 to release layer 13 is higher than the adhesion of the lower surface of conductive layer 22 to release layer 13.

[0144] Intermediate layer 14 has light-shielding properties due to its metal nature. Therefore, when light is irradiated onto peeling layer 13 during the peeling process of peeling rewiring layer 20 from carrier substrate 12, intermediate layer 14 prevents the light from reaching rewiring layer 20. This, for example, prevents the state of insulating layer 21 of rewiring layer 20 from changing due to light exposure. In the following description, this function of intermediate layer 14 will also be referred to as the "first function of intermediate layer 14."

[0145] Intermediate layer 14 also functions to suppress the propagation of state changes occurring in peeling layer 13 during the peeling process to rewiring layer 20. If insulating layer 21 of rewiring layer 20 is in contact with peeling layer 13 over a large area, expansion and temperature rise occurring in peeling layer 13 during the peeling process are likely to propagate to insulating layer 21. This can result in a degradation of the properties of rewiring layer 20 or make it difficult to peel rewiring layer 20 from peeling layer 13. Positioning intermediate layer 14 between peeling layer 13 and rewiring layer 20 can suppress these issues. In the following description, this function of intermediate layer 14 will also be referred to as the "second function of intermediate layer 14."

[0146] Intermediate layer 14 also functions to facilitate the peeling of rewiring layer 20 from carrier substrate 12. If peeling layer 13 and insulating layer 21 of rewiring layer 20 are made of the same resin, contact between insulating layer 21 and peeling layer 13 could hinder peeling. Positioning intermediate layer 14 between peeling layer 13 and rewiring layer 20 can mitigate this issue. In the following description, this function of intermediate layer 14 will also be referred to as the "third function of intermediate layer 14."

[0147] Intermediate layer 14 also functions to suppress damage to release layer 13 during the process of forming rewiring layer 20. The process of forming insulating layer 21 of rewiring layer 20 includes, for example, applying a solution containing a resin and a solvent. If the solvent comes into contact with release layer 13, it may be absorbed by release layer 13, causing it to swell. Positioning intermediate layer 14 between release layer 13 and rewiring layer 20 can suppress this problem. In the following description, this function of intermediate layer 14 will also be referred to as the "fourth function of intermediate layer 14."

[0148] In this embodiment, the intermediate layer 14 may realize all of the first to fourth functions or may realize part of the first to fourth functions.

[0149] The thickness T5 of the intermediate layer 14 is, for example, 30 nm or more, 50 nm or more, or 100 nm or more. The thickness T5 of the intermediate layer 14 is, for example, 2.0 μm or less, 1.0 μm or less, or 500 nm or less.

[0150] However, the present inventors' research has revealed that when the first upper surface 132 of the release layer 13 is completely covered by the intermediate layer 14, new issues may arise. The release layer 13 may contain components with low boiling points, such as moisture and low-molecular-weight components. If the temperature of the release layer 13 rises during the rewiring layer formation process, gas may be generated within the release layer 13. Furthermore, depending on the material, light and heat from the storage environment may cause changes in the molecular structure, generating gas. If such generated gas accumulates at the interface between the release layer 13 and the intermediate layer 14, for example, there is a risk that the intermediate layer 14 may peel off from the release layer 13 at unexpected times.

[0151] In order to solve such a problem, in this embodiment, Figure 2 as well as Figure 3 As shown, it is proposed to form an opening 143 in a portion of the intermediate layer 14. Gas generated inside the separation layer 13 is discharged through the opening 143. Therefore, it is possible to suppress the intermediate layer 14 from being separated from the separation layer 13 due to the gas.

[0152] Furthermore, if the area of ​​the opening 143 becomes larger, there is a possibility that the first to fourth functions of the intermediate layer 14 may be reduced. Therefore, it is preferable to limit the area of ​​the opening 143 .

[0153] The opening 143 of the intermediate layer 14 is described in detail. Figure 2 as well as Figure 3 As shown, opening 143 penetrates the intermediate layer 14 in the thickness direction. Therefore, a portion of the first upper surface 132 of the release layer 13 is exposed through opening 143. The third lower surface 201 of the redistribution layer 20 includes a portion facing the second upper surface 142 of the intermediate layer 14 and a portion located in the first opening 143 and facing the first upper surface 132 of the release layer 13. The insulating layer 21 of the redistribution layer 20 located in the first opening 143 may also be in contact with the first upper surface 132 of the release layer 13. Gas generated within the release layer 13 is discharged to the exterior of the wiring substrate assembly 10 through opening 143 and the insulating layer 21.

[0154] Figure 5A It is a bottom view showing an example of the intermediate layer 14 and the third lower surface 201 of the redistribution layer 20 . Figure 5AIt can also be said that it is a rear view of the wiring board assembly 10 in the case where the carrier substrate 12 and the peeling layer 13 are removed.

[0155] like Figure 5A As shown, the opening 143 may be located at the boundary between the first wiring layers 20A of two adjacent redistribution layers 20 when viewed from above. In the following description, the opening located at the boundary between the first wiring layers 20A is also referred to as the first opening. The first opening 143 is located between the conductive layers 22 of the first wiring layers 20A of two adjacent redistribution layers 20 when viewed from above.

[0156] The first opening 143 may extend along the boundary of the first wiring layer 20A. For example, the first opening 143 may include a portion extending along the first direction D1 and a portion extending along the second direction D2.

[0157] Symbol K1 represents the dimension in the first direction D1 of the first opening 143 located at the boundary of the first wiring layer 20A arranged in the first direction D1. Symbol K2 represents the dimension in the second direction D2 of the first opening 143 located at the boundary of the first wiring layer 20A arranged in the second direction D2. The dimensions K1 and K2 of the first opening 143 are, for example, not less than 100 μm, or not less than 200 μm. Thus, the gas generated inside the peeling layer 13 is properly discharged through the first opening 143. The dimensions K1 and K2 of the first opening 143 are, for example, not more than 500 μm, or not more than 400 μm. Thus, the degradation of the first to fourth functions of the above-mentioned intermediate layer 14 can be suppressed. The dimensions of the openings of the intermediate layer 14, such as the first opening 143, are determined on the second lower surface 141.

[0158] The dimensions K1 and K2 of the first opening 143 may also be determined relative to the arrangement pitches P1 and P2 of the redistribution layer 20. K1 / P1, which is the ratio of dimension K1 to arrangement pitch P1, is, for example, 0.0010 or greater, 0.0030 or greater, or 0.010 or greater. K1 / P1 is, for example, 0.10 or less, 0.050 or less, or 0.020 or less. The numerical range of K2 / P2, which is the ratio of dimension K2 to arrangement pitch P2, can be within the numerical range of K1 / P1.

[0159] The size of the first opening 143 may also be determined relative to the size of the first region of the redistribution layer 20. Figure 5B The first region and the second region of the redistribution layer 20 will be described. Figure 5B A dashed line indicating the boundary between the first region 21A and the second region 21B is added to Figure 5A Picture.

[0160] The insulating layer 21 of the first wiring layer 20A includes a first region 21A and a second region 21B. In other words, the insulating layer 21 of the first wiring layer 20A is divided into the first region 21A and the second region 21B. Figure 5B As shown, second region 21B is located in the region where multiple conductive layers 22 of first wiring layer 20A are distributed when viewed from above. First region 21A surrounds second region 21B when viewed from above. The boundary between first region 21A and second region 21B is defined by an imaginary rectangle encompassing all conductive layers 22 included in first wiring layer 20A of a single rewiring layer 20. The region surrounded by the rectangle is second region 21B. The rectangle includes a pair of sides extending in first direction D1 and a pair of sides extending in second direction D2. Each side of the rectangle circumscribes the conductive layers 22. First opening 143 of intermediate layer 14 is located in first region 21A when viewed from above.

[0161] exist Figure 5B In the figure, symbol S1 represents the dimension of the first region 21A located between two adjacent second regions 21B in the first direction D1. Dimension K1 of the first opening 143 can also be determined relative to dimension S1 of the first region 21A. K1 / S1, which is the ratio of dimension K1 to dimension S1, is, for example, 0.01 or greater, 0.03 or greater, or 0.10 or greater. K1 / S1 is, for example, 0.50 or less, 0.30 or less, or 0.20 or less.

[0162] exist Figure 5B In the figure, symbol S2 represents the dimension in the second direction D2 of the first region 21A between two second regions 21B adjacent in the second direction D2. The numerical range of K2 / S2, which is the ratio of dimension K2 to dimension S2, can be the numerical range of K1 / S1.

[0163] (Method for Manufacturing Wiring Board Assembly)

[0164] Next, a method for manufacturing the wiring board assembly 10 will be described.

[0165] First, if Figure 6 As shown, prepare the carrier substrate 12. Then, as Figure 6 As shown, a release layer 13 is formed on a carrier substrate 12. The process of forming the release layer 13 includes, for example, a coating step of applying a solution containing a resin and a solvent, and a drying step of evaporating the solvent after the coating step. Examples of the solvent include propylene glycol monomethyl ether, 2-methoxy-1-methylethyl acetate, N-methyl-2-pyrrolidone, γ-butyrolactone, ethyl lactate, and toluene. The drying step includes, for example, heating the carrier substrate 12.

[0166] Then, if Figure 7As shown in FIG. 1 , an intermediate layer 14 is formed on the first upper surface 132 of the peeling layer 13. For example, the intermediate layer 14 is formed by a sputtering process. Figure 7 As shown, a seed layer 221 is formed on the second upper surface 142 of the intermediate layer 14. For example, the seed layer 221 is formed by a sputtering process.

[0167] Then, if Figure 8 As shown, a first resist layer 71 is formed on the seed layer 221. The first resist layer 71 has an opening 711 that penetrates the first resist layer 71 in the thickness direction. The opening 711 has a shape corresponding to the plating layer 222 in a plan view.

[0168] Next, the plating process is performed. In the plating process, Figure 9 As shown in FIG. 1 , a plating layer 222 is formed in the opening 711 by electrolytic plating. Figure 10 As shown in FIG. 1 , a process of removing the first resist layer 71 is performed. Figure 10 As shown, a step of removing the seed layer 221 overlapping the first resist layer 71 is performed. In this way, the conductive layer 22 including the seed layer 221 and the plating layer 222 is formed.

[0169] Then, if Figure 11 As shown, a second resist layer 72 is formed on the second upper surface 142 of the intermediate layer 14. The second resist layer 72 has an opening 721 that penetrates the second resist layer 72 in the thickness direction.

[0170] Then, if Figure 12 As shown, the intermediate layer 14 is etched. For example, the intermediate layer 14 located at the opening 721 is removed by dry etching or wet etching. As a result, a first opening 143 is formed in the intermediate layer 14.

[0171] Next, a step of removing the second resist layer 72 is performed. Figure 13A as well as Figure 13B 1 is a cross-sectional view and a top view showing the peeling layer 13, the intermediate layer 14 and the conductive layer 22 after the second resist layer 72 is removed. Figure 13A as well as Figure 13B As shown, the first upper surface 132 of the release layer 13 is exposed at the first opening 143 of the intermediate layer 14 .

[0172] Then, if Figure 14 As shown, a step of forming insulating layer 21 is performed. Insulating layer 21 is formed to cover intermediate layer 14 and conductive layer 22. In this way, first wiring layer 20A including insulating layer 21 and conductive layer 22 is formed. A portion of insulating layer 21 may contact first upper surface 132 of peeling layer 13 at first opening 143.

[0173] The process of forming insulating layer 21 includes, for example, a coating step of applying a solution containing a resin and a solvent, and a drying step of evaporating the solvent after the coating step. Examples of the solvent include propylene glycol monomethyl ether, 2-methoxy-1-methylethyl acetate, N-methyl-2-pyrrolidone, γ-butyrolactone, ethyl lactate, and toluene. The drying step includes, for example, heating carrier substrate 12.

[0174] According to this embodiment, by forming the intermediate layer 14 on the release layer 13, it is possible to suppress the solvent from coming into contact with the release layer 13 during the step of forming the insulating layer 21. This prevents the release layer 13 from absorbing the solvent and causing it to swell. The intermediate layer 14 includes openings such as the first opening 143, but as mentioned above, the area and size of the openings are limited. Therefore, even if the solvent is absorbed into the release layer 13 through the first opening 143, the absorption can be minimized. Furthermore, as will be described later, the solvent absorbed by the release layer 13 can be discharged to the outside. Therefore, it is possible to suppress the release layer 13 from absorbing the solvent through the first opening 143 and causing adverse effects on the release process.

[0175] According to this embodiment, since first openings 143 are formed in intermediate layer 14, gas generated within release layer 13 can be easily discharged through openings 143. Therefore, it is possible to prevent intermediate layer 14 from being separated from release layer 13 due to the gas during the manufacturing process of wiring board assembly 10. This can improve the manufacturing process yield of wiring board assembly 10, for example. Gas is generated within release layer 13 during a process in which components of wiring board assembly 10 are heated. Examples of heating processes include a drying process to evaporate the solvent in insulating layer 21 and a firing process in which high-temperature heating is performed.

[0176] After forming the first wiring layer 20A, the steps of forming the second wiring layer 20B and the third wiring layer 20C may be performed. In addition, the step of forming the conductive layer 22 constituting the pads 24 and the like may be performed on the third wiring layer 20C. Figure 2 The wiring substrate set 10 is shown.

[0177] (Method for Manufacturing Wiring Board)

[0178] Next, a method for manufacturing wiring substrate 11 and a method for using wiring substrate 11 will be described.

[0179] First, prepare the wiring substrate group 10. Figure 15 As shown, a dividing step is performed to divide the wiring substrate 11. This produces a plurality of wiring substrates 11. The wiring substrate 11 includes: a carrier substrate 12; a peeling layer 13 located on the carrier substrate 12; an intermediate layer 14 located on the peeling layer 13; and a rewiring layer 20 located on the intermediate layer 14.

[0180] In the dividing step, the insulating layer 21, the peeling layer 13, and the carrier substrate 12 of the rewiring layer 20 may be cut along the boundary between two adjacent rewiring layers 20 in a plan view. Figure 15 In FIG, a two-dot chain line labeled CL1 indicates a cutting position in the dividing step. The cutting position CL1 may be located at the first opening 143 of the intermediate layer 14. In this case, the intermediate layer 14 is not cut.

[0181] Then, if Figure 16 As shown, a trimming step may be performed to remove the outer peripheral portion of the wiring substrate 11. In the trimming step, the outer peripheral portion of the wiring substrate 11 may be cut and separated from the portion of the wiring substrate 11 located inside the outer peripheral portion. The trimming step may not be performed.

[0182] exist Figure 16 In FIG. 1 , the double-dashed line with the symbol CL2 indicates the cutting position in the trimming process. The cutting position CL2 may be located outside the conductive layer 22 and overlap the peeling layer 13 and the intermediate layer 14. In this case, the insulating layer 21, the peeling layer 13 and the intermediate layer 14 of the rewiring layer 20 are cut. Figure 16 As shown, the trimming process may also be performed without dividing the carrier substrate 12 .

[0183] like Figure 17 as well as Figure 18 As shown, after the trimming process, a first bonding process of bonding the wiring substrate 11 separated from the peripheral portion to the first member 81 may be performed. The first member 81 may also include a substrate 811 and a plurality of terminals 812 located on the substrate 811. The first member 81 may also include an adhesive layer 813 covering the plurality of terminals. The adhesive layer 813 may also be provided on the wiring substrate 11. In the first bonding process, as shown in FIG. Figure 18 As shown, the conductive layer 22 , which is located on the third upper surface 202 of the redistribution layer 20 and constitutes the pad 24 , may be electrically connected to the terminal 812 of the first member 81 .

[0184] Then, if Figure 18 as well as Figure 19 As shown in FIG. 1 , a stripping process may be performed to strip the redistribution layer 20 from the carrier substrate 12. Figure 18 As shown, the peeling step may also include an irradiation step of irradiating the peeling layer 13 with light L. In the irradiation step, the light L may reach the peeling layer 13 after passing through the carrier substrate 12. The peeling layer 13 may also be decomposed by the heat generated by the irradiation of the light L. The adhesion between the carrier substrate 12 and the intermediate layer 14 is reduced by the decomposition. Therefore, as shown in FIG. Figure 19As shown, the carrier substrate 12 is separated from the intermediate layer 14 and the redistribution layer 20. Then, if there is residue of the peeling layer 13 on the intermediate layer 14, a process of removing the residue may be performed.

[0185] Then, if Figure 20 As shown, a process of removing intermediate layer 14 may also be performed. For example, intermediate layer 14 may be removed by etching. Removal of intermediate layer 14 reveals third lower surface 201 of rewiring layer 20. In this case, first wiring layer 20A constituting third lower surface 201 may also include a plurality of conductive layers 22 constituting pads 24.

[0186] Then, if Figure 21 As shown, a second bonding step may be performed to bond the conductive layer 22 of the first wiring layer 20A of the wiring substrate 11 to the second member 82. The second member 82 may also include a substrate 821 and a plurality of terminals 822 located on the substrate 821. An adhesive layer 823 may also be provided between the substrate 821 of the second member 82 and the first wiring layer 20A of the wiring substrate 11.

[0187] The second component 82 may also be a semiconductor element. Semiconductor elements include transistors formed from semiconductors such as silicon. Examples of semiconductor elements include CPUs, GPUs, FPGAs, sensors, and memory. Alternatively, the semiconductor element may be a chip in which semiconductor elements such as CPUs, GPUs, FPGAs, sensors, and memory are separated by function.

[0188] According to this embodiment, the intermediate layer 14 can suppress the light L from reaching the rewiring layer 20 during the peeling process. This can suppress, for example, the state of the insulating layer 21 of the rewiring layer 20 from changing due to light irradiation.

[0189] According to this embodiment, the intermediate layer 14 can suppress the state change of the peeling layer 13 caused by light irradiation or the like during the peeling process from propagating to the rewiring layer 20. This can suppress the state change of the insulating layer 21 of the rewiring layer 20, for example.

[0190] According to this embodiment, the insulating layer 21 of the rewiring layer 20 can be prevented from adhering closely to the release layer 13 by the intermediate layer 14. This facilitates the release of the rewiring layer 20 from the release layer 13 during the release step.

[0191] Various modifications can be made to the above-described embodiment. Below, modifications will be described with reference to the accompanying drawings as needed. In the following description and the accompanying drawings used in the following description, for parts that can be constructed in the same manner as the above-described embodiment, the same symbols as those used for the corresponding parts in the above-described embodiment are used. Repeated descriptions are omitted. In addition, if the effects obtained in the above-described embodiment can also be obtained in the modification, the description thereof may be omitted.

[0192] (First Modification)

[0193] In the above embodiment, an example is shown in which the first member 81 includes the terminal 812 connected to the conductive layer 22 of the rewiring layer 20, but the structure of the first member 81 is arbitrary. Figure 22 As shown, the first member 81 may also not include the terminal 812. In this case, as shown in FIG. Figure 23 As shown, the first member 81 may be peeled off from the rewiring layer 20 after the third lower surface 201 of the rewiring layer 20 is bonded to the second member 82 .

[0194] Although not shown, a third member may be bonded to the third upper surface 202 of the redistribution layer 20 after the first member 81 is peeled off. The third member may be a wiring substrate including a substrate and terminals. The third member may also be a semiconductor device. The semiconductor device may also include terminals electrically connected to the conductive layer 22 located on the third upper surface 202 of the redistribution layer 20.

[0195] (Second Modification)

[0196] In the above embodiment, the first opening 143 is formed in the intermediate layer 14 after the conductive layer 22 of the first wiring layer 20A is formed. In this modification, the first opening 143 is formed in the intermediate layer 14 before the conductive layer 22 of the first wiring layer 20A is formed.

[0197] First, with Figure 6 as well as Figure 7 Similarly to the above embodiment shown in FIG. 1 , a peeling layer 13 and an intermediate layer 14 are formed on the carrier substrate 12. Figure 24 As shown, first opening 143 is formed in intermediate layer 14. For example, first, the aforementioned second resist layer 72 is formed on second upper surface 142 of intermediate layer 14. Next, an etching step is performed on intermediate layer 14. For example, intermediate layer 14 located at opening 721 is removed by dry etching. Thus, first opening 143 is formed in intermediate layer 14.

[0198] Then, if Figure 25As shown, a process of forming a seed layer 221 on the second upper surface 142 of the intermediate layer 14 is performed. The seed layer 221 may also be formed in the first opening 143 .

[0199] Then, if Figure 26 As shown in FIG. 2 , a first resist layer 71 is formed on the seed layer 221. Figure 26 As shown, the plated layer 222 is formed in the opening 711 by electrolytic plating. Next, the first resist layer 71 is removed. Next, the seed layer 221 overlapping the first resist layer 71 is removed. In this way, the conductive layer 22 including the seed layer 221 and the plated layer 222 is formed.

[0200] (Third Modification)

[0201] In the above embodiment, an example is shown in which the opening of the intermediate layer 14 is located at the boundary between the first wiring layers 20A of two adjacent redistribution layers 20 in a plan view. In this modified example, an example is described in which the opening of the intermediate layer 14 is located in the region where the conductive layer 22 of the first wiring layer 20A of the redistribution layer 20 is distributed. The opening of the intermediate layer 14 located in the second region 21B is also referred to as a second opening and is indicated by reference numeral 144.

[0202] Figure 27 1 is a cross-sectional view showing a wiring board assembly 10 according to this modification. Figure 28 This is a plan view showing the positional relationship between release layer 13, intermediate layer 14, and first wiring layer 20A of wiring board assembly 10 of this modification. Wiring board assembly 10 includes a plurality of second openings 144 that overlap second regions 21B of insulating layer 21 of first wiring layer 20A in a plan view.

[0203] like Figure 28 As shown, the first wiring layer 20A may include a plurality of conductive layers 22 regularly arranged in the plane direction and constituting the pads 24. At least a portion of the plurality of second openings 144 may be located between two adjacent pads 24 in a plan view.

[0204] The plurality of second openings 144 may also be regularly arranged in the plane direction similarly to the plurality of conductive layers 22 constituting the pad 24. For example, the plurality of second openings 144 may also be regularly arranged along the first opening arrangement direction and the second opening arrangement direction orthogonal to the first opening arrangement direction. Figure 29 In the example shown, the first and second opening arrangement directions coincide with the first and second directions D1 and D2. At least a portion of the plurality of conductive layers 22 constituting the pad 24 may be located between two adjacent second openings 144 in a plan view.

[0205] exist Figure 29In the figure, symbol P3 represents the arrangement pitch of the second openings 144 in the first direction of the opening arrangement, and symbol P4 represents the arrangement pitch of the second openings 144 in the second direction of the opening arrangement. The arrangement pitches P3 and P4 are, for example, 500 μm or less, 300 μm or less, 100 μm or less, or 50 μm or less.

[0206] Figure 29 This is an enlarged top view showing the peeling layer 13, intermediate layer 14, and conductive layer 22 overlapping the second region 21B. The second region 21B may also include a twenty-first region 21B1. The twenty-first region 21B1 is located in the region where the plurality of conductive layers 22 constituting the pads 24 of the first wiring layer 20A are regularly arranged. The outline of the twenty-first region 21B1 is defined by an imaginary rectangle surrounding the plurality of regularly arranged pads 24. The area enclosed by the rectangle is the second region 21B. Each side of the rectangle circumscribes the conductive layer 22 constituting the pads 24. At least a portion of the plurality of second openings 144 may also be located in the twenty-first region 21B1 when viewed from above.

[0207] exist Figure 29 In the figure, symbol K3 represents the size of the second opening 144 in the surface direction. The size K3 is determined along the direction in which the size of the second opening 144 is the largest. The size K3 of the second opening 144 is, for example, not less than 0.1 μm, or not less than 0.2 μm. Thus, the gas generated inside the peeling layer 13 is properly discharged through the second opening 144. The size K3 of the second opening 144 is, for example, not more than 50 μm, not more than 30 μm, not more than 10 μm, not more than 3 μm, or not more than 1 μm. Thus, the first to fourth functions of the intermediate layer 14 can be suppressed from being degraded.

[0208] The dimension K3 of the second opening 144 can also be determined relative to the arrangement pitches P3 and P4 of the second opening 144. K3 / P3, which is the ratio of dimension K3 to arrangement pitch P3, is, for example, 0.0010 or greater, 0.0030 or greater, or 0.010 or greater. K3 / P3 is, for example, 0.10 or less, 0.050 or less, or 0.020 or less. A numerical range of K3 / P3, which is the ratio of dimension K3 to arrangement pitch P4, can be employed.

[0209] The total area AR2 of the plurality of second openings 144 can also be determined relative to the area AR1 of the twenty-first region 21B1. The total area AR2 is the sum of the areas of the plurality of second openings 144 overlapping the twenty-first region 21B1. AR2 / AR1, which is the ratio of the total area AR2 of the second openings 144 to the area AR1 of the twenty-first region 21B1, is, for example, 0.0010 or greater, 0.0030 or greater, or 0.010 or greater. AR2 / AR1 is, for example, 0.10 or less, 0.050 or less, or 0.020 or less. AR2 / AR1 is also referred to as the aperture ratio of the second openings 144.

[0210] The number N2 of the second openings 144 overlapping the twenty-first region 21B1 may also be determined relative to the number N1 of the conductive layers 22 overlapping the twenty-first region 21B1. N2 / N1, which is the ratio of the number N2 of the second openings 144 to the number N1 of the conductive layers 22, may be, for example, 0.5 or greater, 0.7 or greater, or 1.0 or greater. N2 / N1 may be, for example, 5.0 or less, 4.0 or less, or 3.0 or less.

[0211] (Fourth Modification)

[0212] Figure 30 14 is a top view of wiring board assembly 10 according to this modification. The openings of intermediate layer 14 may include first opening 143 and a plurality of second openings 144. This more reliably prevents intermediate layer 14 from being peeled off from peeling layer 13 due to gas generated within peeling layer 13.

[0213] (Fifth Modification)

[0214] In the above-described embodiment and modified examples, examples are shown in which the opening of the intermediate layer 14 is located outside the outline of the conductive layer 22 of the first wiring layer 20A in plan view. In this modified example, an example is described in which the opening of the intermediate layer 14 is located inside the outline of the conductive layer 22 of the first wiring layer 20A in plan view.

[0215] Figure 31 1 is a plan view showing wiring board assembly 10 according to this modification. Figure 32 yes Figure 31 FIG2 is a cross-sectional view of wiring substrate assembly 10 along line XXXII-XXXII. The opening in intermediate layer 14 may include a second opening 144 located inside the outline of conductive layer 22 of first wiring layer 20A when viewed from above. In other words, the opening in intermediate layer 14 may include a second opening 144 surrounded by conductive layer 22 of first wiring layer 20A when viewed from above.

[0216] The opening of the intermediate layer 14 may further include a second opening 144 located outside the outline of the conductive layer 22 of the first wiring layer 20A in a plan view. The opening of the intermediate layer 14 may further include a first opening 143 .

[0217] like Figure 31 as well as Figure 32 As shown, the conductive layer 22 of the first wiring layer 20A may also include an opening 224 that overlaps with the second opening 144 in a plan view. The opening 224 penetrates the conductive layer 22. Therefore, the gas generated inside the separation layer 13 is discharged to the outside of the wiring board assembly 10 through the second opening 144 of the intermediate layer 14, the opening 224 of the conductive layer 22, and the insulating layer 21.

[0218] (Sixth Modification)

[0219] In the above embodiment, an example in which the conductive layer 22 includes the seed layer 221 is described. In this modification, an example in which the conductive layer 22 does not include the seed layer 221 will be described.

[0220] Figure 33 2 is a cross-sectional view showing the process of forming the plating layer 222. In this modification, the first resist layer 71 is formed on the second upper surface 142 of the intermediate layer 14. Figure 33 As shown in FIG. 1 , a plating layer 222 is formed in the opening 711 by electrolytic plating. Figure 34 As shown, a step of removing the first resist layer 71 is performed. Thus, the conductive layer 22 composed of the plating layer 222 is formed on the second upper surface 142 of the intermediate layer 14.

[0221] exist Figure 33 as well as Figure 34 , an example is shown in which the first opening 143 is formed in the intermediate layer 14 before forming the plating layer 222. Although not shown, the first opening 143 may be formed in the intermediate layer 14 after the plating layer 222 is formed on the second upper surface 142 of the intermediate layer 14.

[0222] When the first openings 143 are formed in the intermediate layer 14 before forming the plating layer 222 , the first openings 143 are preferably arranged so as to sufficiently ensure a path for current supplied to the plating layer 222 . Figure 35 This is a plan view showing an example of the positional relationship between the conductive layer 22 formed of the plating layer 222 and the second opening 144 of the intermediate layer 14 .

[0223] It is considered that the current supplied to the plating layer 222 is Figure 35 The total θ0 of the supply angles θ1 to θ4 shown has a correlation. The supply angle is determined based on the positional relationship between one conductive layer 22 and a plurality of second openings 144 close to the conductive layer 22 in a plan view. Figure 35In the example, four second openings 144 are located adjacent to one conductive layer 22. The distances between the four second openings 144 and the conductive layer 22 are equal. The feed angle is defined as the angle formed by two imaginary straight lines L1 and L2 that pass through the center of the conductive layer 22 and touch two adjacent openings 144, respectively. For example, feed angle θ1 is the angle formed by straight line L1 that passes through the center of the conductive layer 22 and touches the first second opening 144, and straight line L2 that passes through the center of the conductive layer 22 and touches the second second opening 144 adjacent to the first second opening 144. Figure 35 The supply angles θ2 to θ4 shown are determined in the same manner.

[0224] The total supply angle θ0 is, for example, 60° or more, 90° or more, or 120° or more. This ensures a sufficient path for the current supplied to the plating layer 222. The total supply angle θ0 is, for example, 300° or less, 240° or less, or 180° or less.

[0225] Figure 36 1 is a top view showing an example of the positional relationship between the conductive layer 22 formed of the plating layer 222 and the first opening 143 of the intermediate layer 14. Figure 35 As shown, when the conductive layer 22 has a circular shape in a plan view, the second opening 144 of the intermediate layer 14 may also have a shape extending in the circumferential direction of the conductive layer 22. Figure 36 In the example shown, the path of the current supplied to the plating layer 222 can be sufficiently ensured by setting the total supply angle θ0 within the above-mentioned numerical range.

[0226] (Seventh Modification)

[0227] Figure 37 This is a cross-sectional view showing an example of the second opening 144 of the intermediate layer 14 in this modified example. Reference symbol K31 indicates the dimensions of the second opening 144 on the second lower surface 141. Reference symbol K32 indicates the dimensions of the second opening 144 on the second upper surface 142. Dimension K32 may be smaller than dimension K31. This prevents light that passes through the release layer 13 and enters the second opening 144 from reaching the second upper surface 142.

[0228] The second opening 144 may also be configured such that the size of the second opening 144 decreases in the thickness direction toward the second upper surface 142. This shape of the second opening 144 can be achieved by forming the second opening 144 in the intermediate layer 14 by dry etching, for example.

[0229] K32 / K31, which is the ratio of dimension K32 to dimension K31, is, for example, 0.90 or less, 0.80 or less, or 0.70 or less. K32 / K31 is, for example, 0.30 or more, 0.40 or more, or 0.50 or more.

[0230] Figure 38 This figure shows an example of a product equipped with a wiring substrate 11 or a redistribution layer 20. Wiring substrate 11 or redistribution layer 20 can be used in various products. For example, they can be equipped in a notebook personal computer 110, a tablet terminal 120, a mobile phone 130, a smartphone 140, a digital video camera 150, a digital camera 160, a digital clock 170, a server 180, and the like.

[0231] Several modified examples of the above-mentioned embodiment have been described. It is, of course, possible to appropriately combine a plurality of modified examples and apply them to the above-mentioned embodiment.

[0232] Example

[0233] Next, the first embodiment of the present disclosure will be described in more detail with reference to examples. However, the embodiments of the present disclosure are not limited to the description of the following examples unless departing from the gist of the present disclosure.

[0234] (Example 1)

[0235] Produced Figure 30 The wiring substrate assembly 10 shown includes an intermediate layer 14 having a first opening 143 and a plurality of second openings 144. The release layer 13 is made of a material capable of separating the carrier substrate 12 from the intermediate layer 14 and the redistribution layer 20 by irradiating the release layer 13 with light. Polyimide is used as the material for the insulating layer 21. The formation process of the insulating layer 21 includes heating the insulating layer 21 at 200°C. Titanium is used as the material for the intermediate layer 14. Copper is used as the material for the conductive layer 22.

[0236] The second openings 144 are circular with a diameter of 30 μm when viewed from above. The plurality of second openings 144 are arranged along the first and second opening arrangement directions with an arrangement pitch of 130 μm. The aperture ratio of the second openings 144 is 0.042. The width of the first opening 143 is 200 μm.

[0237] In Example 1, it was confirmed that after the redistribution layer 20 was formed, no bubbles or separation occurred at the interface between the separation layer 13 and the intermediate layer 14 .

[0238] Afterwards, if Figure 18 as well as Figure 19 As shown, after the peeling layer 13 is irradiated with ultraviolet rays, the redistribution layer 20 can be peeled off from the carrier substrate 12 .

[0239] (Comparative Example 1)

[0240] Wiring board assembly 10 was manufactured in the same manner as in Example 1, except that first opening 143 and multiple second openings 144 were not formed in intermediate layer 14. In Comparative Example 1, it was confirmed that, after forming redistribution layer 20, bubbles were generated at the interface between peeling layer 13 and intermediate layer 14, causing peeling.

[0241] (Second embodiment)

[0242] The second embodiment is based on and claims priority from Japanese Patent Application No. 2023-6077 filed on January 18, 2023. The second embodiment relates to a method for manufacturing a redistribution layer and a wiring substrate assembly. The names of the components in the specification of Japanese Patent Application No. 2023-6077 are converted in this application to those shown in Table 1 below.

[0243] [Table 1]

[0244] Name in JP No. 2023-006077 Names in this application Interposer Intermediate Wiring substrate assembly Monolithic Interposer Intermediate Wiring substrate Intermediate interposer layer Rewiring layer group interposer Rewiring layer first resin wiring layer First wiring layer Second resin wiring layer Second wiring layer third resin wiring layer The third wiring layer Resin layer insulation layer light-shielding layer Middle layer BGA First component Substrate body substrate Adhesive materials Adhesive layer

[0245] As described above, the redistribution layer is cut out from the wiring substrate assembly along with a portion of the carrier substrate. This cutting is also called singulation. The redistribution layer is separated from the small pieces of the carrier substrate when being assembled into a semiconductor package, for example.

[0246] When it is intended to perform an operation of peeling the rewiring layer from the carrier substrate pieces, the carrier substrate prior to singulation is typically provided with a peeling layer, on which multiple rewiring layers are collectively formed. The peeling layer may also comprise, for example, polyimide. When the peeling layer comprises polyimide, the rewiring layer can be peeled from the carrier substrate pieces, for example, by irradiating the peeling layer with light through the carrier substrate pieces.

[0247] When a release layer is provided on a carrier substrate, desired adhesion strength may not be ensured at the interface between the carrier substrate and the release layer.

[0248] For example, if the carrier substrate has a smooth surface, is made of an inorganic material, and the release layer is made of an organic material, it can sometimes be difficult to maintain the desired adhesion strength. However, if the adhesion strength between the carrier substrate and the release layer is insufficient, the risk of the release layer peeling from the carrier substrate increases. The release layer is particularly susceptible to peeling from the carrier substrate when, for example, the rewiring layer is cut out.

[0249] An object of the second embodiment of the present disclosure is to provide a method for manufacturing a redistribution layer and a wiring board assembly that can effectively solve such a problem.

[0250] The second embodiment of the present disclosure relates to the following [1] to

[18] .

[0251] [1] A method for manufacturing a redistribution layer, comprising:

[0252] a bonding layer forming step of providing a bonding layer on the first surface of the carrier substrate including a first surface and a second surface located opposite to the first surface;

[0253] a peeling layer forming step of providing a peeling layer containing a resin on a surface of the adhesive layer opposite to a surface in contact with the first surface;

[0254] a rewiring layer forming step of releasably providing one or more rewiring layers including wirings and an insulating layer containing resin covering the wirings on a surface of the release layer opposite to the surface in contact with the adhesion layer; and

[0255] In the peeling treatment step, the rewiring layer can be peeled off from the carrier substrate and the adhesive layer by irradiating the peeling layer with a laser beam that has passed through the first surface from the second surface via the adhesive layer.

[0256] [2] The method for manufacturing a redistribution layer according to [1], wherein:

[0257] The method further comprises a singulation step of cutting out the redistribution layer together with a portion of the carrier substrate from the carrier substrate and one or more redistribution layers provided on the carrier substrate.

[0258] In the stripping process, the laser is irradiated onto the stripping layer between the rewiring layer cut out in the singulation process and a portion of the carrier substrate, thereby stripping the rewiring layer from a portion of the carrier substrate and the adhesion layer provided on a portion of the carrier substrate.

[0259] [3] The method for manufacturing a redistribution layer according to [2], wherein:

[0260] The method further comprises a trimming step of separating, in the rewiring layer and a portion of the carrier substrate cut out in the singulation step, an outer peripheral portion of the rewiring layer from a portion inside the outer peripheral portion by using a cut that penetrates the rewiring layer in a direction in which the rewiring layer and a portion of the carrier substrate overlap and reaches a middle position of the carrier substrate.

[0261] In the stripping process, the laser is irradiated on the stripping layer between at least the inner portion of the rewiring layer after the trimming process and a portion of the carrier substrate, so that the rewiring layer can be stripped from a portion of the carrier substrate and the adhesion layer arranged on a portion of the carrier substrate.

[0262] [4] The method for manufacturing a redistribution layer according to any one of [1] to [3], wherein the adhesion layer is formed by a CVD method.

[0263] [5] The method for manufacturing a redistribution layer according to any one of [1] to [4], wherein the carrier substrate and the adhesion layer are made of the same material.

[0264] [6] The method for manufacturing a redistribution layer according to any one of [1] to [5], wherein the refractive index of the carrier substrate and the refractive index of the adhesion layer are different from each other.

[0265] [7] The method for producing a redistribution layer according to any one of [1] to [6], wherein the adhesion layer contains silicon dioxide.

[0266] [8] The method for manufacturing a redistribution layer according to any one of [1] to [7], wherein the adhesion layer is composed only of a layer containing silicon dioxide as a main component.

[0267] [9] The method for manufacturing a redistribution layer according to any one of [1] to [7], wherein:

[0268] The adhesive layer includes a first portion bonded to the first surface and a second portion overlapping the first portion.

[0269] The first portion contains silicon nitride as a main component, and the second portion contains silicon dioxide as a main component.

[0270]

[10] The method for manufacturing a redistribution layer according to any one of [1] to [9], wherein the carrier substrate contains silicon dioxide.

[0271]

[11] The method for manufacturing a redistribution layer according to any one of [1] to

[10] , wherein the adhesion layer is configured so that the transmittance of the laser beam is 90% or higher.

[0272]

[12] The method for manufacturing a redistribution layer according to

[11] , wherein the wavelength of the laser light is 355 nm.

[0273]

[13] The method for manufacturing a redistribution layer according to any one of [1] to

[12] , wherein an arithmetic mean height of the adhesion layer is 0.01 μm or more and 0.1 μm or less.

[0274]

[14] The method for manufacturing a rewiring layer according to any one of [1] to

[13] , wherein the release layer contains polyimide.

[0275]

[15] The method for manufacturing a redistribution layer according to any one of [1] to

[14] , further comprising an intermediate layer forming step, wherein an intermediate layer for limiting the transmission of the laser light is provided between the peeling layer and the redistribution layer.

[0276]

[16] The method for manufacturing a redistribution layer according to

[15] , wherein the intermediate layer contains at least one of titanium, gold, silver, nickel, and copper.

[0277]

[17] The method for manufacturing a redistribution layer according to

[15] or

[16] , wherein the intermediate layer is configured so that the reflectivity of the laser light is 90% or higher.

[0278]

[18] A wiring substrate assembly comprising:

[0279] a carrier substrate comprising a first surface and a second surface located opposite to the first surface;

[0280] a bonding layer, disposed on the first surface;

[0281] a release layer provided on a surface of the adhesive layer opposite to the surface in contact with the first surface and containing a resin; and

[0282] One or more rewiring layers are provided in a releasable manner on a surface of the release layer opposite to a surface in contact with the adhesion layer, and include wirings and an insulating layer containing resin and covering the wirings.

[0283] According to the second embodiment of the present disclosure, it is possible to suppress the peeling of the peeling layer.

[0284] Figure 39 This is a schematic cross-sectional view of an example of the wiring substrate assembly 10 for manufacturing the redistribution layer 20 . Figure 40 This is a top view of the wiring substrate assembly 10. The wiring substrate assembly 10 has a first direction D1, a second direction D2, and a third direction D3. The first direction D1 and the second direction D2 are included in the plane direction of the wiring substrate assembly 10. The first direction D1 and the second direction D2 are perpendicular to each other. The third direction D3 is the thickness direction of the wiring substrate assembly 10. The third direction D3 is perpendicular to the first direction D1 and the second direction D2.

[0285] The wiring substrate group 10 includes a carrier substrate 12 and one or more redistribution layers 20 that are releasably provided on the carrier substrate 12. In the present embodiment, a plurality of redistribution layers 20 are formed collectively on the carrier substrate 12. In the illustrated example, the plurality of redistribution layers 20 are connected to each other in the first direction D1 or the second direction D2. Hereinafter, the structural element including the plurality of redistribution layers 20 connected to each other will be referred to as the redistribution layer group 30. That is, the redistribution layer group 30 corresponds to the portion including the plurality of redistribution layers 20. The redistribution layer 20 is, for example, a component that is cut out from the redistribution layer group 30 and assembled to a semiconductor package when manufacturing a semiconductor package. The following describes the various structural elements of the wiring substrate group 10.

[0286] (Carrier substrate)

[0287] The carrier substrate 12 is a plate, comprising a first surface 121 and a second surface 122 located on the opposite side of the first surface 121. Figure 40 As shown, the carrier substrate 12 has a rectangular shape when viewed from above. The carrier substrate 12 may also have other shapes such as a circle when viewed from above.

[0288] In this embodiment, the carrier substrate 12 is a quartz substrate primarily composed of silicon dioxide (SiO2). Examples of the carrier substrate 12 include a glass substrate, a sapphire substrate, a silicon substrate, a silicon carbide substrate, an aluminum oxide (Al2O3) substrate, an aluminum nitride (AlN) substrate, a zirconium oxide (ZrO2) substrate, a lithium niobate substrate, or a tantalum niobate substrate. The carrier substrate 12 may include two or more of the following: a quartz substrate, a glass substrate, a sapphire substrate, a silicon substrate, a silicon carbide substrate, an aluminum oxide (Al2O3) substrate, an aluminum nitride (AlN) substrate, a zirconium oxide (ZrO2) substrate, a lithium niobate substrate, a tantalum niobate substrate, and a resin substrate. The resin substrate may be made of an organic material. For example, the resin substrate may be made of epoxy resin, polyethylene, or polypropylene.

[0289] The thickness of the carrier substrate 12 is, for example, 100 μm or more, 200 μm or more, or 500 μm or more. The thickness of the carrier substrate 12 is, for example, 2 mm or less, 1.5 mm or less, or 1 mm or less. The area of ​​the carrier substrate 12 is, for example, 0.5 m 2 Above, can be 1.0m 2 Above, can also be 2.0m 2 Above, can also be 3.0m 2 above.

[0290] The rewiring layer group 30 (a plurality of rewiring layers 20) is provided on the carrier substrate 12 via the adhesive layer 15 and the peeling layer 13. The adhesive layer 15 and the peeling layer 13 are sequentially provided on the first surface 121 of the carrier substrate 12. The adhesive layer 15 has a surface property different from that of the first surface 121. The surface property refers to at least one of the properties such as surface roughness, surface composition, and surface wettability. Specifically, in this embodiment, the surface of the adhesive layer 15 is at least rougher than the first surface 121 of the carrier substrate 12. Specifically, the arithmetic mean height of the adhesive layer 15 is greater than the arithmetic mean height of the first surface 121. The arithmetic mean height of the adhesive layer 15 is, for example, greater than 0.01 μm and less than 0.1 μm. The arithmetic mean height is a value calculated in accordance with JISB 0601:2013.

[0291] Adhesion layer 15 contains silicon dioxide (SiO2) as its main component. Specifically, adhesion layer 15 consists solely of a layer primarily composed of silicon dioxide. Adhesion layer 15 is provided to enhance the adhesion strength between release layer 13 and carrier substrate 12. In this embodiment, adhesion layer 15 consists solely of a layer primarily composed of silicon dioxide, and carrier substrate 12 and adhesion layer 15 are made of the same material.

[0292] The material and / or composition of the adhesive layer 15 are not particularly limited as long as the desired degree of adhesive strength between the release layer 13 and the carrier substrate 12 can be ensured. For example, the adhesive layer 15 may include a first portion bonded to the first surface 121 of the carrier substrate 12 and a second portion overlapping the first portion. The first portion may contain silicon nitride as a main component, and the second portion may contain silicon dioxide as a main component.

[0293] In this embodiment, the adhesive layer 15 is formed using CVD (Chemical Vapor Deposition). Consequently, in this embodiment, the arithmetic mean height of the adhesive layer 15 is greater than the arithmetic mean height of the first surface 121 of the carrier substrate 12. Specifically, the use of CVD results in a rougher surface for the adhesive layer 15 than the first surface 121 of the carrier substrate 12, which has been polished for smoothing. Specifically, in this embodiment, the adhesive layer 15 is formed using plasma CVD, but it can also be formed using thermal CVD. Alternatively, the adhesive layer 15 can be formed using vapor deposition or sputtering.

[0294] In this embodiment, the carrier substrate 12 is cut out from a fused silica substrate or a synthetic quartz substrate. The carrier substrate 12 contains high-purity silicon dioxide. In this embodiment, the carrier substrate 12 and the adhesive layer 15 contain the same material, but the refractive index of the carrier substrate 12 and the refractive index of the adhesive layer 15 are different from each other. The refractive index of the carrier substrate 12 and the refractive index of the adhesive layer 15 are values ​​measured using a spectroscopic ellipsometer (manufactured by Japan Semi-finished Products Co., Ltd., "SE-1000"). That is, when the carrier substrate 12 is composed of a fused silica substrate or a synthetic quartz substrate, and the adhesive layer 15 is composed of a process different from the manufacturing method of the carrier substrate 12, in particular, a film-forming process, the optical properties of the two are different. If the surface properties of the adhesive layer 15 are different from those of the carrier substrate 12, the refractive index of the carrier substrate 12 and the refractive index of the adhesive layer 15 can be the same value. Furthermore, when the carrier substrate 12 is made of a fused silica substrate or a synthetic quartz substrate, and the adhesive layer 15 is formed by CVD-based silicon dioxide film formation, as described above, the compositions of the carrier substrate 12 and the adhesive layer 15 may differ in addition to, or in lieu of, the differences in surface roughness and refractive index. Thus, the composition of the adhesive layer 15 may differ from that of the carrier substrate 12. In the case of different compositions, the adhesive strength of the adhesive layer 13 may differ depending on whether the adhesive layer 13 is provided directly on the carrier substrate 12 or when the adhesive layer 15 is provided on the carrier substrate 12 via the adhesive layer 15.

[0295] Adhesion layer 15 is preferably configured to have a transmittance of 90% or greater for laser light of a given wavelength. In wiring board assembly 10, laser irradiation of release layer 13 allows rewiring layer 20 to be removed from carrier substrate 12. Rewiring layer 20 is part of rewiring layer assembly 30. During the removal process, laser light enters second surface B of carrier substrate 12, travels from first surface 121 through adhesion layer 15, and reaches release layer 13. Therefore, adhesion layer 15 must be transmissive to the laser light.

[0296] As described above, the adhesion layer 15 is preferably configured to have a transmittance of 90% or greater for laser light of a given wavelength. The laser light can penetrate the carrier substrate 12 and the adhesion layer 15 and reach the release layer 13. By irradiating the release layer 13 with the laser light, the rewiring layer 20 in the rewiring layer group 30 can be easily removed while suppressing surface disturbances in the release layer 13.

[0297] In this embodiment, a laser with a wavelength of 355 nm is used as the laser beam irradiating the release layer 13. That is, the adhesive layer 15 is preferably configured so that its transmittance to laser light with a wavelength of 355 nm is 90% or greater. The laser beam used to release the release layer 13 is not particularly limited; laser beams with wavelengths other than 355 nm may be used. The transmittance of the laser beam through the adhesive layer 15 is measured using a spectrophotometer ("SM 245 High-Speed ​​CCD Spectrophotometer," manufactured by Japan Semi-finished Products Co., Ltd.). The laser wavelength is measured using a photodiode sensor ("FPS-1," manufactured by Opto Science).

[0298] The thickness of the adhesive layer 15 can be, for example, from 25 nm to 300 nm. In this case, the light transmittance of the adhesive layer 15 can be easily adjusted to the desired state. The adhesive layer 15 is preferably formed from a material with good light transmittance and heat resistance. From this perspective, the adhesive layer 15 is an inorganic material, preferably containing silicon dioxide or silicon nitride as described above. Alternatively, ITO (indium tin oxide) can be used as the material for the adhesive layer 15.

[0299] The release layer 13 is provided on the surface of the adhesive layer 15 opposite to the surface in contact with the first surface 121 of the carrier substrate 12. Specifically, the adhesive layer 15 includes a lower surface 151 in contact with the first surface 121 of the carrier substrate 12 and an upper surface 152 opposite to the lower surface 151. The release layer 13 is provided on the upper surface 152.

[0300] The peeling layer 13 is a structural element that enables the redistribution layer 20 to be peeled off from the carrier substrate 12. In other words, it is a structural element for facilitating peeling. The peeling layer 13 contains a resin that absorbs laser light. The peeling layer 13 is decomposed by the laser light. That is, the peeling layer 13 decomposes due to the energy imparted by the laser light, thereby achieving a state in which the redistribution layer 20 can be peeled off from the carrier substrate 12. The peeling layer 13 preferably has a decomposition temperature of 300°C or higher. In this embodiment, the peeling layer 13 contains polyimide. The polyimide forming the peeling layer 13 can be either a thermosetting polyimide or a photocuring polyimide.

[0301] The thickness of the release layer 13 is, for example, 0.3 μm or more, or 1 μm or more. The thickness of the release layer 13 is, for example, 30 μm or less, or 50 μm or less.

[0302] Furthermore, in the illustrated wiring board assembly 10, an intermediate layer 14 is provided on the surface of the release layer 13 opposite the surface in contact with the adhesive layer 15 to limit the transmission of laser light, in other words, to reflect the laser light. Specifically, the release layer 13 includes a first lower surface 131 in contact with the upper surface 152 of the adhesive layer 15, and a first upper surface 132 opposite to the first lower surface 131. The intermediate layer 14 is provided on the first upper surface 132.

[0303] As described above, in the wiring substrate assembly 10, the rewiring layer 20 is peeled off from the carrier substrate 12 by irradiating the peeling layer 13 with a laser through the carrier substrate 12. At this time, if the laser reaches the rewiring layer 20, the rewiring layer 20 may be deformed undesirably. The intermediate layer 14 can shield the laser. The intermediate layer 14 is provided at a location in the rewiring layer assembly 30 where the rewiring layer 20 is formed. Alternatively, the intermediate layer 14 may not be provided at a location in the rewiring layer assembly 30 where the rewiring layer 20 is not formed. In other words, the intermediate layer 14 is provided between the peeling layer 13 and the rewiring layer 20.

[0304] In the illustrated example, the intermediate layer 14 is partially provided on the first upper surface 132. Specifically, the intermediate layer 14 is patterned to have a plurality of island portions 14A formed corresponding to the locations where the rewiring layers 20 are formed in the rewiring layer group 30. Each of the island portions 14A is located between a rewiring layer 20 and the peeling layer 13 in the third direction D3. Gaps are provided between adjacent island portions 14A. The size of the gap between adjacent island portions 14A can be, for example, not less than 1.15 mm and not more than 3.15 mm.

[0305] The intermediate layer 14 may contain a metal. The intermediate layer 14 may also contain at least one of titanium, gold, silver, nickel, and copper. For example, the intermediate layer 14 may be formed by attaching a foil containing at least one of titanium, gold, silver, nickel, and copper to the release layer 13 and then patterning the foil by etching. The intermediate layer 14 is preferably configured to have a laser reflectivity of 90% or greater. That is, the intermediate layer 14 in this embodiment is preferably configured to have a laser reflectivity of 90% or greater with a wavelength of 355 nm. The laser reflectivity of the intermediate layer 14 is measured using a spectrophotometer ("SM 245 High-Speed ​​CCD Spectrophotometer" manufactured by Japan Semi-finished Products Co., Ltd.). The intermediate layer 14 may also include pores. The pores in the intermediate layer 14 release gas from the release layer 13. For example, gas generated in the release layer 13 passes through the pores in the intermediate layer 14 and reaches the redistribution layer 20, where it is discharged to the outside through the redistribution layer 20. The intermediate layer 14 is preferably positioned inward of the cut or trimmed surface. In this way, when the intermediate layer 14 is provided at a position inside the cut surface or the trimmed surface, it is possible to prevent the intermediate layer 14 from being easily peeled off due to cutting or trimming. Figure 48 The trimmed surface is formed by cutting out the redistribution layer 20 in the singulation process described later. Figure 49 The surface generated by trimming the rewiring layer 20 in the trimming process described later. In this embodiment, the end of the intermediate layer 14 is as described later. Figure 48As shown in FIG. 1 , the intermediate layer 14 is located at a position further inward than the cut surface produced by the singulation process. In other words, the intermediate layer 14 is provided at a position that is not cut in the singulation process. The end portion of the intermediate layer 14 is as used in the following description. Figure 49 As shown, the intermediate layer 14 is located outside the trimmed surface produced by the trimming step. In other words, the intermediate layer 14 is provided at the position where it is cut during the trimming step. The intermediate layer 14 may also be located inside both the cut surface produced by the singulation step and the trimmed surface produced by the trimming step.

[0306] The thickness of the intermediate layer 14 is, for example, 0.3 μm or more, or 1 μm or more. The thickness of the intermediate layer 14 is, for example, 30 μm or less, or 50 μm or less.

[0307] (Interposer and intermediate interposer layers)

[0308] The following describes the rewiring layer 20 and the rewiring layer group 30. The rewiring layer 20 is provided on the carrier substrate 12 via the adhesive layer 15 and the release layer 13. In this embodiment, the rewiring layer group 30 including a plurality of rewiring layers 20 is formed on the release layer 13, thereby forming a plurality of rewiring layers 20 on the carrier substrate 12 in a concentrated and simultaneous manner. As described above, Figure 39 as well as Figure 40 As shown, the rewiring layer group 30 includes a plurality of rewiring layers 20 that are connected to each other.

[0309] The rewiring layer group 30, i.e., the plurality of rewiring layers 20, is releasably disposed on the first upper surface 132, the surface of the release layer 13 opposite the surface in contact with the adhesion layer 15. In this embodiment, as described above, the intermediate layer 14 is partially disposed on the first upper surface 132. Specifically, the rewiring layer group 30 is disposed such that the portions constituting the rewiring layers 20 overlap with the intermediate layer 14, and the portions not constituting the rewiring layers 20 face the release layer 13 without the intermediate layer 14 interposed therebetween.

[0310] The multiple rewiring layers 20 included in the rewiring layer group 30 each include an insulating layer 21 and a plurality of wirings 25 covered by the insulating layer 21. The rewiring layer group 30 includes a previous-process insulating layer 31 and a previous-process wiring layer 32. The previous-process insulating layer 31 is a layer formed by concentrating parts of the insulating layer 21 constituting each rewiring layer 20. The previous-process wiring layer 32 is a layer formed by concentrating parts or all of the wirings 25 included in each rewiring layer 20. The previous-process insulating layer 31 contains resin. The insulating layer 21 of each rewiring layer 20 contains the same resin as the previous-process insulating layer 31. The previous-process insulating layer 31 is a part that covers the plurality of wirings 25 included in the previous-process wiring layer 32 as a whole. The previous-process insulating layer 31 functions as an insulating layer having insulating properties. Therefore, the insulating layer 21 in the rewiring layer 20 also functions as an insulating layer. Insulation refers to a volume resistivity of 10 10 Ω / m or more.

[0311] The redistribution layer group 30 includes a third upper surface 202 and a third lower surface 201. The third lower surface 201 is located on the opposite side of the third upper surface 202. The redistribution layer group 30 may also include a plurality of stacked wiring layers. Figure 39 In the illustrated example, rewiring layer group 30 includes first wiring layer 20A, second wiring layer 20B, and third wiring layer 20C. Each of the plurality of wiring layers may include a previous-process insulating layer 31 and a previous-process wiring layer 32. Previous-process insulating layer 31 of first wiring layer 20A may also constitute third lower surface 201 of rewiring layer group 30. Previous-process insulating layer 31 of third wiring layer 20C may also constitute third upper surface 202 of rewiring layer group 30. While wiring 25 included in previous-process wiring layer 32 in first wiring layer 20A overlaps with intermediate layer 14, a portion of previous-process insulating layer 31 may also be located between wiring 25 and intermediate layer 14.

[0312] The rewiring layer group 30 may also include a through electrode. A through electrode is a conductive portion extending along the third direction D3 in one wiring layer. The through electrode can electrically connect the previous-process wiring layer 32 included in two wiring layers adjacent in the third direction D3.

[0313] like Figure 39 As shown, the rewiring layer group 30 may also include pads 24. The pads 24 are provided so as to protrude from the third upper surface 202 of the rewiring layer group 30. In the illustrated example, a plurality of pads 24 are provided on the third wiring layer 20C. The pads 24 are provided so as to be exposed from the pre-process insulating layer 31 of the third wiring layer 20C and protrude from the third upper surface 202 of the rewiring layer group 30 formed by the third wiring layer 20C. The pads 24 are electrically connected to a portion of the wiring 25 included in the pre-process wiring layer 32 covered by the pre-process insulating layer 31 of the third wiring layer 20C.

[0314] Bumps 27 may be provided on pads 24. Bumps 27 are made of a conductive material. For example, bumps 27 may be made of solder. Bumps 27 may be connected to terminals in a BGA (Ball Grid Array) or to terminals of a semiconductor device.

[0315] Grooves 28 are formed in the rewiring layer group 30 to define the areas where the rewiring layers 20 are located. Grooves 28 are recessed from the third upper surface 202 toward the third lower surface 201 of the rewiring layer group 30. The bottom surface of the groove 28 is located between the third upper surface 202 and the third lower surface 201 in the third direction D3. For example, the bottom surface of the groove 28 is located midway between the third upper surface 202 and the third lower surface 201. The rewiring layers 20 can be cut out by cutting the rewiring layer group 30 and the carrier substrate 12 in the wiring substrate group 10 along the grooves 28.

[0316] like Figure 40 As shown, as an example, the shape of the groove 28 when viewed from above is formed into a grid shape. In this example, the rewiring layer 20 is located on the inner side of the multiple openings in the grid shape formed by the groove 28. That is, the rewiring layer 20 is located in the area surrounded by the grid-shaped groove 28 when viewed from above. The groove 28 can be formed, for example, by etching the material layer of the previous process insulating layer 31 that forms the third wiring layer 20C, or by removing a portion of the material layer using a cutting tool. In addition, the groove 28 may not be formed. In this embodiment, the wiring substrate group 10 is cut along the groove 28, so that the rewiring layer 20 is cut out together with a portion of the carrier substrate 12, that is, singulation is implemented. The cutting can be performed by a cutting edge or by laser irradiation.

[0317] The thickness of the rewiring layer group 30 is, for example, 30 μm or greater, or 35 μm or greater. The thickness of the rewiring layer group 30 is, for example, 50 μm or less, or 45 μm or less. The thickness of the rewiring layer group 30 is the distance in the third direction D3 from the third upper surface 202 to the third lower surface 201. The thickness of each wiring layer in the rewiring layer group 30 is, for example, 4.0 μm or greater, or 6.0 μm or greater. The thickness of each wiring layer in the rewiring layer group 30 is, for example, 12.0 μm or less, or 10.0 μm or less. The thickness of the rewiring layer 20 is the same as the thickness of the rewiring layer group 30.

[0318] The thickness of the conductive layers such as the wiring 25 and the pads 24 constituting the rewiring layer 20 is, for example, 0.1 μm or more, 0.5 μm or more, or 1.0 μm or more. The thickness of the conductive layers such as the wiring 25 and the pads 24 is, for example, 10.0 μm or less, or 5.0 μm or less.

[0319] The width of the wiring 25 is, for example, not less than 0.5 μm, or not less than 1.0 μm. The width of the wiring 25 is, for example, not more than 5.0 μm, or not more than 3.0 μm, or not more than 2.0 μm. The spacing between two adjacent wirings 25 when viewed from above is, for example, not less than 0.5 μm, or not less than 1.0 μm. The spacing between two adjacent wirings 25 when viewed from above is, for example, not more than 5.0 μm, or not more than 3.0 μm, or not more than 2.0 μm. In addition to the wirings 25 that meet these numerical ranges, the pre-process wiring layer 32 may also include wirings 25 that do not meet these numerical ranges.

[0320] The resin contained in the preceding-step insulating layer 31 (the material of the preceding-step insulating layer 31), that is, the resin contained in the insulating layer 21 in the rewiring layer 20 (the material of the insulating layer 21), may include, for example, a resin such as polyimide. The resin of the preceding-step insulating layer 31 and the resin of the insulating layer 21 may be at least one of polyimide, epoxy resin, acrylic acid, bismaleimide, polybenzoxazole, and benzocyclobutene.

[0321] The wiring 25 (pre-process wiring layer 32 ), pads 24 , and through-electrodes are made of a conductive material. For example, the wiring 25 (pre-process wiring layer 32 ) and pads 24 may be made of a metal such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, chromium, or an alloy thereof.

[0322] (Method for Manufacturing Interposer)

[0323] Next, a method for manufacturing the redistribution layer 20 will be described. A flow of manufacturing the redistribution layer 20 from the wiring board group 10 after manufacturing the wiring board group 10 will be described below.

[0324] like Figure 41 As shown in FIG. 1 , a carrier substrate 12 is prepared. In this embodiment, a quartz substrate is prepared as the carrier substrate 12 .

[0325] Then, if Figure 42 As shown, an adhesive layer 15 is provided on the first surface 121 of the carrier substrate 12 (adhesive layer forming step). In this embodiment, as an example, the adhesive layer 15 is formed by depositing a silicon dioxide film on the first surface 121 using plasma CVD. As an example, the adhesive layer 15 is formed so that its transmittance for a laser beam with a wavelength of 355 nm is 90% or higher and its arithmetic mean height is 0.01 μm to 0.1 μm. The thickness of the adhesive layer 15 can be in the range of 25 nm to 300 nm.

[0326] Then, if Figure 43As shown, a peeling layer 13 is provided on the upper surface 152 of the adhesion layer 15 (peeling layer forming step). As described above, the peeling layer 13 is a structural element that enables the redistribution layer 20 in the redistribution layer group 30 to be peeled off from the carrier substrate 12. In other words, the peeling layer 13 is a structural element that facilitates peeling. In this embodiment, the peeling layer 13 comprises polyimide. In this case, the pre-cured polyimide is applied to the upper surface 152 of the adhesion layer 15 and then cured. If the polyimide is a thermosetting type, it is cured by heating, and if the polyimide is a photocuring type, it is cured by irradiation with light.

[0327] Then, if Figure 44 As shown, an intermediate layer 14 that absorbs laser light is partially provided on the first upper surface 132 of the release layer 13 (light-shielding layer formation step). Intermediate layer 14 is positioned between the release layer 13 and the later-formed redistribution layer 20. As described above, intermediate layer 14 can contain at least one of titanium, gold, silver, nickel, and copper. In this case, intermediate layer 14 can also be formed by attaching a foil containing at least one of titanium, gold, silver, nickel, and copper to the release layer 13 and then patterning it.

[0328] Next, one or more rewiring layers 20 are formed on the peeling layer 13 and the intermediate layer 14. In other words, in this embodiment, an interposer forming process is performed to form a rewiring layer group 30 including a plurality of rewiring layers 20. Figure 45 As shown, a pre-process wiring layer 32 is formed including a plurality of wirings 25 constituting the rewiring layer 20. All or most of the wirings 25 included in the pre-process wiring layer 32 are formed on the intermediate layer 14. Here, the wirings 25 may be formed directly on the intermediate layer 14 or through an insulating resin.

[0329] Then, if Figure 46 As shown, the formation is covered in Figure 45 The process of forming the pre-process wiring layer 32 and the pre-process insulating layer 31 formed in the pre-process wiring layer 32 is repeated. Thus, the first wiring layer 20A is formed. Then, similarly to the process of forming the first wiring layer 20A, the pre-process wiring layer 32 and the pre-process insulating layer 31 are alternately formed to form the second wiring layer 20B and the third wiring layer 20C. Figure 47 As shown in FIG. 1 , the rewiring layer group 30 including the first wiring layer 20A, the second wiring layer 20B, and the third wiring layer 20C is obtained. That is, the wiring substrate group 10 is manufactured.

[0330] In this embodiment, grooves 28 are formed in the redistribution layer group 30 to define the region where each redistribution layer 20 is located. Grooves 28 can be formed, for example, by etching the material layer of the preceding insulating layer 31 forming the third wiring layer 20C or by removing a portion of the material layer using a cutting tool.

[0331] Then, if Figure 48 As shown, a singulation process is performed in which the redistribution layer 20 is cut out from the carrier substrate 12 and the redistribution layer group 30, that is, the wiring substrate group 10, together with a portion of the carrier substrate 12. Figure 48 As shown, by cutting the wiring substrate group 10 along the groove 28 and along the line CL parallel to the third direction D3, the redistribution layer 20 is cut out together with a portion of the carrier substrate 12, that is, singulation is implemented. This cutting can be performed by a cutting edge or by laser irradiation. Through such a singulation process, a plurality of wiring substrates 11 including a portion of the carrier substrate 12 and the redistribution layer 20 are formed. Strictly speaking, the portion of the carrier substrate 12 cut out in the singulation process is not the same as the entire carrier substrate 12, but in the following description, it is represented by the symbol 12 for ease of explanation. In the singulation process of this embodiment, the intermediate layer 14 is not cut.

[0332] Then, if Figure 49 As shown, a trimming process is performed. The trimming process is a process of separating the outer peripheral portion 20e of the rewiring layer 20 and a portion of the carrier substrate 12 cut out in the singulation process, that is, in the wiring substrate 11, from its inner portion 20i. In the trimming process, the outer peripheral portion 20e of the rewiring layer 20 is separated from the inner portion 20i using an incision N. The incision N penetrates the rewiring layer 20 in the direction in which the rewiring layer 20 overlaps with a portion of the carrier substrate 12, and reaches the middle position of the carrier substrate 12. The incision N is continuously formed to form a rectangular shape when viewed from above. The inner portion 20i of the rewiring layer 20 is formed in a rectangular shape when viewed from above. In addition, such a trimming process may not be performed.

[0333] Then, if Figure 50 As shown in FIG. 1 , the wiring substrate 11 after the trimming process is taken out. Figure 49 The illustrated state is reversed and arranged to face the first member 81. The first member 81 includes a substrate 811 and a plurality of terminals 812 provided on the surface of the substrate 811. The wiring substrate 11 is arranged so that the bumps 27 provided on the redistribution layer 20 face the terminals 812 of the first member 81.

[0334] Then, if Figure 51As shown, a heat-sensitive adhesive layer 813 is provided on the plurality of terminals 812 of the first member 81. Adhesive layer 813 can be a non-conductive adhesive material, such as NCP (Non Conductive Paste) or NCF (Non Conductive Film), or an underfill. NCP, NCF, and underfill contain thermosetting resins. Adhesive layer 813 can also be made of other heat-adhesive resins. Adhesive layer 813 can also be provided on the redistribution layer 20 so as to cover the bumps 27.

[0335] Then, if Figure 52 As shown, wiring substrate 11 is positioned relative to first member 81 so that bumps 27 provided on redistribution layer 20 are in contact with terminals 812 of first member 81. Adhesive layer 813 is then heated. As a result, wiring substrate 11 and first member 81 are integrated with each other, with bumps 27 provided on redistribution layer 20 and terminals 812 of first member 81 electrically connected.

[0336] Then, if Figure 53 As shown, a stripping process is performed. In the stripping process, laser light L is irradiated onto the stripping layer 13 via the adhesion layer 15. The laser light L is transmitted from the second surface 122 of the carrier substrate 12 (strictly speaking, a portion of the carrier substrate 12) to the first surface 121 and reaches the stripping layer 13. Through the stripping process, the redistribution layer 20 becomes capable of being stripped from the carrier substrate 12 and the adhesion layer 15. Strictly speaking, the inner portion 20i of the redistribution layer 20 separated from the outer peripheral portion 20e by the trimming process becomes capable of being stripped from a portion of the carrier substrate 12 and the adhesion layer 15 on the portion. In this example, the stripping layer 13 decomposes due to the heat generated by the laser light L. As a result, the stripping layer 13 allows the redistribution layer 20 to be stripped.

[0337] like Figure 54 As shown, a portion of the carrier substrate 12 is separated from the redistribution layer 20. Then, as shown in FIG. Figure 55 As shown, the intermediate layer 14 is removed. Removal of the intermediate layer 14 can also be performed by, for example, etching. Sometimes, a portion of the release layer 13 adheres to the intermediate layer 14. In this case, the release layer 13 is removed before removing the intermediate layer 14. Removal of the release layer 13 can also be performed by, for example, ashing. By removing the intermediate layer 14, the redistribution layer 20 is produced, separated from the carrier substrate 12. Strictly speaking, the redistribution layer 20 is produced in a state of being integrated with the first member 81.

[0338] In the embodiment described above, a release layer 13 is provided on the first surface 121 of the carrier substrate 12 via an adhesive layer 15, and a plurality of rewiring layers 20 (rewiring layer group 30) are provided on the release layer 13. The use of the adhesive layer 15 can enhance the adhesion strength of the release layer 13 to the carrier substrate 12. This can suppress delamination of the release layer 13. Specifically, the release layer 13 can be suppressed from delaminating from the carrier substrate 12 during the period from when the laser light L is irradiated onto the release layer 13 via the adhesive layer 15 until the rewiring layer 20 is peeled from the carrier substrate 12 and the adhesive layer 15. This allows for proper delamination of the rewiring layer 20 after the delamination process, for example, enabling smooth and appropriate transfer to the first member 81.

[0339] In this embodiment, a singulation process is performed to separate the rewiring layer 20 from the wiring substrate assembly 10 along with a portion of the carrier substrate 12. In typical manufacturing steps, the adhesive layer 15 described in this embodiment is not provided, but rather a peeling layer is provided directly on the carrier substrate. However, in this case, the peeling layer easily peels off from the cut surfaces after the singulation process, which involves cutting. In contrast, in this embodiment, the provision of the adhesive layer 15 can also reduce the risk of peeling layer 13 peeling off during singulation.

[0340] In this embodiment, a trimming process is performed on the portion of the rewiring layer 20 and carrier substrate 12 cut during the singulation process to separate the outer peripheral portion 20e of the rewiring layer 20 from its inner portion 20i. In conventional manufacturing processes where a release layer is directly applied to the carrier substrate without providing an adhesive layer 15, the release layer is easily peeled off from the cut surface caused by such trimming. In contrast, in this embodiment, the provision of the adhesive layer 15 further reduces the risk of the layer 13 peeling off due to trimming.

[0341] In this embodiment, the adhesion layer 15 is formed by CVD. This allows for efficient formation of the adhesion layer 15. Specifically, the adhesion layer 15 in this embodiment is intended to provide close contact with the release layer 13, and a high density and smoothness are not particularly desirable. Therefore, in this embodiment, while ensuring a high film density may not necessarily be as good as vapor deposition or sputtering, the CVD method, which is easily implemented, is utilized. This allows for efficient formation of the adhesion layer 15.

[0342] In this embodiment, the carrier substrate 12 and the adhesive layer 15 are made of the same material. This allows the adhesive layer 15 to be firmly bonded to the carrier substrate 12. In particular, the carrier substrate 12 and the adhesive layer 15 are made of silicon dioxide. This is advantageous in terms of cost and also in terms of ensuring the desired transmittance of laser light.

[0343] Adhesion layer 15 is preferably configured to have a transmittance of 90% or greater for laser light of a given wavelength. When adhesion layer 15 maintains a laser transmittance of 90% or greater, the peeling interface during laser decomposition of peeling layer 13 becomes uniform. Consequently, peeling of rewiring layer 20 can be performed smoothly while suppressing desired deformation.

[0344] The arithmetic mean height of the adhesive layer 15 is preferably 0.01 μm or more and 0.1 μm or less. When it is within this range, the adhesive layer 15 and the release layer 13 can be firmly bonded.

[0345] Various modifications can be made to the above-described embodiment. For example, in the above-described embodiment, the wiring substrate assembly 10 includes multiple redistribution layers 20. Subsequently, the wiring substrate assembly 10 is singulated to produce multiple redistribution layers 20. Alternatively, the wiring substrate assembly 10 may include a single redistribution layer 20 formed on the carrier substrate 12 via the adhesion layer 15 and the release layer 13. In this case, the singulation process is not required, and the trimming process is not necessarily required. However, the release layer 13 can be prevented from peeling off during the period until the redistribution layer 20 is peeled off.

[0346] Several modified examples of the above-mentioned embodiment have been described. It is, of course, possible to appropriately combine a plurality of modified examples and apply them to the above-mentioned embodiment.

[0347] (First Modification)

[0348] Figure 56 Modifications of the above-described embodiment will be described. Figure 56 The redistribution layer 20 is shown in Figure 48 After the singulation step described above, the image is transferred to the first member 81 without undergoing a trimming step.

[0349] (Second Modification)

[0350] In the above embodiment, the intermediate layer 14 is shown as having light-shielding properties. However, the intermediate layer 14 does not necessarily have light-shielding properties. For example, the intermediate layer 14 may also include an insulating inorganic material. Examples of inorganic materials include inorganic oxides and inorganic nitrides. An example of an inorganic oxide is silicon oxide such as SiO2. An example of an inorganic nitride is silicon nitride such as SiN. Inorganic materials may include SiOC, SiC, SiOF, SiON, SiCN, and the like.

[0351] The thermal expansion coefficient of the inorganic material of the intermediate layer 14 is smaller than that of the organic material of the insulating layer 21. The thermal expansion coefficient of the inorganic layer 23 is, for example, 10.0 ppm / °C or less, 8.0 ppm / °C or less, or 5.0 ppm / °C or less.

[0352] The process of forming the rewiring layer 20 sometimes includes a process performed at high temperature, such as a heating process for the insulating layer 21. The thermal expansion coefficient of the organic material of the insulating layer 21 is greater than the thermal expansion coefficient of other components of the wiring substrate assembly 10. For example, the thermal expansion coefficient of the organic material of the insulating layer 21 is greater than the thermal expansion coefficient of a substrate such as the carrier substrate 12. For example, the thermal expansion coefficient of the organic material of the insulating layer 21 is greater than the thermal expansion coefficient of the conductive layer 22. It is believed that when the temperature of the components of the rewiring layer 20 decreases after the heating process, stress is generated due to the difference in thermal expansion coefficient between the insulating layer 21 and other components. For example, stress is believed to be generated in the substrate, the conductive layer 22, etc.

[0353] According to this modification, since intermediate layer 14 contains an inorganic material, stress caused by insulating layer 21 can be suppressed from affecting carrier substrate 12 and the like. This can suppress warping of, for example, rewiring layer 20, wiring substrate assembly 10, or wiring substrate 11.

[0354] (Third Modification)

[0355] The structure of the first embodiment described above may also be combined with a portion of the structure of the second embodiment described above. For example, the wiring substrate assembly 10 of the first embodiment described above may also include an adhesive layer 15 located between the carrier substrate 12 and the release layer 13. A portion of the structure of the first embodiment described above may also be combined with the structure of the second embodiment described above. For example, the intermediate layer 14 of the wiring substrate assembly 10 of the second embodiment described above may also include an opening.

[0356] -Explanation of symbols-

[0357] 10 Wiring substrate assembly

[0358] 11 Wiring substrate

[0359] 12 Carrier substrate

[0360] 13 peeling layer

[0361] 131 First lower surface

[0362] 132 first upper surface

[0363] 14 Middle Layer

[0364] 141 Second lower surface

[0365] 142 Second upper surface

[0366] 143 First Opening

[0367] 144 Second Opening

[0368] 14A Island Section

[0369] 15 Adhesive layer

[0370] 151 lower surface

[0371] 152 upper surface

[0372] 20 Rewiring Layer

[0373] 201 Third lower surface

[0374] 202 third upper surface

[0375] 203 Third side

[0376] 20A first wiring layer

[0377] 20B second wiring layer

[0378] 20C third wiring layer

[0379] 20e peripheral part

[0380] 20i inner part

[0381] 21 Insulation layer

[0382] 21A Area 1

[0383] 21B Second Area

[0384] 21B1 Area 21

[0385] 22 conductive layer

[0386] 221 seed layer

[0387] 222 coating

[0388] 24 pads

[0389] 25 Wiring

[0390] 26 through-electrode

[0391] 27 Bump

[0392] 28 slots

[0393] 31 Pre-process insulation layer

[0394] 32 front-end wiring layer

[0395] 71 first resist layer

[0396] 81 First Component

[0397] 82 Second component.

Claims

1. A wiring substrate assembly comprising: a carrier substrate; a peeling layer including a first lower surface facing the carrier substrate and a first upper surface located on an opposite side of the first lower surface and containing a resin; an intermediate layer including a second lower surface facing the first upper surface and a second upper surface located on an opposite side of the second lower surface and comprising metal; and a plurality of redistribution layers including a third lower surface at least partially facing the second upper surface and a third upper surface located on the opposite side of the third lower surface, and arranged in a first direction, The redistribution layer includes a first wiring layer constituting the third lower surface, The first wiring layer includes: a conductive layer comprising a metal different from the metal of the intermediate layer; and an insulating layer comprising a resin, The intermediate layer includes an opening exposing the first upper surface.

2. The wiring substrate assembly according to claim 1, wherein: The opening includes a first opening located between the conductive layers of two rewiring layers adjacent to each other in the first direction in a plan view.

3. The wiring substrate assembly according to claim 2, wherein: The first opening has a size of 100 μm or more and 500 μm or less in the first direction.

4. The wiring substrate assembly according to claim 2, wherein: A ratio of a size of the first opening in the first direction to an arrangement pitch of the plurality of redistribution layers in the first direction is greater than or equal to 0.0010 and less than or equal to 0.

10.

5. The wiring substrate assembly according to claim 1, wherein: The insulating layer includes: a second region located in the region where the conductive layer is distributed when viewed from above; and a first region surrounding the second region when viewed from above. The opening includes a plurality of second openings overlapping the second region in a plan view. The wiring substrate assembly according to claim 5 , wherein: The second opening has a size of 50 μm or less in a plan view.

7. The wiring substrate assembly according to claim 5, wherein: A ratio of an area of ​​the plurality of second openings to an area of ​​the second region is greater than or equal to 0.0010 and less than or equal to 0.

10.

8. The wiring substrate assembly according to claim 5, wherein: The conductive layer of the first wiring layer includes a plurality of pads located on the third lower surface and between two adjacent second openings in a plan view.

9. The wiring substrate assembly according to any one of claims 1 to 8, wherein: The intermediate layer contains titanium, nickel, molybdenum, tungsten, tantalum, chromium, or an alloy containing these metals. The conductive layer includes copper or a copper alloy.

10. The wiring substrate assembly according to any one of claims 1 to 8, wherein: A portion of the insulating layer of the first wiring layer is located in the opening and is in contact with the first upper surface of the peeling layer.

11. The wiring substrate assembly according to any one of claims 1 to 8, wherein: A semiconductor element is provided on the third upper surface of the redistribution layer.

12. A method for manufacturing a wiring substrate assembly, comprising: A step of preparing a laminate comprising: a carrier substrate; and a release layer including a first lower surface facing the carrier substrate and a first upper surface located opposite to the first lower surface and containing a resin; an intermediate layer step of forming an intermediate layer, the intermediate layer including a second lower surface facing the first upper surface and a second upper surface located on the opposite side of the second lower surface and containing metal; and a redistribution layer forming step of forming a plurality of redistribution layers arranged in a first direction, the plurality of redistribution layers including a third lower surface at least partially facing the second upper surface and a third upper surface located on an opposite side of the third lower surface; The redistribution layer includes a first wiring layer constituting the third lower surface, The first wiring layer includes: a conductive layer comprising a metal different from the metal of the intermediate layer; and an insulating layer comprising a resin, The intermediate layer includes an opening exposing the first upper surface.

13. The method for manufacturing a wiring substrate assembly according to claim 12, wherein: The rewiring layer forming step includes: applying a resin solution containing a resin and a solvent on the intermediate layer; and heating the resin solution applied on the intermediate layer.

14. A wiring substrate comprising: a carrier substrate; a peeling layer including a first lower surface facing the carrier substrate and a first upper surface located on an opposite side of the first lower surface and containing a resin; an intermediate layer including a second lower surface facing the first upper surface and a second upper surface located on an opposite side of the second lower surface and comprising metal; and a redistribution layer including a third lower surface at least partially facing the second upper surface and a third upper surface located on an opposite side of the third lower surface, The redistribution layer includes a first wiring layer constituting the third lower surface, The first wiring layer includes: a conductive layer comprising a metal different from the metal of the intermediate layer; and an insulating layer comprising a resin, The insulating layer includes: a second region located in the region where the conductive layer is distributed when viewed from above; and a first region surrounding the second region when viewed from above, The intermediate layer includes a plurality of second openings that overlap with the second region in a plan view and expose the first upper surface.

15. A method for manufacturing a wiring substrate, comprising: A step of preparing the wiring board assembly according to any one of claims 1 to 8; and The step of dividing the wiring board group along a boundary between two adjacent rewiring layers in a plan view.

Images