Semiconductor device

Abstract

This semiconductor device is provided with: a plurality of transistor regions; a gate pad disposed above the semiconductor substrate; a built-in resistor unit electrically connected to the gate pad; a plurality of gate wiring portions electrically connected to the built-in resistor portion and provided so as to correspond to the plurality of transistor regions; and a plurality of wiring resistance sections provided so as to respectively correspond to the plurality of gate wiring sections. The plurality of gate wiring portions may include a gate metal layer provided above the semiconductor substrate, and a gate runner provided below the gate metal layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Background Art

[0002] Patent Document 1 describes a semiconductor device in which “the resistance value of a built-in resistor farther from the gate pad 12 is higher than the resistance value of a built-in resistor closer to the gate pad 12 ”.

[0003] Prior art literature Patent Literature Patent Document 1: Japanese Patent Application Laid-Open No. 2010-98250 Patent Document 2: Japanese Patent No. 6874443 Patent Document 3: Japanese Patent No. 6187697 Patent Document 4: Japanese Patent No. 5493840 Summary of the Invention

[0004] Technical issues It is desirable to suppress oscillation between semiconductor chips connected in parallel and oscillation within a single semiconductor chip.

[0005] Technical Solution In a first embodiment of the present invention, a semiconductor device is provided, comprising: a plurality of transistor regions; a gate groove portion, which is arranged above the plurality of transistor regions; a gate pad, which is arranged above a semiconductor substrate; a plurality of gate wiring portions, which are electrically connected between the gate pad and the gate groove portion and are arranged to correspond to any one of the plurality of transistor regions respectively; and a plurality of wiring resistor portions, which are arranged to correspond to the plurality of gate wiring portions respectively.

[0006] The semiconductor device may further include a built-in resistor portion having one end electrically connected to the gate pad and the other end electrically connected to the plurality of gate wiring portions.

[0007] In any of the above-mentioned semiconductor devices, the plurality of gate wiring portions may include a gate metal layer provided above the semiconductor substrate, and a gate runner provided below the gate metal layer.

[0008] Any of the above-mentioned semiconductor devices may include a contact portion provided between the gate metal layer and the gate flow channel and connecting the gate metal layer and the gate flow channel.

[0009] In any of the above-mentioned semiconductor devices, the gate pad may be provided on an outer peripheral side of the semiconductor substrate relative to the plurality of transistor regions in a plan view.

[0010] In any of the above-described semiconductor devices, each of the plurality of wiring resistor portions may be connected to each of the plurality of transistor regions.

[0011] In any of the above-described semiconductor devices, two or more wiring resistor portions among the plurality of wiring resistor portions may be connected to one transistor region among the plurality of transistor regions.

[0012] In any of the above semiconductor devices, the gate pad may be provided between the plurality of transistor regions in a plan view.

[0013] In any of the above semiconductor devices, the built-in resistor portion may include a first built-in resistor and a second built-in resistor different from the first built-in resistor. The plurality of wiring resistor portions may include one or more first wiring resistors connected to the first built-in resistor, and one or more second wiring resistors connected to the second built-in resistor and different from the first wiring resistor.

[0014] In any of the above-mentioned semiconductor devices, the plurality of gate wiring portions may be provided to be separated from each other in a plan view.

[0015] In any of the semiconductor devices described above, the plurality of wiring resistor portions may be provided in any one of the plurality of gate wiring portions. A cross-sectional area of ​​the wiring resistor portion perpendicular to an extending direction may be smaller than a cross-sectional area of ​​the gate wiring portion perpendicular to the extending direction.

[0016] In any of the semiconductor devices described above, each of the plurality of wiring resistance sections may be arranged closer to the gate pad than each of the plurality of transistor regions.

[0017] In any of the above-mentioned semiconductor devices, the plurality of gate wiring portions may be formed of polysilicon.

[0018] In any of the above-mentioned semiconductor devices, the built-in resistor portion may be formed of polysilicon.

[0019] In any of the above-described semiconductor devices, each of the plurality of wiring resistor portions may be formed of a single-layer structure of polycrystalline silicon.

[0020] Any of the above-mentioned semiconductor devices may further include a first resistance measurement pad for measuring the resistance of the built-in resistor portion.

[0021] Any of the above-mentioned semiconductor devices may further include a second resistance measurement pad for measuring the resistance of the wiring resistance portion.

[0022] Any of the above semiconductor devices may include an emitter electrode disposed above the semiconductor substrate. The emitter electrode may include a plurality of emitter electrode portions disposed separately from one another. The plurality of emitter electrode portions may be disposed corresponding to each of the plurality of wiring resistor portions.

[0023] Any of the above semiconductor devices may include an emitter electrode disposed above the semiconductor substrate. The emitter electrode may include a plurality of emitter electrode portions disposed separately from one another. One of the plurality of emitter electrode portions may be disposed corresponding to two or more of the plurality of wiring resistor portions.

[0024] Any of the above-mentioned semiconductor devices may include one emitter electrode provided above the semiconductor substrate so as to be shared by the plurality of wiring resistor portions.

[0025] In any of the above-mentioned semiconductor devices, a resistance value obtained by combining the plurality of wiring resistor portions may be not less than 10% and not more than 80% of a combined resistance of the built-in resistor portion and the plurality of wiring resistor portions.

[0026] In any of the above semiconductor devices, the plurality of gate wiring sections may include a first gate wiring and a second gate wiring longer than the first gate wiring. The wiring resistance section connected to the first gate wiring may have a greater resistance than the wiring resistance section connected to the second gate wiring.

[0027] In any of the above semiconductor devices, the plurality of transistor regions may include a first transistor region and a second transistor region having an area substantially equal to that of the first transistor region. A resistance value of a wiring resistor portion provided in a gate wiring portion connected to a gate conductive portion of the first transistor region may be substantially equal to a resistance value of a wiring resistor portion provided in a gate wiring portion connected to a gate conductive portion of the second transistor region.

[0028] In any of the above semiconductor devices, the plurality of transistor regions may include a first transistor region and a second transistor region having an area larger than that of the first transistor region. A wiring resistor portion provided in a gate wiring portion connected to a gate conductive portion of the first transistor region may have a resistance value greater than a resistance value of a wiring resistor portion provided in a gate wiring portion connected to a gate conductive portion of the second transistor region.

[0029] In any of the above-mentioned semiconductor devices, each of the plurality of wiring resistor portions may have a resistance value of 3Ω or more and 30Ω or less.

[0030] In any of the above-mentioned semiconductor devices, the resistance value of the gate trench portion may be 6 kΩ or less in any region of the plurality of transistor regions.

[0031] In any of the above-mentioned semiconductor devices, the error of the value of the CR time constant can be within 20% in each of the multiple transistor regions, and the CR time constant is the product of the electrostatic capacitance of the transistor region and the resistance value of the wiring resistance part set corresponding to the transistor region.

[0032] In any of the aforementioned semiconductor devices, the plurality of gate wiring portions may be provided between two adjacent transistor regions among the plurality of transistor regions, with one gate wiring portion connected to one of the two adjacent transistor regions. In any of the aforementioned semiconductor devices, the plurality of gate wiring portions may include a gate wiring portion connected to the other of the two adjacent transistor regions.

[0033] It should be noted that the above summary of the invention does not list all the essential features of the present invention. In addition, sub-combinations of these feature groups can also constitute inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1A 1 is a diagram illustrating an example of the upper surface of the semiconductor device 100 .

[0035] Figure 1B 1 is a diagram illustrating an example of the upper surface of the semiconductor device 100 .

[0036] Figure 1C 1 is a diagram illustrating an example of aa′ cross section of the semiconductor device 100 .

[0037] Figure 2A 1 is a diagram illustrating an example of the upper surface of the semiconductor device 100 .

[0038] Figure 2B This is a diagram showing an example of an enlarged view of the upper surface of the semiconductor device 100 .

[0039] Figure 2C 1 is a diagram illustrating an example of a bb′ cross section of the semiconductor device 100 .

[0040] Figure 2D 1 is a diagram illustrating an example of a CC′ cross section of the semiconductor device 100 .

[0041] Figure 3 This is a diagram showing an example of the upper surface of the resistance measurement pad of this example.

[0042] Figure 4A 1 is a diagram illustrating a modified example of the upper surface of the semiconductor device 100 .

[0043] Figure 4B 1 is a diagram illustrating a modified example of the upper surface of the semiconductor device 100 .

[0044] Figure 5A 1 is a diagram illustrating a modified example of the upper surface of the semiconductor device 100 .

[0045] Figure 5B 1 is a diagram illustrating an example of a dd′ cross section of the semiconductor device 100 .

[0046] Explanation of symbols 10···Semiconductor substrate, 12···Emitter region, 14···Base region, 15···Contact region, 16···Accumulator region, 18···Drift region, 20···Buffer region, 21···Front surface, 22···Collector region, 23···Back surface, 24···Collector electrode, 25···Connection portion, 30···Dummy trench portion, 31···Extension portion, 32···Dummy insulating film, 33···Connection portion, 34···Dummy conductive portion, 38···Interlayer insulating film, 40···Gate trench portion, 41···Extension portion, 42···Gate insulating film, 43···Connection portion, 44···Gate conductive portion, 46···Gate runner, 47·· ·Gate metal layer, 48···Gate wiring portion, 49···Contact hole, 50···Gate pad, 51···Contact portion, 52···Emitter electrode, 54···Contact hole, 55···Contact hole, 56···Contact hole, 61···Built-in resistor portion, 62···Wiring resistor portion, 70···Transistor portion, 80···Diode portion, 82···Cathode region, 100···Semiconductor device, 102···End, 120···Transistor region, 130···Well region, 140···Edge termination structure portion, 141···First resistance measurement pad, 142···Second resistance measurement pad, 152···Emitter electrode portion, 153···Connection region DETAILED DESCRIPTION

[0047] The present invention will be described below by way of embodiments of the invention, but the following embodiments do not limit the invention as defined in the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the technical aspects of the invention.

[0048] In this specification, one side parallel to the depth direction of a semiconductor substrate is referred to as "upper," and the other side is referred to as "lower." One of the two principal surfaces of a substrate, layer, or other component is referred to as the upper surface, and the other is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the orientation when a semiconductor device is mounted.

[0049] In this specification, the X-axis, Y-axis, and Z-axis are sometimes used to describe technical matters. These axes simply determine the relative positions of components and do not define specific directions. For example, the Z-axis is not limited to indicating the height relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite to each other. When the Z-axis direction is specified without specifying a positive or negative sign, it refers to a direction parallel to the +Z and -Z axes.

[0050] In this specification, the axes perpendicular to the upper and lower surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, the axis perpendicular to the upper and lower surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis is sometimes referred to as the depth direction. Furthermore, in this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and Y-axis, is sometimes referred to as the horizontal direction.

[0051] In this specification, when described as P+ type or N+ type, it means that the doping concentration is higher than the doping concentration of the P type or N type, and when described as P- type or N- type, it means that the doping concentration is lower than the doping concentration of the P type or N type.

[0052] Figure 1A An example of the top surface of a semiconductor device 100 is shown. In this example, only some components of the semiconductor device 100 are shown, and some components are omitted. The semiconductor device 100 may be an example of a single semiconductor chip or an example of a semiconductor module including a plurality of semiconductor chips.

[0053] Semiconductor substrate 10 has edges 102 when viewed from above. In this example, semiconductor substrate 10 has two sets of edges 102 that oppose each other when viewed from above. In this example, the X-axis and the Y-axis are parallel to any of the edges 102. Semiconductor substrate 10 is silicon. Semiconductor substrate 10 can be a wide-bandgap semiconductor such as gallium nitride or silicon carbide.

[0054] A plurality of transistor regions 120 are provided on the semiconductor substrate 10. The transistor region 120 is a region where the main current flows in the depth direction between the front surface 21 and the back surface 23 of the semiconductor substrate 10 when the semiconductor device 100 is operating. The front surface 21 and the back surface 23 will be described later. An emitter electrode is provided above the transistor region 120, but this is omitted in this figure.

[0055] The transistor region 120 includes at least one of a transistor section 70 including a transistor element such as an IGBT and a diode section 80 including a diode element such as a freewheeling diode (FWD). Figure 1AIn the example shown, transistor portions 70 and diode portions 80 are alternately arranged along a predetermined arrangement direction (in this example, the X-axis direction) on front surface 21 of semiconductor substrate 10. In other examples, only one of transistor portion 70 and diode portion 80 may be provided in transistor region 120.

[0056] In this example, the region where the transistor portion 70 is located is labeled "I," and the region where the diode portion 80 is located is labeled "F." The transistor portion 70 and the diode portion 80 may each have a long side in the direction in which they extend. That is, the length of the transistor portion 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode portion 80 in the Y-axis direction is greater than its width in the X-axis direction. The extending directions of the transistor portion 70 and the diode portion 80 may be the same as the long side directions of the respective trench portions.

[0057] Transistor section 70 is a region formed by projecting collector region 22, provided on the back side of semiconductor substrate 10, onto the upper surface of semiconductor substrate 10. Collector region 22 will be described later. Transistor section 70 includes a transistor such as an IGBT. In this example, transistor section 70 is an IGBT. It should be noted that transistor section 70 may also be another transistor such as a MOSFET.

[0058] The diode portion 80 is a region formed by projecting a cathode region 82 provided on the back surface 23 of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The cathode region 82 will be described later. A P+ type collector region 22 may be provided on the back surface 23 of the semiconductor substrate 10 in an area other than the cathode region 82.

[0059] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 in this example has a gate pad 50. The semiconductor device 100 may have pads such as an anode pad and a cathode pad. In this example, each pad is arranged near the end 102. The vicinity of the end 102 refers to the area between the end 102 and the transistor region 120 when viewed from above. When the semiconductor device 100 is installed, each pad can be connected to an external circuit via wiring such as a wire. In addition, the arrangement position of each pad may not be arranged near the end 102.

[0060] A gate potential is applied to the gate pad 50. The gate pad 50 is electrically connected to the gate conductive portion of the gate trench portion of the transistor region 120 via a plurality of gate wiring portions 48. Figure 1A In FIG. 1 , the gate wiring portion 48 is marked with oblique hatching.

[0061] The gate wiring portion 48 may be formed of either a gate metal layer 47 or a gate runner 46 described later, or a combination thereof as appropriate. The configuration and arrangement of the gate wiring portion 48 and the transistor region 120 will be described later.

[0062] Edge termination structure 140 is provided on front surface 21 of semiconductor substrate 10. Edge termination structure 140 is provided between transistor region 120 and edge 102 in a plan view. In this embodiment, edge termination structure 140 is disposed between gate wiring portion 48 and edge 102. Edge termination structure 140 mitigates electric field concentration on front surface 21 of semiconductor substrate 10. Edge termination structure 140 can comprise at least one of a guard ring, a field plate, and a surface field reducer, provided in an annular shape surrounding transistor region 120.

[0063] Figure 1B 1 is a diagram illustrating an example of the upper surface of the semiconductor device 100 . Figure 1B yes Figure 1A Magnified view of the area indicated by A. Figure 1B The vicinity of one negative end portion in the Y-axis direction of the plurality of transistor regions 120 is shown. The semiconductor device 100 includes a semiconductor substrate 10 having a transistor portion 70 including transistor elements such as IGBTs and a diode portion 80 including diode elements such as freewheeling diodes (FWDs).

[0064] Semiconductor device 100 of this example includes gate trench 40, dummy trench 30, well region 130, emitter region 12, base region 14, and contact region 15 provided inside the front surface of semiconductor substrate 10. Gate trench 40 and dummy trench 30 are each an example of a trench portion.

[0065] The semiconductor device 100 of this embodiment includes a gate metal layer 47 and an emitter electrode 52 provided above the front surface of the semiconductor substrate 10. The emitter electrode 52 is an example of a front-side electrode. The gate metal layer 47 and the emitter electrode 52 are electrically insulated.

[0066] An interlayer insulating film is provided between the front surface of the semiconductor substrate 10 and the emitter electrode 52 and the gate metal layer 47. Figure 1B The contact holes 49, 54, and 56 are provided in the interlayer insulating film of this embodiment in such a manner as to penetrate the interlayer insulating film. Figure 1B In FIG. 1 , each contact hole is marked with an oblique hatching line.

[0067] Emitter electrode 52 is provided above gate trench 40, dummy trench 30, well region 130, emitter region 12, base region 14, and contact region 15. Emitter electrode 52 is electrically connected to emitter region 12, base region 14, and contact region 15 on the front surface of semiconductor substrate 10 through contact hole 54.

[0068] Furthermore, emitter electrode 52 is connected to the dummy conductive portion within dummy trench 30 via contact hole 56. A connection portion 25 formed of a conductive material such as impurity-doped polysilicon may be provided between emitter electrode 52 and the dummy conductive portion. Connection portion 25 is provided on the front surface of semiconductor substrate 10 via an insulating film such as an interlayer insulating film and the dummy insulating film of dummy trench 30.

[0069] The gate runner 46 is connected to the gate conductive portion in the gate trench 40 through the contact hole 55 on the front surface of the semiconductor substrate 10. The gate runner 46 is electrically connected to the gate metal layer 47 via the contact hole 49. The gate runner 46 is not electrically connected to the dummy conductive portion in the dummy trench 30 or the emitter electrode 52.

[0070] The gate runner 46 is electrically isolated from the emitter electrode 52 by an insulator such as an interlayer insulating film or an oxide film. In this example, the gate runner 46 extends from below the contact hole 49 to the front end (the end in the Y-axis direction) of the gate trench 40. The gate conductive portion is exposed on the front surface of the semiconductor substrate 10 at the front end of the gate trench 40 and is connected to the gate runner 46.

[0071] The emitter electrode 52 is formed of a conductive material including metal, for example, aluminum or an aluminum-silicon alloy. The emitter electrode 52 may include a barrier metal formed of titanium, a titanium compound, or the like, in a layer below the region formed of aluminum or the like.

[0072] The emitter electrode 52 may include a plug made of tungsten in the contact hole. The plug may include a barrier metal on the side in contact with the semiconductor substrate 10, be embedded with tungsten in contact with the barrier metal, and be formed of aluminum on the tungsten.

[0073] The well region 130 extends outside the gate channel 46 in a manner overlapping with the peripheral area and is arranged in a ring shape when viewed from above. The well region 130 also extends to a predetermined width in the transistor region 120 inside the gate channel 46 and is arranged in a ring shape when viewed from above. The well region 130 of this example is arranged in a range that is further away from the gate channel 46 side than the end of the contact hole 54 in the Y-axis direction. The well region 130 is a second conductive type region with a doping concentration higher than the doping concentration of the base region 14. The doping concentration of the well region 130 can be the same as the doping concentration of the contact region 15, or it can be lower than the doping concentration of the contact region 15. The gate channel 46 is electrically insulated from the well region 130.

[0074] In this example, base region 14 is of P-type, and well region 130 is of P+ type. Furthermore, well region 130 is formed from the front surface of the semiconductor substrate to a position deeper than the bottom end of base region 14. In transistor portion 70 and diode portion 80, base region 14 is provided in contact with well region 130. Well region 130 is electrically connected to emitter electrode 52.

[0075] The transistor portion 70 and the diode portion 80 each have a plurality of trench portions arranged along the arrangement direction. In this example, the transistor portion 70 is provided with one or more gate trench portions 40 and one or more dummy trench portions 30 alternately arranged along the arrangement direction. In this example, the diode portion 80 is provided with a plurality of dummy trench portions 30 along the arrangement direction.

[0076] In this example, the trench portions are arranged in the X-axis direction, and the extending direction perpendicular to the arrangement direction is the Y-axis direction. The gate trench portion 40 of this example may include two extending portions 41 extending along the extending direction (portions forming a linear trench along the extending direction), and a connecting portion 43 connecting the two extending portions 41.

[0077] At least a portion of the connecting portion 43 may be curved in a plan view. The connecting portion 43 connects the ends of the two extensions 41 in the Y-axis direction to the gate runner 46, thereby functioning as a gate electrode for the gate trench 40. Furthermore, by having the connecting portion 43 curved, the electric field concentration at the ends can be reduced compared to when the connecting portion 43 terminates at the extension 41.

[0078] In the transistor portion 70 , the dummy trench portion 30 is provided between the respective extension portions 41 of the gate trench portion 40 . Figure 1B In the example shown in FIG. 4 , one dummy groove portion 30 is provided between the extension portions 41 , but two or more dummy groove portions 30 may be provided.

[0079] Furthermore, the dummy trench portion 30 may not be provided between the extension portions 41, and the gate trench portion 40 may be provided. With such a structure, the electron current from the emitter region 12 can be increased, thereby reducing the on-voltage.

[0080] The dummy trench portion 30 may have a linear shape extending along the extending direction, and may have an extending portion 31 and a connecting portion 33 similar to the gate trench portion 40 . Figure 1B The semiconductor device 100 shown includes U-shaped dummy trenches 30 having connection portions 33 and linear dummy trenches 30 without connection portions 33. The semiconductor device 100 may also include only dummy trenches 30 having connection portions 33.

[0081] The diffusion depth of the well region 130 can be deeper than that of the gate trench 40 and the dummy trench 30. The ends of the gate trench 40 and the dummy trench 30 in the Y-axis direction are located within the well region 130 when viewed from above. That is, at the ends of each trench in the Y-axis direction, the bottom of each trench in the depth direction (positive side in the Z-axis direction) is covered by the well region 130. This can alleviate electric field concentration at the bottom of each trench.

[0082] Mesa portions are provided between the groove portions in the arrangement direction. The mesa portion refers to a region sandwiched between the groove portions within the semiconductor substrate 10. As an example, the depth of the mesa portion is from the front surface of the semiconductor substrate to the bottom end of the groove portion.

[0083] The mesa portion of this example is provided so as to be sandwiched between the trench portions adjacent in the X-axis direction, and extends along the trench in the extending direction (Y-axis direction) on the front surface of the semiconductor substrate 10 .

[0084] A base region 14 is provided in each mesa portion. In each mesa portion, at least one of an emitter region 12 of a first conductivity type and a contact region 15 of a second conductivity type can be provided in the region sandwiched by the base region 14 when viewed from above. In this example, the emitter region 12 is of N+ type, and the contact region 15 is of P+ type. The emitter region 12 and the contact region 15 can be provided depth-wise between the base region 14 and the front surface of the semiconductor substrate 10. As an example, the dopant in the emitter region 12 is arsenic (As), phosphorus (P), antimony (Sb), or the like.

[0085] The mesa portion of transistor portion 70 includes emitter region 12 exposed on the front surface of semiconductor substrate 10. Emitter region 12 is provided in contact with gate trench portion 40. Contact region 15 exposed on the front surface of semiconductor substrate 10 is provided in the mesa portion in contact with gate trench portion 40.

[0086] The contact regions 15 and emitter regions 12 in the mesa portion are arranged from one groove portion to the other groove portion in the X-axis direction. As an example, the contact regions 15 and emitter regions 12 in the mesa portion are alternately arranged along the extending direction of the groove portion (Y-axis direction).

[0087] In other examples, the contact regions 15 and emitter regions 12 of the mesa portion may be arranged in a stripe pattern along the extending direction of the groove portion (the Y-axis direction). For example, the emitter regions 12 may be provided in the region contacting the groove portion, and the contact regions 15 may be provided in the region sandwiched by the emitter regions 12.

[0088] The emitter region 12 is not provided in the mesa portion of the diode portion 80. The base region 14 may be provided on the upper surface of the mesa portion of the diode portion 80. The base region 14 may be arranged over the entire mesa portion of the diode portion 80. The base region 14 of the diode portion 80 functions as an anode.

[0089] A contact hole 54 is provided above each mesa portion. Contact hole 54 is located in a region sandwiched between base regions 14 in the direction in which the mesa portion extends (the Y-axis direction). In this example, contact hole 54 is located above each of contact region 15, base region 14, and emitter region 12. Contact hole 54 can be located at the center of the mesa portion in the direction in which the mesa portion is arranged (the X-axis direction).

[0090] In the diode portion 80, an N+ type cathode region 82 is provided in a region adjacent to the back surface of the semiconductor substrate. On the back surface of the semiconductor substrate, a P+ type collector region 22 may be provided in a region where the cathode region 82 is not provided. Figure 1B In FIG. 8 , the boundary between the cathode region 82 and the collector region 22 is indicated by a dotted line.

[0091] The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor portion 70 and the diode portion 80. Specifically, in this example, the transistor portion 70 is the region obtained by projecting the collector region 22 provided on the back side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. Furthermore, the diode portion 80 is the region obtained by projecting the cathode region 82 provided on the back side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10.

[0092] Figure 1C Show Figure 1B . The a-a' cross section is an example of the XZ plane passing through the emitter region 12 in the transistor portion 70. In the a-a' cross section, the semiconductor device 100 of this example includes a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24. The semiconductor substrate 10 includes the emitter region 12, the base region 14, the storage region 16, the drift region 18, the buffer region 20, the collector region 22, and the cathode region 82. The collector electrode 24 is an example of a back-side metal layer provided in contact with the back surface 23 of the semiconductor substrate 10.

[0093] The drift region 18 is a region of the first conductivity type provided in the semiconductor substrate 10. As an example, the drift region 18 in this embodiment is N-type. The drift region 18 may be a region remaining in the semiconductor substrate 10 without forming other doped regions. In other words, the doping concentration of the drift region 18 may be the same as the doping concentration of the semiconductor substrate 10.

[0094] The accumulation region 16 is a region of the first conductivity type provided below the base region 14 in the semiconductor substrate 10. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18. As an example, the accumulation region 16 in this example is of N+ type.

[0095] The accumulation region 16 may be provided in the transistor portion 70 instead of the diode portion 80. The accumulation region 16 may be provided in both the transistor portion 70 and the diode portion 80. Providing the accumulation region 16 can enhance the carrier injection enhancement effect (IE effect) and reduce the on-voltage of the transistor portion 70.

[0096] A buffer region 20 of the first conductivity type may be provided below the drift region 18. In this example, the buffer region 20 is of N-type. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower surface of the base region 14 from reaching the collector region 22 and the cathode region 82.

[0097] In the transistor portion 70 , the collector region 22 is provided below the buffer region 20 . The collector region 22 may be provided on the back surface 23 so as to be in contact with the cathode region 82 .

[0098] In diode section 80, cathode region 82 is provided below buffer region 20. Cathode region 82 can be provided to the same depth as collector region 22 of transistor section 70. Diode section 80 can function as a freewheeling diode (FWD) that allows reverse-conducting freewheeling current to flow when transistor section 70 is turned off.

[0099] The collector electrode 24 is formed on the back surface 23 of the semiconductor substrate 10. The collector electrode 24 is formed of a conductive material such as metal. The collector electrode 24 can be formed of the same conductive material as the emitter electrode 52 or a different conductive material.

[0100] The gate trench portion 40 includes a gate trench formed on the front surface 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed so as to cover the inner wall of the gate trench. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench at a position further inside than the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate trench portion 40 is covered by an interlayer insulating film 38 on the front surface 21.

[0101] The gate conductive portion 44 includes a region facing the base region 14 adjacent to the semiconductor substrate 10 via the gate insulating film 42 in the depth direction. When a predetermined voltage is applied to the gate conductive portion 44, a channel consisting of an electron inversion layer is formed in the surface layer of the interface of the base region 14 in contact with the gate trench.

[0102] The dummy trench portion 30 can have the same structure as the gate trench portion 40. The dummy trench portion 30 includes a dummy trench formed on the front surface 21 side, a dummy insulating film 32, and a dummy conductive portion 34. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 is covered by an interlayer insulating film 38 on the front surface 21.

[0103] An interlayer insulating film 38 is provided on the front surface 21. An emitter electrode 52 is provided above the interlayer insulating film 38. One or more trench contacts for electrically connecting the emitter electrode 52 to the semiconductor substrate 10 may be provided in the interlayer insulating film 38. Contact holes 49, 55, and 56 may also have trench contacts provided so as to penetrate the interlayer insulating film 38.

[0104] Figure 2A 1 is a diagram showing an example of the upper surface of the semiconductor device 100. The semiconductor device 100 of this example includes a gate wiring portion 48, a gate pad 50, a wiring resistor portion 62, a transistor region 120, an emitter electrode portion 152, a first resistance measurement pad 141, and a second resistance measurement pad 142. The semiconductor device 100 may include a built-in resistor portion 61. Figure 2A , an embodiment is shown in which a plurality of gate wiring portions 48, transistor regions 120, emitter electrode portions 152, wiring resistor portions 62, and second resistance measurement pads 142 are provided, and a built-in resistor portion 61 is provided.

[0105] In this specification, a gate wiring portion 48 refers to a wiring portion between the gate pad 50 and the gate trench 40, which electrically connects the gate pad 50 and the gate conductive portion 44 of the gate trench 40. One or more gate wiring portions 48 may extend from a single gate pad 50. The gate wiring portion 48 may have branches, and the branched portions may be connected again. In this example, the multiple gate wiring portions 48 are provided to correspond to each of the multiple transistor regions 120. The gate wiring portion 48 includes a gate metal layer 47 provided above the semiconductor substrate 10 and a gate runner 46 provided below the gate metal layer 47.

[0106] exist Figure 2A , the gate metal layer 47 is represented by a solid line, and the gate runner 46 is represented by a dotted line. In a plan view, the lateral width of the gate runner 46 may be wider than the lateral width of the gate metal layer 47. In a plan view, the gate runner 46 and the gate metal layer 47 may at least partially overlap.

[0107] The gate metal layer 47 is made of a conductive metal material. In one example, the gate metal layer 47 is made of tungsten (W). The gate metal layer 47 can be made of the same material as the emitter electrode 52 and the collector electrode 24, or a different material. Using a metal material to form the gate metal layer 47 can reduce delays in applying a gate voltage.

[0108] The gate runner 46 is made of a conductive material. In one example, the gate runner 46 is made of polysilicon. The gate runner 46 can also be made of a metal material. The gate runner 46 can be positioned below the gate metal layer 47 and above the front surface 21 of the semiconductor substrate 10. An interlayer insulating film 38 can be provided between the gate runner 46 and the gate metal layer 47.

[0109] The gate wiring portion 48 may be formed of only one of the gate metal layer 47 and the gate runner 46. In one example, the gate wiring portion 48 is formed of only the gate runner 46. The gate wiring portion 48 may be formed of polysilicon.

[0110] One end of the built-in resistor portion 61 is electrically connected to the gate pad 50, and the other end is electrically connected to the plurality of gate wiring portions 48. The built-in resistor portion 61 can be provided between the gate pad 50 and the transistor region 120. In this example, the built-in resistor portion 61 is formed simultaneously with the formation of the gate runner 46. In other words, the built-in resistor portion 61 can be made of polysilicon. This allows the built-in resistor portion 61 to be formed during the formation of the gate wiring portion 48, thereby reducing the number of steps. The built-in resistor portion 61 can also be made of a resistive film other than polysilicon.

[0111] The built-in resistor 61 can adjust the relaxation time when switching the gate voltage on and off. This can attenuate gate oscillation and short-circuit oscillation between semiconductor chips when multiple semiconductor chips are connected in parallel, thus suppressing oscillation.

[0112] Between the first resistance measurement pad 141 and the transistor region 120, wiring resistor portions 62 are provided so as to correspond to the gate wiring portions 48, respectively. The wiring resistor portion 62 in this example is a portion of the gate wiring portion 48, and is a portion where the gate metal layer 47 is not provided. In other words, the wiring resistor portion 62 can be formed of a single-layer structure of polysilicon. Thus, since the wiring resistor portion 62 can be formed at the stage of forming the gate wiring portion 48, the number of steps can be reduced. The wiring resistor portion 62 can also be another resistor portion different from the gate wiring portion 48. In one example, the wiring resistor portion 62 is formed of a resistive film other than polysilicon.

[0113] Providing wiring resistor section 62 allows adjustment of the relaxation time when switching the gate voltage on and off. Since wiring resistor section 62 is provided corresponding to gate wiring section 48, when multiple transistor regions 120 and gate wiring section 48 are arranged in parallel within a single semiconductor chip, gate oscillation and short-circuit oscillation between transistor regions 120 within the single semiconductor chip can be attenuated, thereby suppressing oscillation.

[0114] First resistance measurement pad 141 is provided above semiconductor substrate 10 and is electrically connected to gate pad 50 via built-in resistor portion 61. A protective film (not shown) such as polyimide may not be provided above first resistance measurement pad 141. First resistance measurement pad 141 is made of a conductive metal material. The material of first resistance measurement pad 141 may be the same as or different from that of gate pad 50.

[0115] First resistance measurement pad 141 is provided so as to partially overlap built-in resistor section 61 when viewed from above. First resistance measurement pad 141 and built-in resistor section 61 are electrically connected via contact hole 49. The detailed connection relationship between first resistance measurement pad 141, built-in resistor section 61, and gate pad 50 will be described later. First resistance measurement pad 141 can measure the current and voltage between first resistance measurement pad 141 and gate pad 50, and can also measure the resistance of built-in resistor section 61.

[0116] Second resistance measurement pads 142 are provided above semiconductor substrate 10 and are electrically connected to both ends of wiring resistor portion 62. A protective film (not shown) such as polyimide may not be provided above second resistance measurement pads 142. Second resistance measurement pads 142 are made of a conductive metal material. The material of second resistance measurement pads 142 may be the same as or different from the material of first resistance measurement pads 141.

[0117] The second resistance measuring pads 142 are electrically connected to the wiring resistor portion 62 via the contact holes 49. The detailed connection relationship between the second resistance measuring pads 142 and the wiring resistor portion 62 will be described later. The second resistance measuring pads 142 can measure the current and voltage between the two second resistance measuring pads 142, thereby measuring the resistance of the wiring resistor portion 62.

[0118] The first resistance measurement pad 141 and the second resistance measurement pad 142 can be configured to simultaneously measure the resistance of the built-in resistor section 61 and the wiring resistor section 62. The second resistance measurement pad 142 can measure the current and voltage between the first resistance measurement pad 141 and the second resistance measurement pad 142 to measure the resistance of the wiring resistor section 62. As an example, when the wiring resistor section 62 is connected to the first resistance measurement pad 141, the resistance of the built-in resistor section 61 can be measured by measuring the current and voltage between the gate pad 50 and the first resistance measurement pad 141, and the resistance of the wiring resistor section 62 can be measured by measuring the current and voltage between the first resistance measurement pad 141 and the second resistance measurement pad 142.

[0119] The transistor region 120 is a region through which the main current flows in the depth direction between the front surface 21 and the back surface 23 of the semiconductor substrate 10 when the semiconductor device 100 is in operation. The transistor region 120 includes the transistor portion 70 and the diode portion 80. In this specification, one transistor region 120 may be the region surrounded by one gate wiring portion 48.

[0120] The emitter electrode portion 152 is provided above the semiconductor substrate 10 and applies a potential different from the gate potential to the transistor region 120. In this example, the emitter electrode portion 152 is electrically insulated from the gate wiring portion 48. In this specification, one emitter electrode portion 152 may be an emitter electrode formed of a continuous metal plate.

[0121] exist Figure 2A In the semiconductor device 100 shown, a gate pad 50 and a built-in resistor section 61 electrically connected to the gate pad 50 are provided for multiple transistor regions 120. In the semiconductor device 100, one transistor region 120, one gate pad 50, and one built-in resistor section 61 electrically connected to the gate pad 50 can each be provided. In the semiconductor device 100, the built-in resistor section 61 may not be provided. In this example, one gate pad 50 and one built-in resistor section 61 electrically connected to the gate pad 50 are provided for three transistor regions 120-1, 120-2, and 120-3. Providing the built-in resistor section 61 can suppress gate oscillation and short-circuit oscillation between semiconductor chips.

[0122] exist Figure 2AIn the embodiment shown, a semiconductor device 100 is provided with a plurality of gate wiring portions 48 provided corresponding to any one of a plurality of transistor regions 120. The number of gate wiring portions 48 provided in the semiconductor device 100 may be the same as or different from the number of transistor regions 120. In this example, a first gate wiring 48-1, a second gate wiring 48-2, and a third gate wiring 48-3 are provided corresponding to the first transistor region 120-1, the second transistor region 120-2, and the third transistor region 120-3, respectively.

[0123] exist Figure 2A In the embodiment shown, a semiconductor device 100 is provided with a plurality of wiring resistor sections 62 provided corresponding to a plurality of gate wiring sections 48. The number of gate wiring sections 48 and the number of wiring resistor sections 62 provided in the gate wiring sections 48 may be the same or different. One wiring resistor section 62 may be provided for each gate wiring section 48, or two or more wiring resistor sections may be provided.

[0124] In this example, a first wiring resistor 62-1, a second wiring resistor 62-2, and a third wiring resistor 62-3 are shown corresponding to the first gate wiring 48-1, the second gate wiring 48-2, and the third gate wiring 48-3, respectively. Providing a wiring resistor section 62 for each of the gate wiring sections 48 can suppress oscillations within the same chip, for example, oscillations between the first transistor region 120-1 and the second transistor region 120-2 can be suppressed.

[0125] Each of the plurality of wiring resistor sections 62 is provided so as to be connected to each of the plurality of transistor regions 120. The number of wiring resistor sections 62 may be the same as or different from the number of transistor regions 120. One wiring resistor section 62 may be provided for each transistor region 120, or two or more wiring resistor sections 62 may be provided.

[0126] In this example, first wiring resistor 62-1, second wiring resistor 62-2, and third wiring resistor 62-3 are provided to be connected to first transistor region 120-1, second transistor region 120-2, and third transistor region 120-3, respectively. Providing wiring resistor 62 between multiple transistor regions 120 can suppress oscillation within the same chip.

[0127] Each of the plurality of wiring resistor sections 62 is arranged closer to gate pad 50 than each of the plurality of transistor regions 120. For each gate wiring section 48, the length of gate wiring section 48 from first resistance measurement pad 141 to wiring resistor section 62 can be shorter than the length of gate wiring section 48 from wiring resistor section 62 to transistor region 120. Thus, by arranging first resistance measurement pad 141 and the plurality of second resistance measurement pads 142 near gate pad 50, the detection accuracy of each resistance value can be improved.

[0128] The resistance value of each of the plurality of wiring resistor portions 62 may be greater than the resistance value of the built-in resistor portion 61. The resistance value obtained by synthesizing the plurality of wiring resistor portions 62 is greater than 0% and less than 100% of the combined resistance of the built-in resistor portion 61 and the plurality of wiring resistor portions 62. In addition, the combined resistance of the plurality of wiring resistor portions 62 may be greater than 10% of the combined resistance of the built-in resistor portion 61 and the plurality of wiring resistor portions 62, and may be less than 80%. By making the resistance value of each of the plurality of wiring resistor portions 62 greater than the resistance value of the built-in resistor portion 61, it is possible to suppress the variation in the resistance value of the wiring resistor portion 62, thereby making the operating characteristics of the semiconductor device 100 uniform.

[0129] The resistance value of the combined resistance of the built-in resistor section 61 and the plurality of wired resistor sections 62 can be determined based on the rated output of the semiconductor device 100. In one example, the resistance value of the combined resistance of the built-in resistor section 61 and the plurality of wired resistor sections 62 is determined based on the rated output of the semiconductor device 100, and the resistance value of the plurality of wired resistor sections 62 is determined based on the resistance value of the combined resistance. This allows the required rated output of the semiconductor device 100 to be maintained while suppressing both inter-chip oscillation and intra-chip oscillation when multiple semiconductor chips are connected in parallel.

[0130] The gate pad 50 is provided on the outer periphery of the semiconductor substrate 10 relative to the transistor regions 120 in a plan view. Providing the gate pad 50 on the outer periphery of the semiconductor substrate 10 allows the gate wire to be routed without interfering with the main wiring.

[0131] The multiple gate wiring sections 48 are spaced apart from each other in a plan view. Specifically, in this example, the first gate wiring 48-1, the second gate wiring 48-2, and the third gate wiring 48-3 are connected only at the first resistance measurement pad 141 and are disconnected elsewhere. This allows wiring resistor sections 62 to be positioned between the multiple transistor regions 120, thereby suppressing oscillation within the same chip.

[0132] The radiating electrode 52 may include a plurality of radiating electrode portions 152 provided separately from each other. The radiating electrode 52 in this example includes a first radiating electrode portion 152-1, a second radiating electrode portion 152-2, and a third radiating electrode portion 152-3.

[0133] Multiple radiating electrode sections 152 can be provided corresponding to multiple wiring resistor sections 62, respectively. The number of wiring resistor sections 62 can be the same as or different from the number of radiating electrode sections 152. One wiring resistor section 62 can be provided for each radiating electrode section 152, or two or more wiring resistor sections can be provided. In this example, the first radiating electrode section 152-1, the second radiating electrode section 152-2, and the third radiating electrode section 152-3 are provided corresponding to the first wiring resistor 62-1, the second wiring resistor 62-2, and the third wiring resistor 62-3, respectively.

[0134] The multiple transistor regions 120 can include two or more transistor regions with approximately the same area. In this example, the transistor regions include a first transistor region 120-1 and a second transistor region 120-2 with approximately the same area. In this specification, "approximately the same area" of the transistor regions 120 means that the difference in area between the two transistor regions 120 is within 10%. By making the areas of the multiple transistor regions 120 approximately the same, the difference in active area between the transistor regions 120 is reduced, which reduces current concentration during the turn-off of the semiconductor device 100 and improves latch-up resistance.

[0135] The lengths of the plurality of gate wiring portions 48 may be different for each gate wiring portion 48 or may be the same. The lengths of the gate wiring portions 48 may be appropriately adjusted according to the arrangement of the gate pad 50 and the transistor region 120 in the semiconductor device 100. The plurality of gate wiring portions in this example include a first gate wiring 48-1 connected to the first transistor region 120-1 and a second gate wiring 48-2 connected to the second transistor region 120-2 and longer than the first gate wiring 48-1.

[0136] The lengths of the multiple gate wiring portions 48 can be appropriately adjusted within a range that prevents gate signal delays between the multiple transistor regions 120 connected to each gate wiring portion 48. The lengths of the multiple gate wiring portions 48 can also be adjusted so that the gate resistance value remains below a predetermined value in all regions of the multiple transistor regions 120. The resistance value between the ends of the gate trench portion 40 connected to the gate wiring portion 48 in each transistor region 120 can be set to 6 kΩ or less for each gate trench portion 40 in any region.

[0137] The resistance values ​​of the plurality of wiring resistor sections 62 may be different for each wiring resistor section 62 or may be the same. The resistance value of each wiring resistor section 62 may be greater than or equal to 3Ω or less than or equal to 30Ω. The resistance value of the wiring resistor section 62 may vary depending on the electrostatic capacitance of the transistor region 120 to which each wiring resistor section 62 is connected, the mutual inductance received by the gate wiring section 48 in which each wiring resistor section 62 is disposed from surrounding gate wiring sections 48, or the resonance strength of the LC resonant circuit formed within the same chip.

[0138] The resistance value of each of the plurality of wiring resistor sections 62 can be varied depending on the area of ​​the transistor region 120 to which the wiring resistor section 62 is connected. In this example, the resistance values ​​of the wiring resistor sections 62-1 and 62-2 connected to the first transistor region 120-1 and the second transistor region 120-2, which have substantially the same area, can be substantially equal. In this specification, the resistance values ​​of the wiring resistor sections 62 being substantially equal can mean that the difference in resistance between the two wiring resistor sections 62 is within 10%.

[0139] The resistance values ​​of the plurality of wiring resistor sections 62 can be varied depending on the length of the gate wiring section 48 in which each wiring resistor section 62 is provided. In this example, the resistance value of the first wiring resistor 62-1 connected to the first gate wiring section 48-1 is greater than the resistance value of the second wiring resistor 62-2 connected to the second gate wiring section 48-2. Generally, since the parasitic capacitance of a gate wiring section 48 increases as the length of the gate wiring section 48 increases, oscillation can be suppressed even if the resistance value of the wiring resistor section 62 in a particular gate wiring section 48 is smaller than the resistance values ​​of the wiring resistor sections 62 in other gate wiring sections 48.

[0140] The resistance values ​​of the plurality of wiring resistor sections 62 can vary according to the error in the CR time constant, which is the product of the electrostatic capacitance C of each transistor region 120 among the plurality of transistor regions 120 and the resistance value R of each wiring resistor section 62 provided corresponding to each transistor region 120. In this example, the error in the value of the CR time constant, which is the product of the electrostatic capacitance C of the transistor region 120 and the resistance value R of the wiring resistor section 62 provided corresponding to each transistor region 120, is 10% or less in each of the plurality of transistor regions 120. This error can also be 20% or less. By limiting the error in the CR time constant to 20% or less, current unevenness during switching operation of the semiconductor device 100 can be eliminated.

[0141] Figure 2B An example of an enlarged view of the top surface of the semiconductor device 100 is shown. Figure 2B It will Figure 2AFIG1 is an enlarged view of the area B surrounded by the double-dashed line. The first gate wiring 48-1 may include a first gate metal layer 47-1 and a first gate flow channel 46-1, the second gate wiring 48-2 may include a second gate metal layer 47-2 and a second gate flow channel 46-2, and the third gate wiring 48-3 may include a third gate metal layer 47-3 and a third gate flow channel 46-3.

[0142] The plurality of gate wiring portions 48 are provided between two adjacent transistor regions 120 among the plurality of transistor regions 120. A gate wiring portion 48 connected to one of the two adjacent transistor regions 120 and a gate wiring portion 48 connected to the other of the two adjacent transistor regions 120 may be provided. In this example, a first gate wiring portion 48-1 connected to the first transistor region 120-1 and a second gate wiring portion 48-2 connected to the second transistor region 120-2 are provided between a first transistor region 120-1 and a second transistor region 120-2, which are two adjacent transistor regions 120.

[0143] Three or more gate wiring portions 48 may be provided between two adjacent transistor regions 120. In this example, the third gate wiring 48-3 is not provided between the first transistor region 120-1 and the second transistor region 120-2, but the third gate wiring 48-3 may also be provided between the first transistor region 120-1 and the second transistor region 120-2.

[0144] Gate trench portions 40 are provided in the plurality of transistor regions 120. The gate trench portions 40 are electrically connected to gate wiring portions 48 provided corresponding to the transistor regions 120. The gate trench portions 40 are provided so as to extend along a predetermined extension direction (in this example, the Y-axis direction).

[0145] The gate trench portion 40 may be connected to only one gate wiring portion 48. As an example, the gate trench portion 40 included in the first transistor region 120-1 is connected only to the first gate wiring portion 48-1 among the plurality of gate wiring portions 48. The gate trench portion 40 included in the first transistor region 120-1 and the gate trench portion 40 included in the second transistor region 120-2 may be separated from each other by the first gate wiring portion 48-1 and the second gate wiring portion 48-2.

[0146] At least a portion of the plurality of gate trenches 40 included in the transistor region 120 may be provided across adjacent transistor regions 120. At least a portion of the plurality of gate trenches 40 may be connected to the plurality of gate wirings 48. Figure 2BIn the example shown, at least a portion of the multiple gate trench portions 40 can extend across the bottom of the first gate wiring 48-1 and / or the second gate wiring 48-2 in the trench extension direction (in this example, the Y-axis direction) and be arranged throughout both the first transistor region 120-1 and the second transistor region 120-2.

[0147] Figure 2C 1 is a diagram showing an example of a bb' cross section of semiconductor device 100. The bb' cross section is a YZ cross section passing through gate pad 50, first resistance measurement pad 141, second resistance measurement pad 142-1, built-in resistor section 61, and first wiring resistor 62-1 in semiconductor device 100.

[0148] Built-in resistor 61 is provided above semiconductor substrate 10 between gate pad 50 and first resistance measurement pad 141. Built-in resistor 61 is provided within interlayer insulating film 38. Built-in resistor 61 may be made of polysilicon and may be part of gate runner 46.

[0149] Built-in resistor 61 is electrically connected to gate pad 50 and first resistance measurement pad 141 via two contact holes 49. Providing resistors between gate pad 50 and gate wirings 48 can suppress oscillation between chips when multiple semiconductor chips are connected in parallel.

[0150] Above semiconductor substrate 10, first wiring resistor 62-1 is provided between first resistance measurement pad 141 and second resistance measurement pad 142-1. Wiring resistor portion 62 may be provided between the two second resistance measurement pads 142. In the depth direction of semiconductor substrate 10, wiring resistor portion 62 may be provided at the same depth as built-in resistor portion 61, or at a different depth. Wiring resistor portion 62 is provided within interlayer insulating film 38. Wiring resistor portion 62 may be made of polysilicon. Wiring resistor portion 62 may be part of gate runner 46.

[0151] The first wiring resistor 62-1 is electrically connected to the first resistance measuring pad 141 and the second resistance measuring pad 142-1 via two contact holes 49. The wiring resistor portion 62 can be electrically connected to the two second resistance measuring pads 142 via the two contact holes 49. The wiring resistor portion 62 can be provided as part of the gate wiring portion 48. By providing the wiring resistor portion 62 in the gate wiring portion 48, oscillation within the semiconductor chip can be suppressed.

[0152] The first emitter electrode portion 152-1 is provided separately from the second resistance measurement pad 142-1. The emitter electrode 52 may be provided separately from each of the plurality of gate wiring portions 48. The first emitter electrode portion 152-1 may be electrically connected to the connection portion 25 within the interlayer insulating film 38.

[0153] Figure 2D 1 is a diagram illustrating an example of a CC′ cross section of the semiconductor device 100 . The CC′ cross section is a YZ cross section passing through the first gate wiring 48 - 1 and the third wiring resistor 62 - 3 in the semiconductor device 100 .

[0154] The first gate wiring 48-1 includes a gate metal layer 47 provided above the semiconductor substrate 10, and a gate runner 46 provided below the gate metal layer 47. The gate runner 46 may be provided inside the interlayer insulating film 38. The first gate wiring 48-1 may be composed of only one of the gate metal layer 47 and the gate runner 46.

[0155] The semiconductor device 100 of this embodiment may include a contact portion 51 provided between the gate metal layer 47 and the gate runner 46 to electrically connect the gate metal layer 47 and the gate runner 46. This can improve the wiring freedom of the gate wiring portion 48.

[0156] The cross-sectional area of ​​the wiring resistor portion 62 perpendicular to the extending direction may be smaller than the cross-sectional area of ​​the gate wiring portion 48 perpendicular to the extending direction. Figure 2D In the YZ cross section shown, the cross-sectional area S of the third wiring resistor 62-3 is 62 than the cross-sectional area S of the first gate wiring 48-1 48 Thus, by making the resistance value of the wiring resistor portion 62 larger than the resistance value of the gate wiring portion 48 , oscillation within a single semiconductor chip can be suppressed.

[0157] Figure 3 This is an enlarged view of the resistance measurement pad in this example. Figure 3 , an example of the upper surface of the second resistance measurement pad 142 is shown, but the upper surface of the first resistance measurement pad 141 may also have the same form. Figure 3 As shown, the two second resistance measuring pads 142 are connected to the wiring resistor portion 62 provided below the second resistance measuring pads 142 via the contact holes 49 .

[0158] The wiring resistor portion 62 may be a portion of the gate flow channel 46. In this example, the wiring resistor portion 62 is a region having a width W and a length L provided between two contact holes 49. By varying the width W and length L of the wiring resistor portion 62, the resistance value of the wiring resistor portion 62 can be adjusted.

[0159] The width W of the wiring resistor portion 62 may be smaller than the width of the gate runner 46 in the gate wiring portion 48 in a direction perpendicular to the extending direction. The width W of the wiring resistor portion 62 may be the same as or smaller than the width of the gate metal layer 47 in the gate wiring portion 48 in a direction perpendicular to the extending direction. The width W of the wiring resistor portion 62 may be smaller than the width of the second resistance measurement pad 142 in a direction perpendicular to the extending direction of the gate wiring portion 48. The width W of the wiring resistor portion 62 may be greater than or equal to 30 μm, or less than or equal to 1400 μm.

[0160] The length L of the wiring resistor portion 62 may be smaller than the width W of the wiring resistor portion 62. The length L of the wiring resistor portion 62 may be smaller than the width of the second resistance measuring pad 142 in the extending direction of the gate wiring portion 48. The length L of the wiring resistor portion 62 may be greater than or equal to 20 μm, or less than or equal to 800 μm.

[0161] An ammeter and a voltmeter (not shown) are provided between the two second resistance measurement pads 142. This allows the resistance value of the wiring resistor portion 62 between the contact holes 49 to be calculated.

[0162] Figure 4A 1 is a diagram showing a modified example of the upper surface of the semiconductor device 100. Figure 2A Different aspects of Figure 4A A modified example of the present invention will be described. It should be noted that, for simplicity, the gate wiring portion 48 is indicated by a solid line, and the wiring resistor portion 62 provided within the gate wiring portion 48 is indicated by a dashed line. However, the positions of these wirings in the figure are merely schematic, so as not to intersect with other wirings. Furthermore, the second resistance measurement pad 142 is omitted from the illustration.

[0163] exist Figure 4A In a modified example, two or more wiring resistor sections 62 among the plurality of wiring resistor sections 62 are connected to one transistor region 120 of the plurality of transistor regions 120. As an example, a first wiring resistor 62-1 and a second wiring resistor 62-2 are connected to the first transistor region 120-1.

[0164] In this example, two first wiring resistors 62-1a and 62-1b are connected to the first transistor region 120-1, two second wiring resistors 62-2a and 62-2b are connected to the second transistor region 120-2, and two third wiring resistors 62-3a and 62-3b are connected to the third transistor region 120-3. This increases the resistance of the gate wiring portion 48 provided for each transistor region 120, thereby suppressing oscillation within a single semiconductor chip.

[0165] exist Figure 4AIn a modified example, one radiating electrode section 152 among the plurality of radiating electrode sections 152 is provided corresponding to two or more wiring resistor sections 62 among the plurality of wiring resistor sections 62. In this example, the first radiating electrode section 152-1 is provided corresponding to the first wiring resistors 62-1a and 62-1b, the second radiating electrode section 152-2 is provided corresponding to the second wiring resistors 62-2a and 62-2b, and the third radiating electrode section 152-3 is provided corresponding to the third wiring resistors 62-3a and 62-3b.

[0166] The plurality of transistor regions 120 may include two or more transistor regions with different areas. In this example, the transistor region includes a first transistor region 120-1, a second transistor region 120-2 with a larger area than the first transistor region 120-1, and a third transistor region 120-3 with a larger area than the second transistor region 120-2.

[0167] The resistance value of each wiring resistor section 62 of the plurality of wiring resistor sections can be changed according to the area of ​​the transistor region 120 connected to each wiring resistor section 62. In this example, the resistance value of the first wiring resistors 62-1a and 62-1b connected to the first transistor region 120-1 is larger than the resistance value of the second wiring resistors 62-2a and 62-2b connected to the second transistor region 120-2, and the resistance value of the second wiring resistors 62-2a and 62-2b connected to the second transistor region 120-2 is larger than the resistance value of the third wiring resistors 62-3a and 62-3b connected to the third transistor region 120-3.

[0168] Generally, since the parasitic capacitance of the transistor region 120 increases as the area of ​​the transistor region 120 increases, oscillation can be suppressed even if the resistance value of the wiring resistor portion 62 in the transistor region 120 is smaller than the resistance values ​​of the wiring resistor portions 62 in other transistor regions 120. When the area of ​​the transistor region 120 is denoted as S and the resistance value of the wiring resistor portion 62 connected to the transistor region 120 is denoted as R, the resistance value R of the wiring resistor portion 62 can be adjusted so that the value S·R becomes a predetermined value.

[0169] Figure 4B 1 is a diagram showing a modified example of the upper surface of the semiconductor device 100. Figure 2A and Figure 4A Different aspects of Figure 4B A modified example of is described below.

[0170] The gate pad 50 can be provided between the plurality of transistor regions 120 in a plan view. In this example, the gate pad 50 is provided between the plurality of transistor regions 120 and near the center of the semiconductor device 100. This improves the structural symmetry of the semiconductor device 100 and makes the transmission of the gate signal of the semiconductor device 100 uniform.

[0171] Built-in resistor section 61 may include a first built-in resistor 61-1 and a second built-in resistor 61-2 different from first built-in resistor 61-1. Built-in resistor section 61 may include three or more built-in resistors. In this example, built-in resistor section 61 includes a first built-in resistor 61-1 connected to gate pad 50, and a second built-in resistor 62-2 connected to gate pad 50 and different from first built-in resistor 61-1. The resistance values ​​of first built-in resistor 61-1 and second built-in resistor 62-2 may be the same or different.

[0172] The plurality of wiring resistor sections 62 may include one or more first wiring resistors 62-1 connected to the first built-in resistor 61-1, and one or more second wiring resistors 62-2 connected to the second built-in resistor 61-2 and different from the first wiring resistor 62-1. In this example, the plurality of wiring resistor sections include a first wiring resistor 62-1 and a second wiring resistor 62-2 connected to the first built-in resistor 61-1, and a third wiring resistor 62-3 and a fourth wiring resistor 62-4 connected to the second built-in resistor 61-2. Three or more wiring resistors may be connected to one built-in resistor. By separately providing a plurality of built-in resistor sections 61 and a wiring resistor section 62, it is possible to independently adjust the resistance value for suppressing oscillations between semiconductor chips and the resistance value for suppressing oscillations within a semiconductor chip.

[0173] The emitter electrode portion 152 can be provided to correspond to different transistor regions 120. The emitter electrode portion 152 can be provided to correspond to different transistor regions 120 connected to a single built-in resistor. In this example, the first emitter electrode portion 152-1 is provided to correspond to the first transistor region 120-1 and the second transistor region 120-2 connected to the first built-in resistor 61-1, and the second emitter electrode portion 152-2 is provided to correspond to the third transistor region 120-3 and the fourth transistor region 120-4 connected to the second built-in resistor 61-2.

[0174] In this example, emitter electrode portion 152 is disposed so as not to overlap gate wiring portion 48 when viewed from above. Alternatively, emitter electrode portion 152 may overlap gate wiring portion 48 when viewed from above. In this case, gate metal layer 47 is not provided in the overlapping portion. In other words, emitter electrode portion 152 is not electrically connected to gate wiring portion 48. Gate runner 46 may be provided in the portion not provided with gate metal layer 47.

[0175] Multiple first resistance measurement pads 141 may be provided. First resistance measurement pads 141 may be provided corresponding to the multiple built-in resistors included in built-in resistor section 61. A single first resistance measurement pad 141 can measure the resistance values ​​of multiple built-in resistors. In this example, first resistance measurement pad 141-1 is provided corresponding to first built-in resistor 61-1, and first resistance measurement pad 141-2 is provided corresponding to second built-in resistor 61-2.

[0176] Figure 5A 1 is a diagram showing a modified example of the upper surface of the semiconductor device 100. Figure 2A 、 Figure 4A and Figure 4B Different aspects of Figure 5A A modified example of is described below.

[0177] On the semiconductor substrate 10, the emitter electrode 52 may be provided in common with the plurality of wiring resistor sections 62. On the semiconductor substrate 10, the emitter electrode 52 may be provided in common with the plurality of gate wiring sections 48, or may be provided in common with the plurality of transistor regions 120. In this example, a single emitter electrode 52 may be provided in common with the plurality of wiring resistor sections 62-1, 62-2, 62-3, 62-4, 62-5, and 62-6.

[0178] exist Figure 5A In the embodiment, Figure 2A The embodiment of the present invention differs in that the emitter electrode sections 152 indicated by the two-dot chain line are connected via a connection region 153. In this embodiment, the first emitter electrode section 152-1 provided corresponding to the first transistor region 120-1 and the fourth transistor region 120-4, the second emitter electrode section 152-2 provided corresponding to the second transistor region 120-2 and the fifth transistor region 120-5, and the third emitter electrode section 152-3 provided corresponding to the third transistor region 120-3 and the sixth transistor region 120-6 are connected via the connection region 153. By connecting the emitter electrode sections 152 via the connection region 153 to form a single emitter electrode 52, the operational stability of the semiconductor device 100 can be improved.

[0179] Figure 5B It shows Figure 5A FIG1 is a diagram showing an example of a dd′ cross section of the semiconductor device 100 in FIG1 . The dd′ cross section is an XZ cross section passing through the gate wiring portion 48 and the emitter electrode 52 .

[0180] Gate wiring portion 48 is provided separately from emitter electrode 52. Gate runner 46 of gate wiring portion 48 is connected to gate metal layer 47 via contact portion 51. Contact portion 51 is not provided below emitter electrode 52. In other words, gate runner 46 is not electrically connected to emitter electrode 52. This allows for electrical insulation between gate wiring portion 48 and emitter electrode 52.

[0181] The gate runner 46 does not need to be provided below the emitter electrode 52. In this example, the gate runner 46 is provided below the emitter electrode 52. Thus, even when the gate metal layer 47 above the semiconductor substrate 10 is separated by the emitter electrode 52, the gate runner 46 can be used to connect the gate wiring portion 48.

[0182] The emitter electrode 52 of the connection region 153 has a predetermined width D in a direction perpendicular to the connection direction of the emitter electrode portion 152. The width D may be greater than the width between the emitter electrode 52 and the gate metal layer 47. The width D may be greater than or equal to 0 μm or less than the width of the emitter electrode portion 152. The width D may be less than or equal to 1000 μm.

[0183] While the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. As can be clearly seen from the description of the claims, embodiments in which such changes or improvements are made are also included in the technical scope of the present invention.

[0184] It should be noted that the order of execution of actions, sequences, steps, stages, and other processes in the apparatus, system, program, or method described in the claims, specifications, and drawings may be implemented in any order, unless otherwise indicated by phrases such as "before," "prior to," and so forth, and unless the output of a previous process is used in a subsequent process. Even if the phrases "first," "next," and so forth are used for convenience in describing the process flow in the claims, specifications, and drawings, this does not necessarily imply that the processes must be performed in that order.

Claims

1. A semiconductor device, characterized in that: have: a plurality of transistor regions; a gate trench portion, which is provided in the plurality of transistor regions; a gate pad disposed above the semiconductor substrate; a plurality of gate wiring portions electrically connected between the gate pad and the gate trench portion and arranged to correspond to any one of the plurality of transistor regions; as well as A plurality of wiring resistor portions are provided to correspond to the plurality of gate wiring portions, respectively.

2. The semiconductor device according to claim 1, wherein The semiconductor device includes a built-in resistor portion having one end electrically connected to the gate pad and the other end electrically connected to the plurality of gate wiring portions.

3. The semiconductor device according to claim 1, wherein The plurality of gate wiring portions include a gate metal layer provided above the semiconductor substrate and a gate runner provided below the gate metal layer.

4. The semiconductor device according to claim 3, wherein The semiconductor device includes a contact portion, which is provided between the gate metal layer and the gate runner and connects the gate metal layer and the gate runner.

5. The semiconductor device according to claim 1, wherein The gate pad is provided on an outer peripheral side of the semiconductor substrate relative to the plurality of transistor regions in a plan view.

6. The semiconductor device according to claim 1, wherein Each of the plurality of wiring resistor sections is connected to each of the plurality of transistor regions.

7. The semiconductor device according to claim 1, wherein Two or more wiring resistor portions among the plurality of wiring resistor portions are connected to one transistor region among the plurality of transistor regions.

8. The semiconductor device according to claim 2, wherein The gate pad is disposed between the plurality of transistor regions in a plan view.

9. The semiconductor device according to claim 8, wherein The built-in resistor portion includes a first built-in resistor and a second built-in resistor different from the first built-in resistor. The plurality of wiring resistor sections include one or more first wiring resistors connected to the first built-in resistor, and one or more second wiring resistors connected to the second built-in resistor and different from the one or more first wiring resistors.

10. The semiconductor device according to claim 1, wherein The plurality of gate wiring portions are provided to be separated from each other in a plan view.

11. The semiconductor device according to claim 1, wherein The plurality of wiring resistor portions are provided in any one of the plurality of gate wiring portions, A cross-sectional area of ​​the wiring resistor portion perpendicular to the extending direction is smaller than a cross-sectional area of ​​the gate wiring portion perpendicular to the extending direction.

12. The semiconductor device according to claim 1, wherein Each of the plurality of wiring resistance sections is arranged closer to the gate pad than each of the plurality of transistor regions.

13. The semiconductor device according to claim 1, wherein The plurality of gate wiring portions are made of polysilicon.

14. The semiconductor device according to claim 2, wherein The built-in resistor portion is made of polysilicon.

15. The semiconductor device according to claim 1, wherein Each of the plurality of wiring resistor portions is formed of a single-layer structure of polysilicon.

16. The semiconductor device according to claim 2, wherein The semiconductor device includes a first resistance measurement pad for measuring the resistance of the built-in resistor portion.

17. The semiconductor device according to claim 1, wherein The semiconductor device includes a second resistance measurement pad for measuring the resistance of the wiring resistance portion.

18. The semiconductor device according to claim 1, wherein The semiconductor device includes an emitter electrode provided above the semiconductor substrate. The emitting electrode has a plurality of emitting electrode portions that are respectively provided separately from each other. The plurality of emitter electrode portions are provided corresponding to respective wiring resistor portions of the plurality of wiring resistor portions.

19. The semiconductor device according to claim 1, wherein The semiconductor device includes an emitter electrode provided above the semiconductor substrate. The emitting electrode has a plurality of emitting electrode portions that are respectively provided separately from each other. One of the plurality of emitter electrode portions is provided corresponding to two or more of the plurality of wiring resistor portions.

20. The semiconductor device according to claim 1, wherein The semiconductor device includes one emitter electrode provided above the semiconductor substrate so as to be shared by the plurality of wiring resistor portions.

21. The semiconductor device according to claim 2, wherein A resistance value obtained by combining the plurality of wiring resistor portions is not less than 10% and not more than 80% of a combined resistance of the built-in resistor portion and the plurality of wiring resistor portions.

22. The semiconductor device according to any one of claims 1 to 21, wherein: The plurality of gate wiring sections include a first gate wiring and a second gate wiring that is longer than the first gate wiring. The resistance value of the wiring resistance portion connected to the first gate wiring is larger than the resistance value of the wiring resistance portion connected to the second gate wiring.

23. The semiconductor device according to any one of claims 1 to 21, wherein: The plurality of transistor regions include a first transistor region and a second transistor region having an area substantially the same as that of the first transistor region. The resistance value of the wiring resistor portion provided in the gate wiring portion connected to the gate conductive portion of the first transistor region is substantially equal to the resistance value of the wiring resistor portion provided in the gate wiring portion connected to the gate conductive portion of the second transistor region.

24. The semiconductor device according to any one of claims 1 to 21, wherein: The plurality of transistor regions include a first transistor region and a second transistor region having an area larger than that of the first transistor region. The resistance value of the wiring resistor portion provided in the gate wiring portion connected to the gate conductive portion of the first transistor region is greater than the resistance value of the wiring resistor portion provided in the gate wiring portion connected to the gate conductive portion of the second transistor region.

25. The semiconductor device according to any one of claims 1 to 21, wherein The resistance value of each of the plurality of wiring resistor sections is 3Ω or more and 30Ω or less.

26. The semiconductor device according to any one of claims 1 to 21, wherein: The resistance value of the gate trench portion is 6 kΩ or less in any region of the plurality of transistor regions.

27. The semiconductor device according to any one of claims 1 to 21, wherein: An error in a value of a CR time constant, which is a product of an electrostatic capacitance of the transistor region and a resistance value of a wiring resistance portion provided corresponding to the transistor region, is within 20% in each of the plurality of transistor regions.

28. The semiconductor device according to any one of claims 1 to 21, wherein The plurality of gate wiring portions are provided between two adjacent transistor regions among the plurality of transistor regions, and include a gate wiring portion connected to one of the two adjacent transistor regions and a gate wiring portion connected to the other of the two adjacent transistor regions.

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