Digital auxiliary adaptive zero-cross detection circuit

Abstract

The invention relates to the technical field of integrated circuits, and discloses a digital auxiliary adaptive zero-cross detection circuit. The circuit comprises a digital auxiliary comparator module, a digital logic module, a detection and discrimination module and a counter module. Wherein the digital auxiliary comparator module compares a switch node voltage signal with a power ground signal to generate a first output signal; the digital logic module processes the first output signal and then generates a zero-cross detection signal to control the power tube to be turned off; the detection and discrimination module receives the second output signal of the digital logic module and the zero-cross detection signal and then generates a digital tuning signal; the counter module receives the digital tuning signal and then generates a six-bit digital signal, a resistor array in the digital auxiliary comparator module is dynamically adjusted, and the overturning offset of a comparator is adaptively adjusted by changing the resistance value of the resistor array, so that the turn-off opportunity of a power tube is changed. According to the invention, the turn-off time of the synchronous rectification power tube can be accurately controlled, the reverse current is reduced, and the dynamic power consumption is reduced.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a zero-crossing detection circuit technology for a DC-DC switching power converter. Background Art

[0002] With the continuous advancement of electronic technology, DC-DC converters have become widely used in various fields, including communications, computers, and consumer electronics. As a common DC-DC converter topology, the buck converter is widely favored for its simple structure and high efficiency. However, in practical applications, buck converters also face some technical challenges that need to be addressed.

[0003] First, buck converters typically use DCM (Discontinuous Conduction Mode) control to reduce switching losses when operating at light loads. However, in DCM mode, the inductor current drops to zero during each switching cycle, accompanied by ringing. If the synchronous rectifier's turn-off timing is improperly controlled, it may remain on during current reversal, causing current to flow from the output back to the input, resulting in power loss.

[0004] Secondly, ideally, the synchronous rectifier should shut down immediately when the inductor current crosses zero to minimize conduction losses. However, factors such as device characteristics, circuit board layout, and control signal delays in actual circuits make it difficult to accurately predict and control the zero-crossing timing. Traditional zero-crossing detection circuits rely solely on comparators with fixed thresholds, making it difficult to adapt to the optimal shutdown timing under different operating conditions.

[0005] Third, the magnitude of the inductor current ripple is closely related to the load state. When the load changes suddenly, large current ripple can cause a brief reverse current, which in turn causes additional power transistor losses. Achieving smooth mode transitions and suppressing reverse current spikes is key to improving system robustness.

[0006] Therefore, it is necessary to design a zero-crossing detection circuit that can be adaptively adjusted to achieve efficient and accurate synchronous rectifier control, suppress current backflow, and improve the operating efficiency of the buck converter in DCM mode. Summary of the Invention

[0007] The purpose of this application is to provide a digitally assisted adaptive zero-crossing detection circuit to solve the problems raised in the above background technology.

[0008] The present application discloses a digitally assisted adaptive zero-crossing detection circuit, comprising:

[0009] a digital auxiliary comparator module, comprising a resistor array, configured to sample and compare the switch node voltage signal Vsw with the power ground signal pvss when the power transistor in the power stage of the buck converter is turned on, and generate a first output signal Vcp;

[0010] a digital logic module, electrically connected to the digital auxiliary comparator module, configured to receive the first output signal Vcp and the upper power tube control signal HS and the lower power tube control signal LS in the buck converter power stage, and generate a dynamic bias signal Vdb, a second output signal Vcmp, and a zero-crossing detection signal ZCD after logic processing;

[0011] a detection and discrimination module, electrically connected to the digital logic module, configured to receive the second output signal Vcmp and the zero-crossing detection signal ZCD, and generate a digital tuning signal UP / DN after logical processing;

[0012] A counter module is electrically connected to the detection and discrimination module, and is used to receive the digital tuning signal UP / DN and generate a six-bit digital control signal Q<5:0> after counting. The six-bit digital control signal Q<5:0> is connected to the resistor array of the digital auxiliary comparator module. By dynamically changing the resistance value of the resistor array, adaptive adjustment of the flip offset of the digital auxiliary comparator module is achieved.

[0013] In a preferred example, the digital auxiliary comparator module includes: a power supply terminal, a reference ground terminal, a first input terminal, a second input terminal, a third input terminal, a six-bit digital input terminal and an output signal terminal, the power supply terminal receives a power supply potential VDD, the reference ground terminal receives a reference ground potential, the first input terminal receives a switch node voltage signal Vsw, the second input terminal receives a power ground signal pvss, the third input terminal receives a dynamic bias signal Vdb, the six-bit digital input terminals sequentially receive a six-bit digital control signal Q<5:0> from the counter module, and the output signal terminal outputs a first output signal Vcp.

[0014] In a preferred embodiment, the resistor array includes a first group of resistors R5 to R0 and a second group of resistors R5b to R0b; the six-bit digital control signal Q<5:0> generates a corresponding inverted signal Qb<5:0> through an inverter; wherein Q<5:0> controls the first group of resistors R5 to R0, and Qb<5:0> controls the second group of resistors R5b to R0b; when Q<5:0> and Qb<5:0> are high, the corresponding resistors are short-circuited, and when Q<5:0> and Qb<5:0> are low, the corresponding resistors are connected to the circuit; when the dynamic bias signal Vdb is high, the digital auxiliary comparator module compares the magnitude of the input switch node voltage signal Vsw with the power ground signal pvss, and outputs a first output signal Vcp when the switch node voltage signal Vsw is greater than the power ground signal pvss.

[0015] In a preferred example, the digital logic module includes: a power supply terminal, a reference ground terminal, an enable terminal, a first input terminal, a second input terminal, a third input terminal, a first output terminal, a second output terminal and a third output terminal, the power supply terminal receives a power supply potential VDD, the reference ground terminal receives a reference ground potential, the enable terminal receives an enable signal, the first input terminal receives a first output signal Vcp from the digital auxiliary comparator module, the second input terminal receives an upper power tube control signal HS in a buck converter power stage, the third input terminal receives a lower power tube control signal LS in a buck converter power stage, the first output terminal outputs a dynamic bias signal Vdb, the second output terminal outputs a second output signal Vcmp, and the third output terminal outputs a zero-crossing detection signal ZCD.

[0016] In a preferred example, when the received first output signal Vcp flips to a high level, the second output signal Vcmp and the zero-crossing detection signal ZCD output by the digital logic module flip to a high level successively; when the first output signal Vcp flips to a low level, the second output signal Vcmp flips to a low level; when the received upper power tube control signal HS flips to a high level, the zero-crossing detection signal ZCD flips to a low level; when the received lower power tube control signal LS flips to a high level, the dynamic bias signal Vdb flips to a high level, and the falling edge of the lower power tube control signal LS triggers the dynamic bias signal Vdb to flip to a low level after delay processing.

[0017] In a preferred example, the detection and discrimination module includes: a power supply terminal, a reference ground terminal, a first input terminal, a second input terminal and an output signal terminal, the power supply terminal receives a power supply potential VDD, the reference ground terminal receives a reference ground potential, the first input terminal receives a second output signal Vcmp from the digital logic module, the second input terminal receives a zero-crossing detection signal ZCD from the digital logic module, and the output signal terminal outputs the digital tuning signal UP / DN.

[0018] In a preferred example, the detection and discrimination module generates a clock signal CLKD of the D flip-flop after delay processing of the zero-crossing detection signal ZCD; when the rising edge of the clock signal CLKD arrives, the level state of the second output signal Vcmp is sampled; when the second output signal Vcmp obtained by sampling is a high level, it indicates that the lower power tube is delayed in shutting down, and the detection and discrimination module outputs a digital tuning signal UP / DN of a low level; when the second output signal Vcmp obtained by sampling is a low level, it indicates that the lower power tube is shut down in advance, and the detection and discrimination module outputs a digital tuning signal UP / DN of a high level.

[0019] In a preferred example, the counter module includes: a power supply terminal, a reference ground terminal, a first input terminal, a second input terminal, a third input terminal and a six-bit digital signal output terminal, the power supply terminal receives the power supply potential VDD, the reference ground terminal receives the reference ground potential, the first input terminal receives the digital tuning signal UP / DN from the detection and judgment module, the second input terminal receives the set signal SET, the third input terminal receives the clock signal CLK, and the six-bit digital signal output terminal outputs the six-bit digital control signal Q<5:0>.

[0020] In a preferred example, when the set signal SET is at a low level, the six-bit digital signal output end of the counter module outputs low level, high level, high level, high level, high level, and high level in sequence from high to low; when the digital tuning signal UP / DN is at a low level, when the rising edge of the clock signal CLK arrives, the decimal value of the six-bit digital control signal Q<5:0> output by the counter module is reduced by one; when the digital tuning signal UP / DN is at a high level, when the rising edge of the clock signal CLK arrives, the decimal value of the six-bit digital control signal Q<5:0> output by the counter module is increased by one.

[0021] The digitally assisted adaptive zero-crossing detection circuit provided in this application achieves the following technical effects through the coordinated cooperation of a digitally assisted comparator, a digital logic module, a detection and discrimination module, and a counter module:

[0022] First, this circuit's quiescent current can be precisely controlled at the nanoampere level, significantly reducing power consumption compared to traditional solutions. This makes it particularly suitable for ultra-low-power applications with stringent power requirements, such as portable electronic devices and IoT terminals. This low power consumption is due to the circuit's streamlined design, requiring only a comparator and a small amount of basic digital logic circuitry to implement complex adaptive loop control.

[0023] Secondly, the digital auxiliary comparator of this application is multifunctional. Not only can it accurately detect the inductor current zero crossing point, but its output signal also provides key information for the detection and discrimination module, accurately determining the early or late power tube shutdown moment. This integrated design reduces the need for additional comparators while improving detection accuracy and system consistency.

[0024] Third, during the initial startup phase of the circuit, the digital auxiliary comparator can directly detect and quickly shut down the power tube, significantly reducing initial errors. This rapid convergence avoids the severe deviation in initial shutdown timing that can occur in traditional solutions, ensuring rapid system stability.

[0025] Furthermore, the six-bit digitally controlled adaptive feedback mechanism employed in this application enables the digital auxiliary comparator to gradually approach the optimal turn-off moment of the lower power tube through up to 64 levels of subtle adjustments under the regulation of the feedback loop. This refined control enables precise optimization of the circuit's operating state, effectively improving the conversion efficiency of the DC-DC converter in DCM mode while reducing ringing at the switch node.

[0026] The above technical effects are achieved thanks to the unique digital-analog hybrid architecture and adaptive control method of this application, which provides an innovative solution for zero-crossing detection in DC-DC converters while taking into account both accuracy and power consumption.

[0027] The specification of this application records a large number of technical features, which are distributed in various technical solutions. If all possible combinations of technical features of this application (i.e., technical solutions) are to be listed, the specification will be too lengthy. In order to avoid this problem, the various technical features disclosed in the above-mentioned invention content of this application, the various technical features disclosed in the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions are all deemed to have been recorded in this specification), unless such a combination of technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed. Features C and D are equivalent technical means that play the same role. Technically, only one of them can be used, and it is impossible to use them at the same time. Feature E can be technically combined with feature C. Then, the solution of A+B+C+D should not be considered as having been recorded because it is technically infeasible, while the solution of A+B+C+E should be considered as having been recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 1 is a schematic diagram of the overall architecture of a digitally assisted adaptive zero-crossing detection circuit according to an embodiment of the present application;

[0029] Figure 2 1 is a circuit structure diagram of a digitally assisted comparator module of a digitally assisted adaptive zero-crossing detection circuit according to an embodiment of the present application;

[0030] Figure 3 1 is a circuit structure diagram of a digital logic module of a digitally assisted adaptive zero-crossing detection circuit according to an embodiment of the present application;

[0031] Figure 4 1 is a schematic diagram of operating waveforms of a digital logic module of a digitally assisted adaptive zero-crossing detection circuit according to an embodiment of the present application;

[0032] Figure 5 1 is a schematic diagram of the circuit structure of a detection and discrimination module of a digitally assisted adaptive zero-crossing detection circuit according to an embodiment of the present application;

[0033] Figure 6 1 is a schematic diagram of operating waveforms of a detection and discrimination module of a digitally assisted adaptive zero-crossing detection circuit according to an embodiment of the present application;

[0034] Figure 7 1 is a circuit structure diagram of a counter module of a digitally assisted adaptive zero-crossing detection circuit according to an embodiment of the present application. DETAILED DESCRIPTION

[0035] In the following description, many technical details are provided to help readers better understand this application. However, those skilled in the art will understand that even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in this application can be implemented.

[0036] Description of some concepts:

[0037] Buck converter: A switching power supply circuit that converts an input voltage into a lower output voltage. In this application, it is used as the application carrier of the zero-crossing detection circuit and is also referred to as a "step-down converter" in this article.

[0038] DCM (Discontinuous Conduction Mode) is a step-down converter operating mode in which the inductor current drops to zero and remains at zero for a period of time during each switching cycle. This requires precise control of the synchronous rectifier turn-off timing to prevent current backflow.

[0039] Switching node voltage signal (Vsw): The voltage signal sampled at the switching node of the buck converter.

[0040] Power ground signal (pvss): Power ground potential signal used as a comparison reference.

[0041] First output signal (Vcp): The signal output by the digital auxiliary comparator module after comparison, which serves as the basis for subsequent digital logic processing.

[0042] Dynamic bias signal (Vdb): A signal generated by the digital logic block that dynamically controls the bias of the digital auxiliary comparator block.

[0043] The second output signal (Vcmp) is a signal generated by the digital logic module. It presents a double pulse feature when the lower power tube is turned off early and a single pulse feature when it is turned off with delay. It is used to determine the early or late moment of the synchronous rectifier tube shutdown.

[0044] Zero Crossing Detection Signal (ZCD): A signal output by the digital logic module that detects the moment when the current crosses zero and is used to control the shutdown of the lower power tube.

[0045] Digital tuning signal (UP / DN): A signal generated by the detection and discrimination module based on the sampling result, used to indicate the counting operation of the counter module.

[0046] Six-bit digital control signal (Q<5:0>): A digital signal generated by the counter module that dynamically adjusts the resistance of the resistor array within the digital auxiliary comparator module to achieve adaptive adjustment of the flip offset.

[0047] Resistor array: A resistor network within the digital auxiliary comparator module. It consists of two resistor groups, R5 to R0 and R5b to R0b. Its access status is dynamically controlled by the six-bit digital control signal Q<5:0> and its inverted signal Qb<5:0>, enabling precise adjustment of the comparator flip offset.

[0048] Upper power tube control signal (HS) and lower power tube control signal (LS): control signals that respectively control the upper power tube and lower power tube in the buck converter to turn on or off.

[0049] The following is a summary of some of the innovative features of this application:

[0050] In summary, this application proposes a hybrid digital-analog dynamic adaptive closed-loop control scheme to address the current backflow problem caused by control errors at the turn-off time of the synchronous rectifier in the DCM mode of a buck switching power supply. In the range where the inductor current is close to zero, high-speed real-time sampling and comparison of the switch node voltage signal are used, and logical combination and discrimination are performed in combination with the control signal to form an iterative optimization closed-loop, achieving dynamic adjustment of the comparison offset threshold, thereby accurately controlling the turn-off time of the synchronous rectifier. Its technical contributions are mainly reflected in:

[0051] First, to address the large turn-off timing errors and low conversion efficiency caused by traditional fixed-threshold comparison schemes, this application adopts a hybrid digital-analog dynamic closed-loop control architecture. By adjusting the analog comparator offset via a programmable digital resistor array, this architecture combines digital feedback with analog comparison, improving the adaptability of turn-off control.

[0052] Furthermore, the present application utilizes the pulse characteristics of the second output signal, Vcmp, to determine the timing of shutdown based on the LC resonance characteristics of the switch node voltage waveform. Specifically, when the lower power tube is shut down prematurely, the switch node voltage is pulled down to a negative value due to the conduction voltage drop of the body diode, and then rebounds due to the LC resonance, causing Vcmp to exhibit a double pulse characteristic. When the lower power tube is shut down later, the current has passed zero, and the switch node voltage remains positive, causing Vcmp to exhibit a single pulse characteristic. Based on this principle, a feedback path of sampling and comparison, feature extraction, logical judgment, and digital tuning is constructed.

[0053] Furthermore, in the digital feedback path, this application uses a six-bit programmable counter, coupled with a latch trigger circuit for the digital tuning signals UP / DN, to convert the lead / lag information at the turn-off moment into addition / subtraction operations on the resistor array. This iterative adjustment ensures the continuity of the comparison threshold adjustment and mitigates the effects of analog circuit instabilities such as drift and offset.

[0054] Furthermore, this application combines digital assistance, adaptive closed-loop control, and mixed-signal processing to improve the accuracy and stability of control at the shutdown moment. Dynamic closed-loop control eliminates the impact of device deviations, achieving superior control results.

[0055] Furthermore, the present application introduces dynamic bias control technology, using the dynamic bias signal Vdb to control the enabling and disabling of the circuit module. The digital auxiliary comparator is enabled only for a short period of time in a cycle, greatly reducing the overall static power consumption of the circuit.

[0056] This application integrates digital control with analog comparison to upgrade current zero-crossing detection to a closed-loop system with signal sampling, feature extraction-logic discrimination, and parameter tuning. Simultaneously, through the design and matching of digital-analog circuits, precise control of the shutdown moment is achieved while maintaining the quiescent current of the control circuit at the nanoampere level. This hybrid digital-analog technical solution offers improvements over existing technologies in terms of accuracy and power consumption, providing a new approach to zero-crossing detection control in switching power supplies.

[0057] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0058] In the specification of this application, in order to make the article more clear and concise, some technical features are represented by English letter codes. It should be clear that the technical features represented by letter codes in this application are exactly the same as the technical features represented by the corresponding Chinese names plus letter codes. For example, "Vsw" and "switch node voltage signal Vsw" refer to the same technical feature, "ZCD" and "zero crossing detection signal ZCD" refer to the same technical feature, and other similar technical features represented by English letter codes are equivalent to the technical features represented by their corresponding Chinese names plus letter codes. When reading and understanding this application, please treat the technical features represented by letter codes only as the same as the technical features represented by their corresponding Chinese names plus letter codes. The technical features with English letter codes involved include but are not limited to:

[0059] Switch node voltage signal Vsw;

[0060] Power ground signal pvss;

[0061] A first output signal Vcp;

[0062] Dynamic bias signal Vdb;

[0063] A second output signal Vcmp;

[0064] Zero crossing detection signal ZCD;

[0065] Digital tuning signal UP / DN;

[0066] Six-bit digital control signal Q<5:0>;

[0067] Six-bit digital control signal inversion signal Qb<5:0>;

[0068] Upper power tube control signal HS;

[0069] Lower power tube control signal LS;

[0070] Clock signal CLK;

[0071] The clock signal CLKD of the D flip-flop;

[0072] Set signal SET;

[0073] Power supply potential VDD;

[0074] Inductor current IL;

[0075] Input voltage VIN;

[0076] Pre-amplifier common-mode output Vp;

[0077] Pre-amplifier inverting output Vn;

[0078] Current source Ip of the pre-amplifier;

[0079] Buck converter;

[0080] Discontinuous conduction mode DCM.

[0081] Furthermore, the same reference numerals are used throughout the drawings to denote the same elements or structures, wherein:

[0082] 100: Zero-crossing detection circuit

[0083] 110: Digital auxiliary comparator module

[0084] 120: Digital logic module

[0085] 130: Detection and discrimination module

[0086] 140: Counter module.

[0087] The first embodiment of the present application relates to a digitally assisted adaptive zero-crossing detection circuit 100, such as Figure 1 As shown, including:

[0088] The digital auxiliary comparator module 110 includes a resistor array and is configured to sample and compare the switch node voltage signal Vsw with the power ground signal pvss when the power transistor in the power stage of the buck converter is turned on, and generate a first output signal Vcp;

[0089] a digital logic module 120 electrically connected to the digital auxiliary comparator module 110, configured to receive the first output signal Vcp and the upper power tube control signal HS and the lower power tube control signal LS in the buck converter power stage, and generate a dynamic bias signal Vdb, a second output signal Vcmp, and a zero-crossing detection signal ZCD after logic processing;

[0090] a detection and discrimination module 130 , electrically connected to the digital logic module 120 , configured to receive the second output signal Vcmp and the zero-crossing detection signal ZCD, and generate a digital tuning signal UP / DN after logical processing;

[0091] The counter module 140 is electrically connected to the detection and discrimination module 130 and is used to receive the digital tuning signal UP / DN and generate a six-bit digital control signal Q<5:0> after counting.

[0092] The six-bit digital control signal Q<5:0> is connected to the resistor array of the digital auxiliary comparator module 110 , and adaptive adjustment of the flip offset of the digital auxiliary comparator module 110 is achieved by dynamically changing the resistance value of the resistor array.

[0093] Optionally, the digital auxiliary comparator module 110 includes: a power supply terminal, a reference ground terminal, a first input terminal, a second input terminal, a third input terminal, a six-bit digital input terminal and an output signal terminal, the power supply terminal receives the power supply potential VDD, the reference ground terminal receives the reference ground potential, the first input terminal receives the switching node voltage signal Vsw, the second input terminal receives the power ground signal pvss, the third input terminal receives the dynamic bias signal Vdb, the six-bit digital input terminals sequentially receive the six-bit digital control signal Q<5:0> from the counter module 140, and the output signal terminal outputs the first output signal Vcp.

[0094] Furthermore, the resistor array includes a first group of resistors R5 to R0 and a second group of resistors R5b to R0b; the six-bit digital control signal Q<5:0> generates a corresponding inverted signal Qb<5:0> through an inverter; wherein Q<5:0> controls the first group of resistors R5 to R0, and Qb<5:0> controls the second group of resistors R5b to R0b; when Q<5:0> and Qb<5:0> are high, the corresponding resistors are short-circuited, and when Q<5:0> and Qb<5:0> are low, the corresponding resistors are connected to the circuit; when the dynamic bias signal Vdb is high, the digital auxiliary comparator module 110 compares the magnitude relationship between the input switch node voltage signal Vsw and the power ground signal pvss, and outputs a first output signal Vcp when the switch node voltage signal Vsw is greater than the power ground signal pvss.

[0095] Optionally, the digital logic module 120 includes: a power supply terminal, a reference ground terminal, an enable terminal, a first input terminal, a second input terminal, a third input terminal, a first output terminal, a second output terminal and a third output terminal, the power supply terminal receives a power supply potential VDD, the reference ground terminal receives a reference ground potential, the enable terminal receives an enable signal, the first input terminal receives a first output signal Vcp from the digital auxiliary comparator module 110, the second input terminal receives an upper power tube control signal HS in the buck converter power stage, the third input terminal receives a lower power tube control signal LS in the buck converter power stage, the first output terminal outputs a dynamic bias signal Vdb, the second output terminal outputs a second output signal Vcmp, and the third output terminal outputs a zero-crossing detection signal ZCD.

[0096] Furthermore, when the received first output signal Vcp flips to a high level, the second output signal Vcmp and the zero-crossing detection signal ZCD output by the digital logic module 120 flip to a high level successively; when the first output signal Vcp flips to a low level, the second output signal Vcmp flips to a low level; when the received upper power tube control signal HS flips to a high level, the zero-crossing detection signal ZCD flips to a low level; when the received lower power tube control signal LS flips to a high level, the dynamic bias signal Vdb flips to a high level, and the falling edge of the lower power tube control signal LS triggers the dynamic bias signal Vdb to flip to a low level after delay processing.

[0097] Optionally, the detection and judgment module 130 includes: a power supply end, a reference ground end, a first input end, a second input end and an output signal end, the power supply end receives the power supply potential VDD, the reference ground end receives the reference ground potential, the first input end receives the second output signal Vcmp from the digital logic module 120, the second input end receives the zero-crossing detection signal ZCD from the digital logic module 120, and the output signal end outputs the digital tuning signal UP / DN.

[0098] Furthermore, the detection and judgment module 130 generates a clock signal CLKD for the D flip-flop after delay processing of the zero-crossing detection signal ZCD; when the rising edge of the clock signal CLKD arrives, the level state of the second output signal Vcmp is sampled; when the second output signal Vcmp obtained by sampling is a high level, it indicates that the lower power tube is delayed in shutting down, and the detection and judgment module 130 outputs a digital tuning signal UP / DN as a low level; when the second output signal Vcmp obtained by sampling is a low level, it indicates that the lower power tube is shut down in advance, and the detection and judgment module 130 outputs a digital tuning signal UP / DN as a high level.

[0099] Optionally, the counter module 140 includes: a power supply terminal, a reference ground terminal, a first input terminal, a second input terminal, a third input terminal and a six-bit digital signal output terminal, the power supply terminal receives the power supply potential VDD, the reference ground terminal receives the reference ground potential, the first input terminal receives the digital tuning signal UP / DN from the detection and judgment module 130, the second input terminal receives the set signal SET, the third input terminal receives the clock signal CLK, and the six-bit digital signal output terminal outputs the six-bit digital control signal Q<5:0>.

[0100] Furthermore, when the set signal SET is at a low level, the six-bit digital signal output end of the counter module 140 outputs low level, high level, high level, high level, high level, and high level in sequence from high to low; when the digital tuning signal UP / DN is at a low level, when the rising edge of the clock signal CLK arrives, the decimal value of the six-bit digital control signal Q<5:0> output by the counter module 140 is reduced by one; when the digital tuning signal UP / DN is at a high level, when the rising edge of the clock signal CLK arrives, the decimal value of the six-bit digital control signal Q<5:0> output by the counter module 140 is increased by one.

[0101] In order to make the technical solution of the present invention clearer, Figures 1 to 7 The preferred embodiments of the present invention are described in detail, but it should be understood that the described embodiments are only illustrative and not restrictive.

[0102] Reference Figure 1 The digitally assisted adaptive zero-crossing detection circuit 100 of the present application includes four main functional modules: a digitally assisted comparator module 110 , a digital logic module 120 , a detection and discrimination module 130 , and a counter module 140 .

[0103] The digital auxiliary comparator module 110 receives the switch node voltage signal Vsw and the power ground signal pvss as inputs. The module outputs a first output signal Vcp to the digital logic module 120 . It also receives the six-bit digital control signal Q<5:0> from the counter module 140 and the dynamic bias signal Vdb from the digital logic module 120 .

[0104] Digital logic module 120 receives the first output signal Vcp from digital auxiliary comparator module 110, as well as the upper power transistor control signal HS and the lower power transistor control signal LS in the buck converter power stage. This module generates three output signals: a dynamic bias signal Vdb, which is fed back to digital auxiliary comparator module 110; a second output signal Vcmp, which is transmitted to detection and discrimination module 130; and a zero-crossing detection signal ZCD.

[0105] The detection and discrimination module 130 receives the second output signal Vcmp and the zero-crossing detection signal ZCD output by the digital logic module 120 , generates a digital tuning signal UP / DN after logic discrimination, and transmits the digital tuning signal UP / DN to the counter module 140 .

[0106] Counter module 140 receives the digital tuning signals UP / DN from detection and discrimination module 130, as well as the externally input set signal SET and clock signal CLK. Based on the changes in the input signals, this module generates a six-bit digital control signal Q<5:0>, which is used to dynamically adjust the resistor array within digital auxiliary comparator module 110, achieving adaptive optimization of the comparison threshold.

[0107] Figure 1 The simplified structure of the buck converter power stage is schematically shown, including the input voltage VIN, upper and lower power transistors, output inductor L0, output capacitor C0, and load. The zero-crossing detection circuit of this application is primarily used to detect in real time whether the current flowing through the output inductor L0 crosses zero, and accordingly shut down the synchronous rectifier in a timely manner to prevent current backflow.

[0108] Reference Figure 2 The digital auxiliary comparator module 110 is mainly composed of a pre-amplifier, a dynamic bias adjustment circuit, a comparator and a resistor array.

[0109] The preamplifier includes two differential input terminals and two differential output terminals. Its positive phase input terminal receives the switch node voltage signal Vsw, its negative phase input terminal receives the power ground signal pvss, its non-phase output terminal outputs a signal Vp, and its negative phase output terminal outputs a signal Vn.

[0110] The dynamic bias adjustment circuit provides dynamic bias for the preamplifier and includes three PMOS transistors, MP0, MP1, and MP2. The sources of MP0 and MP1 are connected to the power supply voltage VDD, and their drains are connected to the preamplifier's non-inverting output Vp and inverting output Vn, respectively. The source of MP2 is connected to the power supply voltage VDD, and its gate and drain receive the dynamic bias signal Vdb and the preamplifier's current source Ip, respectively. When the dynamic bias signal Vdb is high, the preamplifier's current source Ip is activated, turning on MP0 and MP1 and establishing a voltage difference between the preamplifier's non-inverting output Vp and inverting output Vn.

[0111] The positive and negative input terminals of the comparator are connected to the preamplifier's in-phase output Vp and inverting output Vn, respectively. When the in-phase output Vp is greater than the inverting output Vn, the comparator outputs a high level to obtain the first output signal Vcp; otherwise, it outputs a low level.

[0112] The resistor array is divided into two groups: a first group of resistors R5 to R0 and a second group of resistors R5b to R0b. R5 to R0 are connected sequentially between the preamplifier's non-inverting output terminal Vp and the power ground, and R5b to R0b are connected sequentially between the preamplifier's inverting output terminal Vn and the power ground. The six-bit digital control signal Q<5:0> and its inverted signal Qb<5:0> output by the counter module 140 respectively control the access status of the first and second groups of resistors: a high-level signal in Q<5:0> shorts the corresponding resistor, while a low-level signal connects the corresponding resistor to the circuit; the control effect of Qb<5:0> is exactly the opposite of that of Q<5:0>. By adjusting the access combination of the resistors in the resistor array, a certain initial voltage difference can be formed between the preamplifier's output terminals Vp and Vn, thereby affecting the comparator's input voltage, ultimately achieving dynamic optimization of the zero-crossing detection threshold.

[0113] Reference Figure 3 , the digital logic module 120 includes a first logic unit, a second logic unit and a delay unit.

[0114] The first logic unit receives the first output signal Vcp from the digital auxiliary comparator module 110 and the upper power transistor control signal HS in the buck converter power stage. When the upper power transistor control signal HS is low, the first logic unit outputs a zero-crossing detection signal ZCD controlled by the first output signal Vcp. When the upper power transistor control signal HS is high, the zero-crossing detection signal ZCD is forced low, indicating that zero-crossing detection is not required during the upper power transistor conduction period.

[0115] The second logic unit receives the first output signal Vcp and the dynamic bias signal Vdb. When both are high, the second logic unit outputs a high-level second output signal Vcmp; otherwise, it outputs a low-level signal. This signal will be used for feature sampling in the subsequent detection and discrimination module.

[0116] The delay unit receives the lower power tube control signal LS from the buck converter's power stage. When the lower power tube control signal LS is high, the delay unit outputs a high dynamic bias signal Vdb, activating the sampling and comparison functions of the digital auxiliary comparator module. Upon the falling edge of the lower power tube control signal LS, the delay unit transitions the dynamic bias signal Vdb to a low level after a preset delay time. This delay mechanism ensures that the digital auxiliary comparator module 110 has sufficient time to complete sampling and comparison of the switch node voltage, preventing transient interference from the power tube switching state from affecting detection accuracy.

[0117] Reference Figure 4This figure shows the main operating waveforms of digital logic module 120. From top to bottom, the figure shows the changes of the upper power tube control signal HS, the lower power tube control signal LS, the first output signal Vcp, the second output signal Vcmp, the zero-crossing detection signal ZCD, and the dynamic bias signal Vdb over time t. The period T marked in the figure represents a complete cycle of these signal changes.

[0118] Regarding the dynamic bias signal Vdb, when the lower power tube control signal LS turns to a high level, Vdb turns to a high level accordingly; when LS turns to a low level, Vdb turns to a low level after a delay time.

[0119] Regarding the processing of the first output signal Vcp, when Vcp flips to a high level, if the dynamic bias signal Vdb is at a high level (i.e., during the conduction period of the lower power transistor), the second output signal Vcmp and the zero-crossing detection signal ZCD successively flip to a high level. When Vcp flips to a low level, Vcmp also flips to a low level.

[0120] In addition to being controlled by Vcp, the zero-crossing detection signal ZCD is also affected by the upper power tube control signal HS: when HS is low, ZCD is controlled by Vcp; when HS flips to a high level, ZCD will be forced to be pulled low, indicating that zero-crossing detection is not performed during the conduction period of the upper power tube.

[0121] The waveforms clearly show the timing relationships and logical dependencies between the signals. The changes in these signals coordinate with each other to achieve accurate detection of the zero-crossing point of the inductor current.

[0122] Reference Figure 5 The detection and discrimination module 130 is mainly composed of a D flip-flop and a delay unit.

[0123] The data input terminal D of the D flip-flop is connected to the second output signal Vcmp output by the digital logic module 120, and the clock input terminal CLK is connected to the signal CLKD processed by the delay unit. The zero-crossing detection signal ZCD generates the clock signal CLKD after passing through the delay unit.

[0124] When the clock signal CLKD rises, the D flip-flop samples the instantaneous level of the second output signal Vcmp. When the second output signal Vcmp is high during sampling, the output digital tuning signal UP / DN is low. When the second output signal Vcmp is low during sampling, the output digital tuning signal UP / DN is high.

[0125] The delay unit delays the zero-crossing detection signal ZCD to ensure signal stability when sampling the second output signal Vcmp. The digital tuning signal UP / DN output by this module is used to indicate the offset state of the actual turn-off moment of the power tube relative to the ideal zero-crossing point.

[0126] Reference Figure 6 This figure illustrates the waveform changes of the detection and discrimination module 130 in two operating states. The figure shows the delayed and early shutdown of the lower power transistor, respectively. In each case, the timing relationship between the switch node voltage signal Vsw, the inductor current IL, the second output signal Vcmp, the zero-crossing detection signal ZCD, the clock signal CLKD, and the digital tuning signal UP / DN is shown.

[0127] The zero-crossing detection signal ZCD generates a clock signal CLKD of the D flip-flop after a delay. When the rising edge of the clock signal CLKD arrives, the D flip-flop samples the level state of the second output signal Vcmp.

[0128] When the lower power transistor is turned off with a delayed shutdown, the current has already passed zero, the switch node voltage Vsw remains at a high level, and the second output signal Vcmp exhibits a single pulse characteristic. At this point, the D-type flip-flop samples the high level of Vcmp on the rising edge of the clock signal CLKD and outputs a low-level digital tuning signal UP / DN.

[0129] When the lower power transistor is turned off prematurely, the body diode conducts, causing the switch node voltage Vsw to drop to a negative value and then rebound, resulting in a double pulse characteristic in the second output signal Vcmp. At this time, the D-type flip-flop samples the low level of Vcmp on the rising edge of the clock signal CLKD and outputs a high-level digital tuning signal UP / DN.

[0130] In this way, the detection and judgment module 130 can determine the offset of the actual shutdown moment of the lower power tube relative to the ideal zero-crossing point, and pass this information to the counter module 140 through the level state of the digital tuning signal UP / DN for subsequent compensation adjustment.

[0131] Reference Figure 7 The counter module 140 is mainly composed of a six-bit binary up / down counter and a six-bit digital signal output terminal.

[0132] Counter module 140 receives three input signals: a set signal SET, a digital tuning signal UP / DN, and a clock signal CLK. Set signal SET is active low. When the set signal is low, the six digital signal output terminals of counter module 140 output the following sequence: low, high, high, high, high, high, high, from high to low.

[0133] Under normal operating conditions, when the digital tuning signal UP / DN from the detection and discrimination module 130 is at a low level, the decimal representation of the six-bit digital control signal Q<5:0> output by the counter module 140 is decremented by one at the rising edge of the clock signal CLK. When the digital tuning signal UP / DN is at a high level, the decimal representation of the six-bit digital control signal Q<5:0> output by the counter module 140 is incremented by one at the rising edge of the clock signal CLK.

[0134] Through this increasing or decreasing counting method, the counter module 140 can dynamically adjust the output six-bit digital control signal Q<5:0> according to the indication of the digital tuning signal UP / DN, thereby controlling the access state of the resistor array in the digital auxiliary comparator module 110 and realizing adaptive optimization of the comparison threshold.

[0135] Working principle:

[0136] The working principle of the digitally assisted adaptive zero-crossing detection circuit of this embodiment is described in detail below.

[0137] This application addresses the efficiency and electromagnetic compatibility issues of step-down DC-DC converters operating in DCM mode and proposes a hybrid digital-analog adaptive control scheme. This scheme achieves precise detection of the inductor current zero-crossing point and optimal shutdown control of the synchronous rectifier by dynamically adjusting the comparator's flip threshold.

[0138] The workflow of the entire system can be divided into the following key steps:

[0139] First, during the conduction period of the lower power transistor, the digital auxiliary comparator module 110 monitors the switch node voltage signal Vsw and the power ground signal pvss in real time. When Vsw is greater than pvss, the comparator outputs a high-level first output signal Vcp, indicating that the inductor current may be about to cross zero.

[0140] Next, the digital logic module 120 performs logical operations on the first output signal Vcp and the power tube control signals HS and LS to generate three key signals: a dynamic bias signal Vdb for feedback control of the comparator bias, a second output signal Vcmp indicating the current zero-crossing feature, and a zero-crossing detection signal ZCD for controlling the power tube shutdown.

[0141] It is worth noting that the actual turn-off moment may deviate from the ideal zero-crossing point. Figure 6 As shown in the figure, when the lower power tube is turned off early, the receptor diode conduction voltage drop affects Vsw, which is first pulled to a negative value and then rebounds, causing Vcmp to show a double pulse feature; when the lower power tube is turned off with delay, the current has passed zero, Vsw remains at a high level, and Vcmp only shows a single pulse feature.

[0142] Detection and discrimination module 130 utilizes this differential characteristic to sample the second output signal Vcmp by sampling the rising edge of clock signal CLKD, which is generated by delaying zero-crossing detection signal ZCD. When the sampled value is high (corresponding to delayed shutdown of the lower power transistor), the digital tuning signal UP / DN is output at a low level; when the sampled value is low (corresponding to early shutdown of the lower power transistor), the digital tuning signal UP / DN is output at a high level.

[0143] The counter module 140 dynamically adjusts the value of the six-bit digital control signal Q<5:0> at the rising edge of the clock signal CLK according to the level of the digital tuning signal UP / DN, thereby changing the access state of the internal resistor array of the digital auxiliary comparator module 110. Figure 2 As shown, the combination of the resistor arrays R5 to R0 and R5b to R0b controlled by Q<5:0> and its inverted signal Qb<5:0> affects the output voltage difference of the pre-amplifier, and ultimately adjusts the flip offset of the comparator.

[0144] During system operation, if the lower power transistor is detected to be turned off later than the zero-crossing point, counter module 140 will reduce the value of Q<5:0>, causing the comparator to flip earlier in the next cycle. Conversely, if the lower power transistor is turned off earlier than the zero-crossing point, the value of Q<5:0> will be increased, delaying the comparator flip. After several cycles of adaptive iteration, the system will converge to the optimal shutdown time.

[0145] In summary, this application cleverly combines digital-analog circuits and adaptive control algorithms, and achieves dynamic optimization of the synchronous rectifier tube shutdown moment through a closed-loop feedback mechanism of sampling comparison-feature extraction-logical judgment-digital tuning, effectively improving the efficiency performance of the DC-DC converter in DCM mode and suppressing the ringing phenomenon of the switch node, with significant technical effects and application value.

[0146] In order to better understand the technical solution of the present application, a specific example is provided below for illustration. The details listed in the example are mainly for ease of understanding and are not intended to limit the scope of protection of the present application.

[0147] In general, the characteristics of this example are: the digital auxiliary comparator module compares the switch node voltage signal Vsw with the power ground signal pvss and generates a first output signal Vcp; the digital logic module processes the first output signal Vcp to generate a zero-crossing detection signal ZCD, and generates a power tube control signal through the logic drive module to control the power tube to be turned off; the detection and judgment module receives the second output signal Vcmp and the zero-crossing detection signal ZCD from the digital logic module and generates a digital tuning signal UP / DN; the counter module receives the digital tuning signal UP / DN from the detection and judgment module and generates a six-bit digital signal Q<5:0>, dynamically adjusts the resistor array in the digital auxiliary comparator module, and adaptively adjusts the flip offset of the comparator by changing the resistance value of the resistor array, thereby accurately controlling the shutdown timing of the power tube.

[0148] Furthermore, this example aims to provide a digitally assisted adaptive zero-crossing detection circuit. By comparing the switch node voltage signal Vsw with the power ground signal pvss, this circuit generates a zero-crossing detection signal ZCD to control the shutdown of the power transistor. This example implements high-precision zero-crossing detection in various application scenarios, while also improving the chip's conversion efficiency in DCM mode and reducing switch node ringing.

[0149] The digitally assisted adaptive zero-crossing detection circuit of this example includes: a digitally assisted comparator module 110, a digital logic module 120, a detection and discrimination module 130, and a counter module 140. The digitally assisted comparator module 110 is configured to sample the switch node voltage signal Vsw and the power ground signal pvss when the lower power tube in the buck converter power stage is turned on, compare them, and generate a first output signal Vcp; the digital logic module 120 is configured to receive the first output signal Vcp from the digitally assisted comparator module 110 and the upper power tube control signal HS and the lower power tube control signal HS in the buck converter power stage when the lower power tube in the buck converter power stage is turned on. signal LS, and generates a dynamic bias signal Vdb, a second output signal Vcmp and a zero-crossing detection signal ZCD after logical processing; wherein, the detection and discrimination module 130 is configured to receive the second output signal Vcmp and the zero-crossing detection signal ZCD from the digital logic module 120, and generate a digital tuning signal UP / DN after logical processing; wherein, the counter module 140 is configured to receive the digital tuning signal UP / DN from the detection and discrimination module 130, and generate a six-bit digital control signal Q<5:0> after counting processing, and dynamically adjust the resistor array in the digital auxiliary comparator module 110, and adaptively adjust the flip offset of the comparator by changing the resistance value of the resistor array.

[0150] In this example, optionally, the digital auxiliary comparator module 110 includes: a power supply terminal, a reference ground terminal, a first input terminal, a second input terminal, a third input terminal, a six-bit digital input terminal and an output signal terminal, the power supply terminal receives the power supply potential, the reference ground terminal receives the reference ground potential, the first input terminal receives the switching node voltage signal Vsw, the second input terminal receives the power ground signal pvss, the third input terminal receives the dynamic bias signal Vdb, the six-bit digital input terminals sequentially receive the six-bit digital control signal Q<5:0> from the counter module 140, and the output signal terminal outputs the first output signal Vcp. Furthermore, the digital auxiliary comparator module 110 is configured to compare the input switch node voltage signal Vsw with the power ground signal pvss when the dynamic bias signal Vdb is at a high level, and output a first output signal Vcp when the switch node voltage signal Vsw is greater than the power ground signal pvss. The received six-bit digital control signal Q<5:0> is used to control the resistance value of the resistor array inside the module, and the offset of the comparator flip is changed by changing the resistance value of the resistor array.

[0151] In this example, optionally, the digital logic module 120 includes: a power supply terminal, a reference ground terminal, an enable terminal, a first input terminal, a second input terminal, a third input terminal, a first output terminal, a second output terminal and a third output terminal, the power supply terminal receives a power supply potential, the reference ground terminal receives a reference ground potential, the enable terminal receives an enable signal, the first input terminal receives a first output signal Vcp from the digital auxiliary comparator module 110, the second input terminal receives an upper power tube control signal HS from the buck converter power stage, the third input terminal receives a lower power tube control signal LS from the buck converter power stage, the first output terminal outputs a dynamic bias signal Vdb, the second output terminal outputs a second output signal Vcmp, and the third output terminal outputs a zero-crossing detection signal ZCD. Furthermore, the digital logic module 120 is configured such that when the first output signal Vcp received from the digital auxiliary comparator module 110 flips to a high level, the second output signal Vcmp and the zero-crossing detection signal ZCD flip to a high level; when the first output signal Vcp flips to a low level, the second output signal Vcmp flips to a low level; when the upper power tube control signal HS received from the buck converter power stage flips to a high level, the zero-crossing detection signal ZCD flips to a low level; when the lower power tube control signal LS received from the buck converter power stage flips to a high level, the dynamic bias signal Vdb flips to a high level; and the falling edge of the lower power tube control signal LS triggers the dynamic bias signal Vdb to flip to a low level after a delay.

[0152] In this example, the detection and discrimination module 130 optionally includes: a power supply terminal, a reference ground terminal, a first input terminal, a second input terminal, and an output signal terminal. The power supply terminal receives a power supply potential, the reference ground terminal receives a reference ground potential, the first input terminal receives the second output signal Vcmp from the digital logic module 120, the second input terminal receives the zero-crossing detection signal ZCD from the digital logic module 120, and the output signal terminal outputs the digital tuning signal UP / DN. Furthermore, the detection and discrimination module 130 is configured to sample the second output signal Vcmp at the rising edge of the delayed zero-crossing detection signal ZCD. When the second output signal Vcmp is at a high level during sampling, the output digital tuning signal UP / DN is at a low level. When the second output signal Vcmp is at a low level during sampling, the output digital tuning signal UP / DN is at a high level.

[0153] In this example, optionally, the counter module 140 includes: a power supply terminal, a reference ground terminal, a first input terminal, a second input terminal, a third input terminal and a six-bit digital signal output terminal, the power supply terminal receives a power supply potential, the reference ground terminal receives a reference ground potential, the first input terminal receives a digital tuning signal UP / DN from the detection and judgment module 130, the second input terminal receives a set signal SET, the third input terminal receives a clock signal CLK, and the six-bit digital signal output terminal outputs a six-bit digital control signal Q<5:0>. Furthermore, the counter module 140 is configured to receive a set signal SET at a low level and valid. When the set signal SET is at a low level, the six-bit digital signal output end of the counter module 140 outputs low level, high level, high level, high level, high level, and high level from high to low respectively. When the received digital tuning signal UP / DN is at a low level, at the rising edge of the received clock signal CLK, the decimal representation of the output six-bit digital control signal Q<5:0> is reduced by one. When the received digital tuning signal UP / DN is at a high level, at the rising edge of the received clock signal CLK, the decimal representation of the output six-bit digital control signal Q<5:0> is increased by one.

[0154] In this example, the quiescent current can be controlled at the nanoampere level, making it suitable for ultra-low-power applications. Efficient adaptive loop control can be achieved with just a comparator and a small amount of basic digital logic circuitry. The multifunctional digital auxiliary comparator not only accurately detects the current zero crossing point, but also uses its output signal, Vcp, to provide a key basis for the detection and discrimination module, thereby accurately determining the timing of shutdown. During the initial startup of the circuit, the initial error is significantly reduced because the digital auxiliary comparator can directly detect and quickly shut down the power tube.

[0155] Furthermore, if Figure 1The zero-crossing detection circuit 100 includes: a digital auxiliary comparator module 110, a digital logic module 120, a detection and discrimination module 130, and a counter module 140. The digital auxiliary comparator module 110 is configured to sample the switch node voltage signal Vsw and the power ground signal pvss when the lower power tube in the buck converter power stage is turned on, compare and generate a first output signal Vcp; the digital logic module 120 is configured to receive the first output signal Vcp from the digital auxiliary comparator module 110 and the upper power tube control signal H in the buck converter power stage when the lower power tube in the buck converter power stage is turned on. After logical processing of the S and the lower power tube control signal LS, a dynamic bias signal Vdb, a second output signal Vcmp and a zero-crossing detection signal ZCD are generated; wherein the detection and judgment module 130 is configured to receive the second output signal Vcmp and the zero-crossing detection signal ZCD from the digital logic module 120 and perform logical processing thereon to generate a digital tuning signal UP / DN; wherein the counter module 140 is configured to receive the digital tuning signal UP / DN from the detection and judgment module 130 and perform counting processing thereon to generate a six-bit digital control signal Q<5:0> to control the flip offset of the digital auxiliary comparator module 110.

[0156] The digital auxiliary comparator module 110 is as follows Figure 2 As shown, when the dynamic bias signal Vdb is high, this module compares the input switch node voltage signal Vsw with the power ground signal pvss. When the switch node voltage signal Vsw is greater than the power ground signal pvss, it outputs a first output signal Vcp. This module receives the six-bit digital control signal Q<5:0> from the counter module 140 and generates the logically opposite six-bit digital control signal Qb<5:0> after passing through inverters. The six-bit digital control signals Q<5:0> and Qb<5:0> control the resistor arrays R5 to R0 and R5b to R0b, respectively. When the six-bit digital control signals Q<5:0> and Qb<5:0> are high, the corresponding resistors are short-circuited. When the six-bit digital control signals Q<5:0> and Qb<5:0> are low, the corresponding resistors are connected to the circuit. In the initial state of the circuit, Q<5:0> is low, high, high, high, high, high, and high from high to low. At this time, only R5 from R5 to R0 is connected to the circuit, and Qb<5:0> is high, low, low, low, low, low, and low from high to low. At this time, R4b, R3b, R2b, R1b, and R0b from R5b to R0b are connected to the circuit.

[0157] Digital logic module 120 is as follows Figure 3 As shown, the working waveform is as follows Figure 4When the first output signal Vcp received from the digital auxiliary comparator module 110 flips to a high level, the second output signal Vcmp and the zero-crossing detection signal ZCD flip to a high level; when the first output signal Vcp flips to a low level, the second output signal Vcmp flips to a low level; when the upper power tube control signal HS received from the buck converter power stage flips to a high level, the zero-crossing detection signal ZCD flips to a low level; when the lower power tube control signal LS received from the buck converter power stage flips to a high level, the dynamic bias signal Vdb flips to a high level, and the falling edge of the lower power tube control signal LS triggers the dynamic bias signal Vdb to flip to a low level after a delay.

[0158] The detection and discrimination module 130 is as follows Figure 5 As shown, the working waveform is as follows Figure 6 As shown. During operation of the circuit, when the lower power tube is turned off prematurely, the current will continue to flow through the body diode of the lower power tube. Due to the certain conduction voltage drop of the body diode, the switch node voltage signal Vsw will be pulled down to approximately negative several hundred millivolts. This voltage value is significantly lower than the Vsw voltage threshold when the comparator flips, so the second output signal Vcmp will flip to a low level. However, with the resonance of the LC circuit, Vsw will gradually rise and trigger the comparator to flip to a high level again after a period of time until the comparator is finally turned off. Therefore, in this case, the second output signal Vcmp will exhibit the characteristics of two pulse signals. In contrast, when the lower power tube is turned off with delay, the current has passed the zero point, the switch node voltage signal Vsw has become positive and remains greater than zero for a period of time until the comparator is finally turned off. Therefore, in this case, the second output signal Vcmp will appear as a single pulse signal.

[0159] The detection and discrimination module 130 generates a clock signal CLKD for the D-type flip-flop after delaying the zero-crossing detection signal ZCD from the digital logic module 120. The second output signal Vcmp is sampled on the rising edge of the clock signal CLKD. When the second output signal Vcmp is high during sampling, the output digital tuning signal UP / DN is low. When the second output signal Vcmp is low during sampling, the output digital tuning signal UP / DN is high.

[0160] The counter module 140 is as follows Figure 7As shown, the received set signal SET is valid at a low level. When the set signal SET is at a low level, the six-bit digital signal output terminal Q<5:0> of the counter module 140 outputs low level, high level, high level, high level, high level, high level from high bit to low bit respectively. When the received digital tuning signal UP / DN is at a low level, at the rising edge of the received clock signal CLK, the decimal representation of the output six-bit digital control signal Q<5:0> is reduced by one. When the received digital tuning signal UP / DN is at a high level, at the rising edge of the received clock signal CLK, the decimal representation of the output six-bit digital control signal Q<5:0> is increased by one.

[0161] Taking the delayed shutdown of the lower power transistor as an example, when the digital tuning signal UP / DN is low, the counter module 140 performs a subtraction operation, updating its output six-bit digital control signal Q<5:0> from its initial binary value of 011111 to 011110. Correspondingly, the six-bit digital control signal Qb<5:0> is updated from its initial binary value of 100000 to 100001. At this point, R5 and R0 in the resistor array R5 to R0 are connected to the circuit, increasing their resistance, while R4b, R3b, R2b, and R1b in the resistor array R5b to R0b are connected to the circuit, decreasing their resistance. This adjustment of the resistor array further affects the output voltage of the preamplifier: the voltage signal Vp at the non-inverting output terminal increases, while the voltage signal Vn at the inverting output terminal decreases. This voltage change causes the comparator to flip early in the next operating cycle, prompting the lower power transistor to shut down early.

[0162] Conversely, when the lower power transistor is shut down prematurely, the digital tuning signal UP / DN is high, and the counter module 140 performs an addition operation. This updates the six-bit digital control signal Q<5:0> it outputs from its initial binary value of 011111 to 100000. Correspondingly, the six-bit digital control signal Qb<5:0> is updated from its initial binary value of 100000 to 011111. At this point, resistors R4, R3, R2, R1, and R0 in the resistor array R5 to R0 are connected to the circuit, decreasing their resistance, while resistors R5b to R0b are connected to the circuit, increasing their resistance. This adjustment of the resistor array further affects the output voltage of the preamplifier: the voltage signal Vp at the non-inverting output decreases, while the voltage signal Vn at the inverting output increases. This voltage change delays the comparator's flipping in the next operating cycle, thereby delaying the shutdown of the lower power transistor.

[0163] Through the adaptive feedback mechanism, after several cycles of tuning, the digital auxiliary comparator module 110 can gradually approach the optimal turn-off moment of the lower power tube under the regulation of the feedback loop, thereby achieving precise control and optimization of the circuit working state.

[0164] It should be noted that in this patent application, relational terms such as first and second, etc., are used solely to distinguish one entity or operation from another, and do not necessarily require or imply any actual relationship or order between these entities or operations. Furthermore, the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. Without further limitation, an element specified by the phrase "comprising a" does not preclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element. In this patent application, reference to performing an action in accordance with an element means performing the action in accordance with at least that element, including two situations: performing the action in accordance with that element alone, and performing the action in accordance with that element and other elements. Expressions such as "plurality," "multiple times," and "many" include "two," "twice," "two kinds," and "more than two," "more than two times," and "more than two kinds."

[0165] All documents mentioned in this application are considered to be included in their entirety in the disclosure of this application so that they can be used as a basis for modification when necessary. In addition, it should be understood that after reading the above disclosure of this application, those skilled in the art may make various changes or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application.

Claims

1. A digitally assisted adaptive zero-crossing detection circuit, comprising: a digital auxiliary comparator module comprising a resistor array, configured to sample and compare a switch node voltage signal (Vsw) and a power ground signal (pvss) when a power transistor in a lower power stage of a buck converter is turned on, and generate a first output signal (Vcp); a digital logic module, electrically connected to the digital auxiliary comparator module, configured to receive the first output signal (Vcp) and the upper power tube control signal (HS) and the lower power tube control signal (LS) in the buck converter power stage, and generate a dynamic bias signal (Vdb), a second output signal (Vcmp), and a zero-crossing detection signal (ZCD) after logic processing; a detection and discrimination module, electrically connected to the digital logic module, configured to receive the second output signal (Vcmp) and the zero-crossing detection signal (ZCD), and generate a digital tuning signal (UP / DN) after logical processing; A counter module is electrically connected to the detection and discrimination module, and is used to receive the digital tuning signal (UP / DN) and generate a six-bit digital control signal (Q<5:0>) after counting. The six-bit digital control signal (Q<5:0>) is connected to the resistor array of the digital auxiliary comparator module. By dynamically changing the resistance value of the resistor array, adaptive adjustment of the flip offset of the digital auxiliary comparator module is achieved.

2. The digitally assisted adaptive zero-crossing detection circuit according to claim 1 is characterized in that the digitally assisted comparator module includes: a power supply terminal, a reference ground terminal, a first input terminal, a second input terminal, a third input terminal, a six-bit digital input terminal, and an output signal terminal, the power supply terminal receives a power supply potential (VDD), the reference ground terminal receives a reference ground potential, the first input terminal receives a switch node voltage signal (Vsw), the second input terminal receives a power ground signal (pvss), the third input terminal receives a dynamic bias signal (Vdb), the six-bit digital input terminals sequentially receive a six-bit digital control signal (Q<5:0>) from the counter module, and the output signal terminal outputs a first output signal (Vcp).

3. The digitally assisted adaptive zero-crossing detection circuit according to claim 2, wherein the resistor array comprises a first group of resistors (R5 to R0) and a second group of resistors (R5b to R0b); the six-bit digital control signal (Q<5:0>) generates a corresponding inverted signal (Qb<5:0>) through an inverter; wherein Q<5:0> controls the first group of resistors (R5 to R0), and Qb<5:0> controls the second group of resistors (R5b to R0b); when Q<5:0> and Qb<5:0> are high, the corresponding resistors are short-circuited, and when Q<5:0> and Qb<5:0> are low, the corresponding resistors are connected to the circuit; when the dynamic bias signal (Vdb) is high, the digitally assisted comparator module compares the magnitude of the input switch node voltage signal (Vsw) with the power ground signal (pvss), and outputs a first output signal (Vcp) when the switch node voltage signal (Vsw) is greater than the power ground signal (pvss).

4. The digitally assisted adaptive zero-crossing detection circuit according to claim 1, characterized in that the digital logic module includes: a power supply terminal, a reference ground terminal, an enable terminal, a first input terminal, a second input terminal, a third input terminal, a first output terminal, a second output terminal, and a third output terminal, wherein the power supply terminal receives a power supply potential (VDD), the reference ground terminal receives a reference ground potential, the enable terminal receives an enable signal, the first input terminal receives a first output signal (Vcp) from the digitally assisted comparator module, the second input terminal receives an upper power tube control signal (HS) in a buck converter power stage, the third input terminal receives a lower power tube control signal (LS) in a buck converter power stage, the first output terminal outputs a dynamic bias signal (Vdb), the second output terminal outputs a second output signal (Vcmp), and the third output terminal outputs a zero-crossing detection signal (ZCD).

5. The digitally assisted adaptive zero-crossing detection circuit according to claim 4 is characterized in that when the received first output signal (Vcp) flips to a high level, the second output signal (Vcmp) and the zero-crossing detection signal (ZCD) output by the digital logic module flip to a high level successively; when the first output signal (Vcp) flips to a low level, the second output signal (Vcmp) flips to a low level; when the received upper power tube control signal (HS) flips to a high level, the zero-crossing detection signal (ZCD) flips to a low level; when the received lower power tube control signal (LS) flips to a high level, the dynamic bias signal (Vdb) flips to a high level, and the falling edge of the lower power tube control signal (LS) triggers the dynamic bias signal (Vdb) to flip to a low level after delay processing.

6. The digitally assisted adaptive zero-crossing detection circuit according to claim 1 is characterized in that the detection and discrimination module includes: a power supply terminal, a reference ground terminal, a first input terminal, a second input terminal and an output signal terminal, the power supply terminal receives a power supply potential (VDD), the reference ground terminal receives a reference ground potential, the first input terminal receives a second output signal (Vcmp) from the digital logic module, the second input terminal receives a zero-crossing detection signal (ZCD) from the digital logic module, and the output signal terminal outputs the digital tuning signal (UP / DN).

7. The digitally assisted adaptive zero-crossing detection circuit according to claim 6 is characterized in that the detection and discrimination module generates a clock signal (CLKD) of the D flip-flop after delay processing of the zero-crossing detection signal (ZCD); when the rising edge of the clock signal (CLKD) arrives, the level state of the second output signal (Vcmp) is sampled; when the second output signal (Vcmp) obtained by sampling is a high level, it indicates that the lower power tube is delayed in shutting down, and the detection and discrimination module outputs a digital tuning signal (UP / DN) of a low level; when the second output signal (Vcmp) obtained by sampling is a low level, it indicates that the lower power tube is shut down in advance, and the detection and discrimination module outputs a digital tuning signal (UP / DN) of a high level.

8. The digitally assisted adaptive zero-crossing detection circuit according to claim 1 , wherein the counter module comprises: a power supply terminal, a reference ground terminal, a first input terminal, a second input terminal, a third input terminal, and a six-bit digital signal output terminal, wherein the power supply terminal receives a power supply potential (VDD), the reference ground terminal receives a reference ground potential, the first input terminal receives a digital tuning signal (UP / DN) from the detection and discrimination module, the second input terminal receives a set signal (SET), the third input terminal receives a clock signal (CLK), and the six-bit digital signal output terminal outputs the six-bit digital control signal (Q<5:0>).

9. The digitally assisted adaptive zero-crossing detection circuit according to claim 8, characterized in that when the set signal (SET) is at a low level, the six-bit digital signal output terminal of the counter module outputs low level, high level, high level, high level, high level, high level in descending order; when the digital tuning signal (UP / DN) is at a low level, upon the rising edge of the clock signal (CLK), the decimal value of the six-bit digital control signal (Q<5:0>) output by the counter module is reduced by one; When the digital tuning signal (UP / DN) is at a high level, when the rising edge of the clock signal (CLK) arrives, the decimal value of the six-bit digital control signal (Q<5:0>) output by the counter module is increased by one.

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