A si c mosfet gate oxide layer reliability test device and method

Abstract

The application relates to the technical field of testing and application of power semiconductors, in particular to a SiC MOSFET gate oxide layer reliability testing device and method. The device is provided with a high-voltage direct-current voltage power supply, an auxiliary direct-current voltage source, a signal generating device, a half-bridge testing circuit, a gate driving circuit, a load inductor, a load resistor and a measuring device, can significantly shorten the stress time required for device reliability evaluation, can more accurately describe the device threshold voltage drift characteristics under different drain-source voltage stresses, compared with the traditional static bias and gate switching stress test method, effectively introduces the influence of dynamic drain-source voltage and current, improves the accuracy of the model test result, and has certain application value for SiC MOSFET gate oxide layer reliability evaluation.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor testing and application technology, and in particular to a SiC MOSFET gate oxide reliability testing device and method. Background Technology

[0002] Due to their excellent high voltage and high temperature resistance, SiC MOSFETs are widely used in high power density converters, including electric vehicle charging stations and photovoltaic inverters. Compared with power devices such as IGBTs, SiC MOSFETs can increase the operating voltage and frequency of the converter and provide a basis for the miniaturization of passive components such as inductors and capacitors, significantly improving the performance of the converter.

[0003] However, due to limitations in manufacturing processes and device characteristics, SiC MOSFETs exhibit deficiencies in gate oxide reliability. Under the influence of electric field stress, particularly the gate oxide stress, significant gate oxide degradation occurs during long-term operation, leading to drift in its electrical characteristic parameters. Specifically, the device's threshold voltage and on-resistance may gradually increase, causing further changes in characteristics such as switching time. This can result in converter characteristics failing to meet design requirements and increasing the risk of failure. Therefore, accurate assessment of the gate oxide reliability and expected lifetime of SiC MOSFETs under high electric field stress is necessary.

[0004] For SiC MOSFETs, current reliability testing primarily focuses on two aspects: packaging and semiconductor performance. Packaging testing mainly examines the bonding wires and solder layers, applying thermal stress to the device through internal heating or external heat sources to accelerate packaging degradation and assess its reliability in long-term applications. For semiconductor reliability testing, current semiconductor reliability assessments of SiC MOSFETs can be categorized into the following two types:

[0005] (1) Static stress test methods, such as high temperature gate bias and high temperature reverse bias tests. This method mainly applies static high electric field and high temperature stress to the device, but it cannot characterize the dynamic stress faced by the device in the converter. It is often used for the passability test of the device rather than for accurate evaluation of its life.

[0006] (2) Dynamic gate stress test method. This method mainly applies dynamic stress to the gate and source of the device to simulate the effect of the gate switching process, but it cannot evaluate the effect of dynamic drain-source voltage and current stress.

[0007] In recent years, some literature has proposed device testing methods under dynamic drain-source voltage (Cai Y, Sun P, Chen C, et al. Investigation on gate oxide degradation of SiC MOSFET in switching operation [J]. IEEE Transactions on Power Electronics, 2024, 39(8): 9565-9578.), but there is a lack of test schemes and corresponding lifetime assessment methods under different operating conditions, and the device design lacks sufficient flexibility. Therefore, there is an urgent need for a gate oxide reliability testing device with flexible configuration to fully characterize the aging characteristics of SiC MOSFETs under drain-source voltage and current conditions. Summary of the Invention

[0008] In view of this, the purpose of this invention is to provide a reliability testing device and method for SiC MOSFET gate oxide layer, so as to solve the problems of insufficient accuracy and flexibility of existing testing devices and methods.

[0009] To achieve the above objectives, the present invention provides a SiC MOSFET gate oxide layer reliability testing device, comprising:

[0010] High voltage DC power supply, auxiliary DC voltage source, signal generator, half-bridge test circuit, gate drive circuit, load inductor, load resistor and measuring equipment;

[0011] The high-voltage DC power supply is used to provide a specified DC voltage to the half-bridge test circuit, and the auxiliary DC voltage source is used to power the gate drive circuit.

[0012] The half-bridge test circuit includes a bus capacitor, an upper switching transistor, a lower switching transistor, and a switch for configuring the circuit's operating mode.

[0013] The gate drive circuit is used to provide the upper and lower switching transistors with adjustable gate-source voltages of maximum and minimum values.

[0014] The load inductor is used to limit the drain-source current in the upper and lower switching transistors, and the load resistor is an optional load that is connected to the circuit through a switch.

[0015] The signal generating device is used to input a test signal to the device under test, and the measuring device is used to measure the threshold voltage change of the device under test.

[0016] The present invention also provides a test method based on the above-mentioned SiC MOSFET gate oxide layer reliability test device, characterized in that the test method includes the following steps:

[0017] The device under test is set as the lower switch in the half-bridge test circuit and operates in the switching state. The upper switch is a SiC MOSFET of the same model as the device under test or a diode is used instead.

[0018] The device under test is tested under constant duty cycle and constant switching frequency, and its threshold voltage change is measured using measuring equipment to evaluate the degree of degradation of the gate oxide layer.

[0019] By adjusting the positive and negative values ​​of the gate-source voltage of the device under test and the magnitude of the driving resistor in the gate driving circuit, the degradation characteristics of the gate oxide layer of SiC MOSFET under different gate voltages and gate resistors are analyzed.

[0020] By adjusting the voltage of the high-voltage DC power supply and the value of the load inductance, the drain-source voltage and current of the device under test are regulated, and the degradation characteristics of the gate oxide layer of SiC MOSFET under different operating conditions are analyzed.

[0021] Preferably, the method further includes:

[0022] By adjusting the duty cycle, under the same conditions of high-voltage DC power supply and load inductance, the drain-source current of the device under test is increased. By increasing the switching frequency, the gate oxide degradation of the device is accelerated, and the test time is shortened.

[0023] Preferably, the method further includes:

[0024] The degradation characteristics of the gate oxide layer of the device were tested under different temperature conditions, and the degradation characteristics of the gate oxide layer of SiC MOSFET under different operating environments were analyzed.

[0025] Preferably, the test is repeated more than three times for each working condition and stress condition. When the results of the three sets of tests differ significantly, further supplementary tests are conducted. The threshold voltage change of the device is tested at fixed intervals. When the change exceeds 20%, the device is considered to have failed and the test is terminated.

[0026] Preferably, the test method further includes:

[0027] Test the device's initial threshold voltage, on-resistance, switching time, and avalanche breakdown voltage to confirm that the device can be used normally;

[0028] Select the required drain-source voltage and peak current, and calculate the load resistance parameters and conduction time based on the above conditions;

[0029] Calculate the losses of a single switching process and simulate the junction temperature of the device based on the thermal resistance provided in the datasheet. When the junction temperature of the device exceeds the maximum junction temperature specified in the datasheet, adjust the switching frequency to reduce the junction temperature.

[0030] Accelerated aging tests were conducted on the device under specified operating conditions. The threshold voltage of the device was measured and recorded at fixed time intervals. When the threshold voltage of the device changed by more than 20%, the device was considered to have failed and the test was terminated.

[0031] Model parameters were obtained based on two sets of experiments under different voltages;

[0032] The model is validated based on the remaining experimental data. If the predicted results deviate significantly from the actual measurement results, the model parameters are corrected until the test requirements are met.

[0033] The beneficial effects of this invention are as follows: The test device and method proposed in this invention can significantly shorten the stress time required for device reliability assessment, and can more accurately describe the threshold voltage drift characteristics of the device under different drain-source voltage stresses. Compared with the traditional static bias and gate switch stress test methods, it effectively introduces the influence of dynamic drain-source voltage and current, improves the accuracy of model test results, and has certain application value for the reliability assessment of SiC MOSFET gate oxide layers. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only for this invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of the test device based on the clamping inductive switch circuit of the present invention;

[0036] Figure 2 This refers to the current path under the turn-on and turn-off conditions of the lower switching transistor in this invention.

[0037] Figure 3 The drain-source voltage and current waveforms of the upper and lower switching transistors in this invention are shown.

[0038] Figure 4 This invention provides the change in the threshold voltage of the switching transistor under a certain operating condition.

[0039] Figure 5 This is a flowchart illustrating how the present invention obtains life model parameters based on different operating conditions;

[0040] Figure 6 This invention compares the model prediction results with the actual results under different operating conditions. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments.

[0042] It should be noted that, unless otherwise defined, the technical or scientific terms used in this invention should have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0043] Example 1: This invention proposes an accelerated aging test device for power semiconductor devices based on a half-bridge inductive switching circuit, specifically including a high-voltage DC power supply VDC, an auxiliary DC voltage source, a signal generator, a half-bridge test circuit, a gate drive circuit, a load inductor L, a load resistor R, and measuring equipment.

[0044] The aforementioned high-voltage DC power supply is used to provide a specified DC voltage to the half-bridge circuit, while the auxiliary DC voltage source is used to power the gate drive circuit.

[0045] The aforementioned half-bridge test circuit includes a bus capacitor, an upper switch S1, a lower switch S2, and a switch S for configuring the circuit's operating mode.

[0046] The aforementioned gate drive circuit can provide gate-source voltage to the upper and lower switching transistors, and the maximum and minimum values ​​of this voltage are adjustable. Figure 1 VGS1 and VGS2 in the middle.

[0047] The load inductor L is used to limit the drain-source current in the switching transistor, while the load resistor R is an optional load that is connected to the circuit via a switch.

[0048] Example 2: This invention proposes a reliability testing method for the gate oxide layer of SiC MOSFETs considering dynamic drain-source voltage and current. The reliability of the SiC MOSFET is evaluated based on the test circuit proposed in the first aspect. The device under test is configured as the lower switch and operates in a switching state. The upper switch can be replaced by a SiC MOSFET of the same type or a diode.

[0049] When the device under test (DUT) is turned on, its drain-source current gradually increases and flows through the load inductor, causing the DUT to undergo a hard-start process. When the DUT is turned off, its drain-source current is 0, and the load inductor current flows through the diode, or the diode and the load resistor (optional), gradually decreasing to 0.

[0050] Under constant duty cycle and constant switching frequency, the device under test is tested for a long time, and its threshold voltage change is measured using measuring equipment to assess the degree of degradation of the gate oxide layer.

[0051] Accelerated aging tests were conducted on the device under test under different operating conditions, and model parameters were calculated based on the threshold voltage drift results. The threshold voltage degradation model is given below:

[0052] (1)

[0053] In the formula, A1 is a constant related to the device and operating conditions, γ is an acceleration factor related to the number of switching Ncy, and A2 is an acceleration factor related to the drain-source voltage VDS.

[0054] To analyze the gate oxide degradation characteristics of SiC MOSFETs under different gate voltages and gate resistances, the driving circuit can be adjusted. Specific parameters include the sign of the gate-source voltage of the device under test and the magnitude of the driving resistor RG in the gate circuit. In this invention, the driving resistor is divided into a positive driving circuit resistor and a negative driving circuit resistor, or it can be set as a single driving resistor.

[0055] To analyze the gate oxide degradation characteristics of SiC MOSFETs under different operating conditions, the voltage of the high-voltage DC power supply and the value of the load inductance can be adjusted, thereby regulating the drain-source voltage and current of the device under test. Specifically, increasing the DC source voltage leads to an increase in drain-source voltage and current, while increasing the load inductance decreases the drain-source current.

[0056] Meanwhile, the duty cycle and switching frequency can be adjusted based on the signal generator. By adjusting the duty cycle, under the same conditions of high-voltage DC power supply and load inductance, the drain-source current of the device under test can be increased. By increasing the switching frequency, the gate oxide degradation of the device can be accelerated, and the test time can be shortened.

[0057] To analyze the gate oxide degradation characteristics of SiC MOSFETs under different operating environments, the above experiments can also be conducted under high or low temperature conditions. A programmable constant temperature test chamber was used to test the gate oxide degradation characteristics of the device under different temperature conditions.

[0058] To improve the reliability of the test results, each of the above operating conditions and stress conditions was repeated at least three times. When the results of the three sets of tests differed significantly, further supplementary tests were conducted. The threshold voltage change of the device was tested at fixed time intervals. When the change exceeded 20%, the device was considered to have failed and the test was terminated.

[0059] Example 3 analyzes the results of device aging tests. The relationship between test results at different time periods and switching tests is analyzed, and the corresponding degradation model parameters are derived:

[0060] (2)

[0061] By fitting the threshold voltage changes under two different drain-source voltages, the above parameters can be obtained: A1, A2, and γ, where A1 is a constant related to the device and operating conditions, γ is an acceleration factor related to the number of switching operations Ncy, and A2 is an acceleration factor related to the drain-source voltage VDS. The accuracy of the above model can be verified based on the third set of data.

[0062] It should be noted that devices may exhibit different degradation rates at different test times, corresponding to changes in model parameters.

[0063] To simplify the testing and modeling process, test results from different stages can be described using the same model. To ensure the accuracy of the test results, the testing time needs to be extended to accurately describe the gate oxide degradation of the device under long-term stress.

[0064] To speed up the testing process, higher gate voltages or drain-source voltages can be used to enhance the gate oxide electric field and accelerate device degradation.

[0065] based on Figure 1 The schematic diagram shown simulates the voltage and current waveforms of the device under test to analyze its electrical stress characteristics. Figure 2 The current paths under the conditions of turn-on and turn-off of the lower transistor are given, with a switching frequency of 1kHz and a conduction time of 1μs.

[0066] Figure 3 (a) and (b) show the drain-source voltage and current waveforms of the device under test, respectively. It can be seen that the device is in a hard-switching state and the average current is small. This means that the junction temperature of the device changes little during the test, and the device degradation is mainly caused by the electric field stress of the gate oxide layer.

[0067] The device under test was subjected to a total of 60 hours of testing under high drain-source voltage stress. The threshold voltage of the device was tested every 5 hours. A set of test results is presented in... Figure 4 As given, DUT1, DUT2, and DUT3 all refer to the test results of the lower switch S2.

[0068] The analysis process of multiple test results is in Figure 5 The process, as described above, mainly includes the following steps:

[0069] Step 1: Device health status test: Test the device's initial threshold voltage, on-resistance, switching time, and avalanche breakdown voltage to confirm that the device can be used normally;

[0070] Step 2: Test Environment Configuration: Select the required drain-source voltage VDS and peak current ID(max). Based on the above conditions, calculate the load resistance parameters and conduction time:

[0071] (3)

[0072] In the formula, Ton is the conduction time.

[0073] Using a higher drain-source voltage can accelerate device aging and shorten the testing time.

[0074] Step 3: Electrothermal Stress Calculation: Calculate the losses during a single switching process and perform simulation calculations based on the thermal resistance provided in the datasheet to estimate the junction temperature of the device. The loss Esw during a single switching process is expressed as:

[0075] (4)

[0076] In the formula, Eon is the turn-on loss, Eoff is the turn-off loss, and Econ is the turn-on loss.

[0077] The above losses can be obtained based on experimental or simulated waveforms, that is:

[0078] (5)

[0079] In the formula, t1 and t2 are the start and end times of a single switching process, respectively.

[0080] The junction temperature Tj of the device can be expressed as:

[0081] (6)

[0082] In the formula, Tc is the temperature of the casing of the device under test, and Zj-a is the junction-to-case thermal resistance.

[0083] When the junction temperature of a device exceeds the maximum junction temperature Tj(max) specified in the datasheet, the switching frequency needs to be adjusted to reduce the junction temperature.

[0084] Step 4: Accelerated Aging Test: Perform an accelerated aging test on the device under specified operating conditions. Measure and record the threshold voltage of the device at fixed time intervals T1.

[0085] When the threshold voltage of a device changes by more than 20%, the device is considered to have failed and the test is terminated.

[0086] Step 5: Obtain model parameters based on two sets of experiments under different voltages.

[0087] Step 6: Validate based on the remaining experimental data. If the predicted results deviate significantly from the actual measurement results, correct the model parameters until the prediction requirements are met.

[0088] Figure 6 The model prediction results and actual results under different working conditions are compared to demonstrate the effectiveness of the proposed prediction model.

[0089] The SiC MOSFET gate oxide reliability testing device proposed in this invention significantly simplifies testing time and enables more accurate and convenient evaluation of device threshold voltage degradation under different voltages. By using a clamped inductive switch test based on a half-bridge circuit, it can simulate the drain-source voltage and current stress experienced by the device in the converter, solving the problems of long testing time and large deviation between test results and actual lifespan in traditional gate switch testing and static bias testing methods.

[0090] This invention can be applied to the threshold voltage degradation and gate oxide reliability assessment of SiC MOSFETs under different voltage conditions. At the same time, the above test method can also be applied to the reliability assessment of devices under different application conditions, including duty cycle, temperature, etc.

[0091] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples; within the framework of the invention, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of the different aspects of the invention as described above, which are not provided in the details for the sake of brevity.

[0092] This invention is intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A SiC MOSFET gate oxide reliability test apparatus, characterized by, include: High voltage DC power supply, auxiliary DC voltage source, signal generator, half-bridge test circuit, gate drive circuit, load inductor, load resistor and measuring equipment; The high-voltage DC power supply is used to provide a specified DC voltage to the half-bridge test circuit that is adapted to the high-voltage operating characteristics of the SiC MOSFET, and the auxiliary DC voltage source is used to supply power to the gate drive circuit. The half-bridge test circuit includes a bus capacitor, an upper switching transistor, a lower switching transistor, and a switch for configuring the circuit's operating mode. The lower switching transistor is the SiC MOSFET under test and operates in a hard-switching state. The gate drive circuit is used to provide the upper and lower switching transistors with adjustable gate-source voltages of maximum and minimum values. The gate-source voltage is used to simulate the gate stress of the device under test during actual operation. The load inductor is used to limit the dynamic drain-source current in the upper and lower switching transistors. The load resistor is an optional load that is connected to the circuit through a switch. It works in conjunction with the load inductor to precisely control the dynamic drain-source current of the device under test, thereby introducing the influence of dynamic drain-source voltage and current. The signal generating device is used to input test signals simulating the operation of a SiC MOSFET in an actual converter for the device under test, and the measuring device is used to measure the threshold voltage change of the device under test under dynamic drain-source voltage and current stress.

2. A SiC MOSFET gate oxide reliability test method based on the SiC MOSFET gate oxide reliability test device as claimed in claim 1, characterized in that, The testing method includes the following steps: The device under test is set as the lower switch in the half-bridge test circuit and operates in the switching state. The upper switch is a SiC MOSFET of the same model as the device under test or a diode is used instead. The device under test is tested under constant duty cycle and constant switching frequency, and its threshold voltage change is measured using measuring equipment to evaluate the degree of degradation of the gate oxide layer. By adjusting the positive and negative values ​​of the gate-source voltage of the device under test and the magnitude of the driving resistor in the gate driving circuit, the degradation characteristics of the gate oxide layer of SiC MOSFET under different gate voltages and gate resistors are analyzed. By adjusting the voltage of the high-voltage DC power supply and the value of the load inductance, the drain-source voltage and current of the device under test are regulated, and the degradation characteristics of the gate oxide layer of SiC MOSFET under different operating conditions are analyzed.

3. The SiC MOSFET gate oxide reliability test method of claim 2, wherein, The method further includes: By adjusting the duty cycle, under the same conditions of high-voltage DC power supply and load inductance, the drain-source current of the device under test is increased. By increasing the switching frequency, the gate oxide degradation of the device is accelerated, and the test time is shortened.

4. The SiC MOSFET gate oxide reliability test method of claim 2, wherein, The method further includes: The degradation characteristics of the gate oxide layer of the device were tested under different temperature conditions, and the degradation characteristics of the gate oxide layer of SiCMOSFET under different operating environments were analyzed.

5. The SiC MOSFET gate oxide reliability test method of claim 2 or 3 or 4, wherein, Each working condition and stress condition is repeated more than three times. When the results of the three sets of tests differ significantly, further supplementary tests are conducted. The threshold voltage change of the device is tested at fixed intervals. When the change exceeds 20%, the device is considered to have failed and the test is terminated.

6. The SiC MOSFET gate oxide reliability test method of claim 2, wherein, The testing method further includes: Test the device's initial threshold voltage, on-resistance, switching time, and avalanche breakdown voltage to confirm that the device can be used normally; Select the required drain-source voltage and peak current, and calculate the load resistance parameters and conduction time based on the above conditions; Calculate the losses of a single switching process and simulate the junction temperature of the device based on the thermal resistance provided in the datasheet. When the junction temperature of the device exceeds the maximum junction temperature specified in the datasheet, adjust the switching frequency to reduce the junction temperature. Accelerated aging tests were conducted on the device under specified operating conditions. The threshold voltage of the device was measured and recorded at fixed time intervals. When the threshold voltage of the device changed by more than 20%, the device was considered to have failed and the test was terminated. Model parameters were obtained based on two sets of experiments under different voltages; The model is validated based on the remaining experimental data. If the predicted results deviate significantly from the actual measurement results, the model parameters are corrected until the test requirements are met.

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