Printed circuit board assembly testing system and method

Abstract

The present application discloses a printed circuit board assembly testing system and method, which relates to the field of server technology. The test signal transmitted from the mainboard of the device to be tested to the backplane is shunted through an intervenor, and the test signal is sent to the main control board through the main circuit module of the intervenor. The main control board generates the test results and sends the test results to the client. There is no need to reserve test points on the device to be tested for testing. Therefore, the technical problems of the existing testing methods that are prone to test omissions and low test efficiency can be solved, and the technical effect of avoiding test omissions and improving test efficiency can be achieved.

Description

Technical Field

[0001] The present application relates to the field of server technology, and in particular to a printed circuit board assembly testing system and method. Background Art

[0002] With the development of the server industry, complex communication protocols and increased power consumption have placed higher demands on server hardware. The yield rate of printed circuit board assemblies is key to hardware quality and performance. Current quality testing methods for printed circuit board assemblies mainly include integrated circuit testing methods and functional testing methods.

[0003] In current related technologies, integrated circuit testing methods detect the functionality of printed circuit board assemblies by puncturing reserved test points on them. Functional testing methods determine whether the PCB assembly functions abnormally by performing a stress test on the PCB assembly for a long period of time. However, in related technologies, integrated circuit testing methods require reserved test points on the PCB assembly, and this process can lead to missed test points, resulting in incomplete functional testing. Functional testing methods also take too long to stress test, and existing testing methods are prone to test omissions and low test efficiency. Summary of the Invention

[0004] The present application provides a printed circuit board assembly testing system and method to at least solve the problems of test omissions and low test efficiency in related technologies.

[0005] The present application provides a printed circuit board assembly testing system, comprising:

[0006] Intervention device, main control board and client:

[0007] The intervenor includes a main circuit module, a first connector, a second connector and a solder pad;

[0008] The main circuit module is communicatively connected to the first connector, the second connector and the pad respectively;

[0009] The first connector is communicatively connected to the mainboard of the device under test;

[0010] The second connector is communicatively connected to the backplane of the device under test;

[0011] The pad is connected to the main control board for communication;

[0012] The main control board communicates with the client;

[0013] The mainboard of the device under test transmits the test signal to the backplane of the device under test through the first connector, the main circuit module and the second connector in sequence;

[0014] The main circuit module diverts the signal to be tested to the main control board through the pad. The main control board monitors the changes in the signal to be tested to obtain the test results and sends the test results to the client.

[0015] The present application also provides a printed circuit board assembly testing method, comprising:

[0016] The client sends a test instruction to the main control board in response to the user's trigger operation of starting the test;

[0017] The main control board monitors the level information of the signal to be tested according to the test instruction, generates a first test result according to the level information, and sends the first test result and the level information to the client;

[0018] The client generates a second test result based on the level information;

[0019] The client generates a comprehensive test result based on the first test result and the second test result;

[0020] The client outputs comprehensive test results.

[0021] Through this application, since the intervenor transmits the test signal transmitted from the main board of the device to be tested to the backplane for diversion, the test signal is sent to the main control board through the main circuit module of the intervenor, and the main control board generates the test results and sends the test results to the client, there is no need to reserve test points on the device to be tested for testing. Therefore, the technical problems of the existing testing methods that are prone to test omissions and low test efficiency can be solved, and the technical effect of avoiding test omissions and improving test efficiency can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0023] Figure 1 A schematic diagram of the system structure of a printed circuit board assembly testing system provided in an embodiment of the present application;

[0024] Figure 2 Schematic diagram of the structure of the interventional device provided in the embodiment of the present application Figure 1 ;

[0025] Figure 3 Schematic diagram of the structure of the interventional device provided in the embodiment of the present application Figure 2 ;

[0026] Figure 4 A schematic diagram of the structure of the main control board provided in an embodiment of the present application;

[0027] Figure 5 A schematic flow chart of a printed circuit board assembly testing method provided in an embodiment of the present application.

[0028] The above drawings include the following reference numerals:

[0029] 10-Intervention device;

[0030] 101-main circuit module;

[0031] 102-first connector;

[0032] 103-second connector;

[0033] 104- soldering pad;

[0034] 1011-first power supply unit;

[0035] 1012-Logical processor;

[0036] 1013-Firmware burning module;

[0037] 1014-high-speed signal line;

[0038] 1015-first low-speed signal line;

[0039] 1016-first signal line;

[0040] 1017-second signal line;

[0041] 1018-first communication bus;

[0042] 1019-Firmware upgrade bus;

[0043] 1020-Repeater;

[0044] 1021-programmable memory;

[0045] 1022-data selector;

[0046] 1023-jump cap;

[0047] 1024-second communication bus;

[0048] 1025 - third communication bus;

[0049] 1026 - fourth communication bus;

[0050] 1027-Jumper pin header;

[0051] 1028-second low-speed signal line;

[0052] 1029-third signal line;

[0053] 20-main control board;

[0054] 201- programmable processor;

[0055] 202-Flash memory;

[0056] 203- flash memory base;

[0057] 204-third connector;

[0058] 205-fourth connector;

[0059] 206-second power supply unit;

[0060] 207-serial bus;

[0061] 208-serial input bus;

[0062] 209-serial output bus;

[0063] 210-first communication line;

[0064] 211-second communication line;

[0065] 212-power conversion unit;

[0066] 213- filter capacitor group;

[0067] 214-power cord;

[0068] 215-voltage suppression component;

[0069] 216-interface protection line;

[0070] 217-Dynamic Random Access Memory;

[0071] 218-memory bus;

[0072] 2041-first sub-connector;

[0073] 2042-second sub-connector;

[0074] 2101-fifth communication bus;

[0075] 2102-third low-speed signal line;

[0076] 2111-sixth communication bus;

[0077] 2112-Fourth low-speed signal line;

[0078] 30-Client;

[0079] 40- Mainboard of the device under test;

[0080] 50-Backplane of the device under test. DETAILED DESCRIPTION

[0081] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0082] It should be noted that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "back," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like, indicating positions or relationships, are based on the positions or relationships shown in the accompanying drawings and are intended solely for ease of description and simplification of the present application. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limiting the present application. The terms "mounted," "connected," and "connected" should be interpreted broadly, and may include, for example, fixed, removable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediary; and internal communication between two components. The terms "parallel," "perpendicular," and "equal" encompass the described conditions and conditions similar to the described conditions, provided that the range of the similar conditions is within an acceptable range of deviation, as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes both absolute parallelism and approximate parallelism, where the acceptable deviation range for approximate parallelism may be, for example, within 5°; "perpendicular" includes both absolute perpendicularity and approximate perpendicularity, where the acceptable deviation range for approximate perpendicularity may also be, for example, within 5°. "Equal" includes both absolute equality and approximate equality, where the acceptable deviation range for approximate equality may be, for example, that the difference between the two is less than or equal to 5% of either. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0083] In order to solve the problems of test omissions and low test efficiency that are prone to occur in related technologies, the embodiments of the present application propose the following technical concepts: the inventor considered designing an intervener, which includes a main circuit module, a first connector, a second connector and a solder pad. The first connector is connected to the main board of the device to be tested, and the second connector is connected to the backplane of the device to be tested. The test signal transmitted from the main board to the backplane through the main circuit module is diverted to the main control board through the solder pad. The changes in the test signal are monitored by the main control board to obtain the test results. The main control board sends the test results to the client, and there is no need to reserve the function of the test point test circuit.

[0084] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0085] Figure 1 This is a schematic diagram of the system structure of the printed circuit board assembly test system provided in the embodiment of the present application. Figure 1 As shown, including:

[0086] The intervening device 10, the main control board 20 and the client 30.

[0087] The interposer 10 includes a main circuit module 101 , a first connector 102 , a second connector 103 , and a pad 104 .

[0088] In this embodiment, the interventional device 10 includes a high-speed interventional device and a low-speed interventional device.

[0089] Among them, the high-speed intervener is adapted to high-speed scenarios and mixed scenarios of high and low speeds; the low-speed intervener is adapted to low-speed scenarios.

[0090] Among them, the high-speed intervener includes a first connector 102, a second connector 103, a solder pad 104, a first power supply unit 1011, a logic processor 1012, a firmware burning module 1013, a high-speed signal line 1014, a first low-speed signal line 1015, a first signal line 1016, a second signal line 1017, a first communication bus 1018, a firmware upgrade bus 1019, a repeater 1020, a programmable memory 1021, a data selector 1022, a jumper cap 1023, a second communication bus 1024, a third communication bus 1025, a fourth communication bus 1026 and a jumper pin 1027.

[0091] The low-speed interposer includes a first connector 102 , a second connector 103 , a pad 104 , a second low-speed signal line 1028 , and a third signal line 1029 .

[0092] In this embodiment, the first connector 102 and the second connector 103 in the intervener 10 are multi-form connectors, which can adapt to the connection of various detachable parts in the server and can adapt to the multi-functional scenario circuit testing of the detachable parts.

[0093] The main circuit module 101 is communicatively connected to the first connector 102 , the second connector 103 , and the pad 104 .

[0094] In this embodiment, the main body circuit module 101 includes a high-speed main body circuit module and a low-speed main body circuit module.

[0095] The first connector 102 is in communication connection with the mainboard 40 of the device under test.

[0096] In this embodiment, a connector is provided on the mainboard 40 of the device under test, and the connector provided on the mainboard 40 of the device under test and the first connector are male and female to each other.

[0097] In this embodiment, the connection between the first connector 102 and the mainboard 40 of the device under test may be a wired connection or a plug-in connection.

[0098] The second connector 103 is in communication connection with the backplane 50 of the device under test.

[0099] In this embodiment, a connector is provided on the back panel 50 of the device under test, and the connector provided on the back panel 50 of the device under test and the second connector are male and female to each other.

[0100] In this embodiment, the connection between the second connector 103 and the backplane 50 of the device under test may be a wired connection or a plug-in connection.

[0101] The pad 104 is communicatively connected to the main control board 20 .

[0102] In this embodiment, the connection between the pad 104 and the main control board 20 is a wired connection.

[0103] The main control board 20 is in communication connection with the client 30 .

[0104] In this embodiment, the connection between the main control board 20 and the client 30 is a wired connection.

[0105] The mainboard 40 of the device under test transmits the test signal to the backplane 50 of the device under test through the first connector 102 , the main circuit module 101 and the second connector 103 in sequence.

[0106] In this embodiment, the signal to be tested includes a high-speed signal and a low-speed signal.

[0107] The main circuit module 101 shunts the signal to be tested to the main control board 20 through the pad 104 . The main control board 20 monitors the change of the signal to be tested to obtain a test result, and sends the test result to the client 30 .

[0108] Specifically, the main circuit module 101 collects the signal to be tested and diverts the signal to be tested to the main control board 20 through the pad 104. The main control board 20 obtains the level change of the signal to be tested, generates a test result according to the level change of the signal to be tested, and sends the test result to the client 30. The client 30 displays the test result.

[0109] It can be seen from the above embodiments that the test signal transmitted from the mainboard of the device to be tested to the backplane is shunted through the intervenor, and the test signal is sent to the main control board through the main circuit module of the intervenor. The main control board generates the test results and sends the test results to the client. There is no need to reserve test points on the device to be tested for testing, which avoids the problems of test omissions and low test efficiency.

[0110] Figure 2 Schematic diagram of the structure of the interventional device provided in the embodiment of the present application Figure 1 .like Figure 2 As shown, the main circuit module 101 includes: a first power supply unit 1011, a logic processor 1012, a firmware burning module 1013, a high-speed signal line 1014 and a first low-speed signal line 1015, as well as a first signal line 1016, a second signal line 1017, a first communication bus 1018 and a firmware upgrade bus 1019;

[0111] The first power supply unit 1011 is electrically connected to the logic processor 1012 and the firmware burning module 1013 respectively.

[0112] In this embodiment, the first power supply unit 1011 is a 3.3V power supply unit.

[0113] In this embodiment, the logic processor 1012 and the firmware burning module 1013 need to be grounded.

[0114] In this embodiment, the logic processor 1012 is a CPLD (Complex Programmable Logic Device).

[0115] The first connector 102 and the second connector 103 establish a high-speed communication connection via the high-speed signal line 1014 .

[0116] Specifically, the high-speed signal in the signal to be tested is transmitted via the high-speed signal line 1014 .

[0117] The first connector 102 and the second connector 103 establish a low-speed communication connection via the first low-speed signal line 1015 .

[0118] Specifically, the low-speed signal in the signal to be tested is transmitted via the first low-speed signal line 1015 .

[0119] The logic processor 1012 is connected to the high-speed signal line 1014 through the first signal line 1016 and is connected to the first low-speed signal line 1015 through the second signal line 1017 .

[0120] In this embodiment, the first signal line 1016 is a high-speed signal line.

[0121] In this embodiment, the second signal line 1017 is a low-speed signal line.

[0122] The logic processor 1012 is connected to the pads 104 via a first communication bus 1018 .

[0123] In this embodiment, the logic processor 1012 is used to receive the diverted test signal, detect the real-time level state and level change of the test signal, and send the detected real-time level state and level change of the test signal to the programmable processor 201 through the first communication bus 1018 through the pad 104.

[0124] In this embodiment, the level state includes a high level and a low level.

[0125] In this embodiment, the first communication bus 1018 is an I2C bus (Inter-Integrated Circuit, a bidirectional two-wire synchronous serial bus).

[0126] The signals transmitted by the first communication bus include unidirectional signals and bidirectional signals.

[0127] In this embodiment, the soldering pad 104 is used to solder cables to connect the cables to the connector of the main control board to transmit signals to the main control board.

[0128] In this embodiment, a communication bus is reserved between the logic processor 1012 and the pad 104 for a tester to define the function of the reserved communication bus.

[0129] In this embodiment, the reserved communication bus is an I2C bus (Inter-Integrated Circuit, a bidirectional two-wire synchronous serial bus).

[0130] The firmware burning module 1013 and the logic processor 1012 are in communication with each other via a firmware upgrade bus 1019 .

[0131] In this embodiment, the firmware burning module 1013 is used to update the firmware of the logical processor 1012 .

[0132] In this embodiment, the firmware upgrade bus 1019 is a JTAG (Joint Test Action Group) bus.

[0133] It can be seen from the above embodiments that the level and level change of the signal to be tested are judged by the logic processor to generate a test result, and the test result is transmitted to the main control board through the pad. The main control board compares the level status of the preset signal to be tested and generates a judgment result. There is no need to reserve test points on the device to be tested for testing, which improves the test efficiency.

[0134] In one embodiment of the present application, the main circuit module 101 further includes: a repeater 1020, a programmable memory 1021, a data selector 1022 and a jumper cap 1023, as well as a second communication bus 1024, a third communication bus 1025, a fourth communication bus 1026 and a jumper pin header 1027;

[0135] The repeater 1020 establishes a high-speed communication connection with the first connector 102 via the high-speed signal line 1014 .

[0136] In this embodiment, the repeater 1020 is a redriver, which is a physical layer conditioning device used for high-speed signal transmission.

[0137] In this embodiment, the high-speed signal line 1014 between the repeater 1020 and the second connector 103 is a high-speed signal input line.

[0138] In this embodiment, the repeater 1020 is used to compensate for the high-frequency loss caused by the intervening device to the high-speed signal, so as to ensure the function of the high-speed link.

[0139] In this embodiment, the repeater 1020 compensates for high frequency loss through equalization parameters.

[0140] The equalization parameters include but are not limited to high frequency loss dependent gain, isolation and dynamic power.

[0141] In this embodiment, the repeater 1020 needs to be grounded.

[0142] The repeater 1020 establishes a high-speed communication connection with the second connector 103 via the high-speed signal line 1014 .

[0143] In this embodiment, the high-speed signal line 1014 between the repeater 1020 and the second connector 103 is a high-speed signal output line.

[0144] The repeater 1020 is connected to the data selector 1022 via the second communication bus 1024 .

[0145] In this embodiment, the second communication bus 1024 is an I2C bus (Inter-Integrated Circuit, a bidirectional two-wire synchronous serial bus).

[0146] The signals transmitted by the second communication bus include unidirectional signals and bidirectional signals.

[0147] The data selector 1022 is connected to the programmable memory 1021 via the third communication bus 1025 .

[0148] In this embodiment, the third communication bus 1025 is an I2C bus (Inter-Integrated Circuit, a bidirectional two-wire synchronous serial bus).

[0149] In this embodiment, the programmable memory 1021 is used to store the firmware of the data selector 1022. The memory data of the programmable memory 1021 can be read or modified and burned through the I2C bus.

[0150] In this embodiment, the programmable memory 1021 is an EEPROM (Electrically-Erasable Programmable Read-Only Memory).

[0151] In this embodiment, the data selector 1022 is a MUX (Multiplexer).

[0152] The data selector 1022 and the jumper cap 1023 are connected via a jumper pin 1027 .

[0153] In this embodiment, the jumper cap 1023 is used to control the data selector 1022 to perform signal switching. The jumper cap 1023 is connected to the SEL (Select, input) pin of the data selector 1022 .

[0154] The data selector 1022 is connected to the pad 104 via a fourth communication bus 1026 .

[0155] In this embodiment, the fourth communication bus 1026 is an I2C bus (Inter-Integrated Circuit, a bidirectional two-wire synchronous serial bus).

[0156] In this embodiment, the data selector 1022 is used to switch the link connected to the programmable memory 1021 .

[0157] Specifically, the working process of the high-speed intervenor is as follows: after the first power supply unit is powered on, the jumper cap 1023 presets the link on the second communication bus 1024, the repeater 1020 loads the firmware in the programmable memory 1021 through the second communication bus 1024, and the logic processor 1012 reads the loaded firmware. After the device to be tested is started, the signal to be tested is transmitted from the mainboard to the backplane through the intervenor, and the intervenor diverts the signal to be tested to the logic processor 1012. The logic processor 1012 determines the level and level change of the signal to be tested, and sends the level and level change of the signal to be tested to the main control board via the pad 104.

[0158] In this embodiment, the firmware loaded by the logic processor 1012 is configured as follows: after receiving a test instruction from the main control board, the logic processor 1012 collects the default state and default value of the pin of the signal to be tested every 5 ms and compares the value with a preset level threshold. The low level threshold is 30% of the default value, and the high level threshold is 70% of the default value.

[0159] It can be seen from the above embodiments that by providing a repeater, signal compensation is performed on the high-speed signal transmitted from the first connector to the second connector, thereby avoiding loss of the high-speed signal and improving the reliability of the high-speed link.

[0160] Figure 3 Schematic diagram of the structure of the interventional device provided in the embodiment of the present application Figure 2 .like Figure 3 As shown, the main circuit module 101 includes: a second low-speed signal line 1028 and a third signal line 1029;

[0161] The first connector 102 is communicatively connected to the second connector 103 via the second low-speed signal line 1028 .

[0162] The pad 104 is connected to the second low-speed signal line 1028 through the third signal line 1029 .

[0163] In this embodiment, the third signal line is a low-speed signal line.

[0164] Specifically, the working process of the low-speed intervenor is as follows: after the first power supply unit is powered on, the device to be tested is started, and the signal is transmitted from the mainboard to the backplane through the intervenor. The intervenor diverts the signal to be tested to the main control board, and the programmable processor in the main control board determines the level and level change based on the signal to be tested.

[0165] As can be seen from the above embodiments, the signal to be tested is transmitted to the main control board via the intervenor, and the level and level change of the signal to be tested are determined by the main control board, which saves the device construction space inside the intervenor under low speed conditions.

[0166] Figure 4 This is a schematic diagram of the structure of the main control board provided in the embodiment of the present application. Figure 4 As shown, the main control board 20 includes: a programmable processor 201, a flash memory 202, a flash memory base 203, a third connector 204, a fourth connector 205 and a second power supply unit 206, as well as a serial port bus 207, a serial input bus 208, a serial output bus 209, a first communication line 210 and a second communication line 211;

[0167] The third connector 204 is connected to the pad 104 through the first communication line 210 .

[0168] In this embodiment, the third connector 204 includes a first sub-connector 2041 and a second sub-connector 2042 .

[0169] The first sub-connector 2041 is a high-speed sub-connector; the second sub-connector 2042 is a low-speed sub-connector.

[0170] In this embodiment, the first communication line 210 includes a fifth communication bus line 2101 and a third low-speed signal line 2102 .

[0171] The fifth communication bus 2101 is an I2C bus.

[0172] The signals transmitted by the fifth communication bus include unidirectional signals and bidirectional signals.

[0173] The third connector 204 is connected to the programmable processor 201 through the second communication line 211 .

[0174] In this embodiment, the second communication line 211 includes a sixth communication bus line 2111 and a fourth low-speed signal line 2112 .

[0175] The sixth communication bus 2111 is an I2C bus.

[0176] The signals transmitted by the sixth communication bus include unidirectional signals and bidirectional signals.

[0177] The programmable processor 201 is communicatively connected to the fourth connector 205 via the serial bus 207 .

[0178] In this embodiment, the programmable processor 201 is a Field Programmable Gate Array (FPGA).

[0179] In this embodiment, the serial port bus 207 is a UART (Universal Asynchronous Receiver / Transmitter) serial port bus.

[0180] The programmable processor 201 and the flash memory base 203 are communicatively connected via a serial input bus 208 .

[0181] In this embodiment, the serial input bus 208 is a SPI (full-duplex synchronous serial) bus.

[0182] In this embodiment, the programmable processor 201 reads the preset state in the firmware in the flash memory 202 through the serial input bus 208 and the flash memory base 203, compares the actual level state of the signal to be tested with the predicted state, and sends the comparison result to the client 30 through the serial port bus 207.

[0183] The flash memory base 203 and the flash memory 202 are communicatively connected via a serial output bus 209 .

[0184] In this embodiment, the flash memory base 203 is a detachable base of the flash memory 202 , and the flash memory 202 can be removed from the flash memory base 203 for firmware burning.

[0185] In this embodiment, the serial output bus 209 is a SPI (full-duplex synchronous serial) bus.

[0186] In this embodiment, the flash memory 202 is loaded with the firmware of the programmable processor 201 , and the firmware is provided with a level preset state and a level preset value.

[0187] The second power supply unit 206 is electrically connected to the programmable processor 201 , the flash memory 202 and the flash memory base 203 .

[0188] In this embodiment, the voltage provided by the second power supply unit is 3.3V.

[0189] It can be seen from the above embodiments that the level state and level change of the signal to be tested transmitted through the main control board receiving pad are compared with the preset level state set by the firmware in the programmable processor to generate a test result. There is no need to reserve test points on the device to be tested for testing, which improves the test efficiency.

[0190] In one embodiment of the present application, the third connector 204 includes a first sub-connector 2041 and a second sub-connector 2042; the first communication line 210 includes a fifth communication bus 2101 and a third low-speed signal line 2102; the second communication line 211 includes a sixth communication bus 2111 and a fourth low-speed signal line 2112;

[0191] The first sub-connector 2041 is connected to the pad 104 through the fifth communication bus 2101 .

[0192] In this embodiment, the fifth communication bus 2101 is an I2C bus.

[0193] The signals transmitted by the fifth communication bus include unidirectional signals and bidirectional signals.

[0194] The first sub-connector 2041 is connected to the programmable processor 201 through the sixth communication bus 2111 .

[0195] In this embodiment, the sixth communication bus 2111 is an I2C bus.

[0196] The signals transmitted by the sixth communication bus include unidirectional signals and bidirectional signals.

[0197] The second sub-connector 2042 is connected to the pad 104 through the third low-speed signal line 2102 .

[0198] The second sub-connector 2042 is connected to the programmable processor 201 through the fourth low-speed signal line 2112 .

[0199] In one embodiment of the present application, the main control board 20 further includes: a power conversion unit 212;

[0200] The power conversion unit 212 is electrically connected to the client 30 and is configured to convert the power supply voltage of the client 30 into a voltage of the second power supply unit 206 .

[0201] In this embodiment, the voltage output by the client 30 is 5V.

[0202] As can be seen from the above embodiments, the power supply voltage of the client is converted into the power supply voltage of the second power supply unit through the power conversion unit. The power conversion avoids the need for additional external power supply and reduces the complexity of the circuit.

[0203] In one embodiment of the present application, the main control board 20 further includes: a filter capacitor group 213 and a power line 214;

[0204] The filter capacitor bank 213 is connected to the second power supply unit 206 via a power line 214 .

[0205] In this embodiment, the capacitors in the filter capacitor group 213 are connected in parallel.

[0206] It can be seen from the above embodiments that by providing a filter capacitor group on the second power supply unit, the filter capacitor group is used to filter out power supply noise and ripple, thereby providing a purer voltage for the second power supply unit.

[0207] In one embodiment of the present application, the main control board 20 further includes: a voltage suppression component 215 and an interface protection line 216;

[0208] The voltage suppression component 215 is connected to the serial bus 207 via the interface protection line 216 .

[0209] In this embodiment, the voltage suppression component 215 is a bidirectional transient voltage suppression diode, which is used to protect the voltage of the programmable processor 201 .

[0210] As can be seen from the above embodiment, by providing a voltage suppression component, the interference voltage transmitted from the programmable processor to the fourth connector is filtered out, thereby avoiding device damage caused by overvoltage transmitted from the programmable processor to the fourth connector.

[0211] In one embodiment of the present application, the main control board 20 further includes: a dynamic random access memory 217 and a memory bus 218;

[0212] The dynamic random access memory 217 is connected to the programmable processor 201 through the memory bus 218 .

[0213] In this embodiment, the dynamic random access memory 217 is a DRAM (Dynamic Random Access Memory).

[0214] In this embodiment, the dynamic random access memory 217 is used to store historical test data.

[0215] In this embodiment, the memory bus 218 is a DDR (Double Data Rate) bus.

[0216] Specifically, the working process of the main control board 20 is as follows: the power conversion unit 212 converts the client's 5V power supply into the operating voltage 3.3V of the second power supply unit 206, the programmable processor 201 reads the firmware in the flash memory 202, obtains the preset level status and level change threshold in the firmware, compares the level status and level status threshold of the signal to be tested with the preset level status and level change threshold in the firmware, generates a test result, and transmits the test result to the dynamic random access memory 217. After the dynamic random access memory 217 saves the test result, the programmable processor 201 transmits the test result to the client 30 through the serial port bus 207.

[0217] In this embodiment, the firmware settings loaded by the programmable processor 201 are as follows: when the programmable processor 201 receives the test instruction sent by the client 30, it sends an acquisition instruction to the high-speed main circuit module of the intervenor. The high-speed intervenor collects the default state and default value of the pin of the signal to be tested every 5 ms. The programmable processor 201 compares the level information collected by the high-speed intervenor with the preset level threshold, where the low level threshold is 30% of the default value and the high level threshold is 70% of the default value.

[0218] It can be seen from the above embodiments that by providing a dynamic random access memory to store historical test data, it is convenient for the main control board to read the historical test data, thereby improving test efficiency.

[0219] Figure 5A flow chart of a printed circuit board assembly testing method provided in an embodiment of the present application. The method includes:

[0220] S501: The client sends a test instruction to the main control board in response to a user's trigger operation to start the test.

[0221] In this embodiment, the display interface of the client displays a compile window, and the user triggers the test start operation in the compile window.

[0222] In the compilation window, you can select the connector form of the device under test (wired connection or wireless plug-in), edit the expected state of the signal under test (normally high, normally low, high level converted to low level, low level converted to high level) and the default value of the high level, and compile to generate the burning file.

[0223] S502: The main control board monitors the level information of the signal to be tested according to the test instruction, generates a first test result according to the level information, and sends the first test result and the level information to the client.

[0224] Specifically, the main control board obtains the preset level state and level change threshold in the firmware, compares the level state and level state threshold of the signal to be tested with the preset level state and level change threshold in the firmware, and generates a test result.

[0225] S503: The client generates a second test result according to the level information.

[0226] Specifically, the client obtains the level information collected by the interventioner, compares the level state and the level change threshold in the level information with a preset level threshold, and generates a second test result.

[0227] S504: The client generates a comprehensive test result according to the first test result and the second test result.

[0228] In this embodiment, the client can read the test records stored in the dynamic random access memory of the main control board to obtain the test results.

[0229] Specifically, the client compares the first test result and the second test result to determine whether they are the same, and generates a comprehensive test result.

[0230] S505: The client outputs the comprehensive test results.

[0231] Specifically, the client displays the comprehensive test results on the client display interface.

[0232] In this embodiment, the comprehensive test results displayed by the client include but are not limited to the test results of the main control board, the test results of the client, the level status and level change value of the signal to be tested, and the expected state value of the signal to be tested.

[0233] It can be seen from the above embodiments that by initiating a test operation on the client, the main control board monitors the level information of the signal to be tested according to the test instructions, the client generates a test result based on the level information, and compares the test results of the client and the main control board to generate a comprehensive test result. The function of the signal to be tested is judged based on the comprehensive test result. There is no need to reserve test points on the circuit board for testing, which avoids the omission of test functions and improves test efficiency.

[0234] In one embodiment of the present application, before step S501, the following steps are further included:

[0235] S601: The client generates a pre-burned compiled file in response to a compilation operation by the user.

[0236] Specifically, the user selects the form of the connector to be tested on the client, edits the expected state of the signal to be tested and the high-level default value in each state, and generates a pre-burned compilation file through the compilation software.

[0237] S602: The client sends the pre-burned compiled file to the access device or the main control board, so that the access device or the main control board completes the burning of the compiled file.

[0238] Specifically, the pre-burned compilation file is sent to the logic processor of the intervenor and the programmable processor of the main control board, and the compilation file is burned into the logic processor and the programmable processor.

[0239] From the above embodiment, it can be seen that the client generates the compiled files pre-burned by the intervenor and the main control board, and sends the compiled files to the intervenor and the main control board respectively, thereby improving the test efficiency of the intervenor and the main control board.

[0240] In one embodiment of the present application, before step S601, the following steps are further included:

[0241] S701: The client obtains the user's compilation information.

[0242] In this embodiment, the user's compiled information includes but is not limited to the form of the connector to be tested, the expected state of the signal to be tested, the high level default value in each state, and the pin to be tested.

[0243] S702: The client verifies the pin information in the compilation information and determines whether the pin in the pin information is in an edited state.

[0244] Specifically, if all pins in the pin information are in an edited state, a burning file is generated.

[0245] S703: If there are unedited pins in the pin information, generate prompt information.

[0246] Specifically, if there are unedited pins in the pin information, a pop-up window will be displayed on the client interface to prompt the user of the unedited pin information and confirm whether the user ignores the unedited pins. A compilation file will be generated based on the unedited pin information confirmed by the user.

[0247] As can be seen from the above embodiment, by obtaining compilation information, determining whether there are unedited pins in the compilation information, and generating prompt information for the unedited pins, omission of pins to be tested in the circuit to be tested is avoided.

[0248] In one embodiment of the present application, after step S505, the following steps are further included:

[0249] S506: If the first test result and the second test result are different in the comprehensive test result, test difference information is obtained according to the first test result and the second test result, and alarm information is generated according to the test difference information.

[0250] Specifically, if the first test result is different from the second test result, the expected state of the signal to be tested and the actual state of the signal to be tested of the compared difference item are displayed, and an alarm prompt is generated.

[0251] As can be seen from the above embodiment, the test result of the client is compared with the test result of the main control board. If the comparison results are different, an alarm message is generated to prompt the tester to check the main control board and the intervenor.

[0252] In one embodiment of the present application, after step S505, the following steps are further included:

[0253] S801: If the comprehensive test result is a test abnormality, obtain abnormal pin information in the comprehensive test result.

[0254] Specifically, if in the comprehensive test result, the actual test level state is different from the expected level state, or the actual test level value exceeds the preset level threshold, the test result is marked as abnormal, and the abnormal pin in the abnormal result is obtained.

[0255] S802: Generate a preview page according to the abnormal pin information.

[0256] In this embodiment, the abnormal pin information displayed in the preview page includes but is not limited to the pin number of the abnormal pin, the level status of the abnormal pin, the level value of the abnormal pin, and the preset level status and level value of the abnormal pin.

[0257] S803: On the preview page, the abnormal pin is highlighted.

[0258] As can be seen from the above embodiment, by obtaining the abnormal pin information in the test results and highlighting the abnormal pin information, the tester can intuitively observe the abnormal pin.

[0259] The above is a detailed introduction to the printed circuit board assembly testing system and method provided by the present application. This article uses specific examples to illustrate the principles and implementation methods of the present application. The description of the above examples is only intended to help understand the method and core concept of the present application. It should be noted that for those skilled in the art, without departing from the principles of the present application, various improvements and modifications can be made to the present application, and such improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A printed circuit board assembly testing system, characterized in that: include: Intervention device (10), main control board (20) and client (30): The interventioner (10) comprises a main circuit module (101), a first connector (102), a second connector (103), and a solder pad (104); The main circuit module (101) is communicatively connected to the first connector (102), the second connector (103), and the soldering pad (104) respectively; The first connector (102) is communicatively connected to a mainboard (40) of the device under test; The second connector (103) is communicatively connected to the backplane (50) of the device under test; The soldering pad (104) is communicatively connected to the main control board (20); The main control board (20) is in communication connection with the client (30); The mainboard (40) of the device under test transmits the signal under test to the backboard (50) of the device under test via the first connector (102), the main circuit module (101), and the second connector (103) in sequence; The main circuit module (101) shunts the signal to be tested to the main control board (20) via the pad (104); the main control board (20) monitors changes in the signal to be tested to obtain a test result, and sends the test result to the client (30).

2. The printed circuit board assembly testing system according to claim 1, wherein: If the signal to be tested is a high-speed signal, the main circuit module (101) includes: a first power supply unit (1011), a logic processor (1012), a firmware burning module (1013), a high-speed signal line (1014), a first low-speed signal line (1015), a first signal line (1016), a second signal line (1017), a first communication bus (1018), and a firmware upgrade bus (1019); The first power supply unit (1011) is electrically connected to the logic processor (1012) and the firmware burning module (1013) respectively; The first connector (102) and the second connector (103) establish a high-speed communication connection via the high-speed signal line (1014); The first connector (102) and the second connector (103) establish a low-speed communication connection via the first low-speed signal line (1015); The logic processor (1012) is connected to the high-speed signal line (1014) via the first signal line (1016), and is connected to the first low-speed signal line (1015) via the second signal line (1017); The logic processor (1012) is connected to the pad (104) via the first communication bus (1018); The firmware burning module (1013) and the logic processor (1012) are communicatively connected via the firmware upgrade bus (1019).

3. The printed circuit board assembly testing system according to claim 2, wherein: The main circuit module (101) further includes: a repeater (1020), a programmable memory (1021), a data selector (1022) and a jumper cap (1023), as well as a second communication bus (1024), a third communication bus (1025), a fourth communication bus (1026) and a jumper pin header (1027); The repeater (1020) and the first connector (102) establish a high-speed communication connection via the high-speed signal line (1014); The repeater (1020) and the second connector (103) establish a high-speed communication connection via the high-speed signal line (1014); The repeater (1020) is connected to the data selector (1022) via the second communication bus (1024); The data selector (1022) is connected to the programmable memory (1021) via the third communication bus (1025); The data selector (1022) is connected to the jumper cap (1023) via the jumper pin header (1027); The data selector (1022) is connected to the pad (104) via the fourth communication bus (1026).

4. The printed circuit board assembly testing system according to claim 1, wherein: If the signal to be tested is a low-speed signal, the main circuit module (101) comprises: a second low-speed signal line (1028) and a third signal line (1029); The first connector (102) is communicatively connected to the second connector (103) via the second low-speed signal line (1028); The pad (104) is connected to the second low-speed signal line (1028) via the third signal line (1029).

5. The printed circuit board assembly testing system according to claim 1, wherein: The main control board (20) includes: a programmable processor (201), a flash memory (202), a flash memory base (203), a third connector (204), a fourth connector (205) and a second power supply unit (206), as well as a serial port bus (207), a serial input bus (208), a serial output bus (209), a first communication line (210) and a second communication line (211); The third connector (204) is connected to the pad (104) via the first communication line (210); The third connector (204) is connected to the programmable processor (201) via the second communication line (211); The programmable processor (201) and the fourth connector (205) are communicatively connected via the serial bus (207); The programmable processor (201) and the flash memory base (203) are communicatively connected via the serial input bus (208); The flash memory base (203) and the flash memory (202) are communicatively connected via the serial output bus (209); The second power supply unit (206) is electrically connected to the programmable processor (201), the flash memory (202) and the flash memory base (203).

6. The printed circuit board assembly testing system according to claim 5, wherein: The third connector (204) includes a first sub-connector (2041) and a second sub-connector (2042); the first communication line (210) includes a fifth communication bus (2101) and a third low-speed signal line (2102); the second communication line (211) includes a sixth communication bus (2111) and a fourth low-speed signal line (2112); The first sub-connector (2041) is connected to the pad (104) via the fifth communication bus (2101); The first sub-connector (2041) is connected to the programmable processor (201) via the sixth communication bus (2111); The second sub-connector (2042) is connected to the pad (104) via the third low-speed signal line (2102); The second sub-connector (2042) is connected to the programmable processor (201) via the fourth low-speed signal line (2112).

7. The printed circuit board assembly testing system according to claim 5, wherein: The main control board (20) further includes: a power conversion unit (212); The power conversion unit (212) is electrically connected to the client (30) and is used to convert the power supply voltage of the client (30) into the voltage of the second power supply unit (206).

8. The printed circuit board assembly testing system according to claim 5, wherein: The main control board (20) further includes: a filter capacitor group (213) and a power line (214); The filter capacitor group (213) is connected to the second power supply unit (206) via the power line (214).

9. The printed circuit board assembly testing system according to claim 5, wherein: The main control board (20) further includes: a voltage suppression component (215) and an interface protection line (216); The voltage suppression component (215) is connected to the serial port bus (207) via the interface protection line (216).

10. The printed circuit board assembly testing system according to claim 5, wherein: The main control board (20) further includes: a dynamic random access memory (217) and a memory bus (218); The dynamic random access memory (217) is connected to the programmable processor (201) via the memory bus (218).

11. A printed circuit board assembly testing method, characterized in that: A printed circuit board assembly testing system according to any one of claims 1 to 10, comprising: The client sends a test instruction to the main control board in response to a user's trigger operation of starting a test; The main control board monitors the level information of the signal to be tested according to the test instruction, generates a first test result according to the level information, and sends the first test result and the level information to the client; The client generates a second test result according to the level information; The client generates a comprehensive test result based on the first test result and the second test result; The client outputs the comprehensive test result.

12. The printed circuit board assembly testing method according to claim 11, wherein: The client, in response to a user's trigger operation for starting a test, sends a test instruction to the main control board, further comprising: The client generates a pre-burned compiled file in response to a compilation operation by the user; The client sends the pre-burned compiled file to the intervening device or the main control board, so that the intervening device or the main control board completes the burning of the compiled file.

13. The printed circuit board assembly testing method according to claim 12, wherein: The client, in response to a user's compiling operation, before generating a pre-burned compiled file, includes: The client obtains the compiled information of the user; The client verifies the pin information in the compilation information and determines whether the pin in the pin information is in an edited state; If there are unedited pins in the pin information, a prompt message is generated.

14. The printed circuit board assembly testing method according to claim 11, wherein: After the client outputs the comprehensive test result, the method further includes: If the first test result and the second test result are different in the comprehensive test result, test difference information is obtained according to the first test result and the second test result, and alarm information is generated according to the test difference information.

15. The printed circuit board assembly testing method according to claim 11, wherein: After the client outputs the comprehensive test result, the method further includes: If the comprehensive test result is a test abnormality, obtaining abnormal pin information in the comprehensive test result; Generate a preview page according to the abnormal pin information; On the preview page, abnormal pins are highlighted.

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