An optical computing architecture

Abstract

The application relates to the technical field of photonic computing, in particular to a light computing architecture, which comprises a plurality of photonic processors, a light source module, a high-speed data transceiver module connected with a multi-core data distributor and a multi-core data synthesizer, and the multi-core data distributor and the multi-core data synthesizer are connected with all the photonic processors through a bus structure. The initial light signal of the light source module is converted into a wavelength multiplexed light signal through a first optical demultiplexer, an optical beam splitter and an electro-optical modulation unit of a data loading module, parallel light computing is carried out by a light computing module, the output light signal is converted into an electrical signal by a data receiving module, and a processed electrical signal is output. In this way, on the basis of realizing matrix multiplexing through multi-wavelength multiplexing, the light computing architecture can realize core-level data multiplexing and matrix parallel operation through the synergistic effect of the multi-core distributor and the multi-core data synthesizer, thereby improving the throughput and computing efficiency of light computing.

Description

Technical Field

[0001] This application relates to the field of photonic computing technology, and more particularly to an optical computing architecture. Background Technology

[0002] Optical computing architecture refers to a system architecture that uses photons as information carriers to perform computational tasks. It mainly uses optical elements to perform parallel computational operations such as matrix operations and convolution in the optical domain. Compared with traditional electronic computing, optical computing architecture utilizes the physical characteristics of light, such as wavelength division multiplexing, low-latency propagation, and high parallelism, to achieve high-speed and low-power computing capabilities.

[0003] However, traditional optical computing architectures typically use demultiplexers to input different wavelengths into different waveguides, resulting in a single chip being able to perform only a single matrix operation and failing to achieve multi-wavelength parallel computing, which greatly limits throughput and computing efficiency.

[0004] Therefore, there is an urgent need for an optical computing architecture to improve the throughput and computational efficiency of optical computing. Summary of the Invention

[0005] This invention provides an optical computing architecture to improve the throughput and computational efficiency of optical computing.

[0006] Firstly, this application provides an optical computing architecture.

[0007] The architecture includes multiple photonic processors, a light source module, a high-speed data transceiver module, a multi-core data distributor, and a multi-core data synthesizer. The high-speed data transceiver module is connected to the multi-core data distributor and the multi-core data synthesizer. The multi-core data distributor and the multi-core data synthesizer are connected to all photonic processors through a bus structure. Each photonic processor includes a data loading module, an optical computing module, and a data receiving module.

[0008] The data loading module is used to decompose the initial optical signal generated by the light source module into multiple wavelength channels through a first optical demultiplexer to obtain multiple first optical signals; to perform energy equalization on each of the first optical signals through an optical beam splitter to obtain multiple second optical signals; and to load the parallel electrical signal of the high-speed data transceiver module into the second optical signal of the corresponding wavelength channel through an electro-optic modulation unit to generate wavelength multiplexed optical signals.

[0009] The optical computing module is used to perform parallel optical computing on the wavelength multiplexed optical signal based on a preset optical computing strategy and output the corresponding optical signal.

[0010] The data receiving module is used to convert the optical signal output by the optical computing module into an electrical signal and output the corresponding processed electrical signal.

[0011] The multi-core data allocator is used to synchronously load the same data to each photonic processor when the target address range covers all photonic processors, so as to realize multi-core data reuse.

[0012] Optionally, the data receiving module further includes a second optical demultiplexer, an optical detection unit, and a transimpedance amplifier.

[0013] The second optical demultiplexer is used to separate the optical signal output by the optical computing module into independent wavelength signals of multiple independent wavelength channels;

[0014] The optical detection unit is used to perform photoelectric conversion on each independent wavelength signal to obtain the corresponding current signal;

[0015] The transimpedance amplifier is used to perform linear conversion on each current signal to obtain the electrical signal.

[0016] Optionally, the light source module further includes a continuous wave laser, a frequency comb generation unit, and an optical amplifier.

[0017] The light source module is also used to generate a single-wavelength laser through the continuous wave laser, and to convert the single-wavelength laser into a flat frequency comb signal through the frequency comb generation unit.

[0018] The optical amplifier amplifies the power of the flat frequency comb signal and transmits the amplified flat frequency comb signal to each data loading module.

[0019] Optionally, the optical computing architecture further includes a high-speed data processing module for receiving processed electrical signals from each data receiving module, integrating the processed electrical signals into a new signal to be processed, and transmitting it to the high-speed data transceiver module.

[0020] Optionally, the high-speed data transceiver module is further used for:

[0021] The high-speed data processing module performs deserialization on the signal to be processed, and the resulting multiple parallel signals are transmitted to the data loading modules of each core through the multi-core data distributor.

[0022] Optionally, the high-speed data processing module is further used for:

[0023] Based on a preset feedback compensation strategy, feedback compensation is performed on each processed electrical signal to generate a feedback signal.

[0024] Based on the feedback signal and the signal to be processed, the signals are integrated to obtain a new signal to be processed.

[0025] Optionally, the data loading module is further configured to update the weight parameters of the electro-optic modulation unit based on the new signal to be processed; the weight parameters include the splitting ratio and the phase parameter.

[0026] Optionally, the plurality of photonic processors includes a master processor and at least one slave processor, wherein the master processor and the at least one slave processor form a distributed network.

[0027] The beneficial effects of this invention are as follows:

[0028] This application provides an optical computing architecture, which includes multiple photonic processors, a light source module, a high-speed data transceiver module, a multi-core data distributor, and a multi-core data synthesizer. The high-speed data transceiver module is connected to the multi-core data distributor and the multi-core data synthesizer. The multi-core data distributor and the multi-core data synthesizer are connected to all photonic processors via a bus structure. In each photonic processor, a data loading module uses a first optical demultiplexer to decompose the initial optical signal generated by the light source module into multiple independent wavelength channels. An optical beamsplitter then evenly distributes the energy of the first optical signal on each wavelength channel, achieving equal distribution of optical power. Next, an electro-optic modulation unit loads multiple parallel electrical signals from the high-speed data transceiver module onto the optical signals of the corresponding independent wavelength channels, combining them into a wavelength-multiplexed optical signal. The optical computing module performs parallel optical computation on the wavelength-multiplexed optical signal using a preset optical computing strategy, outputting the corresponding optical signal. Finally, a data receiving module converts the optical signal output by the optical computing module into an electrical signal, outputting the corresponding processed electrical signal. Thus, this application combines optical wavelength-level parallel computing. On the basis of performing independent matrix operations on a single core and multiple wavelengths, it realizes multi-core data reuse and flexible parallel matrix operations through a multi-core data distributor and a multi-core data synthesizer. This breaks through the limitations of single-core computing power, data transmission redundancy and multi-core collaborative efficiency bottlenecks, thereby improving the throughput and computing efficiency of optical computing. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of an optical computing architecture provided in an embodiment of this application;

[0031] Figure 2 A schematic diagram of a multi-core optical computing process provided for an embodiment of this application;

[0032] Figure 3This is a schematic diagram of the structure of a light source module provided in an embodiment of this application;

[0033] Figure 4 This is a schematic diagram of the structure of a data loading module provided in an embodiment of this application;

[0034] Figure 5 This is a schematic diagram of the structure of a data receiving module provided in an embodiment of this application;

[0035] Figure 6 A schematic diagram of the structure of a single-core photonic processor provided in an embodiment of this application;

[0036] Figure 7 A computational schematic diagram of a Mach-Zehnder interferometer network provided for embodiments of this application;

[0037] Figure 8 A schematic diagram of multi-wavelength calculation for a microring resonator provided in an embodiment of this application;

[0038] Figure 9 This is a schematic diagram of nonlinear calculation for a microring resonator provided in an embodiment of this application. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. Unless otherwise specified, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than that shown here.

[0040] The terms "first" and "second" in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the term "comprising" and any variations thereof are intended to cover non-exclusive protection. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices. The term "multiple" in this application can mean at least two, for example, two, three, or more, and this application does not impose limitations.

[0041] The term "and / or" in the embodiments of this application is merely a description of the association relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0042] The design concept of the embodiments of this application will be briefly introduced below.

[0043] Optical computing architecture refers to a system architecture that uses photons as information carriers to perform computational tasks. It mainly uses optical elements to perform parallel computational operations such as matrix operations and convolution in the optical domain. Compared with traditional electronic computing, optical computing architecture utilizes the physical characteristics of light, such as wavelength division multiplexing, low-latency propagation, and high parallelism, to achieve high-speed and low-power computing capabilities.

[0044] However, traditional optical computing architectures typically use demultiplexers to input different wavelengths into different waveguides, resulting in a single chip being able to perform only a single matrix operation, thus hindering multi-wavelength parallel computing and severely limiting throughput and computational efficiency. Furthermore, traditional technologies rely heavily on optical waveguide cascading and matrix splicing, which easily leads to optical signal crosstalk and increased loss, and can only utilize a limited number of wavelength channels, with the light source power insufficient to support ultra-large-scale computing. Existing technologies typically employ single-chip solutions with a limited number of electrical ports, further restricting the scale of matrix operations.

[0045] In view of the above problems, this application provides an optical computing architecture, which includes multiple photonic processors, a light source module, and a high-speed data transceiver module. Each photonic processor includes a data loading module, which can decompose the initial optical signal generated by the light source module into multiple independent wavelength channels through a first optical demultiplexer, physically isolating each wavelength, reducing signal crosstalk in traditional single-wavelength waveguides, and establishing an independent modulation path for each wavelength, laying the foundation for subsequent multi-wavelength parallel optical computing. An optical beamsplitter evenly distributes the energy of the first optical signal on each wavelength channel, achieving equal distribution of optical power and ensuring consistent intensity of the second optical signal in each wavelength channel. This blocks the cumulative error of traditional cascaded beam splitting from the source and avoids distortion caused by uneven power in subsequent modulation. Next, an electro-optic modulation unit loads multiple parallel electrical signals from the high-speed data transceiver module onto the optical signals of the corresponding independent wavelength channels, combining them into a single-wavelength multiplexed optical signal, i.e., a wavelength multiplexed optical signal. Thus, the optical computing architecture of this application enables each wavelength channel to independently carry parallel electrical signals, allowing multiple matrix operations to be executed simultaneously within a single chip. This overcomes the limitations of traditional single-wavelength serial computing and improves the throughput and computational efficiency of optical computing. Furthermore, this application loads multiple parallel electrical signals onto independent wavelength channels and then multiplexes them onto a single optical signal, expanding a single physical input port into multiple logical input ports. This supports thousands of parallel signal processing channels, overcoming the port number bottleneck of traditional architectures.

[0046] Furthermore, in this embodiment, the data loading module separates wavelengths using a first optical demultiplexer, modulates them independently using an electro-optic modulation unit, and then combines them using an optical multiplexer. This reduces crosstalk within the same waveguide, allowing each input port to carry multi-wavelength information, enabling parallel optical computing and significantly improving computing power without changing the chip design. Moreover, through the aforementioned parallel computing structure, this application can simultaneously complete multiple vector-matrix multiplication tasks on a single computing chip, achieving matrix multiplexing calculations with different data but the same matrix, significantly improving computing power density.

[0047] Furthermore, the optical computing architecture of this application also configures each photonic processor with an independent light source module and an independent optical amplifier, thereby compensating for splitting losses locally and avoiding cascaded power attenuation.

[0048] Furthermore, the optical computing architecture of this application also provides a dynamically adjustable feedback mechanism. By deserializing thousands of electrical signal inputs through a high-speed data transceiver module and dynamically compensating for uneven beam splitting through a high-speed data processing module, a closed-loop negative feedback mechanism is formed. This allows for real-time optimization of the optical modulation unit parameters, compensation for weak signal paths, improvement of the signal-to-noise ratio, and resolution of insufficient optical signal power and beam splitting errors. Simultaneously, it enables time-series superposition operations, expanding the temporal computing capabilities of the optical computing architecture and adapting it to nonlinear tasks such as deep learning.

[0049] Furthermore, in this embodiment, the multiple photonic processors include a master processor and at least one slave processor, forming a distributed network. Each photonic processor is not spatially connected but functions as an independent computing core, independently undertaking computational tasks. Each computing core can receive computation results from other computing cores as input to achieve continuous computation. Moreover, each photonic processor has an independent electrical port, facilitating integration while significantly increasing the number of electrical ports. By connecting multiple photonic processors using a multi-core data distributor 500 and a multi-core data synthesizer 501, computational tasks can be distributed to the optical computing units of each photonic processor, and results can be integrated through electrical signals, overcoming the limitation of the number of ports per core. Thus, this application, through a distributed network architecture, enables each optical computing core to be independent yet interconnected, achieving different computational matrices but reuse of input data, greatly improving the flexibility of optical computing.

[0050] The system architecture provided by exemplary embodiments of this application will now be described with reference to the accompanying drawings, such as... Figure 1 The diagram shown is a schematic representation of an optical computing architecture provided in an embodiment of this application. The system includes:

[0051] Multiple photonic processors 001, including a main processor (OPU1) and slave processors (OPU2~OPU2). m ).

[0052] The light source module 400 is used to generate the initial optical signal and transmit it to the data loading module of each photonic processor to provide a multi-wavelength light source and ensure optical power consistency.

[0053] The high-speed data transceiver module 002 is connected to the multi-core data distributor 500. It is used to receive electrical signals to be processed or processed electrical signals, and deserialize serial electrical signals into thousands of parallel signals. The same or different electrical signals are then input into the multi-core data distributor 500 to be transmitted to the data loading module 100 of each OPU core. This adapts to the needs of large-scale matrix operations and solves the bottleneck of electrical ports.

[0054] The multi-core data distributor 500 connects to the data input of each photonic processor via a bus, and obtains the data of the corresponding photonic processor by reading the target address range of the bus, thereby realizing the allocation of different cores and different computing tasks.

[0055] The multi-core data synthesizer 501 connects to the data outputs of each photonic processor via a bus. The output data is sorted on the bus in a specific time sequence to complete real-time parallel computing and real-time multi-core data splicing data synthesis processing. It also performs high-speed data transmission and processing through the high-speed data transceiver module 002 and the high-speed data processing module 003 to realize multi-core photonic processing.

[0056] The high-speed data processing module 003 is used to receive the output electrical signals of each data receiving module 300 and integrate them into a new signal to be processed, so that the high-speed data transceiver module 002 can perform subsequent processing based on the new signal to be processed, thereby realizing closed-loop control.

[0057] In one possible implementation, when the target address range of the multi-core data distributor 500 in this embodiment of the application covers all photonic processors, multiple photonic processors can synchronously load the same data, realizing data multiplexing where one data transmission is performed and multiple cores receive the data synchronously.

[0058] Specifically, the multi-core data allocator 500 controls the data flow through a target address range, thereby supporting multiple modes of distributed computing and data reuse computing. For example, specifying a single processor by target address allows for the allocation of independent tasks, while when the target address covers all processors, the same data can be loaded synchronously, enabling functions such as weight matrix reuse. Thus, in this embodiment, the multi-core data allocator 500 can achieve intelligent task allocation through address decoding, reducing redundant data transmission. Specifically, refer to... Figure 2 The diagram illustrates a multi-core optical computing process according to an embodiment of this application. After receiving the target address and target data, the multi-core data distributor 500 first determines whether to reuse the task flow. If reuse is used and the target address covers multiple cores, a shared data mode is executed. In this mode, after the optical computing core reads the target address, all photonic processors are selected and synchronously loaded with the reused data. If reuse is not used and the data corresponding to different target addresses is different, a distributed processing mode is executed. In this mode, the optical computing core selects different processors according to their address order to load the different data. After task distribution, each photonic processor obtains a balanced light source through the optical power equalizer 700. The data loading module 100 performs multi-wavelength parallel modulation, and the optical computing module 200 completes parallel multi-core optical computing based on the target data, generating independent outputs from calculation result 1 to calculation result n. Next, the multi-core data synthesizer 501 sorts and splices the calculation results through the timing bus, and finally outputs the parallel multi-core optical calculation results. The whole process realizes multi-core communication through the high-speed data transceiver module 002 and closed-loop feedback through the high-speed data processing module 003, forming a complete distributed multi-core multi-wavelength computing system.

[0059] In one possible implementation, the optical computing architecture in this application embodiment further includes an optical power divider 700, which is used to divide the energy of the initial optical signal generated by the light source module and transmit the obtained multiple optical signals to each photonic processor respectively.

[0060] Specifically, such as Figure 1As shown, the optical power equalizer 700 is located between the light source module 400 and each photonic processor, and distributes the multi-wavelength light source equally to each photonic processor 001, ensuring the consistency of the input optical power of each computing core from the source.

[0061] In one possible implementation, the main processor is connected to multiple slave processors to form a distributed network. Each OPU constitutes the core unit of the distributed optical computing architecture and can independently complete local optical computing tasks. Furthermore, each photonic processor includes a data loading module, an optical computing module, and a data receiving module to achieve parallel optical information processing of multiple wavelength data signals loaded simultaneously on the same waveguide and a single OPU, as well as parallel matrix operations of different data with the same matrix.

[0062] Specifically, in this application, each photonic processor 001 is not spatially spliced ​​but functions as an independent computing core, independently undertaking computing tasks. Each computing core can receive the computing results of other computing cores as input to achieve continuous computing. Furthermore, each photonic processor can be equipped with an independent electrical port, facilitating integration while significantly increasing the number of electrical ports. By connecting multiple photonic processors using a multi-core data distributor 500 and a multi-core data synthesizer 501, computing tasks can be distributed to the optical computing units of each photonic processor, and results can be integrated through electrical signals, overcoming the limitation of the number of ports per core. Thus, this application, through a distributed network architecture, enables each optical computing core to be independent yet interconnected, achieving different computing matrices but reuse of input data, greatly improving the flexibility of optical computing.

[0063] In one possible implementation, the optical beam splitter of the main OPU core (OPU1) in this application can be connected to each slave OPU core (OPU2-OPU) via an optical waveguide. m This forms a distributed computing network. Furthermore, the high-speed data transceiver modules of each OPU core can be connected through the multi-core data distributor 500 and the multi-core data synthesizer 501 to achieve electrical signal coordination and load balancing.

[0064] In one possible implementation, refer to Figure 3 The diagram shown is a schematic diagram of a light source module provided in an embodiment of this application. In this embodiment, the light source module 400 may include a continuous wave (CW) laser 401, a frequency comb generation unit 402, and an optical amplifier 403.

[0065] Specifically, the light source module 400 responds to an external laser driving signal, generating a single-wavelength laser through a continuous-wave laser 401, and converting the single-wavelength laser into a multi-wavelength flat frequency comb signal through a frequency comb generation unit 402 to provide a multi-wavelength light source. Next, the optical amplifier 403 amplifies the power of the flat frequency comb signal to obtain a processed initial optical signal, which is then input to the data loading module. The data loading module then passes through the optical beam splitter 104 to obtain multiple optical signals (I1, I2...I...) with consistent power. n Thus, this application can configure an independent light source module 400 for each OPU core and compensate for optical power loss locally through optical amplifier 403, avoiding insufficient power caused by cascading losses.

[0066] In one possible implementation, such as Figure 1 As shown, each photonic processor OPU in this application may include:

[0067] (1) Data loading module 100 is used to generate wavelength multiplexed optical signals based on the initial optical signal of light source module 400 and the parallel electrical signal after deserialization of high-speed data transceiver module 002, and transmit them to optical computing module 200.

[0068] (2) Optical computing module 200 is used to perform parallel optical computing based on a preset optical computing strategy and output the calculated optical signal to data receiving module 300.

[0069] (3) Data receiving module 300 is used to convert the optical signal output by the optical computing module into an electrical signal, that is, to output an electrical signal.

[0070] In one possible implementation, the data loading module in this embodiment may include a first optical demultiplexer, an optical beamsplitter, an electro-optic modulation unit, and an optical multiplexer. Specifically, the data loading module can use the first optical demultiplexer to decompose the initial optical signal input from the light source module into multiple wavelength channels, obtaining first optical signals on multiple wavelength channels. Then, the optical beamsplitter performs energy equalization processing on each first optical signal to obtain multiple equalized second optical signals. Next, the electro-optic modulation unit can load the parallel electrical signals from the high-speed data transceiver module onto the second optical signals of the corresponding wavelength channels, generating wavelength-multiplexed optical signals.

[0071] For details, please refer to Figure 4 The diagram shown is a structural schematic of a data loading module provided in an embodiment of this application. The data loading module 100 may include a first optical demultiplexer 101, an optical beam splitter 104, an electro-optic modulation unit 102, and an optical multiplexer 103.

[0072] Specifically, the data loading module can use the first optical demultiplexer 101 to decompose the initial optical signal input from the light source module 400 into multiple wavelength channels (such as...). Figure 4 The values ​​λ1, λ2...λ shown are shown. n-1 , λ n The system obtains first optical signals on multiple wavelength channels. The energy of each first optical signal is equally distributed through an optical beamsplitter 104 to obtain multiple second optical signals after energy equalization. The second optical signals of each wavelength channel are respectively connected to the corresponding electro-optic modulation unit 102, where intensity modulation is used to load the deserialized multiple electrical signals from the high-speed data transceiver module 002 onto the second optical signal of the corresponding wavelength channel. Thus, the modulated initial optical signals are re-bundled into a single optical fiber or waveguide by an optical multiplexer 103 to form wavelength-multiplexed optical signals, which are then output to the optical computing module 200 for subsequent processing. Therefore, this application adopts a multi-wavelength independent modulation architecture (λ1, λ2...λ...). n-1 , λ n The first optical demultiplexer 101 separates the wavelength channels and transmits them in the same waveguide, thereby ensuring balanced optical power of each wavelength and reducing crosstalk of long-distance signals.

[0073] In one possible implementation, refer to Figure 5 The diagram shown is a schematic of a data receiving module provided in an embodiment of this application. The data receiving module 300 may include a second optical demultiplexer 301, an optical detection unit 304, and a transimpedance amplifier 302.

[0074] Specifically, the data receiving module 300 can use the second optical demultiplexer 301 to separate the optical signal output by the optical computing module into independent wavelength signals on multiple independent wavelength channels (such as...). Figure 5 The λ1...λ shown n The photodetector unit 304 performs photoelectric conversion on each independent wavelength signal to obtain the corresponding current signal. Then, the transimpedance amplifier 302 performs linear conversion on each current signal to output the corresponding electrical signal, i.e., the processed electrical signal.

[0075] In one possible implementation, refer to Figure 6The diagram shows a schematic of a photonic processor OPU provided in an embodiment of this application. The initial optical signal generated by the light source module 400 is input to the single-core photonic processor and enters the data loading module 100. The first optical demultiplexer 101 decomposes the signal into multiple independent wavelength channels. An optical beam splitter then evenly distributes the optical power of each channel. Finally, an electro-optic modulation unit loads a high-speed parallel electrical signal onto the corresponding wavelength to generate a wavelength-multiplexed optical signal. This wavelength-multiplexed optical signal is sent to the optical computing module 200 for multi-wavelength parallel matrix operations. The operation result is transmitted to the data receiving module 300, where a photodetector separates the wavelengths and converts the optical signal into an electrical signal for output. The final result is integrated by the second optical demultiplexer 301 and output as processed data. Thus, the single-core OPU completes closed-loop processing, realizing multi-wavelength parallel computing and optoelectronic collaborative processing within a single chip. In one possible implementation, the optical computing module is composed of an optical computing chip that can support a variety of mainstream photonic computing architectures. The optical computing module can realize linear or nonlinear operations on optical signals through a preset optical computing strategy and combined with an optical waveguide structure. After completing optical computing tasks such as matrix multiplication and convolution, it outputs the optical signals to the data receiving module for subsequent processing.

[0076] Specifically, the optical computing strategies that can be selected for the optical computing module in this application include, but are not limited to: micro-ring resonator scheme and Mach-Zehnder interferometer (MZI) scheme (e.g., triangular, rectangular, parallelogram computing networks), etc.

[0077] Specifically, such as Figure 7 The diagram illustrates a computational schematic of a Mach-Zehnder interferometer network (MZI) provided in an embodiment of this application. This MZI network can be used to achieve discrete parallel computation of multi-wavelength signals. The target matrix is ​​decomposed to obtain the MZI network weights. Voltages are configured on the MZI network using an iterative method or a direct loading method to complete the matrix configuration. Multi-wavelength signals are input into the MZI network, and parallel computation is simultaneously completed during propagation due to interference effects. Signal detection and parallel information reading are performed at the output port.

[0078] Specifically, such as Figure 8The diagram illustrates a multi-wavelength calculation using a microring resonator provided in this application embodiment, which can be used to achieve multi-wavelength aliasing calculation. Multi-wavelength signals are input to the microring array via a transverse waveguide. Different microrings are adjusted to different resonant points, allowing different wavelength signals such as λ1, λ2, and λ3 to enter the vertical waveguide in different proportions. Different wavelengths are coupled by microrings in the same column but different rows according to preset weights. For example, a1 a2 a3, b1b2b3, and c1c2c3 represent the aliasing weights of different wavelength signals λ1, λ2, and λ3 in the first, second, or third column output channels, respectively. This enables arbitrary aliasing control of different wavelengths. The aliased multi-wavelength signals are output via the vertical waveguide, completing signal detection and parallel information reading.

[0079] Specifically, such as Figure 9 The diagram illustrates a nonlinear calculation using a microring resonator according to an embodiment of this application. The microring enables optoelectronic collaborative nonlinear calculation. Multiple wavelength optical signals (λ1, λ2, λ3, etc.) are input, and the sampling and control module extracts the intensity information of each wavelength signal in real time. This information is then converted into control signals and fed back to the bias control unit of the microring resonator, dynamically adjusting its resonant point. Utilizing the nonlinearity of the microring resonator, the output intensity changes nonlinearly under different input light intensities. Different input light intensities are then output to two separate output ports after adjustment: nonlinear output 1 and nonlinear output 2. This achieves synchronous wavelength-adaptive nonlinear transformation at both ports, overcoming the functional limitations of a single-channel output and providing dynamically adjustable optical computing hardware support for deep learning.

[0080] In one possible implementation, to address the issue of inconsistent signal strengths caused by uneven beam splitting or transmission loss, the high-speed data processing module 003 in this embodiment can perform feedback compensation on the output signals of each OPU core using a preset feedback compensation strategy, generating a feedback signal. The feedback signal and the signal to be processed are then integrated to generate a new signal to be processed. The data loading module updates the weight parameters of the electro-optic modulation unit based on the new signal to be processed, thereby forming a closed-loop control to balance the signal strengths of each path.

[0081] Specifically, in combination Figure 1 As shown, the photodetector unit in the data receiving module 300 detects the intensity of optical signals at each wavelength, and the transimpedance amplifier outputs the corresponding multiple electrical signals. The high-speed data processing module 003 compares the intensity of each electrical signal to identify weak signal paths (e.g., the intensity of λ1 is lower than that of λ2). The high-speed data processing module can generate a feedback signal 600 for the weak path, which is a voltage-driven signal. The feedback signal 600 is input to the electro-optic modulation unit 102 of the data loading module, thereby fine-tuning the splitting ratio of the weak path (e.g., increasing the modulation voltage of λ2). In this way, the light intensity of the weak signal path is improved, so that the data receiving module outputs electrical signals with consistent intensity, i.e., processed electrical signals, making the power of each wavelength balanced and eliminating the accumulation of static errors.

[0082] Specifically, in this application, the feedback signal is processed by the high-speed data module according to the calculation program, rearranged according to the timing and format of the input signal, superimposed on the signal to be processed, and input into the high-speed data transceiver module, which then distributes it to each OPU. The data loading module of each OPU then drives the electro-optic modulation unit to dynamically adjust the weight parameters such as the splitting ratio and phase according to the new signal to be processed, so as to update the weights of the optical computing unit.

[0083] In one possible implementation, for training tasks requiring real-time updates, the optical detection unit outputs an electrical signal corresponding to the calculation result, and the high-speed data processing module converts the electrical signal into a calculation result vector. An external computing unit provides the target result (e.g., label data), and the high-speed data processing module compares the target with the calculation result to generate a loss vector. Based on the loss vector, it calculates the weight update value using an iterative algorithm (e.g., gradient descent). The high-speed data processing module decomposes the weight update value into a splitting ratio or phase parameter and sends it to the high-speed data transceiver module via a feedback signal. The transceiver module deserializes the received serial electrical signal into thousands of parallel signals, driving the electro-optic modulation unit to adjust the weight parameters of the optical computing module in real time.

[0084] Specifically, in this application, an external computing unit generates a target matrix. The high-speed data processing module generates an electro-drive signal based on the weight parameters of the target matrix, such as the splitting ratio and phase shift, to adjust the splitting ratio and phase of the electro-optic modulation unit in real time. The external computing unit may include, but is not limited to, a graphics processing unit (GPU) or a central processing unit (CPU), providing initial or intermediate data for the optical computing architecture of this application. After receiving multi-wavelength optical signals from each OPU core, the high-speed data processing module can compensate for weaker signal paths according to a feedback compensation strategy for signal strength consistency, i.e., adjusting the splitting ratio through feedback signals to achieve balanced signal strength across all paths. Furthermore, in this process, the multi-core data allocator 500 and the multi-core data synthesizer 501 can support real-time updates of the weight parameters of the optical computing module among multiple cores, supporting dynamic weight synchronization updates and adapting to nonlinear computing tasks (e.g., deep learning dynamic weights).

[0085] In one possible implementation, combined with Figure 1As shown, based on the optical computing architecture of this application embodiment, the electrical signal to be processed is preprocessed by the high-speed data processing module 003, and then input to the high-speed data transceiver module 002 for signal deserialization. The split electrical signal is transmitted to the data loading module 100 of each photonic processor through the multi-core data distributor 500 to achieve electro-optical conversion. The optical signal generated by the light source module 400 is evenly split and then demultiplexed into multi-wavelength optical signals by the first demultiplexer in the data loading module 100. Subsequently, the electrical signal is loaded into each wavelength by intensity modulation by the electro-optic modulation unit to obtain wavelength-multiplexed optical signals. The optical computing module 200 performs parallel operations on the wavelength-multiplexed optical signals, and the calculation results are transmitted to the data receiving module 300 in the form of optical signals. The optical signals are converted into electrical signals by the photodetector unit therein, and collected into digital signals by the analog-to-digital converter therein. Thus, the calculated digital data enters the high-speed data processing module 003 through the multi-core data synthesizer 501 and the high-speed data transceiver module 002 to complete data collection and storage. For data that requires iterative calculation, this embodiment of the application calculates the data using a high-speed digital-to-analog processing module and an external computing unit. The processed feedback signal 600 can be combined with the signal to be processed to form a new signal to be processed, and the overall weights can be readjusted in the multi-core photonic processor architecture.

[0086] In one possible implementation, the operation process of the optical computing mechanism of this application embodiment can be as follows: the electrical signal to be processed can first be input into the high-speed data transceiver module to complete the serial-to-parallel conversion, and the parallel electrical signal generated by deserialization can be distributed to the data loading module of each OPU through the multi-channel interface. The data loading module adopts a hierarchical optical-to-electrical signal conversion design.

[0087] The light source module employs a distributed design to ensure multi-core scalability. A continuous-wave laser generates the initial optical signal, which is then converted into a multi-wavelength light source via an optical frequency comb. An optical amplifier compensates for splitting losses, ensuring consistent optical power across each OPU core. The continuous-wave optical signal generated by the light source module is then evenly distributed to multiple OPUs via an optical beam splitter. Within each OPU core, the optical signal is separated into preset wavelengths by a first optical demultiplexer and input to an independent electro-optic modulation unit. The electrical signal to be processed is deserialized into thousands of parallel signals by a high-speed data transceiver module, driving the electro-optic modulation unit to load the signal onto the corresponding wavelength. The modulated multi-wavelength optical signals are then combined into a single-channel multiplexed signal via an optical multiplexer and input to the optical computing module via a low-loss optical waveguide.

[0088] The optical computing module constructs a parallel computing network using optical computing schemes such as micro-ring resonators or Mach-Zehnder interferometers. The wavelength-multiplexed optical signals, after being bundled, perform matrix multiplication or convolution operations in the optical waveguide, utilizing the physical isolation characteristics of different wavelengths to reduce signal crosstalk. The computation results obtained by the optical computing module are output to the data receiving module in the form of optical signals, eliminating the need for photoelectric conversion throughout the process and significantly reducing latency.

[0089] The data receiving module employs a collaborative architecture of optical demultiplexing and electrical amplification. The input optical signal is separated into independent wavelengths (λ1-λ2) by a second optical demultiplexer. n Each wavelength corresponds to a photodetector unit that performs photoelectric conversion. The generated micro-current signal is converted into a high signal-to-noise ratio electrical signal by a transimpedance amplifier array, and finally integrated into a complete calculation result by a high-speed data processing module. In the above process, the high-speed data transceiver module and the high-speed data processing module can coordinate with each other through a multi-core data distributor 500 and a multi-core data synthesizer 501. Furthermore, the splitting ratio and phase parameters of the electro-optic modulation unit are adjusted in real time by the feedback signal generated by the high-speed digital-to-analog processing module and the external computing unit to achieve dynamic weight updates and adapt to the requirements of nonlinear tasks such as deep learning.

[0090] For ease of description, the above sections are divided into functional units (or modules) and described separately. Of course, in implementing this application, the functions of each unit (or module) can be implemented in one or more software or hardware components. Those skilled in the art will understand that various aspects of this application can be implemented as systems, methods, or program products. Therefore, various aspects of this application can be specifically implemented in the following forms: a completely hardware implementation, a completely software implementation (including firmware, microcode, etc.), or a combination of hardware and software implementations, collectively referred to herein as "circuit," "module," or "system."

[0091] It should be noted that although several units or sub-units of the device have been mentioned in the detailed description above, this division is merely exemplary and not mandatory. In fact, according to embodiments of this application, the features and functions of two or more units described above can be embodied in one unit. Conversely, the features and functions of one unit described above can be further divided and embodied by multiple units.

[0092] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0093] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. An optical computing architecture, characterized in that, The architecture includes multiple photonic processors, a light source module, a high-speed data transceiver module, a multi-core data distributor, and a multi-core data synthesizer. The high-speed data transceiver module is connected to the multi-core data distributor and the multi-core data synthesizer. The multi-core data distributor and the multi-core data synthesizer are connected to all photonic processors through a bus structure. Each photonic processor includes a data loading module, an optical computing module, and a data receiving module. The data loading module is used to decompose the initial optical signal generated by the light source module into multiple wavelength channels through a first optical demultiplexer to obtain multiple first optical signals; and to perform energy equalization on each of the first optical signals through an optical beam splitter to obtain multiple second optical signals. The parallel electrical signal of the high-speed data transceiver module is loaded onto the second optical signal of the corresponding wavelength channel through the electro-optic modulation unit to generate a wavelength multiplexed optical signal. The optical computing module is used to perform parallel optical computing on the wavelength multiplexed optical signal based on a preset optical computing strategy and output the corresponding optical signal. The data receiving module is used to convert the optical signal output by the optical computing module into an electrical signal and output the corresponding processed electrical signal. The high-speed data transceiver module is used to deserialize the signal to be processed by the high-speed data processing module and transmit the obtained multiple parallel signals to the data loading module of each photonic processor through the multi-core data distributor. The multi-core data allocator is used to synchronously load the same data to each photonic processor when the target address range covers all photonic processors, so as to realize multi-core data reuse. The multi-core data synthesizer connects the data outputs of each photonic processor via a bus. The output data is sorted on the bus in a specific time sequence to complete real-time parallel computing and real-time multi-core data splicing data synthesis processing.

2. The architecture as described in claim 1, characterized in that, The data receiving module also includes a second optical demultiplexer, an optical detection unit, and a transimpedance amplifier. The second optical demultiplexer is used to separate the optical signal output by the optical computing module into independent wavelength signals of multiple independent wavelength channels; The optical detection unit is used to perform photoelectric conversion on each independent wavelength signal to obtain the corresponding current signal; The transimpedance amplifier is used to perform linear conversion on each current signal to obtain the electrical signal.

3. The architecture as described in claim 1, characterized in that, The light source module also includes a continuous wave laser, a frequency comb generation unit, and an optical amplifier. The light source module is also used to generate a single-wavelength laser through the continuous wave laser, and to convert the single-wavelength laser into a flat frequency comb signal through the frequency comb generation unit. The optical amplifier amplifies the power of the flat frequency comb signal and transmits the amplified flat frequency comb signal to each data loading module.

4. The architecture as described in claim 1, characterized in that, The optical computing architecture also includes a high-speed data processing module, which receives the processed electrical signals from each data receiving module, integrates the processed electrical signals into a new signal to be processed, and transmits it to the high-speed data transceiver module.

5. The architecture as described in claim 1, characterized in that, The high-speed data processing module is also used for: Based on a preset feedback compensation strategy, feedback compensation is performed on each processed electrical signal to generate a feedback signal. Based on the feedback signal and the signal to be processed, the signals are integrated to obtain a new signal to be processed.

6. The architecture as described in claim 5, characterized in that, The data loading module is also used to update the weight parameters of the electro-optic modulation unit based on the new signal to be processed; the weight parameters include the splitting ratio and the phase parameter.

7. The architecture as described in claim 1, characterized in that, The plurality of photonic processors includes a master processor and at least one slave processor, wherein the master processor and the at least one slave processor form a distributed network.

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