A cordic computation circuit, computation method, and accelerated computation system

Abstract

The application discloses a Cordic computing circuit, a computing method and an accelerated computing system, and relates to the technical field of electronic circuits.A Cordic computing circuit comprises a logic control module, an X computing module and a Y computing module; the logic control module is connected with the X computing module and the Y computing module; the logic control module is used for determining a computing execution signal and a computing type signal according to an obtained X input value, a Y input value and a computing order; the X computing module is used for obtaining the X input value, performing computation on the X input value according to the computing execution signal and outputting an X computing result; and the Y computing module is used for obtaining the Y input value, performing computation on the Y input value according to the computing execution signal and outputting a Y computing result.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuits, in particular to a Cordic calculation circuit, a calculation method and an accelerated calculation system. BACKGROUND

[0002] The traditional Cordic algorithm circuit has the problem of non-convergent circle near the origin of the coordinate system in the vector mode. When the input solving point falls within the non-convergent circle, the final solved angle will have a huge deviation, resulting in non-convergent calculation results.

[0003] The number of rotations of the traditional Cordic algorithm circuit when solving is fixed in the circuit implementation, but for regular Cordic applications, a large number of rotations are not needed in most cases, which will result in wasted invalid calculation time.

[0004] Although the traditional Cordic algorithm circuit has replaced a large number of multiplication calculations with addition calculations to optimize the calculation circuit and save the calculation amount, due to the large calculation bit width of the Cordic algorithm, the use of traditional multi-bit adders will still bring about large delay critical paths and calculation overheads, and replacing full adders with or gates in low bits can truncate the critical path, effectively accelerating the circuit. At the same time, since the low bits of the approximate calculation region are mostly 0, using or gates for addition calculation will not bring about too much error. Therefore, there is an urgent need for a Cordic calculation circuit, a calculation method and an accelerated calculation system to overcome the above problems. SUMMARY

[0005] To solve the above problems, the present application provides the following technical solutions:

[0006] In a first aspect, a Cordic calculation circuit is provided, comprising a logic control module 100, an X calculation module 200 and a Y calculation module 300.

[0007] The logic control module 100 is connected to the X calculation module 200 and the Y calculation module 300.

[0008] The logic control module 100 is configured to determine a calculation execution signal and a calculation type signal according to the obtained X input value Xin, Y input value Yin and calculation order i.

[0009] The X calculation module 200 is configured to obtain the X input value Xin and perform calculation on the X input value Xin according to the calculation execution signal and output an X calculation result.

[0010] In response to performing calculation on the X input value Xin, the X calculation module 200 is configured to perform full addition calculation or approximate addition calculation on the X input value Xin according to the calculation type signal.

[0011] The Y calculation module 300 is configured to obtain the Y input value Yin, and perform calculation on the Y input value Yin according to the calculation execution signal and output the Y calculation result.

[0012] In response to performing calculation on the Y input value Yin, the full-addition calculation or the approximate addition calculation is performed on the Y input value Yin according to the calculation type signal.

[0013] Further, the logic control module 100 has a logic first port 100a, a logic second port 100b, a logic third port 100c, a logic fourth port 100d, a logic fifth port 100e, a logic sixth port 100f and a logic seventh port 100g.

[0014] The X calculation module 200 has an X calculation first port 200a, an X calculation second port 200b, an X calculation third port 200c, an X calculation fourth port 200d, an X calculation fifth port 200e and an X calculation sixth port 200f.

[0015] The Y calculation module 300 has a Y calculation first port 300a, a Y calculation second port 300b, a Y calculation third port 300c, a Y calculation fourth port 300d, a Y calculation fifth port 300e and a Y calculation sixth port 300f.

[0016] The logic first port 100a is connected with the X calculation first port 200a, configured to obtain the X input value Xin, the logic second port 100b is connected with the Y calculation first port 300a, configured to obtain the Y input value Yin, the logic third port 100c is configured to obtain the calculation order i, the logic fourth port 100d is connected with the X calculation fourth port 200d and the X calculation fifth port 200e, the logic fifth port 100e is connected with the Y calculation fourth port 300d and the Y calculation fifth port 300e, the logic sixth port 100f is connected with the X calculation second port 200b and the Y calculation second port 300b, the logic seventh port 100g is connected with the X calculation third port 200c and the Y calculation third port 300c, the X calculation sixth port 200f is configured to output the X calculation result, and the Y calculation sixth port 300f is configured to output the Y calculation result.

[0017] Further, the logic control module 100 includes a first shifter 110, a second shifter 120, a first determinator 130, a second determinator 140, a third determinator 150, a first exclusive-OR gate 160, a second exclusive-OR gate 170, a third exclusive-OR gate 180 and a fourth exclusive-OR gate 190.

[0018] The first shifter 110 has a first value input end 110a, a first order input end 110b and a first value output end 110c.

[0019] The second shifter 120 has a second numerical input end 120a, a second order input end 120b, and a second numerical output end 120c.

[0020] The first numerical input end 110a is a logical first port 100a, the second numerical input end 210a is a logical second port 100b, the first order input end 110b and the second order input end 120b are connected to be a logical third port 100c, the first numerical output end 110c is connected to one input end of the third XOR gate 180, the other input end of the third XOR gate 180 is connected to one input end of the first XOR gate 160, one input end of the second XOR gate 170, and the output end of the first judging device 130, the output end of the third XOR gate 180 is a logical fifth port 100e, the second numerical output end 120c is connected to the input end of the first judging device 130, the other input end of the first XOR gate 160, one input end of the fourth XOR gate 190, and the other input end of the second XOR gate 170, the output end of the first XOR gate 160 is connected to the input end of the second judging device 140, the output end of the second judging device 140 is a logical sixth port 100f, the output end of the second XOR gate 170 is a logical fourth port 100d, the output end of the fourth XOR gate 190 is connected to the input end of the third judging device 150, and the output end of the third judging device 150 is a logical seventh port 100g.

[0021] Further, the X computing module 200 includes an X channel selection unit 210, an X full adder unit 220, and an X approximate adder unit 230.

[0022] The X channel selection unit 210 has an X channel first port 210a, an X channel second port 210b, an X channel third port 210c, an X channel fourth port 210d, an X channel fifth port 210e, and an X channel sixth port 210f.

[0023] The X channel first port 210a is connected to one input end of the X full adder unit 220 and one input end of the X approximate adder unit 230 to be an X computing first port 200a, the X channel second port 210b is an X computing sixth port 200f, the X channel third port 210c is connected to the output end of the X full adder unit 220, the X channel fourth port 210d is connected to the output end of the X approximate adder unit 230, the X channel fifth port 210e is an X computing second port 200b, the X channel sixth port 210f is an X computing third port 200c, the other input end of the X full adder unit 220 is an X computing fourth port, and the other input end of the X approximate adder unit 230 is an X computing fifth port 200e.

[0024] Further, the X channel selection unit 210 comprises a first channel selector 211 and a second channel selector 212.

[0025] The first channel selector 211 has a first selector first input end 211a, a first selector second input end 211b, a first selector output end 211c and a first selector selection end 211d.

[0026] The second channel selector 212 has a second selector first input end 212a, a second selector second input end 212b, a second selector output end 212c and a second selector selection end 212d.

[0027] The first selector first input end 211a is the X channel first port 210a, the first selector output end 211c is the X channel second port 210b, the first selector selection end 211d is the X channel fifth port 210e, the first selector second input end 211b is connected with the second selector output end 212c, the second selector first input end 212a is the X channel fourth port 210d, the second selector second input end 212b is the X channel third port 210c, and the second selector selection end 212d is the X channel sixth port 210f.

[0028] Further, the Y calculation module 300 comprises a Y channel selection unit 310, a Y full adder unit 320 and a Y approximate adder unit 330.

[0029] The Y channel selection unit 310 has a Y channel first port 310a, a Y channel second port 310b, a Y channel third port 310c, a Y channel fourth port 310d, a Y channel fifth port 310e and a Y channel sixth port 310f.

[0030] The Y channel first port 310a is connected with one input end of the Y full adder unit 320 and one input end of the Y approximate adder unit 330 and then serves as the Y calculation first port 300a, the Y channel second port 310b serves as the Y calculation sixth port 300f, the Y channel third port 310c is connected with the output end of the Y full adder unit 320, the Y channel fourth port 310d is connected with the output end of the Y approximate adder unit 330, the Y channel fifth port 310e serves as the Y calculation second port 300b, the Y channel sixth port 310f serves as the Y calculation third port 300c, the other input end of the Y full adder unit 320 serves as the Y calculation fourth port, and the other input end of the Y approximate adder unit 330 serves as the Y calculation fifth port 300e.

[0031] Further, the Y channel selection unit 310 comprises a third channel selector 311 and a fourth channel selector 312.

[0032] The third channel selector 311 has a third selector first input end 311a, a third selector second input end 311b, a third selector output end 311c and a third selector selection end 311d.

[0033] The fourth channel selector 312 has a fourth selector first input end 312a, a fourth selector second input end 312b, a fourth selector output end 312c and a fourth selector selection end 312d.

[0034] The third selector first input end 311a is the Y channel first port 310a, the third selector output end 311c is the Y channel second port 310b, the third selector selection end 311d is the Y channel fifth port 310e, the third selector second input end 311b is connected with the fourth selector output end 312c, the fourth selector first input end 312a is the Y channel fourth port 310d, the fourth selector second input end 312b is the Y channel third port 310c, and the fourth selector selection end 312d is the Y channel sixth port 310f.

[0035] In a second aspect, a Cordic calculation method is provided, which is applicable to the Cordic calculation circuit in the first aspect, and includes the following steps:

[0036] S100: obtaining an X input value, a Y input value and a calculation order i.

[0037] S200: shifting the X input value and the Y input value according to the calculation order i.

[0038] S300: determining a calculation type signal according to the Y transformed value.

[0039] S400: determining a calculation execution signal according to the X transformed value and the Y transformed value.

[0040] S500: transmitting the calculation type signal and the calculation execution signal to an X calculation module and a Y calculation module of the Cordic calculation circuit, so that the X calculation module calculates an X calculation result and the Y calculation module calculates a Y calculation result.

[0041] Further, the method further includes: taking the calculation result of the current order as the input value of the next order, and repeating the Cordic calculation method until the calculation result corresponding to the calculation order is obtained.

[0042] In a third aspect, an acceleration calculation system is provided, which includes a configuration register, a data register, an error feedback unit, a coordinate system deployment unit, a data pre / post-processing unit, a pre-stored lookup table and a Cordic array.

[0043] The Cordic array comprises at least one Cordic calculation circuit according to the first aspect.

[0044] The configuration register is connected with the error feedback unit, the coordinate system adjusting unit and the data pre / post-processing unit, the data register is connected with the error feedback unit, the coordinate system adjusting unit and the data pre / post-processing unit, and the coordinate system adjusting unit is connected with the error feedback unit, the data pre / post-processing unit, the pre-stored lookup table and the Cordic array.

[0045] The Cordic calculation circuit, the calculation method and the acceleration calculation system according to the embodiments of the present application can remove the non-convergent circle of the traditional Cordic calculation unit near the coordinate point of the coordinate system 0, reduce the complexity of the pre-processing in the Cordic calculation module, reduce the timing constraint requirement of the Cordic calculation module under high frequency, optimize the addition array in the Cordic calculation unit, shorten the critical path, improve the adaptability of the Cordic calculation unit to higher frequency, and achieve the purpose of further accelerating the Cordic calculation, and introduce the rotation stopping mechanism for the Cordic calculation, so that the Cordic calculation can be pipelined under high frequency. BRIEF DESCRIPTION OF DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0047] Figure 1 is a Cordic calculation circuit schematic diagram provided by the embodiments of the present application;

[0048] Figure 2 is a Cordic calculation circuit execution logic schematic diagram provided by the embodiments of the present application;

[0049] Figure 3 is a Cordic calculation method schematic diagram provided by the embodiments of the present application;

[0050] Figure 4 is an acceleration calculation system provided by the embodiments of the present application. DETAILED DESCRIPTION

[0051] In order to make the objects, technical solutions and advantages of the present application clearer, the following will be used in conjunction with the accompanying drawings for a clear and complete description of the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application and not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0052] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning as understood by a person of ordinary skill in the art to which the present disclosure belongs. The terms "first", "second" and similar terms used in the present disclosure do not denote any order, quantity or importance, but are used to distinguish different components. Similarly, the terms "one", "a" or "the" and similar terms do not denote a quantity limitation, but mean that there is at least one. The numbers in the drawings of the specification only represent the distinction of the respective functional components or modules, and do not represent the logical relationship between the components or modules. The terms "include" or "contain" and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right" and the like only represent relative positional relationships, which can change accordingly when the absolute position of the described object changes.

[0053] In the following, various embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that in the drawings, the same reference signs are assigned to components having substantially the same or similar structure and function, and repeated description about them will be omitted.

[0054] In view of the foregoing, the present application provides the following embodiments.

[0055] In some embodiments, as shown in FIG. 1, a Cordic calculation circuit includes a logic control module 100, an X calculation module 200 and a Y calculation module 300. Figure 1

[0056] The logic control module 100 is connected with the X calculation module 200 and the Y calculation module 300.

[0057] The logic control module 100 is configured to determine a calculation execution signal and a calculation type signal according to an obtained X input value Xin, a Y input value Yin and a calculation order i.

[0058] ​The X calculation module 200 is configured to obtain an X input value Xin, and perform calculation on the X input value Xin according to a calculation execution signal and output an X calculation result.

[0059] In response to performing calculation on the X input value Xin, full add calculation or approximate addition calculation is performed on the X input value Xin according to a calculation type signal.

[0060] The Y calculation module 300 is configured to obtain a Y input value Yin, and perform calculation on the Y input value Yin according to a calculation execution signal and output a Y calculation result.

[0061] In response to performing calculation on the Y input value Yin, full add calculation or approximate addition calculation is performed on the Y input value Yin according to a calculation type signal.

[0062] Specifically, the logic control module 100 has a logic first port 100a, a logic second port 100b, a logic third port 100c, a logic fourth port 100d, a logic fifth port 100e, a logic sixth port 100f and a logic seventh port 100g.

[0063] The X calculation module 200 has an X calculation first port 200a, an X calculation second port 200b, an X calculation third port 200c, an X calculation fourth port 200d, an X calculation fifth port 200e and an X calculation sixth port 200f.

[0064] The Y calculation module 300 has a Y calculation first port 300a, a Y calculation second port 300b, a Y calculation third port 300c, a Y calculation fourth port 300d, a Y calculation fifth port 300e and a Y calculation sixth port 300f.

[0065] The logic first port 100a is connected with the X calculation first port 200a, configured to obtain an X input value Xin, the logic second port 100b is connected with the Y calculation first port 300a, configured to obtain a Y input value Yin, the logic third port 100c is configured to obtain a calculation order i, the logic fourth port 100d is connected with the X calculation fourth port 200d and the X calculation fifth port 200e, the logic fifth port 100e is connected with the Y calculation fourth port 300d and the Y calculation fifth port 300e, the logic sixth port 100f is connected with the X calculation second port 200b and the Y calculation second port 300b, the logic seventh port 100g is connected with the X calculation third port 200c and the Y calculation third port 300c, the X calculation sixth port 200f is configured to output an X calculation result, and the Y calculation sixth port 300f is configured to output a Y calculation result.

[0066] Specifically, the logic control module 100 comprises a first shifter 110, a second shifter 120, a first determinator 130, a second determinator 140, a third determinator 150, a first XOR gate 160, a second XOR gate 170, a third XOR gate 180 and a fourth XOR gate 190.

[0067] The first shifter 110 has a first value input end 110a, a first order input end 110b and a first value output end 110c.

[0068] The second shifter 120 has a second value input end 120a, a second order input end 120b and a second value output end 120c.

[0069] The first value input end 110a is a logic first port 100a, the second value input end 210a is a logic second port 100b, the first order input end 110b and the second order input end 120b are connected and are a logic third port 100c, the first value output end 110c is connected with one input end of the third XOR gate 180, the other input end of the third XOR gate 180 is connected with one input end of the first XOR gate 160, one input end of the second XOR gate 170 and an output end of the first determinator 130, the output end of the third XOR gate 180 is a logic fifth port 100e, the second value output end 120c is connected with an input end of the first determinator 130, the other input end of the first XOR gate 160, one input end of the fourth XOR gate 190 and the other input end of the second XOR gate 170, the output end of the first XOR gate 160 is connected with an input end of the second determinator 140, the output end of the second determinator 140 is a logic sixth port 100f, the output end of the second XOR gate 170 is a logic fourth port 100d, the output end of the fourth XOR gate 190 is connected with an input end of the third determinator 150, the output end of the third determinator 150 is a logic seventh port 100g.

[0070] The first shifter 110 in the logic control module 100 is configured to obtain an X input value Xin from a first numerical input end 110a and a calculation order i from a first order input end 110b, shift the X input value Xin to the right by the calculation order i, and pad the highest bit of the shifted X input value to obtain an X transformed value Xs corresponding to the X input value Xin, wherein the number of bits to be padded is also the calculation order i, the X transformed value Xs has the same number of bits as the X input value Xin, and the padded value is "0" or "1". The application takes "0" as an example to illustrate the embodiment. Illustratively, the X input value Xin is 10011010, which has 8 bits, and the leftmost bit is the highest bit, i.e., the 8th bit. The calculation order i is 3. The first shifter 110 shifts 10011010 to the right by 3 bits and pads "0" to obtain the X transformed value Xs as 00010011.

[0071] The second shifter 120 in the logic control module 100 is configured to obtain a Y input value Yin from a second numerical input end 120a and a calculation order i from a second order input end 120b, shift the Y input value Yin to the right by the calculation order i, and pad the highest bit of the shifted Y input value to obtain a Y transformed value Ys corresponding to the Y input value Yin, wherein the number of bits to be padded is also the calculation order i, the Y transformed value Ys has the same number of bits as the Y input value Yin, and the padded value is "0" or "1". The method of obtaining the Y transformed value from the Y input value is the same as the method of transforming the X input value into the X transformed value, which will not be described here.

[0072] The logic control module 100 processes the input X input value Xin, Y input value Yin, and calculation order i to obtain the values of three-bit symbol bits, i.e., u[0], u[1], and u[2]. The u[0] represents the rotation direction of the Cordic calculation. When u[0] is 0, it indicates that the Cordic calculation is counterclockwise rotation. When u[0] is 1, it indicates that the Cordic calculation is clockwise rotation.

[0073] The u[1] is a calculation execution signal, which indicates whether to stop the rotation of the Cordic calculation. When u[1] is 0, it indicates that the rotation of the Cordic calculation is not stopped. When u[1] is 1, it indicates that the rotation of the Cordic calculation is stopped. When the rotation of the Cordic calculation is stopped, the X calculation result is equal to the X input value Xin, i.e., Xout=Xin, and the Y calculation result is equal to the Y input value Yin, i.e., Yout=Yin.

[0074] In the embodiment of the present application, u[2] is a calculation type signal, which represents the method of using adder in Cordic calculation. When u[2] is 0, it means that full adder is used in Cordic calculation; when u[2] is 1, it means that approximate adder is used in Cordic calculation.

[0075] The approximate adder in the present application includes X approximate adder and Y approximate adder, which are XOR approximate adders. The structure and working principle of the XOR approximate adder are not described herein. The full adder includes X full adder and Y full adder, and the number of bits of the addition operation performed by the approximate adder can be adjusted according to the actual situation of the task, which is not limited in the present application.

[0076] The function and working principle of the components of the logic control module 100 in the Cordic calculation circuit shown in FIG. 2 are described below. Figure 2 Figure 1 The function and working principle of the components of the logic control module 100 in the Cordic calculation circuit shown in FIG. 2 are described below.

[0077] The value of the sign bit u[0] is obtained from the output level state of the first judge. When the output level state of the first judge is high, the value of the sign bit u[0] is 1; when the output level state of the first judge is low, the value of the sign bit u[0] is 0.

[0078] The value of the sign bit u[1] is obtained from the output level state of the second judge. When the output level state of the second judge is high, the value of the sign bit u[1] is 1; when the output level state of the second judge is low, the value of the sign bit u[1] is 0.

[0079] The value of the sign bit u[2] is obtained from the output level state of the third judge. When the output level state of the third judge is high, the value of the sign bit u[2] is 1; when the output level state of the third judge is low, the value of the sign bit u[2] is 0.

[0080] The first XOR gate 160 is used to perform XOR operation between the value of the first preset bit range of the Y transformed value Ys and the output value of the first judge, and output the result of the XOR operation at the output of the first XOR gate. The first preset bit range is obtained by pre-setting. Illustratively, the first preset bit range is 32-8 bits of the Y transformed value Ys. Figure 2

[0081] ​​The function of the second XOR gate 170 is to perform an XOR operation on the Y conversion value Ys and the output value of the first determiner, and output the XOR operation result of the Y conversion value Ys and the output value of the first determiner at the output terminal of the second XOR gate.

[0082] The third XOR gate 180 performs an XOR operation on the X-transformed value Xs and the output value of the first determiner, and outputs the XOR operation result of the X-transformed value Xs and the output value of the first determiner at the output of the third XOR gate.

[0083] The fourth XOR gate 190 is used to perform an XOR operation on the value of the second preset range of digits of the Y conversion value Ys and the value of the output terminal of the first judgement device, and output the second preset range of digits of the Y conversion value Ys (corresponding to Figure 2 The second preset bit range is obtained by presetting. Schematically, the second preset bit range is 32 to 16 bits of the Y conversion value Ys.

[0084] The function of the first judge is to detect the highest bit of the Y conversion value Ys (corresponding to Figure 2 The first determiner determines whether the MSB of the Y-transformed value Ys is "1." When the first determiner input receives a high level, the output of the first determiner outputs a high level. A high level output from the output of the first determiner indicates that the value of the sign bit u[0] is 1; otherwise, it is 0.

[0085] The function of the second judge is to detect whether any bit of the output value of the first XOR gate is all 0. When it is detected that any bit of the output value of the first XOR gate is all 0, a high level is output at the output end of the second judge, indicating that the value of the sign bit u[1] is 1; otherwise, it is 0.

[0086] The function of the third judge is to detect whether any bit of the value at the output end of the fourth XOR gate is all 0. When it is detected that any bit of the value at the output end of the third XOR gate is all 0, a high level is output at the output end of the third judge, indicating that the value of the sign bit u[2] is 1; otherwise, it is 0.

[0087] Specifically, the X calculation module 200 includes an X channel selection unit 210 , an X full adder unit 220 , and an X approximate addition unit 230 .

[0088] The X channel selection unit 210 includes an X channel first port 210 a , an X channel second port 210 b , an X channel third port 210 c , an X channel fourth port 210 d , an X channel fifth port 210 e , and an X channel sixth port 210 f .

[0089] The first port 210a of the X channel is connected with one input end 220a of the X full adder unit 220 and one input end 230a of the X approximate adder unit 230, and serves as the first computing port 200a of the X channel; the second port 210b of the X channel serves as the sixth computing port 200f of the X channel; the third port 210c of the X channel is connected with the output end 220c of the X full adder unit 220; the fourth port 210d of the X channel is connected with the output end 230c of the X approximate adder unit 230; the fifth port 210e of the X channel serves as the second computing port 200b of the X channel; the sixth port 210f of the X channel serves as the third computing port 200c of the X channel; the other input end 220b of the X full adder unit 220 serves as the fourth computing port 200d of the X channel; and the other input end 230b of the X approximate adder unit 230 serves as the fifth computing port 200e of the X channel.

[0090] Specifically, the X channel selection unit 210 comprises a first channel selector 211 and a second channel selector 212.

[0091] The first channel selector 211 has a first selector first input end 211a, a first selector second input end 211b, a first selector output end 211c and a first selector selection end 211d.

[0092] The second channel selector 212 has a second selector first input end 212a, a second selector second input end 212b, a second selector output end 212c and a second selector selection end 212d.

[0093] The first selector first input end 211a serves as the first port 210a of the X channel, the first selector output end 211c serves as the second port 210b of the X channel, the first selector selection end 211d serves as the fifth port 210e of the X channel, the first selector second input end 211b is connected with the second selector output end 212c, the second selector first input end 212a serves as the fourth port 210d of the X channel, the second selector second input end 212b serves as the third port 210c of the X channel, and the second selector selection end 212d serves as the sixth port 210f of the X channel.

[0094] The first selector selection terminal 211d is used to receive the output terminal level signal of the second judgement device 140, and according to the output terminal level signal of the second judgement device 140, determines whether the first selector output terminal 211c outputs the signal received by the first selector first input terminal 211a or the signal received by the first selector second input terminal 211b. Since the output terminal of the second judgement device represents the value of the sign bit u[1], when the value of the sign bit u[1] is 1, the rotation of the Cordic calculation is stopped, and the X calculation result output by the first selector output terminal 211c is the X input value Xin; when the value of the sign bit u[1] is 0, the rotation of the Cordic calculation is not stopped, and the X calculation result output by the first selector output terminal 211c is the output signal of the second selector output terminal 212c. In principle, when the output terminal level signal of the second judgement device 140 received by the first selector selection terminal 211d is a high level signal, the signal received by the first selector first input terminal 211a is output at the first selector output terminal 211c.

[0095] The second selector selection terminal 212d is used to receive the output terminal level signal of the third judge 150, and determine whether the second selector output terminal 212c outputs the signal received by the second selector first input terminal 212a or the signal received by the second selector second input terminal 212b based on the output terminal level signal of the third judge 150. Since the output terminal of the third judge represents the value of the sign bit u[2], when the value of the sign bit u[2] is 1, the second selector output terminal 212c outputs the calculation result of the X approximate addition unit 230; conversely, when the value of the sign bit u[2] is 0, the second selector output terminal 212c outputs the calculation result of the X full adder unit 220. Schematically, when the output terminal level signal of the third judge 150 received by the second selector selection terminal 212d is a high level signal, the signal received by the second selector first input terminal 212a is output at the second selector output terminal 212c.

[0096] Specifically, the Y calculation module 300 includes a Y channel selection unit 310 , a Y full adder unit 320 , and a Y approximate addition unit 330 .

[0097] The Y channel selection unit 310 includes a Y channel first port 310 a , a Y channel second port 310 b , a Y channel third port 310 c , a Y channel fourth port 310 d , a Y channel fifth port 310 e , and a Y channel sixth port 310 f .

[0098] The first port 310a of the Y channel is connected with one input end 320a of the Y full adder unit 320 and one input end 330a of the Y approximate adder unit 330, and then serves as a first Y calculation port 300a; the second port 310b of the Y channel serves as a sixth Y calculation port 300f; the third port 310c of the Y channel is connected with an output end 320c of the Y full adder unit 320; the fourth port 310d of the Y channel is connected with an output end 330c of the Y approximate adder unit 330; the fifth port 310e of the Y channel serves as a second Y calculation port 300b; the sixth port 310f of the Y channel serves as a third Y calculation port 300c; another input end 320b of the Y full adder unit 320 serves as a fourth Y calculation port 300d; and another input end 330b of the Y approximate adder unit 330 serves as a fifth Y calculation port 300e.

[0099] Specifically, the Y channel selection unit 310 comprises a third channel selector 311 and a fourth channel selector 312.

[0100] The third channel selector 311 has a third selector first input end 311a, a third selector second input end 311b, a third selector output end 311c and a third selector selection end 311d.

[0101] The fourth channel selector 312 has a fourth selector first input end 312a, a fourth selector second input end 312b, a fourth selector output end 312c and a fourth selector selection end 312d.

[0102] The third selector first input end 311a serves as the first port 310a of the Y channel, the third selector output end 311c serves as the second port 310b of the Y channel, the third selector selection end 311d serves as the fifth port 310e of the Y channel, the third selector second input end 311b is connected with the fourth selector output end 312c, the fourth selector first input end 312a serves as the fourth port 310d of the Y channel, the fourth selector second input end 312b serves as the third port 310c of the Y channel, and the fourth selector selection end 312d serves as the sixth port 310f of the Y channel.

[0103] The third selector selection end 311d is used for receiving the output level signal of the second judging device 140, and according to the output level signal of the second judging device 140, the third selector output end 311c outputs the signal received by the third selector first input end 311a or the signal received by the third selector second input end 311b. Since the output of the second judging device represents the value of the sign bit u[1], when the value of the sign bit u[1] is 1, the rotation of the Cordic calculation is stopped, and the Y calculation result output by the third selector output end 311c is the Y input value Yin; when the value of the sign bit u[1] is 0, the rotation of the Cordic calculation is not stopped, and the Y calculation result output by the third selector output end 311c is the output signal of the fourth selector output end 312c. Illustratively, when the third selector selection end 311d receives the output level signal of the second judging device 140 as a high level signal, the signal received by the third selector first input end 311a is output at the third selector output end 311c.

[0104] The fourth selector selection end 312d is used for receiving the output level signal of the third judging device 150, and according to the output level signal of the third judging device 150, the fourth selector output end 312c outputs the signal received by the fourth selector first input end 312a or the signal received by the fourth selector second input end 312b. Since the output of the third judging device represents the value of the sign bit u[2], when the value of the sign bit u[2] is 1, the fourth selector output end 312c outputs the calculation result of the Y approximate adder unit 330; otherwise, when the value of the sign bit u[2] is 0, the fourth selector output end 312c outputs the calculation result of the Y full adder unit 320. Illustratively, when the fourth selector selection end 312d receives the output level signal of the third judging device 150 as a high level signal, the signal received by the fourth selector first input end 312a is output at the fourth selector output end 312c.

[0105] Through the above description of the working principle of the circuit, the Cordic calculation circuit disclosed in the present application optimizes the Cordic algorithm at the hardware level. It can be expressed as follows:

[0106]

[0107]

[0108] According to the value of the introduced sign bit u[1], it is determined whether to stop the rotation of the Cordic; according to the value of the introduced sign bit u[0], it is determined the rotation direction of the Cordic calculation; according to the value of the introduced sign bit u[2], it is determined whether to use the full adder unit or the approximate adder unit to calculate (u[0] · 2 -i · Yin) or (u[0] · 2 -i• Xin) or (u[0] · 2 -i • Yin) or (u[0] · 2 -i • Xin) part.

[0109] By implementing the Cordic calculation circuit described in the embodiments of the present application, the angle rotation and modulus rotation in the Cordic calculation can be stopped synchronously, so as to solve the problem of non-convergent circle near the far point of the coordinate system, that is, in the vector mode, the direction of each rotation is determined by the positive and negative of Y, and when Y approaches 0, the shift calculation on the hardware causes the modulus rotation amount to be 0, and in fact the rotation has stopped, but the conventional Cordic hardware design determines the positive and negative by selecting the sign bit of Y, which can only determine the positive and negative and does not include the case of 0, so the rotation of the angle Z is not stopped, and finally the modulus rotation and the angle rotation are not stopped at the same time, thus causing the angle solution value to be abnormal. Since the value of the sign bit u[1] is obtained by real-time calculation of the logic control module, the rotation and stop rotation of the Cordic calculation can be adaptively set according to the actual calculation accuracy, so as to avoid additional rotation calculation under the condition of meeting the calculation accuracy, thereby causing waste of calculation time, and to improve the calculation efficiency and make the circuit adapt to high-frequency calculation scenarios. Under the condition of meeting the calculation accuracy, the full-addition calculation or approximate addition calculation is controlled by the value of the sign bit u[2], so as to optimize the calculation efficiency of the circuit on the basis of meeting the calculation accuracy.

[0110] In some other embodiments, as shown in FIG. 1, a Cordic calculation method is suitable for the Cordic calculation circuit of the first aspect, and includes: Figure 3

[0111] S100: obtaining an X input value, a Y input value, and a calculation order i.

[0112] S200: shifting the X input value and the Y input value according to the calculation order i, to determine an X transformed value Xs corresponding to the X input value Xin and a Y transformed value Ys corresponding to the Y input value Yin.

[0113] S300: determining a calculation type signal according to the Y transformed value.

[0114] S400: determining a calculation execution signal according to the X transformed value and the Y transformed value.

[0115] ​S500: transmit the calculation type signal and the calculation execution signal to the X calculation module and the Y calculation module of the Cordic calculation circuit, so that the X calculation module calculates the X calculation result, and the Y calculation module calculates the Y calculation result.

[0116] According to the calculation order i, the X input value and the Y input value are shifted, specifically including:

[0117] The X input value Xin is shifted to the right by the calculation order i;

[0118] The highest bit of the original number of the shifted X input value is complemented to obtain the X transformed value Xs corresponding to the X input value Xin, wherein the number of complemented bits is the calculation order i; at this time, the X transformed value Xs is

[0119] The Y input value Yin is shifted to the right by the calculation order i;

[0120] The highest bit of the original number of the shifted Y input value is complemented to obtain the Y transformed value Ys corresponding to the Y input value Yin, wherein the number of complemented bits is the calculation order i.

[0121] According to the Y transformed value, the calculation type signal is determined, specifically including:

[0122] The output level state of the third judge in the Cordic calculation circuit is obtained as the calculation type signal, wherein the third judge is used to detect whether all bits of the output value of the fourth XOR gate are 0, and when it is detected that all bits of the output value of the fourth XOR gate are 0, a high level is output at the output end of the third judge, indicating that the value of the sign bit u[2] is 1; otherwise, it is 0.

[0123] In response to the value of the sign bit u[2] being 1, the full adder unit is used for addition calculation;

[0124] In response to the value of the sign bit u[2] being 0, the approximate adder unit is used for addition calculation.

[0125] The third XOR gate is an XOR operation between the X transformed value Xs and the output value of the first judge, and the XOR operation result between the X transformed value Xs and the output value of the first judge is output at the output end of the third XOR gate.

[0126] According to the X transformed value and the Y transformed value, the calculation execution signal is determined, specifically including:

[0127] The output level state of the second judging device in the Cordic calculation circuit is acquired as a calculation execution signal, wherein the second judging device is used to detect whether all bits of the output value of the first XOR gate are 0, and when it is detected that all bits of the output value of the first XOR gate are 0, a high level is output at the output end of the second judging device, indicating that the value of the sign bit u[1] is 1; otherwise, it is 0.

[0128] When the value of u[1] is 0, the rotation of the Cordic calculation is not stopped.

[0129] When the value of u[1] is 1, the rotation of the Cordic calculation is stopped.

[0130] The first XOR gate is used to perform XOR operation between the first preset bit range of the Y transformed value Ys and the output value of the first judging device, and output the result of the XOR operation at the output end of the first XOR gate.

[0131] The Cordic calculation method further comprises:

[0132] The output level state of the first judging device in the Cordic calculation circuit is acquired as the value of the sign bit u[0], wherein the first judging device is used to detect whether the highest bit of the Y transformed value Ys is 1, and when the first judging device receives a high level at the input end, it indicates that the highest bit of the Y transformed value Ys is 1. When the first judging device receives a high level at the input end, a high level is output at the output end of the first judging device. The output end of the first judging device outputs a high level, indicating that the value of the sign bit u[0] is 1; otherwise, it is 0.

[0133] The Cordic calculation method further comprises: taking the calculation result of the current stage as the input value of the next stage, and repeatedly executing the Cordic calculation method until the calculation result corresponding to the calculation stage number i is obtained.

[0134] It should be understood that, although Figure 3 the steps in the flowchart of the method are shown in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other orders. Moreover, Figure 3 at least part of the steps in the method can include multiple sub-steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least part of other steps or sub-steps or stages of other steps.

[0135] In other embodiments, as shown in Figure 4 An acceleration computing system includes a configuration register, a data register, an error feedback unit, a coordinate system adjustment unit, a data pre / post processing unit, a pre-stored lookup table and a Cordic array.

[0136] The Cordic array includes at least one Cordic computing circuit as described above.

[0137] The configuration register is connected to the error feedback unit, the coordinate system adjustment unit and the data pre / post processing unit, the data register is connected to the error feedback unit, the coordinate system adjustment unit and the data pre / post processing unit, and the coordinate system adjustment unit is connected to the error feedback unit, the data pre / post processing unit, the pre-stored lookup table and the Cordic array.

[0138] The configuration register is configured through an APB bus and saves the relevant configurations of the Cordic computation, such as the 3-bit sign bit as described above.

[0139] The data register loads the operation data through an AHB bus and automatically starts the operation after the data loading is completed.

[0140] The APB (Advanced Peripheral Bus) bus and the AHB (Advanced High-performance Bus) bus are two core bus types in the AMBA (Advanced Microcontroller Bus Architecture) bus protocol, which are widely used in embedded systems and SoC (System on Chip) designs, and are used to connect processors and peripheral devices to optimize the performance, power consumption and scalability of the system.

[0141] The APB bus is a low-power, low-cost and low-bandwidth peripheral bus in the AMBA protocol. Its interface logic is simple, only a small number of signal lines are required, and it is suitable for resource-constrained peripherals. Since it does not use a pipeline mechanism, it is activated only when it needs to work, and has low power consumption. Usually, its address and data are transmitted in the same cycle, and it does not support burst transmission. It is suitable for connecting low-speed interfaces or peripherals, such as UART, GPIO, SPI, I 2 C, ADC / DAC, timer, watchdog, etc.

[0142] AHB bus is a master-slave structure bus in AMBA protocol with high performance and high bandwidth. Burst transfer is supported to improve data throughput rate, multiple master devices access multiple slave devices are supported, and multi-master arbitration mechanism is provided. Address stage and data stage are separated, address pipeline processing is supported, and transmission efficiency is high. It is suitable for connecting high-performance modules such as CPU, DMA controller, memory controller, cache and high-speed peripherals.

[0143] An error feedback unit is configured to check the loaded data, determine whether the data meets the operation requirement under the current configuration condition, and generate an error flag and delete the preloaded data if the operation requirement is not met.

[0144] A coordinate system adjustment unit is configured to save the coordinate system in which the preloaded data is located and rotate the preloaded data to the first coordinate system if the preloaded data has no error.

[0145] A data pre / post-processing unit is configured to process the output data to the corresponding coordinate system according to the calculated data and the saved coordinate system.

[0146] A pre-stored lookup table pre-stores binary parameters of corresponding Cordic operations and loads the binary parameters to the high-speed operation unit according to the operation order.

[0147] The above acceleration calculation system can be applied to the acceleration of calculation processes such as modulation, demodulation in digital communication and coordinate transformation in image processing.

[0148] In a digital communication system, a signal usually needs to be converted into a form suitable for transmission through modulation, and demodulated at the receiving end to recover the original information. Modulation methods include but are not limited to amplitude modulation (AM), frequency modulation (FM), phase modulation (PM) and various combinations thereof such as QAM (quadrature amplitude modulation). These modulation techniques involve a large number of trigonometric function operations.

[0149] For the modulation process: when implementing complex modulation schemes such as QAM, a large number of complex multiplication operations are involved, which can actually be converted into a series of rotation operations. Cordic algorithm can effectively perform these rotation operations, thereby speeding up the modulation process.

[0150] For the demodulation process: angle and amplitude information also need to be calculated, and Cordic can quickly estimate these values through iteration, avoiding complex multiplication and division operations in traditional methods.

[0151] In the field of computer graphics and image processing, it is often necessary to perform geometric transformations such as rotation, scaling, and translation on images. These transformations often involve coordinate transformations in two or three-dimensional space, which can involve a large number of trigonometric calculations, such as sin and cos values in rotation matrices.

[0152] For image rotation: To achieve arbitrary angle rotation of an image, the new position of each pixel must be calculated. This process involves solving for new x and y coordinates, which can be efficiently done using the Cordic algorithm, which can directly calculate the sine and cosine values for a given angle without the need to call library functions directly or perform time-consuming floating-point operations.

[0153] For 3D graphics rendering: Cordic can be used to accelerate vector rotation calculations, which are crucial for quickly generating realistic visual effects. Especially on embedded systems or mobile devices, where resource constraints are a concern, using Cordic algorithms can help reduce power consumption and improve performance.

[0154] By using the Cordic calculation circuit, calculation method, and accelerated calculation system described in the embodiments of the present application, the non-convergent circle near the origin of the coordinate system in the traditional Cordic calculation unit is removed, the complexity of preprocessing in the Cordic calculation module is reduced, and the timing constraints of the Cordic calculation module at high frequencies are reduced. The addition array in the Cordic calculation unit is optimized, the critical path is shortened, and the adaptability of the Cordic calculation unit to higher frequencies is improved, achieving the purpose of further accelerating Cordic calculation. The rotation stopping mechanism is introduced into the Cordic calculation, which can better pipeline the Cordic calculation at high frequencies.

[0155] All the optional technical solutions described above can be combined to form optional embodiments of the present application, which will not be described again.

[0156] Note that the above is only the preferred embodiment of the present application and the technical principle applied. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and those skilled in the art can make various obvious changes, re-adjustments, and substitutions without departing from the scope of the present application. Any modification, equivalent substitution, improvement, etc. made in the spirit and principle of the present application shall be included in the protection scope of the present application. Therefore, although the present application has been described in more detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. A Cordic calculation circuit, characterized in that: include: Logic control module, X calculation module and Y calculation module; The logic control module is connected to the X calculation module and the Y calculation module; The logic control module is used to determine a calculation execution signal and a calculation type signal according to the obtained X input value, Y input value and calculation order; The X calculation module is used to obtain an X input value, perform calculation on the X input value according to the calculation execution signal, and output an X calculation result. In response to performing a calculation on the X input value, performing a full addition calculation or an approximate addition calculation on the X input value according to the calculation type signal; The Y calculation module is used to obtain the Y input value, perform calculation on the Y input value according to the calculation execution signal, and output the Y calculation result. In response to performing calculation on the Y input value, performing a full addition calculation or an approximate addition calculation on the Y input value according to the calculation type signal; wherein the calculation type signal is determined according to a Y transformation value, and the Y transformation value is determined according to the Y input value; The calculation execution signal is determined according to an X transformation value and a Y transformation value, wherein the X transformation value is determined according to the X input value.

2. The Cordic calculation circuit according to claim 1, wherein: The logic control module has: a logical first port, a logical second port, a logical third port, a logical fourth port, a logical fifth port, a logical sixth port and a logical seventh port; The X calculation module has: an X calculation first port, an X calculation second port, an X calculation third port, an X calculation fourth port, an X calculation fifth port and an X calculation sixth port; The Y calculation module has: a Y calculation first port, a Y calculation second port, a Y calculation third port, a Y calculation fourth port, a Y calculation fifth port and a Y calculation sixth port; The first logic port is connected to the first X calculation port for obtaining the X input value. The second logic port is connected to the first Y calculation port for obtaining the Y input value. The third logic port is used to obtain the calculation order. The fourth logic port is connected to the fourth X calculation port and the fifth X calculation port. The fifth logic port is connected to the fourth Y calculation port and the fifth Y calculation port. The sixth logic port is connected to the second X calculation port and the second Y calculation port. The seventh logic port is connected to the third X calculation port and the third Y calculation port. The sixth X calculation port is used to output the X calculation result. The sixth Y calculation port is used to output the Y calculation result.

3. The Cordic calculation circuit according to claim 1 or 2, characterized in that: The logic control module includes: a first shifter, a second shifter, a first judger, a second judger, a third judger, a first XOR gate, a second XOR gate, a third XOR gate and a fourth XOR gate; The first shifter has: a first numerical value input terminal, a first order input terminal and a first numerical value output terminal; The second shifter has: a second numerical value input terminal, a second order input terminal and a second numerical value output terminal; The first numerical input terminal serves as the logical first port, the second numerical input terminal serves as the logical second port, the first order input terminal and the second order input terminal are connected to serve as the logical third port, the first numerical output terminal is connected to one input terminal of a third XOR gate, the other input terminal of the third XOR gate is connected to one input terminal of the first XOR gate, one input terminal of the second XOR gate, and the output terminal of the first judger, the output terminal of the third XOR gate serves as the logical fifth port, the second numerical output terminal is connected to the input terminal of the first judger, the other input terminal of the first XOR gate, one input terminal of the fourth XOR gate, and the other input terminal of the second XOR gate, the output terminal of the first XOR gate is connected to the input terminal of the second judger, the output terminal of the second judger serves as the logical sixth port, the output terminal of the second XOR gate serves as the logical fourth port, the output terminal of the fourth XOR gate is connected to the input terminal of the third judger, and the output terminal of the third judger serves as the logical seventh port.

4. The Cordic calculation circuit according to claim 1 or 2, characterized in that: The X calculation module includes: an X channel selection unit, an X full adder unit and an X approximate addition unit; The X channel selection unit has: an X channel first port, an X channel second port, an X channel third port, an X channel fourth port, an X channel fifth port, and an X channel sixth port; The X channel first port is connected to one input end of the X full adder unit and one input end of the X approximate addition unit to serve as the X calculation first port. The X channel second port serves as the X calculation sixth port. The X channel third port is connected to the output end of the X full adder unit. The X channel fourth port is connected to the output end of the X approximate addition unit. The X channel fifth port serves as the X calculation second port. The X channel sixth port serves as the X calculation third port. Another input end of the X full adder unit serves as the X calculation fourth port. Another input end of the X approximate addition unit serves as the X calculation fifth port.

5. The Cordic calculation circuit according to claim 4, characterized in that: The X channel selection unit includes: a first channel selector and a second channel selector; The first channel selector has: a first selector first input terminal, a first selector second input terminal, a first selector output terminal and a first selector selection terminal; The second channel selector comprises: a second selector first input terminal, a second selector second input terminal, a second selector output terminal and a second selector selecting terminal; The first input end of the first selector serves as the first port of the X channel, the output end of the first selector serves as the second port of the X channel, the selection end of the first selector serves as the fifth port of the X channel, the second input end of the first selector is connected to the output end of the second selector, the first input end of the second selector serves as the fourth port of the X channel, the second input end of the second selector serves as the third port of the X channel, and the selection end of the second selector serves as the sixth port of the X channel.

6. The Cordic calculation circuit according to claim 1 or 2, characterized in that: The Y calculation module includes: a Y channel selection unit, a Y full adder unit and a Y approximate addition unit; The Y channel selection unit has: a Y channel first port, a Y channel second port, a Y channel third port, a Y channel fourth port, a Y channel fifth port and a Y channel sixth port; The first port of the Y channel is connected to an input end of the Y full adder unit and an input end of the Y approximate addition unit as the first port of Y calculation, the second port of the Y channel serves as the sixth port of Y calculation, the third port of the Y channel is connected to the output end of the Y full adder unit, the fourth port of the Y channel is connected to the output end of the Y approximate addition unit, the fifth port of the Y channel serves as the second port of Y calculation, the sixth port of the Y channel serves as the third port of Y calculation, the other input end of the Y full adder unit serves as the fourth port of Y calculation, and the other input end of the Y approximate addition unit serves as the fifth port of Y calculation.

7. The Cordic calculation circuit according to claim 6, characterized in that: The Y channel selection unit includes: a third channel selector and a fourth channel selector; The third channel selector comprises: a third selector first input terminal, a third selector second input terminal, a third selector output terminal and a third selector selecting terminal; The fourth channel selector comprises: a fourth selector first input terminal, a fourth selector second input terminal, a fourth selector output terminal and a fourth selector selecting terminal; The first input end of the third selector serves as the first port of the Y channel, the output end of the third selector serves as the second port of the Y channel, the selection end of the third selector serves as the fifth port of the Y channel, the second input end of the third selector is connected to the output end of the fourth selector, the first input end of the fourth selector serves as the fourth port of the Y channel, the second input end of the fourth selector serves as the third port of the Y channel, and the selection end of the fourth selector serves as the sixth port of the Y channel.

8. A Cordic calculation method, characterized in that: The Cordic calculation circuit according to any one of claims 1 to 7, comprising: Get the X input value, Y input value and calculation order; Shifting the X input value and the Y input value according to the calculation order to determine an X transformation value and a Y transformation value; Determining a calculation type signal according to the Y transformation value; determining a calculation execution signal according to the X transformation value and the Y transformation value; The calculation type signal and the calculation execution signal are transmitted to the X calculation module and the Y calculation module of the Cordic calculation circuit, so that the X calculation module calculates to obtain the X calculation result and the Y calculation module calculates to obtain the Y calculation result.

9. The Cordic calculation method according to claim 8, characterized in that: The method further includes: using the calculation result of the current order as the input value of the next order, and repeatedly executing the Cordic calculation method until a calculation result corresponding to the calculation order is obtained.

10. An accelerated computing system, characterized in that: include: Configuration registers, data registers, error feedback unit, coordinate system allocation unit, data pre / post-processing unit, pre-stored lookup table and Cordic array; The Cordic array comprises at least one Cordic computing circuit according to any one of claims 1 to 7; The configuration register is connected to the error feedback unit, the coordinate system allocation unit and the data pre / post-processing unit, the data register is connected to the error feedback unit, the coordinate system allocation unit and the data pre / post-processing unit, and the coordinate system allocation unit is connected to the error feedback unit, the data pre / post-processing unit, the pre-stored lookup table and the Cordic array.

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