Server dual-mode debugging system and method

Abstract

The invention provides a server dual-mode debugging system and a server dual-mode debugging method. The system comprises a DC-SCM card provided with a CPU, a first CPLD main board, a second CPLD, a BMC controller, a CP2105 chip, a TYPE-C interface, a UID key and an indicator lamp, and a DC-SCM card provided with a first CPLD main board, a second CPLD main board and a second CPLD main board, the BMC controller is used for detecting a current system debugging mode and a key operation state of the UID key, and switching the current system debugging mode according to the key operation state; the controller is also used for detecting the hardware working state of the server system in the current system debugging mode in real time and controlling the indicator light to display the system working state in the current system debugging mode; according to the method, intelligent switching output of serial port information of the BMC and the CPU can be achieved through the rear Type-C interface, clear state indication is provided, debugging mode switching and state recognition can be completed without opening a case, and the maintenance efficiency of the server is remarkably improved.

Description

Technical Field

[0001] The present application relates to the technical field of server hardware design, and in particular to a server dual-mode debugging system and method. Background Art

[0002] The current server system debugging has the following technical problems:

[0003] 1. Interface dispersion: In traditional servers, the BMC debug interface and CPU debug interface are physically separated and usually use different interface standards such as RJ45 and DB9, resulting in the need to prepare multiple debug cables.

[0004] 2. Inconvenient operation: When switching the debugging interface, the server chassis needs to be opened and the specific interface needs to be located in a complex wiring environment, which increases the difficulty and time cost of maintenance.

[0005] 3. Architectural limitations: In modular server designs, the separation of the motherboard and DC-SCM card complicates the serial port signal path, making it difficult to achieve unified interface output with traditional solutions.

[0006] 4. Lack of status indication: There is a lack of an intuitive status display mechanism, and maintenance personnel cannot quickly confirm the current working status of the debugging interface. Summary of the Invention

[0007] The purpose of this application is to provide a server dual-mode debugging system and method, which realizes the intelligent switching output of BMC and CPU serial port information through the rear Type-C interface, and provides clear status indication. Debug mode switching and status identification can be completed without opening the chassis, significantly improving server maintenance efficiency.

[0008] In the first aspect, the present application provides a server dual-mode debugging system, the system comprising: a mainboard and a DC-SCM card; a CPU and a first CPLD are provided on the mainboard; a second CPLD, a BMC controller, a CP2105 chip, a TYPE-C interface, a UID button and an indicator light are provided on the DC-SCM card; wherein the CPU, the first CPLD and the second CPLD are connected in sequence; the BMC controller is respectively connected to the second CPLD, the UID button and the indicator light; the CP2105 chip is respectively connected to the second CPLD, the BMC controller and the TYPE-C interface; the CPU, the first CPLD, the second CPLD, the CP2105 chip and the TYPE-C interface constitute a signal transmission path in the CPU debugging mode; the BMC controller, the CP2105 chip and the TYPE-C interface constitute a B Signal transmission path in MC debugging mode; BMC controller, used to detect the current system debugging mode, detect the key operation status of the UID button, and switch the current system debugging mode according to the key operation status; BMC controller is also used to detect the hardware working status of the server system in the current system debugging mode in real time, and control the indicator light to display the system working status in the current system debugging mode according to the hardware working status; among them, the system working status includes the following four: normal hardware working status in CPU debugging mode, abnormal hardware working status in CPU debugging mode, normal hardware working status in BMC debugging mode, and abnormal hardware working status in BMC debugging mode; the four system working statuses should be indicated by one of the following four indicator light states: off, flashing at a specified interval, always on, and flashing quickly.

[0009] Furthermore, the above-mentioned CPU is connected to the first CPLD through a UART serial port; the first CPLD is connected to the second CPLD through an LVDS differential transmission channel; the CP2105 chip has dual UART channels, which are respectively connected to the BMC control and the second CPLD; the BMC controller is respectively connected to the second CPLD, UID button, and indicator light through the GPIO interface; and the Type-C interface is connected to the output end of the CP2105 chip.

[0010] Furthermore, when the BMC controller detects a long press operation on the UID button and the long press duration reaches a preset duration, it controls the second CPLD to interrupt or restore the CPU serial port output through the GPIO interface to switch the system debugging mode.

[0011] Furthermore, the above-mentioned UID button is equipped with an anti-shake circuit, which is integrated with the indicator light, and the indicator light is a single-color LED indicator light.

[0012] Furthermore, the data transmission between the first CPLD and the second CPLD adopts LVDS differential signal, which is transmitted through the standard gold finger connector between the motherboard and the DC-SCM card; the Type-C interface adopts USB2.0 data channel to transmit serial port signals and is compatible with standard USB Type-C to A cable.

[0013] In the second aspect, the present application also provides a server dual-mode debugging method, which is applied to the BMC controller in the server dual-mode debugging system as described in the first aspect, and the method includes: determining the current system debugging mode based on the UID button status, and determining the current indication state of the indicator light; wherein, the current system debugging mode includes: CPU debugging mode or BMC debugging mode; the current indication state is used to characterize the hardware working state of the system in the current system debugging mode; the current indication state includes one of the following: a first indication state, a second indication state, a third indication state or a fourth indication state; the four indication states correspond to one of the following indicator light states: off, flashing at a specified time interval, always on, flashing quickly; real-time monitoring of whether there is any change in the hardware working state of the server system in the current system debugging mode; if so, changing the current indication state of the indicator light to another indication state; if not, controlling the indicator light to maintain the current indication state.

[0014] Furthermore, the above-mentioned step of determining the current system debugging mode based on the UID button status includes: judging whether a specified long press operation on the UID button is detected; the specified long press operation includes: the duration of the long press operation reaches a specified duration; if not, using the currently detected system debugging mode as the current system debugging mode; if yes, switching the currently detected system debugging mode, and using the switched system debugging mode as the current system debugging mode.

[0015] Furthermore, the above-mentioned step of switching the currently detected system debugging mode includes: if the currently detected system debugging mode is the CPU debugging mode, controlling the second CPLD to interrupt the CPU serial port output through the GPIO interface to switch the CPU debugging mode to the BMC debugging mode; if the currently detected system debugging mode is the BMC debugging mode, controlling the second CPLD to restore the CPU serial port output through the GPIO interface to switch the BMC debugging mode to the CPU debugging mode.

[0016] Furthermore, the above-mentioned step of changing the current indication state of the indicator light to another specified state includes: if the current system debugging mode is the CPU debugging mode, the current indication state is the first indication state, and the first indication state is changed to the second indication state; wherein, the first indication state and the second indication state are respectively used to represent: the system hardware is in a normal state and an abnormal state in the CPU debugging mode; if the current system debugging mode is the BMC debugging mode, the current indication state is the third indication state, and the third indication state is changed to a fourth indication state; wherein, the third indication state and the fourth indication state are respectively used to represent: the system hardware is in a normal state and an abnormal state in the BMC debugging mode.

[0017] In a third aspect, the present application further provides a computer-readable storage medium, which stores computer-executable instructions. When the computer-executable instructions are called and executed by a processor, the computer-executable instructions prompt the processor to implement the method described in the second aspect above.

[0018] The server dual-mode debugging system and method provided in the present application include: a mainboard and a DC-SCM card; a CPU and a first CPLD are provided on the mainboard; a second CPLD, a BMC controller, a CP2105 chip, a TYPE-C interface, a UID button and an indicator light are provided on the DC-SCM card; wherein the CPU, the first CPLD and the second CPLD are connected in sequence; the BMC controller is respectively connected to the second CPLD, the UID button and the indicator light; the CP2105 chip is respectively connected to the second CPLD, the BMC controller and the TYPE-C interface; the CPU, the first CPLD, the second CPLD, the CP2105 chip and the TYPE-C interface constitute a signal transmission path in the CPU debugging mode; the BMC controller, the CP2105 chip and the TYPE-C interface constitute a BMC controller. C signal transmission path in debugging mode; BMC controller, used to detect the current system debugging mode, as well as the key operation status of the UID button, and switch the current system debugging mode according to the key operation status; BMC controller, also used to detect the hardware working status of the server system in the current system debugging mode in real time, and control the indicator light to display the system working status in the current system debugging mode according to the hardware working status; wherein, the system working status includes the following four: normal working status of hardware in CPU debugging mode, abnormal working status of hardware in CPU debugging mode, normal working status of hardware in BMC debugging mode, abnormal working status of hardware in BMC debugging mode; the four system working statuses should be indicated by one of the following four indicator light states: off, flashing at a specified time interval, always on, and flashing quickly. This application realizes the intelligent switching output of BMC and CPU serial port information through the rear Type-C interface, and provides clear status indications. The debugging mode switching and status identification can be completed without opening the chassis, which significantly improves the server maintenance efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0020] Figure 1 A schematic diagram of the structure of a server dual-mode debugging system provided in an embodiment of the present application;

[0021] Figure 2 A schematic diagram of a BMC firmware configuration provided in an embodiment of the present application;

[0022] Figure 3 Another BMC firmware configuration diagram provided in an embodiment of the present application;

[0023] Figure 4 A schematic diagram of a CPLD configuration provided in an embodiment of the present application;

[0024] Figure 5 A schematic diagram of a server dual-mode debugging process provided in an embodiment of the present application;

[0025] Figure 6 A flowchart of a server dual-mode debugging method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] The following will clearly and completely describe the technical solutions of this application in conjunction with the embodiments. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0027] To address the issues of scattered interfaces, inconvenient operation, limited architecture, and lack of status indication in current server system debugging methods, the present invention provides a server dual-mode debugging system and method. This system uses a rear-mounted Type-C interface to intelligently switch and output BMC and CPU serial port information, and provides clear status indications. This allows debugging mode switching and status identification without opening the chassis, significantly improving server maintenance efficiency. To facilitate understanding of this embodiment, the server dual-mode debugging system disclosed in this embodiment is first described in detail.

[0028] Figure 1 This is a schematic diagram of a server dual-mode debugging system provided in an embodiment of the present application, the system comprising: a mainboard and a DC-SCM card; a CPU and a first CPLD are provided on the mainboard; a second CPLD, a BMC controller, a CP2105 chip, a TYPE-C interface, a UID button, and an indicator light are provided on the DC-SCM card; wherein the CPU, the first CPLD, and the second CPLD are connected in sequence; the BMC controller is respectively connected to the second CPLD, the UID button, and the indicator light; and the CP2105 chip is respectively connected to the second CPLD, the BMC controller, and the TYPE-C interface.

[0029] During specific implementation, the above-mentioned CPU is connected to the first CPLD through the UART serial port; the first CPLD is connected to the second CPLD through the LVDS differential transmission channel; the CP2105 chip has dual UART channels, which are respectively connected to the BMC control and the second CPLD; the BMC controller is respectively connected to the second CPLD, UID button, and indicator light through the GPIO interface; and the Type-C interface is connected to the output end of the CP2105 chip.

[0030] The first CPLD, also known as the mainboard CPLD, is used to receive CPU serial port signals and perform level conversion. The LVDS differential transmission channel connects the mainboard CPLD and the second CPLD (i.e., the DC-SCM card CPLD). The DC-SCM card CPLD receives signals transmitted by the mainboard CPLD via LVDS differential signals. The CP2105 chip has dual UART channels, which are connected to the BMC serial port and the DC-SCM card CPLD, respectively. The Type-C interface is connected to the output end of the CP2105 chip. The CPU, the first CPLD, the second CPLD, the CP2105 chip, and the Type-C interface can form a signal transmission path in the CPU debug mode. The BMC controller, the CP2105 chip, and the Type-C interface can form a signal transmission path in the BMC debug mode.

[0031] That is, when the system debug mode is CPU debug mode, that is, the output of the Type-C interface is CPU mode, the signal transmission path is:

[0032] CPU serial port → mainboard CPLD (1.8V to 3.3V) → LVDS differential pair → DC-SCM card CPLD → CP2105 UART1 → Type-C interface;

[0033] When the system debugging mode is BMC debugging mode, that is, the output of the Type-C interface is in BMC mode, the signal transmission path is:

[0034] BMC serial port UART5 → CP2105 UART0 → Type-C port.

[0035] In one preferred embodiment, the UID button is equipped with an anti-shake circuit and is integrated with the indicator light, which is a single-color LED. The UID button and single-color indicator light are used for mode switching and status indication. Data transmission between the first and second CPLDs uses LVDS differential signals, transmitted via a standard gold finger connector between the motherboard and the DC-SCM card. The Type-C interface uses a USB 2.0 data channel to transmit serial port signals and is compatible with standard USB Type-C to A cables.

[0036] The BMC controller is used to detect key operations and control the system status. Specifically, the BMC controller can detect the current system debugging mode in real time, as well as the key operation status of the UID key, and switch the current system debugging mode according to the key operation status. It is also used to detect the hardware working status of the server system in the current system debugging mode in real time, and control the indicator light to display the system working status in the current system debugging mode according to the hardware working status.

[0037] In specific implementation, when the BMC controller detects a long press operation on the UID button and the long press duration reaches a preset duration (4 seconds in this embodiment), it controls the second CPLD to interrupt or restore the CPU serial port output through the GPIO interface to switch the system debugging mode.

[0038] In each system debugging mode, the BMC controller can also perform real-time hardware working status detection, and according to the detection results, control the indicator lights to display different system working states in different system debugging modes.

[0039] In this embodiment, the system working status includes the following four: normal hardware working status in CPU debugging mode, abnormal hardware working status in CPU debugging mode, normal hardware working status in BMC debugging mode, and abnormal hardware working status in BMC debugging mode; the four system working statuses should be indicated by one of the following four indicator light states: off, flashing at a specified interval, always on, and flashing quickly.

[0040] In a preferred embodiment, the system adopts a four-level status indication scheme:

[0041] (1) The indicator light is off, indicating that the hardware is in normal working state in CPU debugging mode, that is, Type-C outputs CPU serial port information and the system is normal;

[0042] (2) The indicator light flashes at intervals of 1 second, indicating that the hardware is in normal working state in BMC debugging mode, that is, BMC serial port information is output and the system is normal;

[0043] (3) If the indicator light is always on, it means that the hardware is in abnormal working state in CPU debugging mode, that is, the CPU serial port output detects hardware abnormality;

[0044] (4) The indicator light flashes quickly, indicating that the hardware is in an abnormal working state in the BMC debugging mode, that is, a hardware abnormality is detected during the BMC serial port output.

[0045] In the server dual-mode debugging system provided by the embodiment of this application, users can switch to debugging mode by long pressing the UID button for 4 seconds. All debugging operations can be completed without opening the chassis. This realizes the standardization and intelligentization of the server debugging interface, significantly improving the efficiency and reliability of server maintenance. In addition, it has the following beneficial effects:

[0046] (1) Improved transmission reliability: LVDS differential transmission improves anti-interference capability by 75%, and the transmission bit error rate is less than 10 -9 , supports inter-board transmission distance of up to 1.5 meters;

[0047] (2) Improved operational convenience: No unpacking mode switching required (by pressing the UID key for 4 seconds), a single Type-C interface compatible with all debugging scenarios, and a four-level status indicator that intuitively displays system status;

[0048] (3) Improved maintenance efficiency: Fault location time is shortened by 80%, automatic abnormality recovery success rate is >99%, and it is compatible with standard USB Type-C cables.

[0049] The hardware structure of the above system is described in detail below:

[0050] (1) Mainboard circuit design:

[0051] CPU_UART is connected to Bank 1 of CPLD A (1.8V operating voltage). The CPLD transmits the UART data from the CPU to Bank 2 of CPLD A. Bank 2 of CPLD A (3.3V operating voltage) is output to the LVDS differential pair.

[0052] (2) DC-SCM card circuit design:

[0053] The LVDS is connected to Bank 3 of CPLD B. CPLD B transmits the UART data from the motherboard LVDS to Bank 4 of CPLD B. Bank 4 of CPLD B is connected to the UART1 interface of CP2105. BMC_UART5 is directly connected to the UART0 interface of CP2105. The Type-C interface is configured in USB 2.0 mode.

[0054] (3) Control circuit design:

[0055] The UID button is connected to the BMC's GPIO12 and configured with an anti-shake circuit as a monitoring button input port. The UID LED is a monochrome LED design. The negative pin of the LED is connected to the BMC's GPIO2, and the positive pin is connected to a 3V3 voltage level. When the BMC pulls GPIO2 low, the LED turns on and the UID light illuminates. A GPIO3 interface is reserved between the BMC chip and CPLD B to notify CPLD B to enable or disable serial port information from the CPU. This GPIO3 external line is pulled high by a 4.7K pull-up resistor, making its default value high.

[0056] The software control process in the above system is described in detail below:

[0057] (1)BMC controller firmware configuration, such as Figure 2 As shown:

[0058] Serial port output mode switch: When the server is just powered on, the default serial port output mode (current_mode) is the CPU serial port output (current == CPU-MODE). At this time, the GPIO3 of the BMC connected to CPLD B is high (GPIO3 is Figure 2 The value of CPLD_CTRL_GPIO in the code).

[0059] After power-on, the BMC detects in real time whether the UID key input to the BMC chip IO interface (GPIO12) is pulled low, that is, whether there is key input. If key input is detected and the key press time is greater than or equal to 4000 milliseconds (the IO port is pulled low for greater than or equal to 4000 milliseconds), the BMC is triggered to determine the current serial port output mode (the value of current_mode):

[0060] If the current output mode is the CPU serial port (i.e., current == CPU-MODE), the BMC pulls down GPIO3 of the CPLD connected to the BMC on the DC-SCM card (CPLD_CTRL_GPIO, LOW) to notify CPLD B to stop outputting the CPU serial port information, and changes the value of "current_mode" to current == BMC-MODE, indicating that the current mode is the BMC serial port output mode.

[0061] If the current output mode is the BMC serial port (i.e., current == CPU-MODE is not true), the BMC pulls up GPIO3 (CPLD_CTRL_GPIO, HIGH) of the CPLD connected to the BMC on the DC-SCM card to notify CPLD B to output the CPU serial port information, and changes the value of "current_mode" to current == CPU-MODE, indicating that the current serial port output mode is CPU, and stops the BMC's own UART5 serial port from outputting data.

[0062] The BMC controls the UID indicator status and monitors the server in real time to see if there is an error (routine server alarm monitoring such as overtemperature and voltage abnormality).

[0063] If there is an error, the BMC first determines whether the current serial port mode is CPU serial port mode or BMC serial port mode, that is, whether "current == CPU-MOD" is true. If it is true, it means the current serial port mode is CPU serial port mode, otherwise it is BMC serial port mode. If it is CPU serial port mode, Figure 3 The value of set_led_mode in the command is CONST_ON. The corresponding operation performed by BMC is to pull down GPIO2 so that the UID LED is turned on and remains on. If it is in BMC serial port mode, Figure 3 The value of set_led_mode in is FAST_BLINK. The corresponding operation performed by BMC is to periodically pull down GPIO2 to make the UID LED keep flashing quickly. The time interval of pulling down is 100 milliseconds.

[0064] If there is no error or the error is resolved, the BMC first determines whether the current serial port mode is CPU serial port mode or BMC serial port mode, that is, whether "current == CPU-MOD" is true. If it is true, it means the current serial port mode is CPU serial port mode, otherwise it is BMC serial port mode. If it is CPU serial port mode, Figure 3 The value of set_led_mode in the command is OFF. The corresponding operation performed by BMC is to pull up GPIO2, so that the UID LED is not turned on and remains off. If it is in BMC serial port mode, Figure 3 The value of set_led_mode in the command is SLOW_BLINK. The corresponding operation performed by BMC is to periodically pull down GPIO2 so that the UID LED keeps flashing slowly. The interval between pulling down is 1 second.

[0065] (2) CPLD logic design:

[0066] CPLD B on the DC-SCM card detects in real time whether the value of the GPIO3 signal from the BMC chip is high or low. In the CPLD side code, the signal value is represented by bmc_ctrl_gpio, such as Figure 4 As shown in .

[0067] When this value is low (bmc_ctrl_gpio == 1'b0), the serial data from the CPU will stop being output (Bank4 of CPLDB is connected to the UART1 interface of CP2105. At this time, the UART1 port connected to CP2105 can be set to high impedance state).

[0068] When this value is not low (i.e., the equation bmc_ctrl_gpio == 1'b0 does not hold), the serial port data from the CPU will be output normally (Bank4 of CPLD B is connected to the UART1 interface of CP2105, and at this time it will be connected to the UART1 port of CP2105 to continue transmitting the serial port data from the CPU).

[0069] The specific workflow of the embodiment of this application is as follows:

[0070] (1) Default working mode:

[0071] After power-on initialization, the system automatically enters CPU debugging mode, the Type-C interface outputs CPU debugging information, and the UID indicator remains off.

[0072] (2) Mode switching process:

[0073] The user presses and holds the UID button for 4 seconds. After the BMC detects the button operation, it pulls down CPLD_CTRL_GPIO to notify CPLD B to interrupt the CPU serial port, sets CP2105_SEL_GPIO to high, switches to BMC UART5, and controls the UID indicator to flash at 1-second intervals. Press and hold the button again for 4 seconds to restore the default state.

[0074] (3) Error handling process:

[0075] When the BMC hardware monitoring thread detects an abnormality, it switches to the abnormal indication state according to the current mode and records the error code; after the fault is eliminated, the system automatically restores the normal indication state of the corresponding mode.

[0076] Figure 5 A schematic diagram of a BMC processing flow provided by an embodiment of the present application is shown, and through key detection and hardware fault detection, four system working status display effects are formed respectively.

[0077] Based on the above system embodiment, the present application embodiment also provides a server dual-mode debugging method, which is applied to the BMC controller in the server dual-mode debugging system as described in the system embodiment, see Figure 6 As shown, the method includes the following steps:

[0078] Step S602: determining the current system debugging mode based on the UID button state and determining the current indication state of the indicator light;

[0079] The current system debugging mode includes: CPU debugging mode or BMC debugging mode; the current indication state is used to represent the hardware working state of the system in the current system debugging mode; the current indication state includes one of the following: first indication state, second indication state, third indication state or fourth indication state; the four indication states correspond to one of the following indicator states: off, flashing at a specified interval, always on, and flashing quickly;

[0080] The above-mentioned steps of determining the current system debugging mode based on the UID button status include: judging whether a specified long press operation of the UID button is detected; the specified long press operation includes: the duration of the long press operation reaches a specified duration; if not, using the currently detected system debugging mode as the current system debugging mode; if yes, switching the currently detected system debugging mode, and using the switched system debugging mode as the current system debugging mode.

[0081] For example, if the currently detected system debugging mode is the CPU debugging mode, if a specified long press operation on the UID button is detected, the CPU debugging mode is switched to the BMC debugging mode as the current system debugging mode. If the specified long press operation is not detected, the CPU debugging mode is used as the current system debugging mode.

[0082] The specific switching method is as follows: if the currently detected system debugging mode is the CPU debugging mode, the second CPLD is controlled through the GPIO interface to interrupt the CPU serial port output, so as to switch the CPU debugging mode to the BMC debugging mode; if the currently detected system debugging mode is the BMC debugging mode, the second CPLD is controlled through the GPIO interface to restore the CPU serial port output, so as to switch the BMC debugging mode to the CPU debugging mode.

[0083] Step S604: monitoring in real time whether there is any change in the hardware working status of the server system in the current system debugging mode;

[0084] There are four types of changes here. The first is that the hardware status changes from abnormal to normal in CPU debugging mode. The second is that the hardware status changes from normal to abnormal in CPU debugging mode. The third is that the hardware status changes from abnormal to normal in BMC debugging mode. The fourth is that the hardware status changes from normal to abnormal in BMC debugging mode.

[0085] If yes, execute step S606 to change the current indication state of the indicator light to another indication state;

[0086] In specific implementation, if the current system debugging mode is the CPU debugging mode, the current indication state is the first indication state, and the first indication state is replaced with the second indication state; wherein the first indication state and the second indication state are respectively used to represent that the system hardware is in a normal state and an abnormal state in the CPU debugging mode; if the current system debugging mode is the BMC debugging mode, the current indication state is the third indication state, and the third indication state is replaced with the fourth indication state; wherein the third indication state and the fourth indication state are respectively used to represent that the system hardware is in a normal state and an abnormal state in the BMC debugging mode.

[0087] If not, execute step S608 to control the indicator light to maintain the current indication state.

[0088] The method provided in the embodiment of the present application has the same implementation principle and technical effects as those in the aforementioned system embodiment. For the sake of brief description, for matters not mentioned in the embodiment of the method, reference can be made to the corresponding content in the aforementioned system embodiment.

[0089] An embodiment of the present application also provides a computer-readable storage medium, which stores computer-executable instructions. When the computer-executable instructions are called and executed by the processor, the computer-executable instructions prompt the processor to implement the above-mentioned method. The specific implementation can be found in the above-mentioned method embodiment, which will not be repeated here.

[0090] The computer program products of the methods, devices, and electronic devices provided in the embodiments of the present application include a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the methods described in the previous method embodiments. For specific implementation, please refer to the method embodiments and will not be repeated here.

[0091] Unless otherwise specifically stated, the relative steps, numerical expressions and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present application.

[0092] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0093] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0094] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The scope of protection of the present application is not limited thereto. Although the present application has been described in detail with reference to the above-described embodiments, those skilled in the art should understand that any person skilled in the art can modify or easily conceive of changes to the technical solutions described in the above-described embodiments within the technical scope disclosed in the present application, or perform equivalent replacements for some of the technical features thereof. These modifications, changes, or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application shall be subject to the scope of protection of the claims.

Claims

1. A server dual-mode debugging system, characterized in that: The system includes: a mainboard and a DC-SCM card; the mainboard is provided with a CPU and a first CPLD; the DC-SCM card is provided with a second CPLD, a BMC controller, a CP2105 chip, a TYPE-C interface, a UID button and an indicator light; wherein the CPU, the first CPLD and the second CPLD are connected in sequence; the BMC controller is connected to the second CPLD, the UID button and the indicator light respectively; the CP2105 chip is connected to the second CPLD, the BMC controller and the TYPE-C interface respectively; The CPU, the first CPLD, the second CPLD, the CP2105 chip and the TYPE-C interface constitute a signal transmission path in a CPU debugging mode; The BMC controller, the CP2105 chip and the TYPE-C interface constitute a signal transmission path in the BMC debugging mode; The BMC controller is used to detect the current system debugging mode and the key operation status of the UID key, and switch the current system debugging mode according to the key operation status; The BMC controller is further configured to detect in real time the hardware operating status of the server system in the current system debugging mode, and control the indicator light to display the system operating status in the current system debugging mode according to the hardware operating status; Among them, the system working status includes the following four: normal hardware working status in CPU debugging mode, abnormal hardware working status in CPU debugging mode, normal hardware working status in BMC debugging mode, and abnormal hardware working status in BMC debugging mode; the four system working statuses should be indicated by one of the following four indicator light states: off, flashing at a specified interval, always on, and flashing quickly.

2. The system according to claim 1, wherein: The CPU is connected to the first CPLD through a UART serial port; the first CPLD is connected to the second CPLD through an LVDS differential transmission channel; the CP2105 chip has dual UART channels, which are respectively connected to the BMC control and the second CPLD; the BMC controller is respectively connected to the second CPLD, the UID button, and the indicator light through a GPIO interface; the Type-C interface is connected to the output end of the CP2105 chip.

3. The system according to claim 2, characterized in that The BMC controller, when detecting a long press operation on the UID button and the long press duration reaches a preset duration, controls the second CPLD to interrupt or restore the CPU serial port output through the GPIO interface to switch the system debugging mode.

4. The system according to claim 1, wherein: The UID button is equipped with an anti-shake circuit and is integrated with the indicator light. The indicator light is a single-color LED indicator light.

5. The system according to claim 1, wherein: The data transmission between the first CPLD and the second CPLD adopts LVDS differential signal, which is transmitted through the standard gold finger connector between the motherboard and the DC-SCM card; the Type-C interface adopts USB2.0 data channel to transmit serial port signals and is compatible with standard USB Type-C to A cable.

6. A server dual-mode debugging method, characterized in that: The method is applied to a BMC controller in a server dual-mode debugging system according to any one of claims 1 to 5, and the method includes: Determine the current system debugging mode based on the UID button state, and determine the current indication state of the indicator light; wherein the current system debugging mode includes: CPU debugging mode or BMC debugging mode; the current indication state is used to represent the hardware working state of the system in the current system debugging mode; the current indication state includes one of the following: a first indication state, a second indication state, a third indication state, or a fourth indication state; the four indication states respectively correspond to one of the following indicator light states: off, flashing at a specified interval, constantly on, and flashing rapidly; Real-time monitoring of whether there is any change in the hardware working status of the server system in the current system debugging mode; If yes, change the current indication state of the indicator light to another indication state; If not, the control indicator light maintains the current indication state.

7. The method according to claim 6, characterized in that The steps for determining the current system debugging mode based on the UID button status include: Determine whether a designated long press operation on the UID button is detected; the designated long press operation includes: the duration of the long press operation reaches a designated duration; If not, the currently detected system debugging mode is used as the current system debugging mode; If yes, the currently detected system debugging mode is switched, and the switched system debugging mode is used as the current system debugging mode.

8. The method according to claim 6, characterized in that The steps for switching the currently detected system debugging mode include: If the currently detected system debugging mode is the CPU debugging mode, controlling the second CPLD to interrupt the CPU serial port output through the GPIO interface to switch the CPU debugging mode to the BMC debugging mode; If the currently detected system debugging mode is the BMC debugging mode, the second CPLD is controlled through the GPIO interface to restore the CPU serial port output, so as to switch the BMC debugging mode to the CPU debugging mode.

9. The method according to claim 6, characterized in that The steps for changing the current indication state of the indicator light to another specified state include: If the current system debugging mode is the CPU debugging mode and the current indication state is the first indication state, the first indication state is changed to the second indication state; wherein the first indication state and the second indication state are respectively used to indicate that the system hardware is in one of a normal state and an abnormal state in the CPU debugging mode; If the current system debugging mode is the BMC debugging mode and the current indication state is the third indication state, the third indication state is changed to a fourth indication state; wherein the third indication state and the fourth indication state are respectively used to indicate that: in the BMC debugging mode, the system hardware is in one of a normal state and an abnormal state.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer-executable instructions. When the computer-executable instructions are called and executed by a processor, the computer-executable instructions prompt the processor to implement the method according to any one of claims 6 to 9.

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